JPH0354828A - Compound conductor layer of semiconductor device, hole-making process of capacitor using compound conductor layer and compound conductor layer - Google Patents
Compound conductor layer of semiconductor device, hole-making process of capacitor using compound conductor layer and compound conductor layerInfo
- Publication number
- JPH0354828A JPH0354828A JP19083089A JP19083089A JPH0354828A JP H0354828 A JPH0354828 A JP H0354828A JP 19083089 A JP19083089 A JP 19083089A JP 19083089 A JP19083089 A JP 19083089A JP H0354828 A JPH0354828 A JP H0354828A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- conductive layer
- composite
- auxiliary
- semiconductor device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000003990 capacitor Substances 0.000 title claims abstract description 25
- 239000004065 semiconductor Substances 0.000 title claims description 29
- 238000000034 method Methods 0.000 title abstract description 30
- 230000008569 process Effects 0.000 title description 17
- 150000001875 compounds Chemical class 0.000 title description 8
- 239000004020 conductor Substances 0.000 title 3
- 229910052719 titanium Inorganic materials 0.000 claims abstract description 53
- 239000000463 material Substances 0.000 claims abstract description 48
- 229910052737 gold Inorganic materials 0.000 claims abstract description 31
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 25
- 229910052732 germanium Inorganic materials 0.000 claims abstract description 18
- 229910052697 platinum Inorganic materials 0.000 claims abstract description 15
- 229910052782 aluminium Inorganic materials 0.000 claims abstract description 5
- 229910052802 copper Inorganic materials 0.000 claims abstract description 5
- 229910052750 molybdenum Inorganic materials 0.000 claims abstract description 4
- 229910052721 tungsten Inorganic materials 0.000 claims abstract description 4
- 239000002131 composite material Substances 0.000 claims description 74
- 239000010936 titanium Substances 0.000 claims description 71
- 239000010931 gold Substances 0.000 claims description 52
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims description 49
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 claims description 36
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims description 31
- 238000005530 etching Methods 0.000 claims description 22
- 239000010703 silicon Substances 0.000 claims description 21
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 20
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 claims description 16
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 10
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 9
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 5
- 239000010949 copper Substances 0.000 claims description 5
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 5
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 4
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 4
- KRHYYFGTRYWZRS-UHFFFAOYSA-M Fluoride anion Chemical compound [F-] KRHYYFGTRYWZRS-UHFFFAOYSA-M 0.000 claims description 3
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 claims description 3
- 239000011733 molybdenum Substances 0.000 claims description 3
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims description 3
- 239000010937 tungsten Substances 0.000 claims description 3
- 238000004519 manufacturing process Methods 0.000 claims description 2
- 230000000149 penetrating effect Effects 0.000 claims description 2
- 239000000126 substance Substances 0.000 claims description 2
- 238000005336 cracking Methods 0.000 abstract description 9
- 239000000758 substrate Substances 0.000 abstract description 9
- 239000000203 mixture Substances 0.000 abstract description 8
- 229910001218 Gallium arsenide Inorganic materials 0.000 abstract description 7
- 229910045601 alloy Inorganic materials 0.000 abstract description 6
- 239000000956 alloy Substances 0.000 abstract description 6
- 150000004767 nitrides Chemical class 0.000 abstract description 5
- 230000002708 enhancing effect Effects 0.000 abstract 1
- 239000010410 layer Substances 0.000 description 415
- 239000007789 gas Substances 0.000 description 13
- 229910052751 metal Inorganic materials 0.000 description 11
- 239000002184 metal Substances 0.000 description 11
- 238000010586 diagram Methods 0.000 description 9
- 238000005553 drilling Methods 0.000 description 8
- 229910004205 SiNX Inorganic materials 0.000 description 6
- 238000009413 insulation Methods 0.000 description 6
- 238000005275 alloying Methods 0.000 description 5
- 238000012360 testing method Methods 0.000 description 5
- QGZKDVFQNNGYKY-UHFFFAOYSA-N Ammonia Chemical class N QGZKDVFQNNGYKY-UHFFFAOYSA-N 0.000 description 4
- 238000005268 plasma chemical vapour deposition Methods 0.000 description 4
- 239000004642 Polyimide Substances 0.000 description 3
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 description 3
- 239000000470 constituent Substances 0.000 description 3
- 150000002291 germanium compounds Chemical class 0.000 description 3
- 150000002739 metals Chemical class 0.000 description 3
- 229920001721 polyimide Polymers 0.000 description 3
- 230000009257 reactivity Effects 0.000 description 3
- LIVNPJMFVYWSIS-UHFFFAOYSA-N silicon monoxide Chemical compound [Si-]#[O+] LIVNPJMFVYWSIS-UHFFFAOYSA-N 0.000 description 3
- 238000003860 storage Methods 0.000 description 3
- KDLHZDBZIXYQEI-UHFFFAOYSA-N Palladium Chemical compound [Pd] KDLHZDBZIXYQEI-UHFFFAOYSA-N 0.000 description 2
- 229910018503 SF6 Inorganic materials 0.000 description 2
- 229910021529 ammonia Inorganic materials 0.000 description 2
- 230000004888 barrier function Effects 0.000 description 2
- 230000008901 benefit Effects 0.000 description 2
- 238000011109 contamination Methods 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 230000007774 longterm Effects 0.000 description 2
- 238000000206 photolithography Methods 0.000 description 2
- 230000001681 protective effect Effects 0.000 description 2
- 239000011241 protective layer Substances 0.000 description 2
- 229910000077 silane Inorganic materials 0.000 description 2
- SFZCNBIFKDRMGX-UHFFFAOYSA-N sulfur hexafluoride Chemical compound FS(F)(F)(F)(F)F SFZCNBIFKDRMGX-UHFFFAOYSA-N 0.000 description 2
- 229960000909 sulfur hexafluoride Drugs 0.000 description 2
- 238000007738 vacuum evaporation Methods 0.000 description 2
- BYHQTRFJOGIQAO-GOSISDBHSA-N 3-(4-bromophenyl)-8-[(2R)-2-hydroxypropyl]-1-[(3-methoxyphenyl)methyl]-1,3,8-triazaspiro[4.5]decan-2-one Chemical compound C[C@H](CN1CCC2(CC1)CN(C(=O)N2CC3=CC(=CC=C3)OC)C4=CC=C(C=C4)Br)O BYHQTRFJOGIQAO-GOSISDBHSA-N 0.000 description 1
- RZSYLLSAWYUBPE-UHFFFAOYSA-L Fast green FCF Chemical compound [Na+].[Na+].C=1C=C(C(=C2C=CC(C=C2)=[N+](CC)CC=2C=C(C=CC=2)S([O-])(=O)=O)C=2C(=CC(O)=CC=2)S([O-])(=O)=O)C=CC=1N(CC)CC1=CC=CC(S([O-])(=O)=O)=C1 RZSYLLSAWYUBPE-UHFFFAOYSA-L 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 238000004891 communication Methods 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 239000003989 dielectric material Substances 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000002474 experimental method Methods 0.000 description 1
- 230000001939 inductive effect Effects 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 229910052763 palladium Inorganic materials 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
- 230000035939 shock Effects 0.000 description 1
- 150000003377 silicon compounds Chemical class 0.000 description 1
- -1 silicon nitrides Chemical class 0.000 description 1
- 239000002210 silicon-based material Substances 0.000 description 1
- 239000002356 single layer Substances 0.000 description 1
- 229910000679 solder Inorganic materials 0.000 description 1
- 238000005476 soldering Methods 0.000 description 1
- 239000006104 solid solution Substances 0.000 description 1
- 238000000992 sputter etching Methods 0.000 description 1
- 150000003608 titanium Chemical class 0.000 description 1
- 238000001771 vacuum deposition Methods 0.000 description 1
Landscapes
- Semiconductor Integrated Circuits (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
【発明の詳細な説明】
（産業上の利用分野）
この発明は、半導体装置の電極、配線等として用いられ
る複合導電層ならびにこの複合導電層を電極とするキャ
パシタおよびこの複合導電層に穴を開ける方法（こ閉す
る。Detailed Description of the Invention (Industrial Application Field) This invention relates to a composite conductive layer used as an electrode, wiring, etc. of a semiconductor device, a capacitor using this composite conductive layer as an electrode, and a method for making holes in this composite conductive layer. Method (closed)
（従来の技術）
半導体装置には、ダイオード、トランジスタ等の半導体
素子、およびこれら半導体素子を、場合Ｃこよっては抵
抗、キャパシタ（容ｊ！素子）およびまたはインダクタ
（誘導素子）と共に、多数組み込んで形成した集積回路
がある．周知の通り、これら半導体装置は、
■基板に作り込んだ能動領域間の相互接続のために、或
いは能動領域と外部回路との間の接続のために、電極層
および配線層を具えており、■場合（こよっては、絶縁
層に設けた穴（孔とが窓ともいう．）を経て絶縁層の上
下の電極層あるいは配線層を相互接続する多層配線構造
を具えたり、
■また、絶縁層に設けた穴に露出した導電層に外部回路
と接続のためのワイヤボンディングを行ったワイヤ配線
構造を具えたり、
■さらには、所要に応じてキャパシタやインダクタを具
えている．
そして、これら電極層、配線層、インダクタおよびキャ
パシタの電極を、１層以上の、電気抵抗の小さい導電層
で構成している．
従来の導電層の典型的な例につき第２図を参照して簡単
｛こ説明する。(Prior Art) A semiconductor device incorporates a large number of semiconductor elements such as diodes and transistors, and these semiconductor elements together with resistors, capacitors (capacitance elements), and/or inductors (inductive elements). There is an integrated circuit that was formed. As is well known, these semiconductor devices include electrode layers and wiring layers for interconnection between active regions formed on the substrate, or for connection between the active region and an external circuit; ■ In some cases, the insulating layer may have a multilayer wiring structure that interconnects the upper and lower electrode layers or wiring layers through holes (holes are also called windows) in the insulating layer. The conductive layer exposed through the hole provided in the electrode layer is provided with a wire wiring structure in which wire bonding is performed for connection with an external circuit, and furthermore, a capacitor or inductor is provided as required. , wiring layers, and electrodes of inductors and capacitors are composed of one or more conductive layers with low electrical resistance.A typical example of a conventional conductive layer will be briefly explained with reference to FIG. .
通常は、ＧａＡｓ基板２０上にＳｉＮ．等の絶縁層２２
設け、この絶縁層２２上に導電層として配線層１０を設
けてある．この配線層１０は、絶締層２２上にチタン（
Ｔｉ）層１２、白金（Ｐｔ）層１４および金（Ａｕ）層
１６を順次に戊膜して形成した３層構造（ Ｔ ｉ ／
Ｐ ｔ ／ Ａ ｕと表わす．）の、電気抵抗の小さ
い導電層である（例えば、文献工：（「エレクトロニク
ス レターズ（ ＥＬＥＣＴＲＯＮＩＣＳＬＥＴＴＥＲ
Ｓ Ｊ ） 、ｖｏｌ．＋８、Ｎｏ． ３、（１９８４
） 、ｐｐｌｌ９〜１２１ ） ） ．チタン層（Ｔｉ
層ともいう。）１２は、上側の金層（Ａｕ層ともいう。Usually, SiN. Insulating layer 22 such as
A wiring layer 10 is provided as a conductive layer on this insulating layer 22. This wiring layer 10 has titanium (
A three-layer structure (Ti/
It is expressed as Pt/Au. ) is a conductive layer with low electrical resistance (for example, literature engineering: ("ELECTRONICS LETTER").
SJ), vol. +8, No. 3, (1984
), ppll9-121)). Titanium layer (Ti
Also called layer. ) 12 is an upper gold layer (also referred to as an Au layer).
）１６と下地としての絶縁層２２との密着を向上させる
ために設けた層であり、通常は１０００人程度の厚い層
とする．白金層（Ｐｉ層ともいう．）１４はチタンと金
の相互拡散による合金化を防止するためのバリア層とし
て設けてある。また、最上層の金層１６は、金属の中で
電気抵抗が特に小さいので低抵抗配線が実現出来ること
、および金の表面は通常は化学的に安定であるため半導
体装置の製造工程中に変威しにくいことという理由で用
いられている．そして、この配線層等としての導電層１
０上には表面リークや汚染を防止するため、あるいは、
キャパシタの下側電極としての導電層１０上には誘電体
として、窒化珪素（ＳｉＮ．）、酸化珪素（Ｓｉｆ２）
、ポリイミド等の絶縁膜２４を設けでいる．
また、シリコンデバイス用の金属電極としての導電層構
造の種々の例が文献■：（「最新しＳＩプロセス技術」
、（株）工業調査会発行、１９８３年、第２３５−２３
６頁）に開示されている．この文献ＩＩにも記載ざれて
いるように、チタン層（Ｔｉ層）は、酸化珪素膜（Ｓｉ
ｎ２膜）と電気抵抗の小さい金層（Ａｕ層）等との中間
層として酸化珪素膜と金層等との密着性を図るために設
けている．この場合にも、Ｔｉ層は通常は１０００大程
度の膜厚で設けているためこのＴｉと上側のＡｕとで合
金化してしまう。このような合金化層は電気抵抗が高く
、しかも、表面が粗くなるため好ましくない．従って、
この合金化を回避するため、通常は、パラジウム（Ｐ（
１）、白金（Ｐｔ）またはその他の金属のバリャ層を設
けて合金化の防止を図っている．
（発明が解決しようとする課題）
しかしながら、この従来の導電層構造の一例として導電
層の最上層を金（Ａｕ）層とし、その上側１こ絶縁層を
直接設けた構造体につき、−５０℃から＋１５０℃の温
度範囲で１０００時間以上にわたる保管試験および−５
０℃と＋８０℃の温度の繰り返しによる短時間熱衝撃試
験を行ったところ、絶縁層のひび割れが生したつ、ある
いは、剥離が生するのが認められ、また、導電層の平面
的な面積が大きくなるに従ってこのひび割れや剥離が増
大することが分った．このような絶縁層のひび割れおよ
び剥離等の現象は、金（Ａｕ）以外の低抵抗金属である
、白金（Ｐｔ）、アルミニウム（Ａｕ） 、銅（Ｃｕ）
等でも、生じる恐れがある．
また、このようなひび割れや剥離の発生を出来るだけ抑
えるために、従来は、導電層の幅を細く形成する必要が
あった．このため、従来の導電層はその平面的形状が著
しく制限を受け、従って、需要に見合った平面形状、例
えばキャパシタの電極として用いるための矩形形状の導
電層を形成することが、実質的に、不可能であった．既
に説明したように、チタン（Ｔ ｉ）が窒化珪素（Ｓｉ
Ｎ．）や酸化珪素（ＳｉＯｚ）等の絶縁層と、電気抵抗
の小さい金（Ａｕ）層との密着性を強化する性質を具え
ている．しかし、チタンが金等と合金化してしまうため
に、従来は、上述した絶縁層のひび割れおよび剥離の防
止のために用いられていなかった．そこで、この出願に
係る発明者等は、このチタンの密着性強化の性質に特Ｃ
こ着目し、この絶縁層のひび割れおよび剥離の発生を回
避するための種々の研究および実験を繰り返し行った。) 16 and the underlying insulating layer 22, and is usually about 1000 thick. A platinum layer (also referred to as a Pi layer) 14 is provided as a barrier layer to prevent alloying between titanium and gold due to mutual diffusion. In addition, the top gold layer 16 has particularly low electrical resistance among metals, making it possible to realize low-resistance wiring, and the surface of gold is usually chemically stable, so it does not change during the manufacturing process of semiconductor devices. It is used because it is less intimidating. Then, a conductive layer 1 as this wiring layer etc.
0 to prevent surface leakage and contamination, or
On the conductive layer 10 as the lower electrode of the capacitor, silicon nitride (SiN.), silicon oxide (Sif2) is used as a dielectric material.
, an insulating film 24 made of polyimide or the like is provided. In addition, various examples of conductive layer structures as metal electrodes for silicon devices can be found in the literature ■: ("Latest SI Process Technology")
, Published by Kogyo Kenkyukai Co., Ltd., 1983, No. 235-23
(page 6). As described in this document II, the titanium layer (Ti layer) is a silicon oxide film (Si
It is provided as an intermediate layer between the silicon oxide film (N2 film) and a gold layer (Au layer), etc., which has low electrical resistance, in order to improve the adhesion between the silicon oxide film and the gold layer, etc. In this case as well, since the Ti layer is usually provided with a thickness of about 1,000 mm, the Ti layer and the Au layer on the upper side become alloyed. Such an alloyed layer has high electrical resistance and has a rough surface, which is not desirable. Therefore,
To avoid this alloying, palladium (P(
1) A barrier layer of platinum (Pt) or other metal is provided to prevent alloying. (Problem to be Solved by the Invention) However, as an example of this conventional conductive layer structure, the uppermost layer of the conductive layer is a gold (Au) layer, and an insulating layer is directly provided on the uppermost layer. Storage test for more than 1000 hours at temperatures ranging from -5 to +150°C
When we conducted a short-time thermal shock test by repeatedly changing the temperature between 0°C and +80°C, it was observed that the insulating layer cracked or peeled, and the planar area of the conductive layer decreased. It was found that as the size increases, the number of cracks and peeling increases. Such phenomena such as cracking and peeling of the insulating layer are caused by low resistance metals other than gold (Au) such as platinum (Pt), aluminum (Au), and copper (Cu).
etc., it may occur. Furthermore, in order to suppress the occurrence of such cracking and peeling as much as possible, it has conventionally been necessary to form the conductive layer with a narrow width. For this reason, the planar shape of conventional conductive layers is severely limited, and therefore, it is practically impossible to form a conductive layer with a planar shape that meets the demand, for example, a rectangular shape for use as an electrode of a capacitor. It was impossible. As already explained, titanium (Ti) is a silicon nitride (Si)
N. ) or silicon oxide (SiOz), and a gold (Au) layer with low electrical resistance. However, since titanium is alloyed with gold etc., it has not been used to prevent the above-mentioned cracking and peeling of the insulating layer. Therefore, the inventors of this application have developed a special technology for the adhesion-enhancing properties of titanium.
Focusing on this, we repeatedly conducted various studies and experiments to avoid cracking and peeling of the insulating layer.
その結果、従来の導電層と絶縁層との間に、チタン（Ｔ
ｉ）あるいはその他の材料を含んだ補助導電層を、適当
に設けることによって、上述したような絶縁層のひび割
れおよび剥離を回避出来ると共に、チタン等の材料が下
層の金等と合金化したりあるいはその他の障害となるべ
き現象の発生を抑えることが出来ることを発見した．そ
こで、この出願の発明の目的は、上述した従来の問題点
に鑑み、絶縁膜のひび割れや剥離を防止出来る、複合導
電層およびこの複合導電層を電極として用いたキャパシ
タを提供すること、およびこの複合導電層に適した穴開
け方法を提供することにある．
（課題を解決するための手段）
この目的の達或を図るため、この発明の半導体装置の複
合導電層においては、
電気抵抗の小さい材料からなる、１層以上の層で構成し
た主導電層を設け、
この主導電層の上面に補助導電層を設けた複合導電層と
し、
この補助導電層を、当該補助導電層の上面に設けられる
絶縁層および当該補助導電層の下面に設けられた主導電
層に対し密着の強化を図る、電気抵抗の小さい材料で構
成することを特徴とする．この補助導電層の膜厚を、最
大でも２００人程度とするのが好適である．
また、この補助導電ＩｉｉＩ！、チタン、シリコンおよ
びゲルマニウムの群のなかから選らばれたいずれか一種
以上の材料を含む層で構成するのが効果的である．
さらに、上述した主導電層を補助導電層側から第１層、
第２層および第３層を順次に具えた３層構造として構成
し、
その第１層を、金、白金、アルミニウムおよび銅の群の
なかから選らばれたいずれか一種以上の材料を含む層と
し、第２層を、白金、タングステンおよびモリブデンの
群のなかから選らばれたいずれか一種以上の材料を含む
層とし、第３層を、チタン、シリコンおよびゲルマニウ
ムの群のなかから選らばれたいずれか一種以上の材料を
含む層として、それぞれ構戊するのが好適である．ざら
に、上述したいずれかの複合導電層で下側および上側電
極層を形威し、これら下側および上側電極層間に誘電体
層を設けて、半導体装置のキャパシタを構成する．
そして、半導体装置の導電層の穴開け方法においては、
下地上にま導電層および補助導電層を順次に戒膜して複
合導電層を設ける第一二程と、この複合導電層を被覆す
る絶締層を設ける第二工程と、
この絶縁層および前述の補助導電層の両者に共通して使
用出来るエッチング用ガスを用いて、この絶縁層および
補助導電層を貫通する穴を開ける第三工程と
を含むことを特徴とする。As a result, titanium (T
i) By properly providing an auxiliary conductive layer containing other materials, cracking and peeling of the insulating layer as described above can be avoided, and materials such as titanium can be alloyed with the underlying gold or other materials. We have discovered that it is possible to suppress the occurrence of phenomena that would otherwise be a hindrance. Therefore, in view of the above-mentioned conventional problems, it is an object of the invention of this application to provide a composite conductive layer and a capacitor using this composite conductive layer as an electrode, which can prevent cracking and peeling of an insulating film, and to provide a capacitor using this composite conductive layer as an electrode. The objective is to provide a hole-drilling method suitable for composite conductive layers. (Means for Solving the Problems) In order to achieve this object, the composite conductive layer of the semiconductor device of the present invention includes a main conductive layer composed of one or more layers made of a material with low electrical resistance. A composite conductive layer is formed by providing an auxiliary conductive layer on the upper surface of the main conductive layer, and the auxiliary conductive layer is combined with an insulating layer provided on the upper surface of the auxiliary conductive layer and a main conductive layer provided on the lower surface of the auxiliary conductive layer. It is characterized by being made of a material with low electrical resistance that strengthens the adhesion to the layers. The thickness of this auxiliary conductive layer is preferably about 200 at most. In addition, this auxiliary conductive III! It is effective to use a layer containing one or more materials selected from the group consisting of , titanium, silicon, and germanium. Furthermore, the above-mentioned main conductive layer is added as a first layer from the auxiliary conductive layer side,
It is constructed as a three-layer structure including a second layer and a third layer sequentially, and the first layer is a layer containing one or more materials selected from the group of gold, platinum, aluminum, and copper. , the second layer is a layer containing one or more materials selected from the group of platinum, tungsten, and molybdenum, and the third layer is a layer containing one or more materials selected from the group of titanium, silicon, and germanium. It is preferable to construct each layer as a layer containing one or more types of materials. Roughly speaking, a capacitor of a semiconductor device is constructed by forming lower and upper electrode layers using one of the composite conductive layers described above, and providing a dielectric layer between these lower and upper electrode layers. The method for drilling a conductive layer in a semiconductor device involves the first and second steps of sequentially forming a conductive layer and an auxiliary conductive layer on a base to form a composite conductive layer, and the second step of forming a composite conductive layer, and then covering the composite conductive layer with an auxiliary conductive layer. a second step of providing a tightening layer; and a third step of drilling a hole through the insulating layer and the auxiliary conductive layer using an etching gas that can be used commonly for both the insulating layer and the auxiliary conductive layer. It is characterized by including.
この場合、絶縁層をシリコンの酸化物またはシリコンの
窒化物とし、および補助導電層を、チタン、シリコンお
よびゲルマニウムの群のなかから選らばれたいずれか一
種以上の材料を含む層とした場合には、エッチング用ガ
ス壱フッ化物系ガスとすることが好適である。In this case, when the insulating layer is made of silicon oxide or silicon nitride, and the auxiliary conductive layer is a layer containing one or more materials selected from the group of titanium, silicon, and germanium, The etching gas (1) is preferably a fluoride gas.
（作用）
上述したこの発明の複合導電層の構造によれば、主導電
層は、電気抵抗の小さい金属の層であり、補助導電層は
、この主導電層および絶縁層と密着性が良く、しかも、
電気抵抗の小さい材料で構成してある．補助導電層が密
着性を向上きせるのは、その構戊材料が下層の主導電層
の金属となじむ材料であること、しかも、この下層の金
属よりも化学的反応を起し易く、従って、補助導電層の
上側に窒化膜あるいは酸化膜などの絶縁層を設ける工程
で、この補助導電層の境界面（こもこの補助導電層を構
戊する材料の窒化物や酸化物が形戊されて、絶縁膜との
なじみが良くなることからであると推測ざれる．従って
、この複合導電層によれば、上側に絶縁膜を設けても、
その絶縁膜にクラックやひび割れが発生するおそれが無
く、このため、この発明の複合導電層は、半導体装置に
用いられる電極、配線、インダクト線、キャパシタの電
極等を構成する種々の導電層に使用して好適である．
また、複合導電層に穴を開ける場合には、上側に設けら
れる絶縁層のエッチング用ガスを、補助導電層の穴開け
のエッチング用ガスとして、そのまま使用するので、複
雑な工程を経すして、同一のエッチング工程て絶締膜と
補助導電層とを貫通する穴を容易かつ簡単に形成出来る
．
（実施例）
以下、図面を譬照して、この発明の実施例につき説明す
る．尚、図は、この発明の構戊を理解出来る程度に、そ
の構成成分の形状、寸法、配置関係を概略的に示してあ
るにすぎず、従って、この出願の発明はこれら図示例に
のみ限定ざれるものではない．
［基本的構造の説明］
先ず、第１図を参照して、この発明の複合導電層につき
説明する．第１図は、この発明の複合導電層の一寅施例
の説明に供する説明図であり、下地面に直交する面での
断面図で示してある．先ず、この複合導電層２０は、主
導電層２２と補助導電層２４とで構戊する．この主導電
層２２を、半導体装置に通常用いられている導電層とし
て構成するので、この主導電層２２は、電気抵抗の小さ
い材料からなる層であって、しかも、１層以上の層で構
成した一層または多層構造となっている。この主導電層
２２を下地２６（図中一点破線で示してある．）の上面
に適当な膜厚で設ける．下地２６を例えば化合物半導体
材料であるＧａＡｓとかシリコンとかの適当な材料自体
で形成するか或はこれらの材料層上に適当な絶縁層を設
けた構造とすることが出来る．
この主導電層２２の上面に補助導電層２４ヲ設ける．こ
の補助導電層２４８、その上面Ｃこ設けられる絶縁層２
８（図中、一点破線で示してある．）およびこの補助導
電層２４の下面に設けられた主導電層２２及び上側に設
ける絶縁層２８に対し密着の強化を図ると共に、電気抵
抗の小さい材料で構成する．従って、この補助導電層２
４としては、主導電層２２の少なくともこの補助導電層
２４と接触する層部分およびこの補助導電層２４の上側
に形成する絶縁層２８と相互拡散し易いこと、固溶体を
作り易いこと、化合物を作り易いことなどの少なくとも
いずれかの反応性を有する材料であれば良い．従って、
補助導電層２４ヲ、チタン（Ｔｉ）、シリコン（Ｓｉ）
およびゲルマニウム（Ｇｅ）の群のなかから選らばれた
いずれか一種以上の材料を含む層として構成する．従っ
て、この補助導電層２４を、チタン（Ｔ１）の層、シリ
コン（Ｓｉ）の層またはゲルマニウム（Ｇｅ）の層とし
て構成しても良いし、チタンとシリコンの混合物（合金
の場合を含む）層、チタンとゲルマニウムの混合物（合
金の場合を含む）層、シリコンとゲルマニウムの混合物
（合金の場合を含む）層、チタンとシリコンとゲルマニ
ウムの混合物（合金の場合を含む）層、チタン、シリコ
ンおよびゲルマニウムから選らばれた一種以上の材料と
他の適当な材料との混合物（合金の場合も含む）として
構威しても良い。(Function) According to the structure of the composite conductive layer of the present invention described above, the main conductive layer is a metal layer with low electrical resistance, and the auxiliary conductive layer has good adhesion to the main conductive layer and the insulating layer. Moreover,
It is made of a material with low electrical resistance. The reason why the auxiliary conductive layer improves adhesion is that its constituent material is a material that is compatible with the metal of the underlying main conductive layer, and moreover, it is more likely to cause a chemical reaction than the metal of the underlying layer. In the process of providing an insulating layer such as a nitride film or an oxide film on the upper side of a conductive layer, the boundary surface of this auxiliary conductive layer (the nitride or oxide of the material constituting the auxiliary conductive layer) is formed and insulated. It is presumed that this is because the compatibility with the film improves. Therefore, according to this composite conductive layer, even if an insulating film is provided on the upper side,
There is no risk of cracks or cracks occurring in the insulating film, and for this reason, the composite conductive layer of the present invention can be used in various conductive layers constituting electrodes, wiring, induct lines, capacitor electrodes, etc. used in semiconductor devices. It is suitable for this purpose. Furthermore, when making holes in the composite conductive layer, the etching gas for the insulating layer provided on the upper side is used as is for making holes in the auxiliary conductive layer, so there is no need to go through a complicated process. A hole penetrating the insulation film and the auxiliary conductive layer can be easily and easily formed using the same etching process. (Examples) Examples of the present invention will be described below with reference to the drawings. Note that the drawings only schematically illustrate the shapes, dimensions, and arrangement relationships of the constituent components to an extent that allows the structure of the present invention to be understood; therefore, the invention of this application is limited only to these illustrated examples. It's not something that can be lost. [Description of Basic Structure] First, the composite conductive layer of the present invention will be explained with reference to FIG. FIG. 1 is an explanatory diagram for explaining one embodiment of the composite conductive layer of the present invention, and is a sectional view taken in a plane perpendicular to the underlying surface. First, this composite conductive layer 20 is composed of a main conductive layer 22 and an auxiliary conductive layer 24. Since the main conductive layer 22 is constructed as a conductive layer commonly used in semiconductor devices, the main conductive layer 22 is a layer made of a material with low electrical resistance, and is composed of one or more layers. It has a single layer or multilayer structure. This main conductive layer 22 is provided on the upper surface of the base 26 (indicated by a dashed line in the figure) with an appropriate film thickness. The base 26 may be formed of a suitable material such as GaAs or silicon, which are compound semiconductor materials, or may have a structure in which a suitable insulating layer is provided on a layer of these materials. An auxiliary conductive layer 24 is provided on the upper surface of this main conductive layer 22. This auxiliary conductive layer 248, an insulating layer 2 provided on its upper surface C
8 (indicated by a dotted line in the figure) and this auxiliary conductive layer 24 is made of a material with low electrical resistance that strengthens the adhesion to the main conductive layer 22 provided on the lower surface and the insulating layer 28 provided on the upper side. It consists of Therefore, this auxiliary conductive layer 2
4, it is easy to interdiffuse with at least the layer portion of the main conductive layer 22 that contacts the auxiliary conductive layer 24 and the insulating layer 28 formed on the upper side of the auxiliary conductive layer 24, it is easy to form a solid solution, and it is easy to form a compound. Any material may be used as long as it has at least one of the reactivity, such as easy reactivity. Therefore,
Auxiliary conductive layer 24, titanium (Ti), silicon (Si)
and germanium (Ge). Therefore, this auxiliary conductive layer 24 may be configured as a layer of titanium (T1), a layer of silicon (Si), a layer of germanium (Ge), or a layer of a mixture (including the case of an alloy) of titanium and silicon. , titanium and germanium mixture (including alloy) layer, silicon and germanium mixture (including alloy) layer, titanium, silicon and germanium mixture (including alloy) layer, titanium, silicon and germanium It may be constructed as a mixture (including the case of an alloy) of one or more materials selected from the above and other suitable materials.
さらに、この補助導電層２４ヲ、チタンとシリコンの化
合物層、チタンとゲルマニウムの化合物層、シリコンと
ゲルマニウムの化合物層、チタンとシリコンとゲルマニ
ウムの化合物層、チタン、シリコンおよびゲルマニウム
から選らばれた一種以上の材料と他の適当な材料との化
合物層として構成しても良い．
また、この補助導電層２４は、上述したこれらのいずれ
かの層が混在して構戊されていても良い，そし゜Ｃ、こ
の補助導電層２４の膜厚は設計に応して定めることが出
来るが、その最大膜厚を２００人程度とするのが好適で
ある．このような膜厚にしておけば、この補助導電層の
成膜時に、下層の主導電層２２の構成材料である、例え
ば金（Ａｕ）の材料と補助導電層の材料である、例えば
チタン（Ｔｉ）との合金化を防止することが出来るので
、複合導電層の電気抵抗が徒に大きくならないように効
果的に抑制することが出来る。Furthermore, this auxiliary conductive layer 24 is one or more selected from a titanium and silicon compound layer, a titanium and germanium compound layer, a silicon and germanium compound layer, a titanium, silicon and germanium compound layer, titanium, silicon and germanium. It may also be constructed as a compound layer of this material and other suitable materials. Further, this auxiliary conductive layer 24 may be composed of a mixture of any of the above-mentioned layers, and the thickness of this auxiliary conductive layer 24 can be determined according to the design. However, it is preferable that the maximum film thickness be approximately 200 people. With such a film thickness, when forming the auxiliary conductive layer, the constituent material of the lower main conductive layer 22, such as gold (Au), and the material of the auxiliary conductive layer, such as titanium ( Since alloying with Ti) can be prevented, the electrical resistance of the composite conductive layer can be effectively suppressed from increasing unnecessarily.
［複合導電層の具体的構造例コ
次に、この複合導電層を下地２６上に設け、この複合導
電層２０上に絶縁層２８ヲ設けた構造の具体例を第３図
〜第５図にそれぞれ示す．
上述した主導電層２２を補助導電層２４側から第１層３
２、第２層３４および第３層３６を順次に具えた３層構
造として、あるいは、第１層３２および第２層３４の２
層構造として、あるいはまた、第１層のみの一層構造と
して構成する．
この場合、第１層３２ヲ、金、白金、アルミニウムおよ
び銅の群のなかから選らばれたいずれか一種以上の材料
を含む層とし、第２層３４を、白金、タングステンおよ
びモリブデンの群のなかから選らばれたいずれか一種以
上の材料を含む層とし、第３層３６ヲ、チタン、シリコ
ンおよびゲルマニウムの群のなかから選らばれたいずれ
か一種以上の材料を含む層として、それぞれ構戊する．
ここで、それぞれの「材料を含む層」とは、その材料の
みの層であっても良いし、それぞれの材料を適当な種類
だけ混合（合金化を含む）したり、あるいは、化合物と
しても良い。[Specific Structure Example of Composite Conductive Layer] Next, specific examples of a structure in which the composite conductive layer is provided on the base 26 and the insulating layer 28 is provided on the composite conductive layer 20 are shown in FIGS. 3 to 5. Each is shown below. The main conductive layer 22 described above is connected to the first layer 3 from the auxiliary conductive layer 24 side.
2. As a three-layer structure with a second layer 34 and a third layer 36 sequentially, or as a two-layer structure with a second layer 32 and a second layer 34.
It can be configured as a layered structure or as a single layered structure with only the first layer. In this case, the first layer 32 is a layer containing one or more materials selected from the group of gold, platinum, aluminum, and copper, and the second layer 34 is a layer containing one or more materials selected from the group of platinum, tungsten, and molybdenum. The third layer 36 is a layer containing one or more materials selected from the group consisting of titanium, silicon, and germanium.
Here, each "layer containing a material" may be a layer containing only that material, a mixture of appropriate types of each material (including alloying), or a compound. .
第３図は、主導電層２２を３層構造として構戊した例、
第４図は、主導電層２２を２層構造として構戊した例、
および第５図は、主導電層２２を１層構造として構成し
た例をそれぞれ示す．これらの実施例における第３図の
構成例につき具体的に説明する。基板２６をＧａＡｓ基
板とし、その上面に設けたｗ！．締層２８を膜厚が５０
００人のシリコンの窒化膜（ＳｉＮ．）とする．゛ざう
に、複合導電層２２を、フォトレジストによるリフトオ
フ法を用いて例えば配線層のパターンとして形成する．
この複合導電層２２の第１層３２を膜厚が５００ＯＡの
金（Ａｕ）の層とし、第２層を膜厚が１０００大の白金
（Ｐｔ）の層としおよび第３層を膜厚が１ ００ＯＡの
チタン（Ｔｉ）の層とする．さらに、この第１層３２の
上側に設けた補助導電層２４を、膜厚が１００大のチタ
ン（Ｔｉ）の層とする．これら第１〜３層３２、３４、
３６と補助導電層２４を真空蒸着法で形成する．
ざらに、この複合導電層２２を被覆するように下地２６
の全面にＳｉＮｘの絶縁層２８ヲ、プラズマＣＶＤ法に
より、３ ０ ０ ’Ｃの温度で、５０００大の膜厚で
形成する。FIG. 3 shows an example in which the main conductive layer 22 has a three-layer structure.
FIG. 4 shows an example in which the main conductive layer 22 has a two-layer structure.
and FIG. 5 each show an example in which the main conductive layer 22 has a one-layer structure. The configuration example shown in FIG. 3 in these embodiments will be specifically explained. The substrate 26 is a GaAs substrate, and the w! ．． The thickness of the tightening layer 28 is 50
00 silicon nitride film (SiN.). First, the composite conductive layer 22 is formed as a pattern of, for example, a wiring layer using a lift-off method using photoresist.
The first layer 32 of this composite conductive layer 22 is a layer of gold (Au) with a thickness of 500 OA, the second layer is a layer of platinum (Pt) with a thickness of 1000 OA, and the third layer is a layer of platinum (Pt) with a thickness of 1 OA. 00OA titanium (Ti) layer. Further, the auxiliary conductive layer 24 provided above the first layer 32 is made of titanium (Ti) with a thickness of 100 mm. These first to third layers 32, 34,
36 and the auxiliary conductive layer 24 are formed by vacuum evaporation. Roughly cover this composite conductive layer 22 with a base 26.
An insulating layer 28 of SiNx is formed on the entire surface by plasma CVD at a temperature of 300'C to a thickness of 5000 mm.
次に、ＧａＡｓ集積回路の配線を第３図に示したこの発
明の複合導電層（ Ｔ ｉ ／ Ｐ ｔ ／ Ａ ｕ
／Ｔｉ）で構戊した場合と、補助導電層を具えていない
従来の導電層（ Ｔ ｉ ／ Ｐ ｔ ／ Ａ ｕ ）
で配線を構戊したＧａＡｓ集積回路につき、長時間保管
試験を行った．この試験で、温度を８５゜Ｃ、相対湿度
を８５％とした雰囲気中に１ ０００時間以上保管して
行った．
ソノ結果、通常の導電層（Ｔ’ｉ／Ｐｔ／Ａｕ）構造の
配線上のＳｉＮｘ絶締層は亀裂を生したが、この発明の
複合導電層（ Ｔ ｉ ／ Ｐ ｔ ／ Ａ ｕ ／Ｔ
ｉ）構造の配線上のＳｉＮｘ絶縁層は亀裂を生しなかっ
た。この実験結果から、非常に安定で化学的に反応性の
小さい金（Ａｕ）の表面上に形成したＳ Ｉ Ｎ Ｘ絶
縁層は密着性が弱いことが分った．一方、金（Ａｕ）の
層（第３図に３２で示す第１層）上にＴｉ層（第３図に
２４で示す補助導電層）を設けた、この発明の複合導電
層２２上にＳ Ｉ Ｎ ｘ ｗ！．縁層（第３図に２８
で示す）を設けた構造では、金（Ａｕ）とチタン（Ｔｉ
）とが金属同志でありしかも相互拡散が低温で起つ始め
るため両者間のなじみが強力となって金層とチタン層と
の密着力が増すと考えられる．また、チタン（Ｔｉ）層
上にＳｉＮｘ絶締層を形成する時、シラン（Ｓｉ日．）
とアンモニア（Ｎ目３）とを反応させるが、このアンモ
ニアがチタンと反応して、チタン層の界面が窒化物とな
るため、チタン層と３ １Ｎ ｘ絶縁層との密着性が増
すと考えられる．従って、このチタン層２４は下層の金
層３２と上層の絶締層２８との間の密着性を向上させて
絶縁層のひび割れや剥Ｍを防止していることが分る．尚
、ここで絶縁膜２８、４２としてＳｉＮ，＋を用いて例
を示したが、Ｓ１０２であっても、また、ＳｉＯ．Ｎ．
であっても良い．
このように、この発明の複合導電層を配線等に用いれば
、絶縁層のひび割れヤ剥Ｍを生じるおそれが無いので、
配線等を下地上に平面的に拡がりのある形状として形成
することが出来る．［キャパシタの例コ
第６図は、この発明の複合導電層を上側電極および下側
電極として用いたキャパシタの実施例を示す断面図であ
る．これら電極の平面形状を正方形等とすることが出来
る．以下、この実施例につき説明する．
この実施例では、第３図に示した３層構造の主導電層と
補助導電層とを含む構造の複合導電層（ Ｔ ｉ ／
Ｐ ｔ ／ Ａ ｕ ／ Ｔ ｉ ）を上下の電極とし
て用いたキャパシタを例に挙げて説明する．ＧａＡｓ基
板６０上にＳ Ｉ Ｎ ＊絶縁層６２を設けてなる下地
６４の表面に、主導電層６６（下地側から第３層６８、
第２層７０、第１層７２）および補助導電層７４からな
る複合導電層を適当な平面形状の下側電極７６として設
ける。次に、この下側電極７６を被覆するように下地６
４に全面に誘電体層７８を設ける．この誘電体層７８と
して、第３図の寅施例で設けたＳ ｉＮ ｘ絶締層２８
と同様な絶縁層を例えば５０００λの膜厚て設ける。次
に、この下側電極７６の上側に、この下側電極７６と同
し構造、同し形状および同じ面積の上側電極８０ヲ、絶
縁層７８ヲ挟んで、下側電極７６に対向させて形戒する
．この場合、上側電極８０の主導電層８２の第３層８４
、第２層８６および第１層８８を絶縁層７８側から形成
し、この主導電層８２の上側に補助導電層９０ヲ設ける
．そして、上側電極８０を被覆するように下地上従って
絶縁層７８上に別のＳ Ｉ Ｎ ｗ絶締層９２を保護膜
として設ける。Next, the wiring of a GaAs integrated circuit is formed using the composite conductive layer (T i / P t / A u
/Ti) and a conventional conductive layer without an auxiliary conductive layer (T i / P t / A u )
Long-term storage tests were conducted on GaAs integrated circuits with wiring configurations. In this test, the specimens were stored for over 1,000 hours in an atmosphere with a temperature of 85°C and a relative humidity of 85%. As a result, cracks appeared in the SiNx tight layer on the wiring with the usual conductive layer (T'i/Pt/Au) structure, but the composite conductive layer of the present invention (T'i/Pt/Au/T)
i) The SiNx insulation layer on the wiring of the structure did not crack. The experimental results revealed that the SINX insulating layer formed on the surface of gold (Au), which is extremely stable and has low chemical reactivity, has weak adhesion. On the other hand, on the composite conductive layer 22 of the present invention, a Ti layer (auxiliary conductive layer shown as 24 in FIG. 3) is provided on a gold (Au) layer (first layer shown as 32 in FIG. 3). I N x lol! ．． Marginal layer (28 in Figure 3)
), gold (Au) and titanium (Ti
) are metals, and interdiffusion begins to occur at low temperatures, so it is thought that the compatibility between the two becomes strong and the adhesion between the gold layer and the titanium layer increases. Also, when forming a SiNx tight layer on a titanium (Ti) layer, silane (SiN.
This ammonia reacts with titanium and the interface of the titanium layer becomes nitride, which is thought to increase the adhesion between the titanium layer and the 3 1N x insulating layer. ．． Therefore, it can be seen that this titanium layer 24 improves the adhesion between the lower gold layer 32 and the upper tightening layer 28 and prevents cracking and peeling of the insulating layer. Although an example is shown here using SiN,+ as the insulating films 28 and 42, even if it is S102, SiO. N.
It may be. As described above, if the composite conductive layer of the present invention is used for wiring etc., there is no risk of cracking or peeling of the insulating layer.
Wiring, etc. can be formed in a planar shape on the base. [Example of Capacitor] FIG. 6 is a sectional view showing an example of a capacitor using the composite conductive layer of the present invention as an upper electrode and a lower electrode. The planar shape of these electrodes can be square, etc. This example will be explained below. In this example, a composite conductive layer (T i /
This will be explained using an example of a capacitor using P t / A u / T i ) as the upper and lower electrodes. A main conductive layer 66 (third layer 68 from the base side,
A composite conductive layer consisting of a second layer 70, a first layer 72) and an auxiliary conductive layer 74 is provided as a lower electrode 76 having a suitable planar shape. Next, a base 6 is applied to cover this lower electrode 76.
4, a dielectric layer 78 is provided on the entire surface. As this dielectric layer 78, the SiNx insulation layer 28 provided in the embodiment shown in FIG.
An insulating layer similar to the above is provided with a thickness of, for example, 5000λ. Next, an upper electrode 80 having the same structure, shape, and area as the lower electrode 76 and an insulating layer 78 are sandwiched between the upper electrode 80 and the insulating layer 78 to face the lower electrode 76. I warn you. In this case, the third layer 84 of the main conductive layer 82 of the upper electrode 80
, a second layer 86 and a first layer 88 are formed from the insulating layer 78 side, and an auxiliary conductive layer 90 is provided above the main conductive layer 82. Then, another SINW insulation layer 92 is provided as a protective film on the base and thus on the insulating layer 78 so as to cover the upper electrode 80.
この実施例にキャパシタにおいて、容量を］○○ｐ「と
する場合には、５０００大の嘆厚のＳ ｘ Ｎ ｘの誘
電体層７８の比誘電率が７であるので、上下の各電極７
６および８０の平面形状は４００ｕｍｘ２ｍｍとなる．
このキャパシタにつき、前述と同様な長時間保管試験を
行って、従来通常のＴ ｉ ／ Ｐ ｔ ／ Ａ ｕ構
造の電極を用いたキャパシタとの比較を行ったところ、
この発明のキャパシタの場合には絶縁層７８および９２
には亀裂とか剥離が全く生じなかったが、従来構造のキ
ャパシタでは、対応する絶縁層に亀裂や剥離が生じた．
ここでは、キャパシタにつき説明したが、この発明の複
合導電層を、トランジスタやダイオードの電極、インダ
クタの線として用いても、絶縁層の亀裂とか剥離の発生
を確実に抑えることが出来る．
尚、上述した実施例では、複合導電膜を（Ｔｉ／ Ｐ
ｔ ／ Ａ ｕ ／ Ｔ ｉ ）構造としたが、これに
限定されるものではなく、第１図の実施例で説明した種
々の材料の組み合わせた構造とすることが出来る．また
、絶縁層６２、７８、９２もＳ ｉＮ ｘの代わりに、
Ｓ１０２やＳｉＯ．Ｎ．！用いるこども出来る．又、基
板６０として、ＧａＡｓ以外の他の化合物半導体材料や
シリコン材料を用いることが出来る．
［穴開け方法および配線接続の説明コ
次に、この発明の複合導電層の穴開け方法につき、第７
図（Ａ）〜（日）を参照して説明する．第７図（Ａ）〜
（Ｈ）は、下側の複合導電層に穴を開けて上側の複合導
電層との配線接続を形成するまでの工程を示す図である
．
先ず、この発明では、第一工程として、下地上にま導電
層および補助導電層を順次に或膜して複合導電層を設け
る．
このため、この実施例ではＧａＡｓ基板１００上にＳ
Ｉ Ｎ ｘ絶縁層１０２を３０００人の層厚で設けて下
地１０４ヲ形成する（第７図（Ａ））．この絶縛層１０
２は、シラン（ＳｉＨ４）とアンモニア（Ｎ目，）ガス
を用いた通常のプラズマＣｖＤ法で形成する．
次に、この下地１０４上にレジストを用いたホトリソ工
程で、下地１０４の、配線を形成予定領域のみｔｉ出す
るように、レジストパターン１０６ヲ形成し、第７図Ｃ
Ｂ）に示すような構造体を得る．次に、このレジストパ
ターン＋０６が形成ざれている構造体の上側全面に、通
常の真空蒸着法を用いて、主導電層１０８と補助導電層
１１０の複合導電層１２０を順次｛こ形戊する（第７図
（Ｃ））．この主導電層１０８として、下地１０４側か
ら、１０００人の膜厚のチタン（Ｔｉ）層（第３層）１
１２、１０００λの膜厚の白金（Ｐｔ）層（第２層）１
１４および５０００Ａの膜厚の金（Ａｕ）層（第１層）
１１６そ設けた後、補助導電層１１０を膜厚１００大の
チタン（Ｔｉ）層として形成する．続いて、通常のりフ
トオフ法によって、この構造体からレジストパターン１
０６ヲ剥離して下地１０４上（このみ複合導電層１２０
を下側配線として残存させる．
次に、第二二程として、中間（層間）ｗＡ縁膜兼保護膜
としてＳ ｘ Ｎ ｘ絶締層１２２を複合導電層１２０
を被覆するように下地１０４上に設け、第７図（Ｄ）に
示すような構造体を得る。この中間絶縁層１２２ヲ、通
常のプラズマＣｖＤ法により形成し、その膜厚を３ｏ○
０大とする。In this embodiment, if the capacitance of the capacitor is ○○p, the dielectric constant of the S x N x dielectric layer 78 with a thickness of 5000 is 7.
The planar shape of 6 and 80 is 400 um x 2 mm. This capacitor was subjected to a long-term storage test similar to the one described above, and compared with a conventional capacitor using electrodes with a normal Ti/Pt/Au structure.
In the case of the capacitor of this invention, insulating layers 78 and 92
No cracks or peeling occurred in the conventionally structured capacitor, but cracks and peeling occurred in the corresponding insulating layer. Although a capacitor has been described here, the composite conductive layer of the present invention can be used as an electrode for a transistor or a diode, or as a wire for an inductor, and can reliably suppress the occurrence of cracks or peeling of the insulating layer. In addition, in the above-mentioned embodiment, the composite conductive film is made of (Ti/P
t / A u / T i ) structure, but the present invention is not limited to this, and a structure combining various materials as explained in the embodiment of FIG. 1 can be used. Moreover, the insulating layers 62, 78, and 92 are also made of SiN x instead of
S102 and SiO. N. ! Children can use it. Further, as the substrate 60, other compound semiconductor materials or silicon materials other than GaAs can be used. [Explanation of hole-drilling method and wiring connection] Next, regarding the hole-drilling method of the composite conductive layer of the present invention, see the seventh section.
This will be explained with reference to Figures (A) to (Sun). Figure 7 (A) ~
(H) is a diagram showing the steps from making a hole in the lower composite conductive layer to forming a wiring connection with the upper composite conductive layer. First, in the present invention, as a first step, a conductive layer and an auxiliary conductive layer are sequentially formed on a base to form a composite conductive layer. Therefore, in this embodiment, S is placed on the GaAs substrate 100.
An I N x insulating layer 102 is provided to a thickness of 3000 to form a base 104 (FIG. 7(A)). This bondage layer 10
2 is formed by the usual plasma CvD method using silane (SiH4) and ammonia (N-th) gas. Next, a resist pattern 106 is formed on this base 104 by a photolithography process using a resist so that only the region of the base 104 where wiring is planned to be formed is exposed, as shown in FIG.
Obtain the structure shown in B). Next, a composite conductive layer 120 consisting of the main conductive layer 108 and the auxiliary conductive layer 110 is sequentially formed on the entire upper surface of the structure on which the resist pattern +06 is formed using a normal vacuum evaporation method. Figure 7 (C)). As this main conductive layer 108, from the base 104 side, a titanium (Ti) layer (third layer) 1 with a thickness of 1000
12. Platinum (Pt) layer (second layer) with a thickness of 1000λ 1
Gold (Au) layer (first layer) with a film thickness of 14 and 5000A
116, the auxiliary conductive layer 110 is formed as a titanium (Ti) layer with a thickness of 100 mm. Next, a resist pattern 1 is formed from this structure by a normal lift-off method.
06 is peeled off and placed on the base 104 (composite conductive layer 120
remains as the lower wiring. Next, as the second second step, the S x N
A structure as shown in FIG. 7(D) is obtained. This intermediate insulating layer 122 is formed by a normal plasma CVD method, and its film thickness is 3o○.
Set to 0 large.
次（こ、第三工程１こおいで、この絶縁層１２２および
補助導電層１１０の両者に共通して使用出来るエッチン
グ用ガスを用いて、この絶縁層１２２および補助導電層
１１０ヲ貫通する穴（コンタクトホール）を開ける．こ
のため、先ず、穴の位置に対応する絶縁層１２２の領域
を露出させるようなレジストパターン１２４を通常の方
法で適当な層厚で設ける（第７図（Ｅ））．このレジス
トパターン１２４は後述するエッチングの際のエッチン
グマスクとして作用し、このマスクの間に露出した絶縁
層１２２の領域を１２２ａで示す．
続いて、この絶縁層１２２と、複合導電層１２０を構成
する補助導電層１１０とをエッチング可能なエッチング
用ガスを用いて、両層１２２および１１０を、同一のエ
ッチング工程で、順次に連続エッチングする．このため
、第７図（Ｅ）に示す構造体を反応性イオンエッチング
（Ｒ 工Ｅ）装置の処理室内にセットし、六フッ化硫黄
（ＳＦｅ）のプラズマを用いてエッチングマスク１２４
の間に露出している絶縁層の領ｔｌｉｌ２２ａのエッチ
ングを行う．このエッチングにより、絶縁層１２２にコ
ンタクトホール用の穴１２６が開き、続いて、チタン（
Ｔｉ）の補助導電層１１０に穴１２８が開いて下側の第
１層１１６である金（Ａｕ）の層の表面が露出する．こ
れら両穴１２６と１２８とは互いに連通した穴であって
、コンタクトホール１３０ヲ構成する．このようにして
得られた構造体を第７図（「）に示す．
次に、このようにして形戒したコンタクトホール１３０
を用いて、上側配線と下側配線との配線接続を行う例を
説明する．
そのため、第７図ＣＦ）で得られた構造体の上側表面に
、この発明の複合導電層で、上側配線１４０をバターニ
ングして形成し、第７図（Ｇ）に示す構造体を得る．こ
の上側配線１４０を好ましくは下側配線１２０と同様の
材料で、同じ構造に形成する．従って、この上側配線１
４０は主導電層１４２と補助導電層１４４とを具え、こ
れらの層を下側配線１２０の形戊の場合と同様に、ホト
リソ工程、真空蒸着工程、リフトオフ工程等の所要の工
程を用いて形成する．その結果、コンタクトホール１３
０内において、上側配線１４０の主導電層１４２のチタ
ン（Ｔｉ）の第３層１４６が下側配線１２０の金（Ａｕ
）の第１層１１６と接触し、その上側に白金（Ｐｔ）の
第２層１４８、ざらにその上側に金（Ａｕ）の第１層１
５０、ざらにその上側にチタン（Ｔｉ）の補助導電層１
４４が形戊ざれた状態となっている．
そして、最終的に、この上側配線１４０を被覆するよう
に絶縁層１２２の全面に保護層となるべき別のＳｉＮｘ
等の適当なｗ！．縁層１５２を、プラズマＣｖＤ法によ
って、層厚３０００大で、設ける（第７図（目））。Next, in the third step 1, a hole (contact For this purpose, first, a resist pattern 124 is formed with an appropriate layer thickness using a normal method to expose the region of the insulating layer 122 corresponding to the hole position (FIG. 7(E)). The resist pattern 124 acts as an etching mask during etching to be described later, and the area of the insulating layer 122 exposed between this mask is indicated by 122a. Using an etching gas capable of etching the conductive layer 110, both layers 122 and 110 are successively etched in the same etching process.For this purpose, the structure shown in FIG. The etching mask 124 is set in the processing chamber of an ion etching (R Engineering) device and uses sulfur hexafluoride (SFe) plasma.
During etching, the exposed area 22a of the insulating layer is etched. This etching opens a hole 126 for a contact hole in the insulating layer 122, and then titanium (
A hole 128 is opened in the auxiliary conductive layer 110 (Ti) to expose the surface of the gold (Au) layer that is the first layer 116 below. These holes 126 and 128 communicate with each other and constitute a contact hole 130. The structure thus obtained is shown in FIG. 7 ( ). Next, the contact hole 130 shaped in this way
We will explain an example of wiring connection between the upper wiring and the lower wiring using . Therefore, on the upper surface of the structure obtained in FIG. 7(CF), an upper wiring 140 is formed using the composite conductive layer of the present invention by patterning to obtain the structure shown in FIG. 7(G). The upper wiring 140 is preferably made of the same material as the lower wiring 120 and has the same structure. Therefore, this upper wiring 1
40 includes a main conductive layer 142 and an auxiliary conductive layer 144, and these layers are formed using a required process such as a photolithography process, a vacuum evaporation process, a lift-off process, etc., as in the case of forming the lower wiring 120. do. As a result, contact hole 13
0, the third layer 146 of titanium (Ti) of the main conductive layer 142 of the upper wiring 140 is made of gold (Au) of the lower wiring 120.
), with a second layer 148 of platinum (Pt) on top thereof, and a first layer 148 of gold (Au) roughly above it.
50, auxiliary conductive layer 1 of titanium (Ti) roughly above it
44 is in a deformed state. Finally, another layer of SiNx to serve as a protective layer is applied to the entire surface of the insulating layer 122 so as to cover the upper wiring 140.
Etc. and other appropriate lol! ．． An edge layer 152 is provided with a layer thickness of 3000 mm by plasma CVD method (FIG. 7 (eye)).
上述した実施例で、下側配線１２０の第１層の金層１１
６と、上側配線１４０の第３層のチタン層１４６とがコ
ンタクトホール１３０内で接触するが、そのコンタクト
抵抗は５Ｘ１０−１０Ω・ｃｍ程度という小ざな値とな
る．また、このコンタクトボール１３０を絶縁層１２２
の穴とチタンの補助導電層Ｎｏとの穴との連通孔として
構威しているが、コンタクトホールのエッチング時にチ
タンの層＋＋ａ部分を除去しないで絶縁層１２２の穴の
みでコンタクトホールを形成してコンタクト抵抗を形戊
する場合には、上述したコンタクト抵抗よりも１桁以上
大きな、バラッキの大きい値となってしまうというＩｌ
！害が生じる。これは、残存するチタン層の表面が極め
て酸化ざれ易く、かつ、汚染を受け易いことに起因して
いると考えられる．
上述した実施例では、下側配線１２０と上側配線１４０
の配線接続をコンタクトホール１３０を介して行った場
合につき説明したが、このコンタクトホール１３０と同
様にして、絶縁層１２２および下側配線１２０の補助導
電層１１０に開口部（図示していない）を設けて、この
開口部に露出した金（Ａｕ）層１１６に金（Ａｕ）線の
ワイヤボンディングあるいは半田付けを直接行ってこの
配線１２０と外部回路または外部素子とを容易かつ確実
に接続することも出来る。これに対し、開口部の補助導
電層であるチタンを除去しないと、チタン層に直接ボン
ディングを行うこととなり、従って、金線が簡単に外れ
てしまうという障害が生ずる。In the embodiment described above, the first gold layer 11 of the lower wiring 120
6 and the third titanium layer 146 of the upper wiring 140 are in contact within the contact hole 130, but the contact resistance is a small value of about 5×10 −10 Ω·cm. Further, this contact ball 130 is connected to the insulating layer 122.
The hole is used as a communication hole between the hole in the titanium auxiliary conductive layer No., but when etching the contact hole, the titanium layer ++a portion is not removed and the contact hole is formed only with the hole in the insulating layer 122. When the contact resistance is shaped by
! Harm occurs. This is thought to be due to the fact that the surface of the remaining titanium layer is extremely susceptible to oxidation and contamination. In the embodiment described above, the lower wiring 120 and the upper wiring 140
Although the case where the wiring connection is made through the contact hole 130 has been described, similarly to the contact hole 130, an opening (not shown) is formed in the insulating layer 122 and the auxiliary conductive layer 110 of the lower wiring 120. It is also possible to wire bond or solder a gold (Au) wire directly to the gold (Au) layer 116 exposed in this opening to easily and reliably connect this wiring 120 to an external circuit or an external element. I can do it. On the other hand, if the titanium that is the auxiliary conductive layer in the opening is not removed, bonding will be performed directly to the titanium layer, resulting in the problem that the gold wire will easily come off.
上述した実施例では、各配線層１２０および＋４０ｉＦ
ｒ Ｔ ｉ ／ Ｐ ｔ ／ Ａ ｕ ／ Ｔ ｉの４
層構造としているが、最上層である補助導電層１１０ヲ
チタンの代わりにシリコン（Ｓｉ）あるいはゲルマニ゜
ウム（Ｇｅ）はもとより、チタン、シリコンおよびゲル
マニウムの群のなかから選らばれたいずれが一種以上の
材料を含む層を使用することが出来る．また、絶縁層１
２２としてＳｉＮ．の代わり｛こＳ１０２やＳ１０ｘＮ
ｘあるいはその他のシリコンの酸化物またはシリコンの
窒化物を使用することが出来る．その場合に、これら絶
縁層１２２および補助導電層１１０に共通のエッチング
用ガスとしてフッ化物系ガス、例えば、ＣＦ， 、０２
Ｆ．、Ｃ３Ｆｌｌ、Ｃ日Ｆ３、ＳＦ８等を使用すること
が出来ると共に、これらガスの一種以上と０２ガスおよ
びまたはＨｅガスとの混合ガスを使用することが出来る
。In the embodiment described above, each wiring layer 120 and +40iF
4 of r T i / P t / A u / T i
However, the uppermost auxiliary conductive layer 110 is made of silicon (Si) or germanium (Ge), as well as one or more selected from the group of titanium, silicon, and germanium, instead of titanium. You can use layers containing materials. In addition, insulating layer 1
22 as SiN. instead of {this S102 or S10xN
x or other silicon oxides or silicon nitrides can be used. In that case, a fluoride-based gas, such as CF, 02
F. , C3Fll, C, F3, SF8, etc. can be used, and a mixed gas of one or more of these gases with 02 gas and/or He gas can be used.
また、上述した種々の絶縁層２８、４２、１０２、＋２
２ 、＋５２としてポリイミド材料を用いることが出来
る．このポリイミドを中周絶締層１２２として使用して
、これに穴を開ける場合には、この層１２２ヲ０２プラ
ズマでエッチングする。そして、チタン層１１０に対し
ては、ガスを切り変えてＳＦ．プラズマでエッチングす
る方法であっても良い．
このように、この発明の複合導電層は、主導電層および
補助導電層とを具え、この補助導電層でこの主導電層と
絶縁層との密着性を向上させる構造となっている，そし
て、この複合導電層を各種半導体デバイスの配線、電極
、インダクタの線およびまたはキャパシタの電極に用い
、その上側に保護層としての絶縁層あるい｛よ中間絶締
層を設けた場合に、所要に応じてこれら絶縁層および補
助導電層にコンタクトホールとかポンデイングのための
開口部とかを設ける必要が生しる．その場合、この発明
によれば、これら絶縁層と補助導電層とを同一のエッチ
ング用ガスで同一のエッチング工程でエッチングしてこ
れらコンタクトホ〜ルヤ開口部を形戊することが出来る
。In addition, the various insulating layers 28, 42, 102, +2 described above
2, a polyimide material can be used as +52. When this polyimide is used as the middle circumferential insulation layer 122 and a hole is to be formed in it, this layer 122 is etched with 02 plasma. Then, for the titanium layer 110, the gas is changed and the SF. A method of etching using plasma may also be used. As described above, the composite conductive layer of the present invention includes a main conductive layer and an auxiliary conductive layer, and has a structure in which the auxiliary conductive layer improves the adhesion between the main conductive layer and the insulating layer, and When this composite conductive layer is used for wiring, electrodes, inductor lines, and/or capacitor electrodes of various semiconductor devices, and an insulating layer as a protective layer or an intermediate insulation layer is provided on the upper side, it can be used as required. Therefore, it becomes necessary to provide contact holes and openings for ponding in these insulating layers and auxiliary conductive layers. In this case, according to the present invention, these contact hole openings can be formed by etching the insulating layer and the auxiliary conductive layer in the same etching process using the same etching gas.
（発明の効果）
上述した説明からも明らかなように、この発明の複合導
電層によれば、主導電層を構戊する低抵抗の金属層上に
、絶縁層との密着性を向上させる材料の補助導電層を設
けた構造としたので、この複合導電層の上側に設けた保
護膜としての絶縁層あるいは中間絶縁層等に亀裂や剥離
が生しるのを効果的に防止出来る。(Effects of the Invention) As is clear from the above description, according to the composite conductive layer of the present invention, a material that improves the adhesion with the insulating layer is placed on the low-resistance metal layer constituting the main conductive layer. Since the structure includes the auxiliary conductive layer, it is possible to effectively prevent cracks or peeling from occurring in the insulating layer or intermediate insulating layer, etc. as a protective film provided on the upper side of the composite conductive layer.
従って、この複合導電層を半導体装置の電極、配線、イ
ンダクタの線およびまたはキャパシタの電極に用いで構
成すれば、半導体装置の信頼性が従来よりも著しく向上
するという利点がある．ざら（こ、この発明の複合導電
層を用いて配線および電極を形成すれば、それらの平面
的形状を、任意好適なしかも大面積の形状とすることが
出来る利点がある。Therefore, if this composite conductive layer is used for the electrodes, wiring, inductor lines, and/or capacitor electrodes of a semiconductor device, there is an advantage that the reliability of the semiconductor device is significantly improved compared to the conventional method. If wiring and electrodes are formed using the composite conductive layer of the present invention, there is an advantage that the planar shape thereof can be any suitable shape and can have a large area.
ざらに、この発明の複合導電層の穴開け方法によれば、
この複合導電層の主導電層を構成する低抵抗の金属層上
に形成ざれている、絶縁層との密着性を向上させる補助
導電層を、この絶締層の穴開けと同一のエッチング工程
で連続的に、穴開けしてしまうので、穴開けのエッチン
グ工程が複雑とならず、しかも、このエッチング工程で
穴（コンタクトホールとか開口部）に低抵抗の金属層が
露出して、その露出面に直接他の配線等との電気的接続
や、金線等のワイヤボンディングあるいは半田付け等を
行って、低抵抗コンタクトで再現性のある接続、あるい
は、金線等の外れのの生じない接続を形成することが出
来る。Roughly speaking, according to the method of drilling a hole in a composite conductive layer of the present invention,
The auxiliary conductive layer, which is formed on the low-resistance metal layer that constitutes the main conductive layer of this composite conductive layer and which improves the adhesion with the insulating layer, is formed in the same etching process as the hole-drilling of this tight layer. Since the holes are continuously drilled, the etching process for making the holes is not complicated, and the low-resistance metal layer is exposed in the hole (contact hole or opening) during this etching process, and the exposed surface is Make direct electrical connections with other wiring, etc., wire bonding or soldering of gold wires, etc. to make reproducible connections with low resistance contacts, or connections that do not cause disconnection of gold wires, etc. can be formed.
第１図は、この発明の半導体装置用の複合導電層の基本
構造を断面で概略的に示す説明図、第２図は、従来の導
電層の構造を部分的に断面で概略的に示す説明図、
第３図〜第５図は、この発明の半導体装置用の複合導電
層の具体的構成例を断面でそれぞれ概略的に示す図、
第６図は、この発明の複合導電層をキャパシタの電極に
用いた構成例を断面で概略的に示す図、第７図（Ａ）〜
（日）は、この発明の複合導電層の穴開け方法を説明す
るため、下側および上側の複合導電層との配線接続を形
成するまでの工程を代表して示す工程図である。
２０・・・複合導電層
２２、６６、８２、＋０８ 、＋４２・・・主導電層２
４、７４、９０、１１０、１４４・・・補助導電層２６
、６４、１０４・・・下地、 ４０、６０、１００・・
・基板２８、４２、６２、７８、９２、＋０２ ． １
２２ ， １５２・・・絶縁層３２、７２、８８、１１
６、１５０・・・第１層３４、７０、８６、Ｎ４ 、＋
４８・・・第２層３６、６Ｂ、８４、１１２ 、＋４６
・・・第３層７６・・・下側電極（複合導電層）
８０・・・上側電極（複合導電層）
＋０６ 、＋２４・・・レジス１−パターン＋２０・・
・下側配線（複合導電層）
１４０・・・上側配線（複合導電層）
１２２ａ・・・露出領域、 １２６、１３０・・・
コンタクトホール。
１２８
０゜０ノｋ
特
許
出
願
人
沖電気工業株式会社
２０：複合導電層
２２：主導電層
２４：補助導電層
２６：下地
２８・絶縁層
この発明の説明図
第１
図
従来技術の説明図
第２
図
３２第１層 ３４第２層
３６ 第３層 ４０ 基板
４２ 絶緑層
主導電層が３層構造の例
第３図
主導電層が２層構造の例
第４図
主導電層が１層構造の例
１４０上側配線（複合導電層）
１４４．補助導電層
１４８：Ｍ２層
１４２主導電層
１４６第３層
１５０：Ｍｌ層
工程図
第７図（Ｇ）
−１６８−
一１飄
レ一
ｃＳＪｏ
ロ ０FIG. 1 is an explanatory diagram schematically showing, in cross section, the basic structure of a composite conductive layer for a semiconductor device according to the present invention, and FIG. 2 is an explanatory diagram, partially in cross section, schematically showing the structure of a conventional conductive layer. 3 to 5 are diagrams each schematically showing a specific configuration example of a composite conductive layer for a semiconductor device of the present invention in cross section, and FIG. 6 is a diagram showing a composite conductive layer of the present invention for a capacitor. Diagrams schematically showing cross-sections of configuration examples used for electrodes, Figures 7(A)-
(Japanese) is a process diagram representatively showing the steps up to forming wiring connections with the lower and upper composite conductive layers in order to explain the method of drilling holes in the composite conductive layer of the present invention. 20... Composite conductive layer 22, 66, 82, +08, +42... Main conductive layer 2
4, 74, 90, 110, 144...auxiliary conductive layer 26
, 64, 104... base, 40, 60, 100...
- Substrates 28, 42, 62, 78, 92, +02. 1
22, 152...Insulating layer 32, 72, 88, 11
6, 150...first layer 34, 70, 86, N4, +
48...Second layer 36, 6B, 84, 112, +46
...Third layer 76...Lower electrode (composite conductive layer) 80...Upper electrode (composite conductive layer) +06, +24...Resist 1-pattern +20...
- Lower wiring (composite conductive layer) 140... Upper wiring (composite conductive layer) 122a... exposed area, 126, 130...
contact hole. 128 0゜0nok Patent applicant Oki Electric Industry Co., Ltd. 20: Composite conductive layer 22: Main conductive layer 24: Auxiliary conductive layer 26: Underlayer 28/insulating layer 2 Figure 32 1st layer 34 2nd layer 36 3rd layer 40 Substrate 42 Fast green layer An example of a three-layer structure for the main conductive layer Figure 3 An example of a two-layer structure for the main conductive layer Figure 4 An example of a two-layer structure for the main conductive layer Structure example 140 Upper wiring (composite conductive layer) 144. Auxiliary conductive layer 148: M2 layer 142 Main conductive layer 146 Third layer 150: Ml layer Process diagram Figure 7 (G) -168-
Claims (7)
構成した主導電層と、 該主導電層の上面に設けた補助導電層と を具え、 該補助導電層は、該補助導電層の上面に設けられる絶縁
層および該補助導電層の下面に設けられた前記主導電層
に対し密着の強化を図る、電気抵抗の小さい材料で構成
してなる ことを特徴とする半導体装置の複合導電層。(1) A main conductive layer composed of one or more layers made of a substance with low electrical resistance, and an auxiliary conductive layer provided on the upper surface of the main conductive layer, the auxiliary conductive layer being the auxiliary conductive layer. Composite conductivity of a semiconductor device, characterized in that the semiconductor device is made of a material with low electrical resistance, and is made of a material with low electrical resistance to strengthen adhesion to the insulating layer provided on the upper surface and the main conductive layer provided on the lower surface of the auxiliary conductive layer. layer.
て、前記補助導電層の膜厚を、最大でも２００Å程度と
することを特徴とする半導体装置の複合導電層。(2) The composite conductive layer for a semiconductor device according to claim 1, wherein the auxiliary conductive layer has a thickness of about 200 Å at most.
て、前記補助導電層を、チタン、シリコンおよびゲルマ
ニウムの群のなかから選らばれたいずれか一種以上の材
料を含む層としたことを特徴とする半導体装置の複合導
電層。(3) In the composite conductive layer of the semiconductor device according to claim 1, the auxiliary conductive layer is a layer containing one or more materials selected from the group of titanium, silicon, and germanium. Composite conductive layer for semiconductor devices.
て、前記主導電層を前記補助導電層側から第１層、第２
層および第３層を順次に具えた３層構造とし、 該第１層を、金、白金、アルミニウムおよび銅の群のな
かから選らばれたいずれか一種以上の材料を含む層とし
、 該第２層を、白金、タングステンおよびモリブデンの群
のなかから選らばれたいずれか一種以上の材料を含む層
とし、 該第３層を、チタン、シリコンおよびゲルマニウムの群
のなかから選らばれたいずれか一種以上の材料を含む層
とした ことを特徴とする半導体装置の複合導電層。(4) In the composite conductive layer of the semiconductor device according to claim 1, the main conductive layer is divided into a first layer, a second layer from the auxiliary conductive layer side.
A three-layer structure including a layer and a third layer in sequence, the first layer containing one or more materials selected from the group of gold, platinum, aluminum and copper, and the second layer The third layer is a layer containing one or more materials selected from the group of platinum, tungsten, and molybdenum, and the third layer is a layer containing one or more materials selected from the group of titanium, silicon, and germanium. 1. A composite conductive layer for a semiconductor device, characterized in that the layer includes a material.
極層を形成し、これら下側および上側電極層間に誘電体
層を設けてなる ことを特徴とする半導体装置のキャパシタ。(5) A capacitor for a semiconductor device, characterized in that lower and upper electrode layers are formed of the composite conductive layer according to claim 1, and a dielectric layer is provided between these lower and upper electrode layers.
して請求項１の複合導電層を設ける第一工程と、 該複合導電層を被覆する絶縁層を設ける第二工程と、 該絶縁層および前記補助導電層の両者に共通して使用出
来るエッチング用ガスを用いて、該絶縁層および前記補
助導電層を貫通する穴を開ける第三工程と を含むことを特徴とする半導体装置の複合導電層の穴開
け方法。(6) a first step of sequentially forming a conductive layer and an auxiliary conductive layer on a base to form the composite conductive layer of claim 1; a second step of providing an insulating layer covering the composite conductive layer; A semiconductor device comprising: a third step of making a hole penetrating the insulating layer and the auxiliary conductive layer using an etching gas that can be commonly used for both the insulating layer and the auxiliary conductive layer. How to drill holes in a composite conductive layer.
物とし、および補助導電層を、チタン、シリコンおよび
ゲルマニウムの群のなかから選らばれたいずれか一種以
上の材料を含む層とした場合には、エッチング用ガスを
フッ化物系ガスとしたことを特徴とする請求項６記載の
半導体装置の複合導電層の穴開け方法。(7) When the insulating layer is made of silicon oxide or silicon nitride, and the auxiliary conductive layer is a layer containing one or more materials selected from the group of titanium, silicon, and germanium, 7. The method of making holes in a composite conductive layer of a semiconductor device according to claim 6, wherein the etching gas is a fluoride gas.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP19083089A JPH0354828A (en) | 1989-07-24 | 1989-07-24 | Compound conductor layer of semiconductor device, hole-making process of capacitor using compound conductor layer and compound conductor layer |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP19083089A JPH0354828A (en) | 1989-07-24 | 1989-07-24 | Compound conductor layer of semiconductor device, hole-making process of capacitor using compound conductor layer and compound conductor layer |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0354828A true JPH0354828A (en) | 1991-03-08 |
Family
ID=16264475
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP19083089A Pending JPH0354828A (en) | 1989-07-24 | 1989-07-24 | Compound conductor layer of semiconductor device, hole-making process of capacitor using compound conductor layer and compound conductor layer |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0354828A (en) |
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH03110862A (en) * | 1989-09-26 | 1991-05-10 | Nec Corp | Semiconductor storage element |
| JPH04221848A (en) * | 1990-03-16 | 1992-08-12 | Philips Gloeilampenfab:Nv | Manufacture of semiconductor device |
| JPH0669362A (en) * | 1992-05-22 | 1994-03-11 | Nec Corp | Semiconductor device |
| KR100301644B1 (en) * | 1997-04-08 | 2001-10-19 | 포만 제프리 엘 | Interconnects using metal spacers and method for forming same |
| JP2004533106A (en) * | 2000-10-05 | 2004-10-28 | モトローラ・インコーポレイテッド | Semiconductor component manufacturing method and semiconductor component |
| GB2426382A (en) * | 2002-11-26 | 2006-11-22 | Gen Electric | Three-layer compound electrode for organic electronic devices |
| JP2007173437A (en) * | 2005-12-21 | 2007-07-05 | Fujitsu Ltd | Electronic component |
-
1989
- 1989-07-24 JP JP19083089A patent/JPH0354828A/en active Pending
Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH03110862A (en) * | 1989-09-26 | 1991-05-10 | Nec Corp | Semiconductor storage element |
| JPH04221848A (en) * | 1990-03-16 | 1992-08-12 | Philips Gloeilampenfab:Nv | Manufacture of semiconductor device |
| JPH0669362A (en) * | 1992-05-22 | 1994-03-11 | Nec Corp | Semiconductor device |
| KR100301644B1 (en) * | 1997-04-08 | 2001-10-19 | 포만 제프리 엘 | Interconnects using metal spacers and method for forming same |
| JP2004533106A (en) * | 2000-10-05 | 2004-10-28 | モトローラ・インコーポレイテッド | Semiconductor component manufacturing method and semiconductor component |
| GB2426382A (en) * | 2002-11-26 | 2006-11-22 | Gen Electric | Three-layer compound electrode for organic electronic devices |
| GB2426382B (en) * | 2002-11-26 | 2007-07-04 | Gen Electric | Electrodes mitigating effcts of defects in organic electronic devices |
| US7368659B2 (en) | 2002-11-26 | 2008-05-06 | General Electric Company | Electrodes mitigating effects of defects in organic electronic devices |
| JP2007173437A (en) * | 2005-12-21 | 2007-07-05 | Fujitsu Ltd | Electronic component |
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