TW355817B - Process for reducing pattern factor effects in CMP planarization - Google Patents

Process for reducing pattern factor effects in CMP planarization

Info

Publication number
TW355817B
TW355817B TW086115532A TW86115532A TW355817B TW 355817 B TW355817 B TW 355817B TW 086115532 A TW086115532 A TW 086115532A TW 86115532 A TW86115532 A TW 86115532A TW 355817 B TW355817 B TW 355817B
Authority
TW
Taiwan
Prior art keywords
planarized
pattern
cmp
pattern factor
layer
Prior art date
Application number
TW086115532A
Other languages
English (en)
Inventor
Nancy Anne Greco
Stephen Edward Greco
Original Assignee
Ibm
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ibm filed Critical Ibm
Application granted granted Critical
Publication of TW355817B publication Critical patent/TW355817B/zh

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/31051—Planarisation of the insulating layers
    • H01L21/31053—Planarisation of the insulating layers involving a dielectric removal step
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/304—Mechanical treatment, e.g. grinding, polishing, cutting

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Mechanical Treatment Of Semiconductor (AREA)
TW086115532A 1996-10-24 1997-10-21 Process for reducing pattern factor effects in CMP planarization TW355817B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US08/738,506 US5928960A (en) 1996-10-24 1996-10-24 Process for reducing pattern factor effects in CMP planarization

Publications (1)

Publication Number Publication Date
TW355817B true TW355817B (en) 1999-04-11

Family

ID=24968304

Family Applications (1)

Application Number Title Priority Date Filing Date
TW086115532A TW355817B (en) 1996-10-24 1997-10-21 Process for reducing pattern factor effects in CMP planarization

Country Status (4)

Country Link
US (1) US5928960A (zh)
JP (1) JP3297359B2 (zh)
KR (1) KR100268210B1 (zh)
TW (1) TW355817B (zh)

Families Citing this family (25)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3660799B2 (ja) * 1997-09-08 2005-06-15 株式会社ルネサステクノロジ 半導体集積回路装置の製造方法
US5946567A (en) * 1998-03-20 1999-08-31 Taiwan Semiconductor Manufacturing Company, Ltd. Method for making metal capacitors for deep submicrometer processes for semiconductor integrated circuits
TW498440B (en) 1998-03-30 2002-08-11 Hitachi Ltd Manufacture method of semiconductor device
US6017780A (en) * 1998-07-06 2000-01-25 Chartered Semiconductor Manufacturing, Ltd. Passivation scheme for LCD and other applications
US6107186A (en) * 1999-01-27 2000-08-22 Advanced Micro Devices, Inc. High planarity high-density in-laid metallization patterns by damascene-CMP processing
TW410377B (en) * 1999-06-17 2000-11-01 Taiwan Semiconductor Mfg Method of planarization and the apparatus of the same
JP2001044272A (ja) * 1999-07-27 2001-02-16 Matsushita Electronics Industry Corp 半導体装置の製造方法
US7049246B1 (en) * 2000-05-19 2006-05-23 Newport Fab, Llc Method for selective fabrication of high capacitance density areas in a low dielectric constant material
US7125809B1 (en) 2000-08-31 2006-10-24 Micron Technology, Inc. Method and material for removing etch residue from high aspect ratio contact surfaces
US6500755B2 (en) * 2000-12-06 2002-12-31 Advanced Micro Devices, Inc. Resist trim process to define small openings in dielectric layers
KR20020050480A (ko) * 2000-12-21 2002-06-27 박종섭 반도체소자의 평탄화 방법
US6395636B1 (en) 2001-01-09 2002-05-28 Honeywell International Inc. Methods for improved planarization post CMP processing
DE10208166B4 (de) * 2002-02-26 2006-12-14 Advanced Micro Devices, Inc., Sunnyvale Verfahren zur Herstellung von Metallleitungen mit verbesserter Gleichförmigkeit auf einem Substrat
DE10240423B4 (de) * 2002-09-02 2007-02-22 Advanced Micro Devices, Inc., Sunnyvale Halbleiterelement mit einem Feldeffekttransistor und einem passiven Kondensator mit reduziertem Leckstrom und einer verbesserten Kapazität pro Einheitsfläche und Verfahren zu dessen Herstellung
US6703318B1 (en) * 2002-10-29 2004-03-09 Silicon Storage Technology, Inc. Method of planarizing a semiconductor die
US7148525B2 (en) * 2004-01-12 2006-12-12 Micron Technology, Inc. Using high-k dielectrics in isolation structures method, pixel and imager device
JP4449076B2 (ja) * 2004-04-16 2010-04-14 セイコーエプソン株式会社 半導体装置の製造方法
US7368302B2 (en) * 2005-04-28 2008-05-06 International Business Machines Corporation Dynamic metal fill for correcting non-planar region
KR100734305B1 (ko) * 2006-01-17 2007-07-02 삼성전자주식회사 디싱 현상 없이 평탄화된 막을 구비하는 반도체 소자의제조방법 및 그에 의해 제조된 반도체 소자
US7929269B2 (en) * 2008-09-04 2011-04-19 Momentive Performance Materials Inc. Wafer processing apparatus having a tunable electrical resistivity
US8557649B2 (en) 2011-10-21 2013-10-15 International Business Machines Corporation Method for controlling structure height
CN103854965B (zh) * 2012-11-30 2017-03-01 中国科学院微电子研究所 平坦化处理方法
US9373524B2 (en) 2014-04-23 2016-06-21 International Business Machines Corporation Die level chemical mechanical polishing
US9773682B1 (en) 2016-07-05 2017-09-26 United Microelectronics Corp. Method of planarizing substrate surface
US9991133B2 (en) * 2016-08-11 2018-06-05 Tokyo Electron Limited Method for etch-based planarization of a substrate

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4007103A (en) * 1975-10-14 1977-02-08 Ibm Corporation Planarizing insulative layers by resputtering
US5104828A (en) * 1990-03-01 1992-04-14 Intel Corporation Method of planarizing a dielectric formed over a semiconductor substrate
US5139608A (en) * 1991-04-01 1992-08-18 Motorola, Inc. Method of planarizing a semiconductor device surface
US5384483A (en) * 1992-02-28 1995-01-24 Sgs-Thomson Microelectronics, Inc. Planarizing glass layer spaced from via holes
US5328553A (en) * 1993-02-02 1994-07-12 Motorola Inc. Method for fabricating a semiconductor device having a planar surface
US5310626A (en) * 1993-03-01 1994-05-10 Motorola, Inc. Method for forming a patterned layer using dielectric materials as a light-sensitive material
JPH0745616A (ja) * 1993-07-29 1995-02-14 Nec Corp 半導体装置の製造方法
US5332467A (en) * 1993-09-20 1994-07-26 Industrial Technology Research Institute Chemical/mechanical polishing for ULSI planarization
US5395801A (en) * 1993-09-29 1995-03-07 Micron Semiconductor, Inc. Chemical-mechanical polishing processes of planarizing insulating layers
US5580826A (en) * 1993-11-17 1996-12-03 Nec Corporation Process for forming a planarized interlayer insulating film in a semiconductor device using a periodic resist pattern
US5663107A (en) * 1994-12-22 1997-09-02 Siemens Aktiengesellschaft Global planarization using self aligned polishing or spacer technique and isotropic etch process

Also Published As

Publication number Publication date
JPH10135211A (ja) 1998-05-22
JP3297359B2 (ja) 2002-07-02
KR100268210B1 (ko) 2000-10-16
US5928960A (en) 1999-07-27
KR19980032308A (ko) 1998-07-25

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