TW334544B - Data processor - Google Patents

Data processor

Info

Publication number
TW334544B
TW334544B TW086100225A TW86100225A TW334544B TW 334544 B TW334544 B TW 334544B TW 086100225 A TW086100225 A TW 086100225A TW 86100225 A TW86100225 A TW 86100225A TW 334544 B TW334544 B TW 334544B
Authority
TW
Taiwan
Prior art keywords
vliw
instructions
risc
instruction
execution
Prior art date
Application number
TW086100225A
Other languages
English (en)
Inventor
Junichi Nishimoto
Hideo Maejima
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Application granted granted Critical
Publication of TW334544B publication Critical patent/TW334544B/zh

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3818—Decoding for concurrent execution
    • G06F9/3822—Parallel decoding, e.g. parallel decode units
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30145—Instruction analysis, e.g. decoding, instruction word fields
    • G06F9/30149—Instruction analysis, e.g. decoding, instruction word fields of variable length instructions
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30181—Instruction operation extension or modification
    • G06F9/30196—Instruction operation extension or modification using decoder, e.g. decoder per instruction set, adaptable or programmable decoders
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3854—Instruction completion, e.g. retiring, committing or graduating
    • G06F9/3858—Result writeback, i.e. updating the architectural state or memory
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3861—Recovery, e.g. branch miss-prediction, exception handling
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3877—Concurrent instruction execution, e.g. pipeline or look ahead using a slave processor, e.g. coprocessor
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3885—Concurrent instruction execution, e.g. pipeline or look ahead using a plurality of independent parallel functional units

Landscapes

  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Advance Control (AREA)
  • Executing Machine-Instructions (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
TW086100225A 1996-01-31 1997-01-10 Data processor TW334544B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP01501696A JP3623840B2 (ja) 1996-01-31 1996-01-31 データ処理装置及びマイクロプロセッサ

Publications (1)

Publication Number Publication Date
TW334544B true TW334544B (en) 1998-06-21

Family

ID=11877080

Family Applications (1)

Application Number Title Priority Date Filing Date
TW086100225A TW334544B (en) 1996-01-31 1997-01-10 Data processor

Country Status (4)

Country Link
US (3) US6023757A (zh)
JP (1) JP3623840B2 (zh)
KR (1) KR100535852B1 (zh)
TW (1) TW334544B (zh)

Families Citing this family (117)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3623840B2 (ja) 1996-01-31 2005-02-23 株式会社ルネサステクノロジ データ処理装置及びマイクロプロセッサ
US6786420B1 (en) 1997-07-15 2004-09-07 Silverbrook Research Pty. Ltd. Data distribution mechanism in the form of ink dots on cards
US6803989B2 (en) * 1997-07-15 2004-10-12 Silverbrook Research Pty Ltd Image printing apparatus including a microcontroller
US6618117B2 (en) 1997-07-12 2003-09-09 Silverbrook Research Pty Ltd Image sensing apparatus including a microcontroller
US6879341B1 (en) 1997-07-15 2005-04-12 Silverbrook Research Pty Ltd Digital camera system containing a VLIW vector processor
US7110024B1 (en) 1997-07-15 2006-09-19 Silverbrook Research Pty Ltd Digital camera system having motion deblurring means
US6985207B2 (en) * 1997-07-15 2006-01-10 Silverbrook Research Pty Ltd Photographic prints having magnetically recordable media
US6690419B1 (en) 1997-07-15 2004-02-10 Silverbrook Research Pty Ltd Utilising eye detection methods for image processing in a digital image camera
AUPO850597A0 (en) 1997-08-11 1997-09-04 Silverbrook Research Pty Ltd Image processing method and apparatus (art01a)
US20040119829A1 (en) 1997-07-15 2004-06-24 Silverbrook Research Pty Ltd Printhead assembly for a print on demand digital camera system
US6624848B1 (en) 1997-07-15 2003-09-23 Silverbrook Research Pty Ltd Cascading image modification using multiple digital cameras incorporating image processing
AUPO802797A0 (en) * 1997-07-15 1997-08-07 Silverbrook Research Pty Ltd Image processing method and apparatus (ART54)
JP3414209B2 (ja) * 1997-07-30 2003-06-09 松下電器産業株式会社 プロセッサ
US6216223B1 (en) * 1998-01-12 2001-04-10 Billions Of Operations Per Second, Inc. Methods and apparatus to dynamically reconfigure the instruction pipeline of an indirect very long instruction word scalable processor
US6219776B1 (en) * 1998-03-10 2001-04-17 Billions Of Operations Per Second Merged array controller and processing element
JP3541669B2 (ja) * 1998-03-30 2004-07-14 松下電器産業株式会社 演算処理装置
JPH11306084A (ja) * 1998-04-23 1999-11-05 Fujitsu Ltd 情報処理装置及び記憶媒体
AUPP702098A0 (en) 1998-11-09 1998-12-03 Silverbrook Research Pty Ltd Image creation method and apparatus (ART73)
US7117342B2 (en) * 1998-12-03 2006-10-03 Sun Microsystems, Inc. Implicitly derived register specifiers in a processor
US7114056B2 (en) * 1998-12-03 2006-09-26 Sun Microsystems, Inc. Local and global register partitioning in a VLIW processor
US6438700B1 (en) * 1999-05-18 2002-08-20 Koninklijke Philips Electronics N.V. System and method to reduce power consumption in advanced RISC machine (ARM) based systems
AUPQ056099A0 (en) 1999-05-25 1999-06-17 Silverbrook Research Pty Ltd A method and apparatus (pprint01)
JP2001092663A (ja) * 1999-09-17 2001-04-06 Sanyo Electric Co Ltd データ処理装置
US7072817B1 (en) 1999-10-01 2006-07-04 Stmicroelectronics Ltd. Method of designing an initiator in an integrated circuit
US6591369B1 (en) 1999-10-01 2003-07-08 Stmicroelectronics, Ltd. System and method for communicating with an integrated circuit
US6615370B1 (en) 1999-10-01 2003-09-02 Hitachi, Ltd. Circuit for storing trace information
JP2001142692A (ja) * 1999-10-01 2001-05-25 Hitachi Ltd ２つの異なる固定長命令セットを実行するマイクロプロセッサ、マイクロコンピュータおよび命令実行方法
US6412043B1 (en) 1999-10-01 2002-06-25 Hitachi, Ltd. Microprocessor having improved memory management unit and cache memory
US6693914B1 (en) 1999-10-01 2004-02-17 Stmicroelectronics, Inc. Arbitration mechanism for packet transmission
US6567932B2 (en) 1999-10-01 2003-05-20 Stmicroelectronics Limited System and method for communicating with an integrated circuit
US7260745B1 (en) 1999-10-01 2007-08-21 Stmicroelectronics Ltd. Detection of information on an interconnect
US7000078B1 (en) 1999-10-01 2006-02-14 Stmicroelectronics Ltd. System and method for maintaining cache coherency in a shared memory system
US6665816B1 (en) 1999-10-01 2003-12-16 Stmicroelectronics Limited Data shift register
US6463553B1 (en) 1999-10-01 2002-10-08 Stmicroelectronics, Ltd. Microcomputer debug architecture and method
US6701405B1 (en) 1999-10-01 2004-03-02 Hitachi, Ltd. DMA handshake protocol
US6601189B1 (en) 1999-10-01 2003-07-29 Stmicroelectronics Limited System and method for communicating with an integrated circuit
US6629115B1 (en) 1999-10-01 2003-09-30 Hitachi, Ltd. Method and apparatus for manipulating vectored data
US6449712B1 (en) 1999-10-01 2002-09-10 Hitachi, Ltd. Emulating execution of smaller fixed-length branch/delay slot instructions with a sequence of larger fixed-length instructions
US6779145B1 (en) 1999-10-01 2004-08-17 Stmicroelectronics Limited System and method for communicating with an integrated circuit
US6457118B1 (en) 1999-10-01 2002-09-24 Hitachi Ltd Method and system for selecting and using source operands in computer system instructions
US6633971B2 (en) 1999-10-01 2003-10-14 Hitachi, Ltd. Mechanism for forward data in a processor pipeline using a single pipefile connected to the pipeline
US6530047B1 (en) 1999-10-01 2003-03-04 Stmicroelectronics Limited System and method for communicating with an integrated circuit
US6349371B1 (en) 1999-10-01 2002-02-19 Stmicroelectronics Ltd. Circuit for storing information
US6574651B1 (en) 1999-10-01 2003-06-03 Hitachi, Ltd. Method and apparatus for arithmetic operation on vectored data
US6598177B1 (en) 1999-10-01 2003-07-22 Stmicroelectronics Ltd. Monitoring error conditions in an integrated circuit
US6732307B1 (en) 1999-10-01 2004-05-04 Hitachi, Ltd. Apparatus and method for storing trace information
US6629207B1 (en) 1999-10-01 2003-09-30 Hitachi, Ltd. Method for loading instructions or data into a locked way of a cache memory
US6487683B1 (en) 1999-10-01 2002-11-26 Stmicroelectronics Limited Microcomputer debug architecture and method
US6859891B2 (en) 1999-10-01 2005-02-22 Stmicroelectronics Limited Apparatus and method for shadowing processor information
US6351803B2 (en) 1999-10-01 2002-02-26 Hitachi Ltd. Mechanism for power efficient processing in a pipeline processor
US6408381B1 (en) 1999-10-01 2002-06-18 Hitachi, Ltd. Mechanism for fast access to control space in a pipeline processor
US6928073B2 (en) 1999-10-01 2005-08-09 Stmicroelectronics Ltd. Integrated circuit implementing packet transmission
US6542983B1 (en) 1999-10-01 2003-04-01 Hitachi, Ltd. Microcomputer/floating point processor interface and method
US6598128B1 (en) 1999-10-01 2003-07-22 Hitachi, Ltd. Microprocessor having improved memory management unit and cache memory
US6460174B1 (en) 1999-10-01 2002-10-01 Stmicroelectronics, Ltd. Methods and models for use in designing an integrated circuit
US6298394B1 (en) 1999-10-01 2001-10-02 Stmicroelectronics, Ltd. System and method for capturing information on an interconnect in an integrated circuit
US6434665B1 (en) 1999-10-01 2002-08-13 Stmicroelectronics, Inc. Cache memory store buffer
US6820195B1 (en) 1999-10-01 2004-11-16 Hitachi, Ltd. Aligning load/store data with big/little endian determined rotation distance control
US6553460B1 (en) 1999-10-01 2003-04-22 Hitachi, Ltd. Microprocessor having improved memory management unit and cache memory
US6826191B1 (en) 1999-10-01 2004-11-30 Stmicroelectronics Ltd. Packets containing transaction attributes
US6918065B1 (en) 1999-10-01 2005-07-12 Hitachi, Ltd. Method for compressing and decompressing trace information
US6590907B1 (en) 1999-10-01 2003-07-08 Stmicroelectronics Ltd. Integrated circuit with additional ports
US7266728B1 (en) 1999-10-01 2007-09-04 Stmicroelectronics Ltd. Circuit for monitoring information on an interconnect
US6557119B1 (en) 1999-10-01 2003-04-29 Stmicroelectronics Limited Microcomputer debug architecture and method
US6772325B1 (en) * 1999-10-01 2004-08-03 Hitachi, Ltd. Processor architecture and operation for exploiting improved branch control instruction
US6496905B1 (en) 1999-10-01 2002-12-17 Hitachi, Ltd. Write buffer with burst capability
US6412047B2 (en) * 1999-10-01 2002-06-25 Stmicroelectronics, Inc. Coherency protocol
US6684348B1 (en) 1999-10-01 2004-01-27 Hitachi, Ltd. Circuit for processing trace information
US6546480B1 (en) 1999-10-01 2003-04-08 Hitachi, Ltd. Instructions for arithmetic operations on vectored data
US6502210B1 (en) 1999-10-01 2002-12-31 Stmicroelectronics, Ltd. Microcomputer debug architecture and method
AU2001245833A1 (en) 2000-03-27 2001-10-08 Infineon Technologies, Ag Method and apparatus for adding user-defined execution units to a processor using configurable long instruction word (cliw)
JP4640880B2 (ja) * 2000-07-14 2011-03-02 国立大学法人東京工業大学 マイクロプロセッサシステム
GB2370380B (en) 2000-12-19 2003-12-31 Picochip Designs Ltd Processor architecture
JP5372307B2 (ja) * 2001-06-25 2013-12-18 株式会社ガイア・システム・ソリューション データ処理装置およびその制御方法
US7346881B2 (en) * 2002-05-13 2008-03-18 Tensilica, Inc. Method and apparatus for adding advanced instructions in an extensible processor architecture
US7937559B1 (en) 2002-05-13 2011-05-03 Tensilica, Inc. System and method for generating a configurable processor supporting a user-defined plurality of instruction sizes
US7376812B1 (en) 2002-05-13 2008-05-20 Tensilica, Inc. Vector co-processor for configurable and extensible processor architecture
EP1378824A1 (en) * 2002-07-02 2004-01-07 STMicroelectronics S.r.l. A method for executing programs on multiple processors and corresponding processor system
US7162617B2 (en) * 2003-02-14 2007-01-09 Fine Arc Incorporated Data processor with changeable architecture
JP3805314B2 (ja) 2003-02-27 2006-08-02 Ｎｅｃエレクトロニクス株式会社 プロセッサ
ATE459042T1 (de) * 2003-04-15 2010-03-15 Koninkl Philips Electronics Nv Rechnersystem mit parallelität auf befehls- und draht-ebene
US20050108509A1 (en) * 2003-11-13 2005-05-19 Safford Kevin D. Error detection method and system for processors that employs lockstepped concurrent threads
US7610476B1 (en) * 2003-12-05 2009-10-27 Advanced Micro Devices, Inc. Multiple control sequences per row of microcode ROM
JP4283131B2 (ja) * 2004-02-12 2009-06-24 パナソニック株式会社 プロセッサ及びコンパイル方法
ITMI20040600A1 (it) * 2004-03-26 2004-06-26 Atmel Corp Sistema dsp su chip a doppio processore a virgola mobile nel dominio complesso
WO2005103922A2 (en) * 2004-03-26 2005-11-03 Atmel Corporation Dual-processor complex domain floating-point dsp system on chip
US7287185B2 (en) * 2004-04-06 2007-10-23 Hewlett-Packard Development Company, L.P. Architectural support for selective use of high-reliability mode in a computer system
US20060112226A1 (en) * 2004-11-19 2006-05-25 Hady Frank T Heterogeneous processors sharing a common cache
KR100636596B1 (ko) * 2004-11-25 2006-10-23 한국전자통신연구원 고에너지 효율 병렬 처리 데이터 패스 구조
GB2420884B (en) * 2004-12-03 2009-04-15 Picochip Designs Ltd Processor architecture
US7461275B2 (en) 2005-09-30 2008-12-02 Intel Corporation Dynamic core swapping
JP4580879B2 (ja) * 2006-03-02 2010-11-17 富士通セミコンダクター株式会社 リコンフィグラブル回路
US8352713B2 (en) * 2006-08-09 2013-01-08 Qualcomm Incorporated Debug circuit comparing processor instruction set operating mode
US20080133879A1 (en) * 2006-12-05 2008-06-05 Electronics And Telecommunications Research Institute SIMD parallel processor with SIMD/SISD/row/column operation modes
GB2454865B (en) * 2007-11-05 2012-06-13 Picochip Designs Ltd Power control
KR100935858B1 (ko) * 2007-12-05 2010-01-07 한국전자통신연구원 재구성 가능한 산술연산기 및 이를 구비한 고효율 프로세서
EP2366144B1 (en) 2008-10-15 2015-09-30 Hyperion Core, Inc. Sequential processor comprising an alu array
GB2466661B (en) * 2009-01-05 2014-11-26 Intel Corp Rake receiver
GB2470037B (en) 2009-05-07 2013-07-10 Picochip Designs Ltd Methods and devices for reducing interference in an uplink
KR101032771B1 (ko) 2009-05-29 2011-05-06 광운대학교 산학협력단 구성형 프로세서에서 ｒｉｓｃ 명령어와 확장 명령어를 병렬 처리하기 위한 방법 및 그에 따른 구성형 프로세서
GB2470891B (en) 2009-06-05 2013-11-27 Picochip Designs Ltd A method and device in a communication network
GB2470771B (en) 2009-06-05 2012-07-18 Picochip Designs Ltd A method and device in a communication network
CN102804136B (zh) * 2009-06-23 2015-03-11 精工爱普生株式会社 副处理器、集成电路装置及电子设备
GB2474071B (en) 2009-10-05 2013-08-07 Picochip Designs Ltd Femtocell base station
US8954714B2 (en) * 2010-02-01 2015-02-10 Altera Corporation Processor with cycle offsets and delay lines to allow scheduling of instructions through time
GB2482869B (en) 2010-08-16 2013-11-06 Picochip Designs Ltd Femtocell access control
JP5565228B2 (ja) 2010-09-13 2014-08-06 ソニー株式会社 プロセッサ
US20120210438A1 (en) * 2011-02-15 2012-08-16 Guobiao Zhang Secure Three-Dimensional Mask-Programmed Read-Only Memory
GB2489716B (en) 2011-04-05 2015-06-24 Intel Corp Multimode base system
GB2489919B (en) 2011-04-05 2018-02-14 Intel Corp Filter
GB2491098B (en) 2011-05-16 2015-05-20 Intel Corp Accessing a base station
KR101849702B1 (ko) 2011-07-25 2018-04-17 삼성전자주식회사 외부 인트린직 인터페이스
US11150721B2 (en) * 2012-11-07 2021-10-19 Nvidia Corporation Providing hints to an execution unit to prepare for predicted subsequent arithmetic operations
GB2546465B (en) 2015-06-05 2018-02-28 Advanced Risc Mach Ltd Modal processing of program instructions
US10708976B2 (en) 2015-09-04 2020-07-07 Ford Global Technologies, Llc Methods and systems for a vehicle computing system to wirelessly communicate data
US10474549B2 (en) * 2017-07-31 2019-11-12 Oracle International Corporation System recovery using a failover processor
US11403254B2 (en) 2018-08-16 2022-08-02 Tachyum Ltd. System and method for populating multiple instruction words

Family Cites Families (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5448746A (en) * 1990-05-04 1995-09-05 International Business Machines Corporation System for comounding instructions in a byte stream prior to fetching and identifying the instructions for execution
US5778423A (en) * 1990-06-29 1998-07-07 Digital Equipment Corporation Prefetch instruction for improving performance in reduced instruction set processor
DE69325826T2 (de) * 1992-01-06 2000-02-24 Hitachi Ltd Rechner mit einer Parallelverarbeitungsfähigkeit
US5309564A (en) * 1992-03-19 1994-05-03 Bradley Graham C Apparatus for networking computers for multimedia applications
JPH06250847A (ja) * 1993-02-25 1994-09-09 Fujitsu Ltd 並列論理型言語の命令をｖｌｉｗ方式の命令に変換する変換方式
JPH07110769A (ja) * 1993-10-13 1995-04-25 Oki Electric Ind Co Ltd Ｖｌｉｗ型計算機
US5542059A (en) * 1994-01-11 1996-07-30 Exponential Technology, Inc. Dual instruction set processor having a pipeline with a pipestage functional unit that is relocatable in time and sequence order
US5574927A (en) * 1994-03-25 1996-11-12 International Meta Systems, Inc. RISC architecture computer configured for emulation of the instruction set of a target computer
US6496922B1 (en) * 1994-10-31 2002-12-17 Sun Microsystems, Inc. Method and apparatus for multiplatform stateless instruction set architecture (ISA) using ISA tags on-the-fly instruction translation
US5638525A (en) * 1995-02-10 1997-06-10 Intel Corporation Processor capable of executing programs that contain RISC and CISC instructions
US5752035A (en) * 1995-04-05 1998-05-12 Xilinx, Inc. Method for compiling and executing programs for reprogrammable instruction set accelerator
US5699536A (en) * 1995-04-13 1997-12-16 International Business Machines Corporation Computer processing system employing dynamic instruction formatting
US5794062A (en) * 1995-04-17 1998-08-11 Ricoh Company Ltd. System and method for dynamically reconfigurable computing using a processing unit having changeable internal hardware organization
JP3451595B2 (ja) * 1995-06-07 2003-09-29 インターナショナル・ビジネス・マシーンズ・コーポレーション 二つの別個の命令セット・アーキテクチャへの拡張をサポートすることができるアーキテクチャ・モード制御を備えたマイクロプロセッサ
US5774686A (en) * 1995-06-07 1998-06-30 Intel Corporation Method and apparatus for providing two system architectures in a processor
US5826089A (en) * 1996-01-04 1998-10-20 Advanced Micro Devices, Inc. Instruction translation unit configured to translate from a first instruction set to a second instruction set
JP3623840B2 (ja) 1996-01-31 2005-02-23 株式会社ルネサステクノロジ データ処理装置及びマイクロプロセッサ
US5784636A (en) * 1996-05-28 1998-07-21 National Semiconductor Corporation Reconfigurable computer architecture for use in signal processing applications
US5828897A (en) * 1996-12-19 1998-10-27 Raytheon Company Hybrid processor and method for executing incrementally upgraded software
US6202143B1 (en) * 1997-08-21 2001-03-13 Samsung Electronics Co., Ltd. System for fetching unit instructions and multi instructions from memories of different bit widths and converting unit instructions to multi instructions by adding NOP instructions

Also Published As

Publication number Publication date
US6496919B1 (en) 2002-12-17
US6760832B2 (en) 2004-07-06
US6023757A (en) 2000-02-08
JPH09212358A (ja) 1997-08-15
KR100535852B1 (ko) 2006-05-10
US20030065911A1 (en) 2003-04-03
KR970059916A (ko) 1997-08-12
JP3623840B2 (ja) 2005-02-23

Similar Documents

Publication Publication Date Title
TW334544B (en) Data processor
MY116751A (en) Processor for executing highly efficient vliw
GB2333384A (en) Processor having replay architecture
GB2285155B (en) Computer system
MY125652A (en) Mixed vector/scalar register file
MY121300A (en) Forwarding of results of store instructions
CA2041507A1 (en) A high performance pipelined emulator
EP0380847A3 (en) Decoding multiple specifiers in a variable length instruction architecture
EP0263288A3 (en) Extended floating point operations supporting emulation of source instruction execution
EP0380849A3 (en) Preprocessing implied specifiers in a pipelined processor
EP0199009A3 (en) Path coverage measuring system in a programme
SE9704475L (sv) Instruktionsavkodare
TW364097B (en) SIMD correction circuit for arithmetic/shift operations
TW355772B (en) Eight-bit microcontroller having a RISC architecture
CA2123448A1 (en) Blackout Logic for Dual Execution Unit Processor
TW360877B (en) Method and system for determining nuclear reactor core control blade positioning
JP3781519B2 (ja) プロセッサの命令制御機構
WO1996008762A3 (en) Processing system with word-aligned branch target
TW377422B (en) Pipeline processor capable of reducing branch hazards with small-scale circuit
TW346595B (en) Single-instruction-multiple-data processing with combined scalar/vector operations
EP0324952A3 (en) Branching circuit for a pipelined processor
TW482978B (en) Method and apparatus for loose register encoding within a pipelined processor
TW355770B (en) Program execution method and device using the same
HU9200024D0 (en) Device for producing intructions of paralelly working instruction processing processors as well as for executing branching within compound instruction
GB2334122A (en) Method for supporting a variety of instruction fetch units in a pipeline with a single microprocessor core