018212 A7 B7 五、發明説明（/ ) 本發明係關於一種資料處理的裝置與方法，可同時 接受多種不同介面性質的週邊裝備之資料輸入，並予以 即時性的處理。 【發明背景】 在對反應時間要求嚴苛的軍事與工業的應用環境中， 系統控制中心必須能夠有效率、並準確地控制多數不同介 面性質的週邊裝備，這些裝備自身具有快慢不等的處理速 度、於系統所提供的擷取信號之時序也有不同要求，但 所有裝備之輸出入資料都必須能夠被即時的處理，不能有 所遺漏；此外，系統控制中心也要能夠在一定容忍時間 內，反應各週邊裝備處理的結果、或自動執行某些週期例 行性工作。 以往有關的資料處理裝置與方法，都僅能連接某些相 同性質的裝備介面，亦無法提供對處理時間要求緊迫的即 時控制應用；因此，本發明申請所提出的處理裝置與方 法，旨在提供一即時控制中心雛型，以期能夠應用在對於 外接裝備處理時間要求嚴格的系統，並達到整合多數不同 裝備介面之目的。 經濟部中央榡準局員工消費合作社印製 (請先閱讀背面之注意事項再填寫本頁) 【發明槪述】 爲能夠提出一種可同時接受多數裝備資料輸入、並予 以即時處理的裝置與方法，本處理裝置內含高速率的微處 理控制器與特殊設計的介面電路，藉以連接多位元、不同 速率且不同傳輸協定之應用界面處理裝置；配合載入於裝 置中的軟體，系統可即時地處理外接裝備信號，而各裝備 本紙張尺度適用中國國家標準（CNS > A4規格（210Χ297公釐） 經濟部中央樣準局員工消費合作枉印製 A7 _B7 五、發明説明（2) 信號的處理程式能以多工的方式同時執行並交換資訊，系 統中多數不同裝備信號之處理順位'以及系統中各工作之 優先權，亦能加以規範，讓所有重要的工作都能在一定的 時間內進行或完成。 此一處理裝置(參閱圖示1)共包含以下的電路模組： 1. 微處理器電路模組(1)，是主要的硬體控制中心，內 含一高速率的微處理機及相關的支援電路，如脈波產 生電路、系統重置電路、直接記憶體存取電路、位址 與資料傳輸緩衝電路等。 2. 即時多工的記億體電路模組(2)，藉即時軟體的載入 與相關資料的存取，提供多工（Multi-Tasking)與 資料通訊的作業環境給應用程式，並可維護裝置^ 「系統時間」以保持所有界面的時間同步。 3. 介面信號處理電路模組(3) ’用以產生微處理器電路 模組與外界裝置連接所需要的控制信號。 【實施例】 圖2爲本發明實際應用在軍機或軍艦上的一種典型例 子，作爲主要的指揮管制與通訊交連系統（11)，如圖中所 示；分別以串列信號界面連接通訊機（12)、以並列信號界 面連接雷達（13)、以1553軍規界面連接飛彈（14)、以1397 軍規界面連接火砲（15)、以類比與數位信號轉換界面連接 使用者操控臺（16)。 【先前之技術】 本紙張尺度適用中國國家標準（CNS ) A4規格（210X 297公釐） I---------t------il—^-----絲 (請先閱讀背面之注意事項再填寫本頁) 經濟部中央標準局員工消费合作社印裝 〇1ϋΒΐ2 Α7 _________Β7_____ 五、發明説明（3 ) 先前所習知有關即時介面資料處理裝置與技術，大都 不能同時提供多種不同性質介面的連接方式，因而無法在 對反應時間要求嚴苛的軍事與工業環境中廣泛應用。有些 針對多數週邊裝置連接信號的處理技術，大都提供了軟體 層次的解決方案，如多工的作業環境之提供等；這些多工 的作業技術雖可提供程序間獨立執行環境的切換，但對於 週邊裝置所產生的激發信號與多工作業環境間的對應，以 及各裝置間資料如何有效率的傳遞，則尙未有相關技術方 法被提出。 如美國專利4972312號「用以處理週邊信號中斷之多程 序計算機與方法」。此一專利案4972312號專注在軟體方 法上，對每一週邊裝置中的處理程序提供一個獨立的執行 環境，由多程序計算機來切換其執行環境，達到多工的目 地。 又如美國專利4394734號「可規劃式週邊裝置控制 器」，提供一種記憶體映對方式，讓每一裝置在軟體的控 制下都存在一個相對應的暫存器，控制器藉由暫存器中所 指的位址來尋找一塊記憶體，作爲與週邊裝置的資料交 換。 以上兩專利案都未考慮硬體週邊裝置的特性及連結方 式，軟體層面上亦未提及各工作或程序之間訊號的傳遞方 法；因此，皆不能達到本專利案中所特別強調之整合多個 不同裝備介面之目的。 【發明詳細說明】 III - L·! - n HI nn i nn n In 1^1 .n HI 一OJ (請先閱讀背面之注意事項再填寫本頁) 本纸張尺度適用中國國家標準（CNS ) Λ4規格（2丨0><297公釐） 經濟部中央標準局員工消费合作社印^ 0^.8912 A7 _____B7__ 五、發明説明（〆） 本專利案中的處理裝置主要包括一片作爲硬體控制中 心的微處理器電路模組（1)，其內含高位元的微處理控制 器與相關電路，用以連接外界不同性質裝備的位址及資料 信號。微處理器電路模組（1)並以內部的高速率信號連接 至一片介面信號處理電路模組(3)，由此介面信號處理模 組(3)產生不同位元與速率的控制信號至外界裝備。另 外，微處理器電路模組(1)亦送出位址及資料信號線至記 憶體電路模組(2)，用以讀取載入於記憶體中的即時多工 的控制軟體，提供多工作業與資料通訊環境給應用程式。 I；····'·：：. f.¾ 以下分別針對此一發明申請中各部份電路模ffiL逐一說 明： A)微處理器電路模組(1) 提供一硬體控制中心，配合載入微處理器中即時軟體 的執行，能以多工的方式處理不同速率的介面資料。此電 路模組包括以下電路(參閱圖示3): ’ a) 高速率微處理器電路（101):包括一高速率的微處理 器及電源與接地電路。 b) 多速率脈波產生電路（102):連接不同速率的裝備介 面，內含一高速率石英振盪器度(1021)，一脈波速率 除法器（1022)，及一緩衝電路(1023);用以產生足夠 的驅動力與不同速率的週期性脈波，供給微處理器模 組內各電路、介面信號處理電路模組、及外接之系統 計時器與其它裝置電路使用。 1^1 nn fen^— ^11^1 In nn If at fm —^^1« l^n 1 0¾. ’a (請先閱讀背面之注意事項再填寫本頁) 本纸掁尺度適用中國國家標準（CNS ) Λ4現格（210Χ2«ί7公釐） 經濟部中夬標準局員Η消費合作杜印裝 A7 B7 五、發明説明（，） C)系統重置電路（103):包括依自動重置或手動重置功 能而有不同阻値設計的前端電阻'電容充放電電路、 單穩態觸發電路（1031)、及一D型正反器(1032)。系統 中的自動重置動作是當電源加入時，藉可變之電阻、 .電容與閘元件組合，產生不同時間長度的重置信號； 手動重置則提供使用者一手動按鈕，由使用者自行決 定重置時間，於按鈕按下時，系統中各電路模組進入 重置狀態，直到按鈕放開，系統才開始正常動作。電 路中的D型正反器用以接入低速率脈波與重置信號，產 生同步作用，藉以連接不同速秦要求之沐界裝置。 d) 直接記憶體存取電路(104):包括由邏輯閘元件組合 之時序轉換的電路（1041)，與兩D型正反器 (1042,1043)。由於若以微處理器提供的匯流排仲裁信 號線作爲直接記憶體存取功能的信號時序，將與外接 裝置所提供的信號時序不匹配，因此必須利用一時序 轉換電路來調配微處理器與外接裝置信號時序。當外 接裝置要求直接存取私用記憶體資料，會適時讓微處 理器停止動作，以釋放位址及資料匯流排使用權利給 外接裝置。此電路中負責處理直接記憶體存取輸入與 輸出信號所用的D型正反器，用來作爲與外界裝置要求 之直接記憶體動作信號同步，可藉以連接不同速率要 求之外界裝置。 e) 位址傳輸緩衝電路（105):包括數個單向邏輯動閘元 件（1051)，在連接多數外界裝置時，可提高位址匯流 排的驅動能力，並確保在外界裝置在執行直接記憶體 —l·-------"ί 裝------訂— (請先閱讀肾面之注意事項再填寫本頁) 本紙伕尺度適用中國國家標準（CNS ) Λ4現格（210X 297公釐） 經濟部中央標隼局負工消費合作社印裝 A7 _B7 五、發明説明（6 ) 存取動作時，不會受到微處理器的位址信號的影響。 此緩衝電路的致能動作是由外接裝置中之直接記億、體 存取要求信號來控制。 f) 資料傳輸緩衝電路（106):包括數個雙向邏輯驅動閘 -元件（1061)，在連接多數外界裝置時，可提高資料匯 流排的驅動能力。此電路只在兩種狀況下動作：一爲 擷取外界裝置的記憶體或輸出入阜資料；另一爲硬體 中斷週期時中斷向量的讀取。由於資料進出爲雙向， 邏輯驅動閘元件必須由微蹲理機的讀寫信號來控制。 g) 中斷週期指示電路（107):爲一邏輯閘組合電路 (1071)，接收由微處理器送出的位址功能識別碼，用 以偵測微處理器是否處於中斷處理的週期，並產生一 中斷週期指示信號，送至介面信號處理電路模組。 ---_------—^-------1T (锖先閱讀背面之注意事項再填寫本頁) B)即時多工的記憶體電路模組(2) 提供給即時控制軟體的載入與微處理器相關資料的存 取，資料可以不同位元組的存取方式進行(8位元、16位 元、32位元）。此模組包含以下電路（參閱圖示4 ): a)記憶體位址解碼電路(201):由可程式規劃之陣列邏 輯元件(2011)、邏輯閘記憶體致能電路(2022)所組 成，以產生對於不同位元數(8、16、32位元)資料擷取 的致能動作。 本紙張尺度適用中國國家榡準（CNS ) A4规格（2丨OX297公釐） 經濟部中央標準局員工消費合作社印製 A7 B7 五、發明説明（7) b) 快速靜態讀寫記憶體(SRAM)電路(202):包括由數個 快速的靜態讀寫記憶體元件及讀寫致能電路所組成； 本模組中各個記憶體元件的致能信號皆由記憶體位址 解碼電路所產生。 c) 快速唯讀記憶體(EPROM)電路(203):包括由數個快速 的唯讀記憶體元件及讀出致能電路所組成；本模組中 各個記憶體元件的致能信號皆由記憶體位址解碼電路 所產生。- 爲了能夠同時接收多筆資料的輸入並予iS即時處理，此 記憶體電路模組內的控制軟體必須具有即時處理並提供多 工作業的功能，敘述如下(參閱圖示6之軟體流程圖）： d) 提供多工(Mul t i -Tasking)作業系統與資料通訊環境 給應用程式，並明白揭示週邊裝置介面所產生的激發 信號與多工作業間的對應關係，使得各裝備可以有效 率的傳遞資訊，工作方式敘述如下： *針對各界面的輸入處理及輸出處理各自形成一個 工作（Task)，並擁有獨立的工作區段，使不同 的工作能同時進行而彼此互不干擾。各工作皆經 由激發而進入備妥啓動的狀態後，再由多工執行 裁決者選中執行。激發的來源共有五種：資料集 激發、訊息包激發、其它工作激發、到期激發、 持續激發。作業系統記錄各工作備妥啓動的原 因，因此各工作在被選中執行時可以得知被激發 的原因。 本紙張尺度適用中國囷家標準（CNS ) A4規格（2丨〇X297公釐） (請先閱護背面之注意事項再填寫本頁) 裝· i訂 3, A7 B7 五、發明説明（8 ) &供標準的資料集（dataset)格式給各工作使 用，發送工作只要將資料集以「廣播」方式送 出’其它工作在判斷需要此資料集後即自行接收 此項資料。資料集的格式如下：018212 A7 B7 V. Description of the invention (/) The present invention relates to a data processing device and method, which can simultaneously accept data input from a variety of peripheral equipment with different interface properties and process it in real time. [Background of the invention] In a military and industrial application environment that requires strict response time, the system control center must be able to efficiently and accurately control most peripheral equipment with different interface properties. These equipment have their own processing speeds of varying speeds. 3. There are different requirements for the timing of the signal acquisition provided by the system, but the input and output data of all equipment must be able to be processed in real time, and there must be no omission; in addition, the system control center must also be able to respond within a certain tolerance time The results of the processing of each peripheral equipment, or automatically perform certain periodic routine work. The related data processing devices and methods in the past can only be connected to certain equipment interfaces of the same nature, and cannot provide real-time control applications that require urgent processing time; therefore, the processing devices and methods proposed in the present application are intended to provide A prototype of an instant control center, which can be applied to a system with strict processing time requirements for external equipment, and to achieve the purpose of integrating most different equipment interfaces. Printed by the Employee Consumer Cooperative of the Central Bureau of Economics of the Ministry of Economic Affairs (please read the precautions on the back before filling in this page) The processing device contains a high-speed micro-processing controller and a specially designed interface circuit to connect multi-bit, different rate and different transmission protocol application interface processing devices; with the software loaded in the device, the system can instantly Processing of external equipment signals, and the paper standard of each equipment is in accordance with Chinese national standards (CNS & A4 specifications (210 × 297 mm). The Central Sample Bureau of the Ministry of Economic Affairs, employee consumption cooperation printed A7 _B7 V. Invention description (2) Signal processing The program can simultaneously execute and exchange information in a multi-tasking manner. The processing order of most different equipment signals in the system and the priority of each task in the system can also be standardized so that all important tasks can be performed within a certain time. Or complete. This processing device (see Figure 1) contains the following circuit modules: 1. Microprocessor Module (1) is the main hardware control center, which contains a high-speed microprocessor and related supporting circuits, such as pulse wave generation circuit, system reset circuit, direct memory access circuit, address and Data transmission buffer circuit, etc. 2. Real-time multiplexing memory circuit module (2), providing real-time working environment for multi-tasking and data communication by loading real-time software and accessing related data Application program, and can maintain the device ^ "System Time" to maintain the time synchronization of all interfaces. 3. Interface signal processing circuit module (3) 'Used to generate the control signal required for the microprocessor circuit module to connect with external devices [Embodiment] Figure 2 is a typical example of the actual application of the present invention on military aircraft or warships, as the main command and control and communication cross-connect system (11), as shown in the figure; respectively, the serial signal interface is connected to the communication machine (12), connect the radar with the parallel signal interface (13), the missile with the 1553 military interface (14), the artillery with the 1397 military interface (15), and the user operation interface with the analog and digital signal conversion interface Taiwan (16). [Previous Technology] This paper scale is applicable to the Chinese National Standard (CNS) A4 specification (210X 297mm) I --------- t ------ il-^- --- Silk (please read the precautions on the back before filling in this page) Printed by the Employee Consumer Cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs 〇1ϋΒΐ2 Α7 _________ Β7 _____ V. Description of the invention (3) Previously known relevant real-time interface data processing devices and technologies Most of them cannot provide multiple connection interfaces with different properties at the same time, so they cannot be widely used in military and industrial environments with strict response time requirements. Some of the processing techniques for connecting signals to most peripheral devices mostly provide software-level solutions. , Such as the provision of multi-tasking operating environments; although these multi-tasking technologies can provide independent execution environment switching between programs, the correspondence between the excitation signals generated by peripheral devices and the multi-tasking business environment, and between devices How to transfer information efficiently, no related technical methods have been proposed. For example, U.S. Patent No. 4,972,312, "Multi-program computer and method for processing peripheral signal interruption". This patent case No. 4972312 focuses on the software method, providing an independent execution environment for the processing procedures in each peripheral device, and the execution environment is switched by a multi-program computer to achieve the goal of multiple tasks. Another example is U.S. Patent No. 4394734 "Programmable Peripheral Device Controller", which provides a memory mapping method, so that each device has a corresponding register under the control of software. The controller uses the register The address referred to in finds a piece of memory to exchange data with peripheral devices. The above two patent cases do not consider the characteristics and connection methods of hardware peripheral devices, nor do they mention the method of signal transmission between tasks or programs on the software level; therefore, they cannot achieve the integration that is particularly emphasized in this patent case. The purpose of a different equipment interface. [Detailed description of the invention] III-L ·!-N HI nn i nn n In 1 ^ 1 .n HI-OJ (please read the precautions on the back before filling in this page) This paper size is applicable to the Chinese National Standard (CNS) Λ4 specification (2 丨 0> < 297mm) Printed by the Employee Consumer Cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs ^ 0 ^ .8912 A7 _____B7__ V. Description of the invention (〆) The processing device in this patent case mainly includes a piece as a hardware control The central microprocessor circuit module (1), which contains a high-bit microprocessor controller and related circuits, is used to connect the address and data signals of external equipment of different nature. The microprocessor circuit module (1) is connected to an interface signal processing circuit module (3) with an internal high-speed signal, whereby the interface signal processing module (3) generates control signals of different bits and rates to the outside world equipment. In addition, the microprocessor circuit module (1) also sends out address and data signal lines to the memory circuit module (2), which is used to read the real-time multiplexing control software loaded in the memory to provide multiplexing Operation and data communication environment for applications. I; ··· '· :: f.¾ The following sections describe the circuit modules ffiL of this part of the invention application one by one: A) Microprocessor circuit module (1) Provide a hardware control center, cooperate with The execution of real-time software loaded into the microprocessor can process interface data at different rates in a multiplexed manner. This circuit module includes the following circuits (see Figure 3): ’a) High-rate microprocessor circuit (101): includes a high-speed microprocessor and power and ground circuits. b) Multi-rate pulse wave generating circuit (102): connecting equipment interfaces of different rates, including a high-rate quartz oscillator (1021), a pulse rate divider (1022), and a buffer circuit (1023); It is used to generate sufficient driving force and periodic pulse waves with different speeds to be supplied to various circuits in the microprocessor module, interface signal processing circuit module, and external system timer and other device circuits. 1 ^ 1 nn fen ^ — ^ 11 ^ 1 In nn If at fm — ^^ 1 «l ^ n 1 0¾. 'A (please read the precautions on the back before filling in this page) The size of this paper is applicable to Chinese national standards (CNS) Λ4 present grid (210Χ2 «ί7mm) Member of the Ministry of Economic Affairs Standards Bureau HM Consumer Cooperation Du Printed A7 B7 Fifth, invention description (,) C) System reset circuit (103): including automatic reset or Front-end resistors with different resistance values, capacitor charge and discharge circuits, monostable trigger circuit (1031), and a D-type flip-flop (1032) with manual reset function. The automatic reset action in the system is that when the power is added, the variable signals, capacitors and gate elements are combined to generate reset signals of different lengths of time; manual reset provides the user with a manual button, which is operated by the user The reset time is determined. When the button is pressed, each circuit module in the system enters the reset state, and the system does not start to operate normally until the button is released. The D-type flip-flop in the circuit is used to connect the low-rate pulse wave and the reset signal to produce a synchronization effect, thereby connecting the Mujie devices required by different speed Qin. d) Direct memory access circuit (104): It includes a circuit (1041) which is composed of a logic gate device and a timing switch, and two D-type flip-flops (1042,1043). If the bus arbitration signal line provided by the microprocessor is used as the signal timing of the direct memory access function, it will not match the signal timing provided by the external device, so a timing conversion circuit must be used to allocate the microprocessor and the external Device signal timing. When the external device requires direct access to private memory data, the microprocessor will be stopped at an appropriate time to release the address and data bus usage rights to the external device. In this circuit, the D-type flip-flop used to process the direct memory access input and output signals is used to synchronize the direct memory action signals required by external devices, which can be used to connect external devices that require different rates. e) Address transmission buffer circuit (105): including several unidirectional logic brake elements (1051), which can improve the driving ability of the address bus when connected to most external devices, and ensure that the external devices are performing direct memory体 —l · ------- " ί 装 ------ 定 — (Please read the notes on the kidney surface before filling this page) This paper is applicable to the Chinese National Standard (CNS) Λ4 cash (210X 297 mm) A7 _B7 printed by the Consumer Labor Cooperative of the Central Standard Falcon Bureau of the Ministry of Economic Affairs V. Description of the invention (6) During the access operation, it will not be affected by the address signal of the microprocessor. The enabling action of this buffer circuit is controlled by the direct memory charge and body access request signal in the external device. f) Data transmission buffer circuit (106): including several bidirectional logic drive gate-components (1061), which can improve the drive capability of the data bus when connected to most external devices. This circuit operates only under two conditions: one is to capture the memory of an external device or input and output data; the other is to read the interrupt vector during the hardware interrupt cycle. Since the data entry and exit are bidirectional, the logic drive gate element must be controlled by the read and write signals of the micro-squatting machine. g) Interrupt cycle indication circuit (107): a logic gate combination circuit (1071), which receives the address function identification code sent by the microprocessor to detect whether the microprocessor is in the interrupt processing cycle and generates a The interrupt period indication signal is sent to the interface signal processing circuit module. ---_-------- ^ ------- 1T (Read the precautions on the back before filling in this page) B) Real-time multiplexed memory circuit module (2) is provided for immediate Control software loading and access to microprocessor-related data. Data can be accessed in different bytes (8-bit, 16-bit, 32-bit). This module contains the following circuits (see Figure 4): a) Memory address decoding circuit (201): It is composed of programmable logic elements (2011) and logic gate memory enabling circuit (2022) Enabling actions for data acquisition of different bit numbers (8, 16, 32 bits) are generated. This paper scale is applicable to China National Standard (CNS) A4 specification (2 丨 OX297mm) A7 B7 printed by the Employee Consumer Cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs 5. Invention description (7) b) Fast static read-write memory (SRAM) Circuit (202): It consists of several fast static read-write memory components and read-write enable circuits; the enable signals of each memory component in this module are generated by the memory address decoding circuit. c) Fast read-only memory (EPROM) circuit (203): consists of several fast read-only memory elements and read-out enable circuits; the enable signals of each memory element in this module are all memorized Generated by the body address decoding circuit. -In order to be able to receive multiple data inputs at the same time and process them in real time by iS, the control software in this memory circuit module must have real-time processing and provide multi-tasking functions, as described below (see software flow chart in Figure 6) : D) Provide multi-tasking (Mul ti-Tasking) operating system and data communication environment to the application, and clearly reveal the correspondence between the excitation signal generated by the peripheral device interface and the multi-tasking industry, so that each equipment can be efficiently transmitted Information and working methods are described as follows: * The input processing and output processing of each interface form a task, and have independent work sections, so that different tasks can be performed simultaneously without interfering with each other. After each task is activated and enters the ready-to-start state, it is selected and executed by the arbitrator. There are five sources of excitation: data set excitation, packet excitation, other work excitation, expiration excitation, and continuous excitation. The operating system records the reason why each job is ready to start, so when each job is selected for execution, the reason for being excited can be known. The size of this paper is applicable to the Chinese standard (CNS) A4 specification (2 丨 X297mm) (please read the precautions on the back side and then fill out this page) 装 · i 定 3, A7 B7 5. Description of the invention (8) & Standard data set (dataset) format is used for each job, as long as the sending job sends the data set in "broadcast" mode, other jobs will receive this data after judging that this data set is needed. The format of the data set is as follows:
DASETJD WC SNDTID DVT 資料集識別碼 資料集字元組數 資料集發送者之工作識別碼 餓集建立時間 DATA1 (請先閱讀背面之注意事項再填寫本頁) DATAn 經濟部中央標準局員工消費合作社印製 各工作（應用程式）所需利用之資料集，在系統啓 動階段即向作業系統註冊。資料集在由工作廣播發 送後即由作業系統處理，作業系統依據註冊記錄， 讀入所需要的資料集，並激發須此資料集的工作進 入備妥狀態。 >提供標準的訊息包（message)給各工作使用，使 得不同工作間可採用點對點式互傳重要訊息。訊 息包的格式如下： 本紙張尺度適用中國國家標率（CNS 規格（2丨ο X 297公釐） A7 B7 五、發明説明（^ ) MSG.ID ^>訊息包識別碼 WC —~>訊息包字元組數 SNDTID 一>訊息包發送者之工作識別碼 RCVTID 一>訊息包建立時間 DATA1 1(¾¾) « I · DATAn 所有訊息包內容均經事先規劃，訊息包在廣播發送 後即由作業系統處理，作業系統以訊息包激發接收 者之工作以進入備妥狀態。 e)即時處理各介面的輸入資料以及將應有的輸出資料 送到各介面所連接的裝備上，工作方式敘述如下： *各工作事先賦予其特定的優先權限，以保障重要 工作能優先進行。 經濟部中央標準局貝工消費合作社印製 Λ— - - - --H ί -. I 1^^11 I (諳先閱讀背面之注意事項再填寫本頁) *輸入處理的工作通常皆由界面之中斷服務程式 (參閱圖式7)激發而進入備妥狀態。輸出處理的 工作則由輸入處理的工作依需要激發，或者由界 面之中斷服務程式要求激發而進入備妥狀態。 *當一工作已被激發而進入備妥狀態，如果其優先 權高於正在執行中的工作，則執行優先權較高的 工作可強迫正在執行中的工作暫停執行 (preempted)，以達到即時的效果。 本紙張尺度適用中國國家標準（CNS > A4说格（2丨Ο X 297公釐） J1S912 A7 B7 五、發明説明（/0) *圖示8爲一工作狀態變換圖。在重置裝置的啓始之 後，各工作先處於非備妥狀態(S1);此工作要等 待事件(A1)的發生來激發以進入備妥狀態(S2)， 此時便等待被啓動執行；在眾多進入備妥狀態的 工作中，操作系統會選擇(A2)優先權限最高的工 作進入啓動執行中狀態(S3);當工作執行結束或 被安排結束執行(A3)的時，便回到非備妥狀態 (S1);當一工作在已進入啓動執行中狀態（S3) 時，遇到有中斷發生而被暫停執行(A4)情形產 生，此工作便重新進入已備妥等待下次 被選中執行(A2)。 f)維護裝置的系統時間以保持所有界面的時間同步，工 作方式敘述如下： *由外接之系統計時器界面利用直接記億體存取方 式將系統定時時間存入外界所連接的雙阜記憶、 體，以提供外界裝備存取。 ♦在某一工作進行廣播資料集時，操作系統同時在 資料集裏塡上系統時間，使得任何取用資料集的 其他工作得以知其資料的產生（或有效）時間。 (t先閱讀背面之注意事項再填寫本頁) 裝· 經濟部中央標準局員工消費合作社印裝 C)介面信號處理電路模組(3) 本紙張尺度適用中國國家標準（CNS > A4規格（210Χ297公釐） A7 __________ 五、發明説明（// ) 提供微處理器電路模組所需的介面控制信號，並用以 連接外界裝置。此模組又包含以下有關電路（參閱圖示 5) · a) 中斷要求信號的處理電路（301):由固定向量中斷 (Vectored Interrupt)處理電路(3011)與非固定向量 中斷(Non-Vectored Interrupt)處理電路（3012)所組 成，共可允許13種外界裝置的中斷要求，6個固定向量 中斷及7個非固定向量中斷。固定向量電路包括一優先 權編碼器及產生自動中斷:結束回報信號的一些邏輯 閘；非固定向量電路與固定向量電路共用一懞先權編 碼器，另包括一中斷向量產生器及中斷結束回報信號 所用的一些邏輯閘元件。由於微處理器的限制，提供 給外界中斷輸入的接線只有三條，因此總共僅能提供7 種固定向量的中斷。但爲了提供更多外界裝置的中斷 輸入，此電路模組將最低優先權的一個固定中斷保留 作爲另7個非固定向量位址的中斷輸入。在有中斷產生 時，藉由中斷向量產生器產生指定的中斷向量，于特 定時序的中斷週期期間，送到資料線上，由微處理器 讀取，用以決定中斷時程式的執行位址。 經濟部中央標準局'•貝工消費合作社印繁 ：---:---L.--1 H ---- (請先閱請背面之注意事項再填寫本頁) b) 輸出入阜控制電路(302):包括一輸出入位址解碼器 (3021)及可延遲輸出入阜讀取週期、並可產生8位元或 16位元的讀取指示信號電路(3022)。微處理器藉由外 界輸入控制的信號，配合內部的存取指令，可擷取8位 元或16位元外界裝置的資料，而亦可利用控制信號來 本紙張尺度適用中國國家標準（CNS > A4規格（210X297公釐} 318912 A7 ___ B7 五、發明説明（A2 ) 延長微處理器對於外界裝置的讀取週期，應用於低速 率的裝置。 c) 雙阜記憶體介面控制電路(303)，用於連接外界的共 用記憶、體，使微處理器與外接裝置可同時共享記憶體 資料。此一控制電路包括雙阜記憶體存取位址解碼電 路(3031)及雙阜記憶體介面信號控制電路(3032)。利 用外界雙阜記憶體控制有關的信號，配合系統的週期 脈波，延長微處理器對於外界共用記憶體的存取時 間，使得微處理器能在特卑時序內存取正確的資料。 d) 介面信號緩衝電路(304)，內含緩衝電路(3041)用以 提高位址匯流排的驅動能力。爲了在外接裝置執行直 接記憶體存取動作時，微處理器的位址信號確實不會 影響外接電路，此緩衝電路的致能動作是由直接記憶 體存取要求信號來控制。 綜合以上所述本案所提之裝置與方法，無論就目的 與功效，都顯示其迥異於以往所知之技術特徵，且其首 先創作亦具先進性並可供產業利用，符合發明之要件， 懇請貴審查委員明察，早日賜與專利，俾嘉惠社會，實 感德便。 經濟部中央標準局員工消費合作社印褽 (請先閱讀背面之注意事項再填寫本頁) 【¥示簡單說明】 圖$1爲本即時多工輸入/輸出處理裝置之方塊圖； 圖示2爲本發明實際應用在軍機或軍艦上的一種典型例 f ； 圖示3爲微處理器電路模組之內部方塊圖 本紙张尺度適用中國國家標隼（CNS ) A4規格（210X297公釐） A7 B7 五、發明説明（A5 ) 圖示4爲即時多工的記憶體電路模組之內部方塊圖 圖示5爲介面信號處理電路模組之內部方塊圖 圖示6爲載入於即時多工的記憶體電路模組之控制軟體之 流程圖 圖示7爲輸出入處理的工作產生之中斷服務程式的流程圖 圖示8爲裝置中某一工作之工作狀態變換圖 圖示9爲微處理器電路模組之詳細電路圖 圖示10爲即時多工的記憶體電路模組之詳細電路圖 圖示11爲介面信號處理電路模組之內部方塊圖 (畤无閱讀背面之注意事項再填寫本頁) .裝 、-° 經濟部中央標準局員工消費合作社印裝 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐）DASETJD WC SNDTID DVT data set identification code data set character number data set sender's work identification code hungry set creation time DATA1 (please read the precautions on the back before filling this page) DATAn printed by the Employee Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs The data sets required for each task (application) are registered with the operating system during the system startup phase. After the data set is sent by the work broadcast, it is processed by the operating system. The operating system reads the required data set according to the registration record, and stimulates the work that requires this data set to enter the ready state. > Provide a standard message package (message) for each job to use, so that different workshops can use point-to-point mutual transmission of important messages. The format of the message package is as follows: This paper scale is applicable to China's national standard rate (CNS specification (2 丨 ο X 297 mm) A7 B7 V. Description of invention (^) MSG.ID ^ > message packet identification code WC — ~ > Number of packet characters SNDTID 1 > work identification code of the packet sender RCVTID 1 > packet creation time DATA1 1 (¾¾) «I · DATAn All packet contents have been planned in advance, after the packet is broadcast and sent It is processed by the operating system, and the operating system stimulates the receiver's work with a message packet to enter the ready state. E) Instantly process the input data of each interface and send the appropriate output data to the equipment connected to each interface, working mode The description is as follows: * Each work is given its specific priority authority in advance to ensure that important work can be carried out first. Printed by the Beigong Consumer Cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs Λ------H ί-. I 1 ^^ 11 I (know the precautions on the back and then fill out this page) * The input processing is usually done by the interface The interrupt service program (see Figure 7) is activated and enters the ready state. The output processing work is triggered by the input processing work as needed, or is triggered by the interface interrupt service program to enter the ready state. * When a job has been stimulated to enter a ready state, if its priority is higher than the job in progress, the job with higher priority can force the job in progress to be suspended (preempted) to achieve immediate effect. This paper scale is applicable to the Chinese National Standard (CNS> A4 said grid (2 x 297 mm) J1S912 A7 B7 V. Description of the invention (/ 0) * Figure 8 is a working state transition diagram. After the start, each work is in the unprepared state (S1); this work must wait for the occurrence of the event (A1) to be excited to enter the ready state (S2), at this time it is waiting to be started and executed; In the state of work, the operating system will select (A2) the job with the highest priority to enter the startup execution state (S3); when the work execution ends or is scheduled to end execution (A3), it will return to the non-ready state (S1 ); When a job has entered the startup execution state (S3), the execution is suspended (A4) when an interruption occurs, the job is re-entered and ready to be selected for execution next time (A2) F) Maintain the system time of the device to maintain the time synchronization of all interfaces. The working method is described as follows: * The system timer time is stored in the external Shuangfu memory connected by the external system timer interface using direct memory access , To provide external equipment storage take. ♦ When a data set is broadcast in a certain job, the operating system simultaneously sets the system time in the data set, so that any other work that accesses the data set can know the time when the data is generated (or valid). (t Read the precautions on the back first and then fill out this page) Installation · Printed and printed by the CSC Employee Consumer Cooperative C) Interface signal processing circuit module (3) This paper standard is applicable to the Chinese National Standard (CNS & A4) ( 210Χ297 mm) A7 __________ 5. Description of the invention (//) Provides interface control signals required by the microprocessor circuit module and is used to connect external devices. This module also contains the following related circuits (see icon 5) · a ) Interrupt request signal processing circuit (301): consists of a fixed vector interrupt (Vectored Interrupt) processing circuit (3011) and a non-fixed vector interrupt (Non-Vectored Interrupt) processing circuit (3012), which allows a total of 13 external devices Interrupt requirements of 6 fixed vector interrupts and 7 non-fixed vector interrupts. The fixed vector circuit includes a priority encoder and generates automatic interrupts: some logic gates for the end report signal; the non-fixed vector circuit and the fixed vector circuit share a precedence encoder, and also includes an interrupt vector generator and an interrupt end report signal Some logic gate components used. Due to the limitation of the microprocessor, there are only three wires for external interrupt input, so only 7 fixed vector interrupts can be provided in total. However, in order to provide more interrupt input for external devices, this circuit module reserves the fixed interrupt with the lowest priority as the interrupt input for the other 7 non-fixed vector addresses. When an interrupt is generated, the specified interrupt vector is generated by the interrupt vector generator, which is sent to the data line during an interrupt cycle of a specific timing and read by the microprocessor to determine the execution address of the program during the interrupt. Central Bureau of Standards of the Ministry of Economic Affairs' • Beigong Consumer Cooperative Indication: ---: --- L .-- 1 H ---- (please read the precautions on the back before filling this page) b) export to Fu Control circuit (302): includes an I / O address decoder (3021) and a read indication signal circuit (3022) that can delay the I / O read cycle and can generate 8-bit or 16-bit reads. The microprocessor can extract the data of 8-bit or 16-bit external devices through external input control signals and internal access commands, and can also use the control signals to apply Chinese national standards (CNS & gt) to this paper standard. ; A4 specification (210X297 mm) 318912 A7 ___ B7 V. Description of invention (A2) Extend the reading cycle of the microprocessor for external devices and apply to low-rate devices. C) Shuangfu memory interface control circuit (303) It is used to connect the external shared memory and body, so that the microprocessor and external devices can share memory data at the same time. This control circuit includes Shuangfu memory access address decoding circuit (3031) and Shuangfu memory interface signals Control circuit (3032). Use external Shuangfu memory to control related signals, cooperate with the system's periodic pulse wave, prolong the access time of the microprocessor to the external shared memory, so that the microprocessor can access within the special sequence Correct information. D) Interface signal buffer circuit (304), which contains buffer circuit (3041) to improve the drive capability of the address bus. In order for the external device to perform the direct memory access operation, the address signal of the microprocessor does not affect the external circuit. The enabling action of this buffer circuit is controlled by the direct memory access request signal. The above-mentioned devices and methods mentioned in this case, no matter in terms of purpose and efficacy, show that they are very different from the previously known technical characteristics, and their first creation is also advanced and can be used by the industry, which meets the requirements of the invention. Your reviewer has made a clear observation and granted the patent as soon as possible, so as to benefit the society and feel virtuous. Printed by the Staff Consumer Cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs (please read the precautions on the back before filling in this page) [¥ shows a simple description] Figure $ 1 is a block diagram of the instant multiplex input / output processing device; Figure 2 is A typical example of the actual application of the invention on a military aircraft or warship f; Figure 3 is the internal block diagram of the microprocessor circuit module. The paper size is applicable to the Chinese National Standard Falcon (CNS) A4 specification (210X297 mm) A7 B7 5. DESCRIPTION OF THE INVENTION (A5) Figure 4 is an internal block diagram of a real-time multiplexing memory circuit module. Figure 5 is an internal block diagram of an interface signal processing circuit module. Figure 6 is a memory circuit loaded in real-time multiplexing. The flow chart of the control software of the module is shown in figure 7. The flow chart of the interrupt service program generated by the input and output processing is shown in the figure. The figure 8 is the working state transition of a certain job in the device. The figure is the microprocessor circuit module. Detailed circuit diagram icon 10 is the detailed circuit diagram of the real-time multiplexed memory circuit module.Figure 11 is the internal block diagram of the interface signal processing circuit module (you can fill out this page without reading the precautions on the back). , - ° Ministry of Economic Affairs Bureau of Standards Employees Co-op India with this paper scale applicable Chinese National Standard (CNS) A4 size (210X297 mm)