經濟部中央標準局員工消費合作社印製 A7 B7 五、發明説明（1 ) 背景說明= PCI(PERIPHERAL COMPONENT INTERCONNECT)匯流排爲目前個人電腦系統內的 一種匯流排標準。此一標準於制定之初，雖然規範有 輸出/入埠（I/O)位址及記憶體（Memory)位址重置 (relocation)的功能，以便提供系統隨插即用（plug-and-play)之特性 。但 此一 功能於 初期並 未能普 遍被相 關的PCI卡裝造商所遵循。一直到最近，因新的作業 系統，如WIN 95，強調隨插即用之功能，新設計、 製造的PCI卡才紛紛提供位址重置的能力。 PCI標準要求每一個與其連接的裝置必須包含 一個類別碼（class code)，此類別碼內須指明裝置的類 別，如 IDE(Integrated Drive Electronic)裝置等等。 IDE爲著名習知的標準。如習知技術，當ID E裝置 的第〇通道致能時此I D E裝置佔用輸出入埠位址 1F0H〜1F7H及3F6H，當IDE裝置的第1通道致 能時此I D E裝置佔用輸出入埠位址170H〜177H 及 376H 〇 另外，爲了支援位址重置，PCI卡另需有驅動程 式（BIOS或driver)相配合，換言之，此一驅動程式 需有指令可供進行輸出/入埠位址或記憶髎位址重置 的動作。但市面上現存舊有的PCI卡驅動程式，如 VGA BIOS 、 IDE BIOS ，大都沒有相關指令πΗ乍位 址重置的動作。 爲了支援傳統VGA裝置，PC I協定包含了一 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） I n .^1 n - I - - I _ I I n I T n I n _ n ——免 、v'口^ (請先閱讀背面之注意事項再填寫本頁) 經濟部中央標準局員工消費合作社印裝 A7 B7 五、發明説明（><) VGA致能位元信號供致能一直接或間接連接於P C I匯流排的VGA裝置。相對的，PC I協定卻未 包含一致能位元信號供致能一直接或間接連接於P CI匯流排的IDE裝置。 標準的PCI/PCI橋接器內之解碼電路有一組可 程式（programmable)的暫存器，配合的驅動程式可更 改其基底位址（Base address)以便橋接器指定一段位 址（如4K或其倍數）供所連接的標準PCI卡的輸出/入 埠佔用。另外，另有二組可程式的暫存器，配合的驅 動程式可更改基底位址値，以便橋接器指定一段記憶 體位址（如1M或其倍數）供所連接標準PCI卡的記憶 體佔用。 過去數年間，已有數以百萬計的非標準的pci 卡流入市場，此等非標準PCI卡的位址解碼電路是固 定無法重新設定的（programmable)，亦即無法支援位 址重置的功能。舉例而言，百萬計的ID.E裝置佔用輸 出入埠位址1F0H〜1F7H及3F6H、170H〜177H及 376H，且其解碼電路是無法程式化.的。 如果使用者不知上述傳統IDE卡的位址安排情 形，而將上述非P C I標準的IDE卡插於系統上之 PCI橋接器上時，他會發現處理器對這些IDE卡所發 動的輸出/入埠週期不會發生動作。這是因爲BIOS並 未能藉由橋接器去存取這些IDE卡的輸出入埠，而導 致位址解碼錯誤的情形。 針對上述可能發生的缺失，本發明乃提供一電路 本紙張尺度適用中國國家標準（CNS ) A4規格（210 X 297公釐） ----------f4.------訂------1 (請先閲讀背面之注意事項再填寫本頁) _248_^_ _248_^_ 經濟部中央標準局員工消費合作社印製 五、發明説明（3 ) 及配合相關程序方法，可解決IDE卡佔用位址的問 題。 圖式的簡要說明= 第一圖揭露系統的硬體架構。 第二圖揭露橋接器內解碼電路相關硬體架構。 第三圖揭露本發明一實施例的流程。 發明之詳細說明= 如第一圖所示，爲目前一典型的個人電腦系統， , ..... ..........Printed by the Employee Consumer Cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs A7 B7 5. Description of invention (1) Background description = PCI (PERIPHERAL COMPONENT INTERCONNECT) bus is a bus standard in the current personal computer system. At the beginning of the formulation of this standard, although the specification has the functions of I / O address and memory address relocation to provide system plug-and-play play). However, this function was not universally followed by relevant PCI card manufacturers in the early days. Until recently, new operating systems, such as WIN 95, emphasized plug-and-play functionality, and newly designed and manufactured PCI cards have provided address reset capabilities. The PCI standard requires that each device connected to it must contain a class code, which must indicate the type of device, such as IDE (Integrated Drive Electronic) devices. IDE is a well-known standard. As is known in the art, this IDE device occupies the I / O port addresses 1F0H ~ 1F7H and 3F6H when the ID E device's channel 0 is enabled, and this IDE device occupies the I / O port address when the IDE device's first channel is enabled 170H ~ 177H and 376H. In addition, in order to support the address reset, the PCI card also needs a driver (BIOS or driver) to cooperate. In other words, this driver needs to have commands for I / O port address or memory The action of resetting the address. However, most of the existing PCI card drivers on the market, such as VGA BIOS and IDE BIOS, do not have the relevant command πΗ to reset the address. In order to support traditional VGA devices, the PC I agreement includes a paper standard applicable to the Chinese National Standard (CNS) A4 specification (210X297 mm) I n. ^ 1 n-I--I _ II n IT n I n _ n — —Free, v 'port ^ (Please read the precautions on the back before filling in this page) A7 B7 printed by the Employees ’Consumer Cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs V. Invention description (> <) VGA enable bit signal for A VGA device that can be directly or indirectly connected to the PCI bus. In contrast, the PC I protocol does not contain uniform energy bit signals for enabling an IDE device that is directly or indirectly connected to the P CI bus. The decoding circuit in the standard PCI / PCI bridge has a set of programmable registers, and the driver can change its base address (Base address) so that the bridge can specify a certain address (such as 4K or its multiple) ) Used by the connected standard PCI card I / O ports. In addition, there are two sets of programmable registers, and the matching driver can change the base address value, so that the bridge can specify a memory address (such as 1M or multiples) for the memory of the connected standard PCI card. In the past few years, millions of non-standard PCI cards have entered the market. The address decoding circuits of these non-standard PCI cards are fixed and cannot be programmed, that is, they cannot support the function of address reset. . For example, millions of ID.E devices occupy the input and output port addresses 1F0H ~ 1F7H and 3F6H, 170H ~ 177H and 376H, and their decoding circuits cannot be programmed. If the user does not know the address arrangement of the traditional IDE card mentioned above, and inserts the non-PCI standard IDE card into the PCI bridge on the system, he will find the I / O ports activated by the processor for these IDE cards No action occurs during the cycle. This is because the BIOS has not been able to access the I / O ports of these IDE cards through the bridge, which caused the address decoding error. In response to the above-mentioned possible defects, the present invention provides a circuit board paper scale applicable to the Chinese National Standard (CNS) A4 specification (210 X 297 mm) ---------- f4 .------ Order ------ 1 (please read the precautions on the back before filling in this page) _248 _ ^ _ _248 _ ^ _ Printed by the Consumer Standardization Cooperative of the Central Standards Bureau of the Ministry of Economy V. Invention Instructions (3) and related procedures and methods, Can solve the problem of the address occupied by the IDE card. Brief description of the diagram = The first diagram reveals the hardware architecture of the system. The second figure discloses the hardware architecture of the decoding circuit in the bridge. The third figure discloses the process of an embodiment of the present invention. Detailed description of the invention = As shown in the first figure, it is a typical personal computer system at present,, .................
其中，中央處理器10藉由主匯流排1與主匯流排/PCI r " 匯流排間橋接器12連接，PCI匯流排2上連結有標 準PCI裝置11、13、PCI/PCI間橋接器14及PCI匯 流排/ISA匯流排間橋接器16。而P.QJ/PC丄間橋.接器 14可連接PCI裝置17 ' 19。基本輸出/入系統唯讀 記憶體（BIOS ROM) 18則藉ISA匯流排3與PCI/ISA 間橋接器16連接。如習知技術，橋接器之主要功能 係作爲不同匯流排（Host.，PCI，ISA)間信號之介 面，並將特定的存取週期轉發給相對應匯流排上的裝 置。 如果PCI/Ρ.ςΐ間橋接器14上所連接的裝置1.7、 I9等皆爲標準PCI.卡，則系統確有隨插即用之功，能， 此時並不會發生前述的缺失，已如上述。但當裝置 17、19中有IDE卡時，針對此IDE卡的存取週期不 .............. ..................... 會發生動作，其原因如上所述。 如第二圖所示，本發明於PCI/PCI間橋接器14 中之位址解碼器22 ||供一第一組暫存器及一第二 本紙張尺度適用中國國家標率（CNS ) A4規格（210X297公釐） ----------Γ-4------1T------f (請先閲讀背面之注意事項再填寫本頁) 經濟部中央梯準局員工消費合作社印裝 Α7 Β7 五、發明説明（4) 組暫存器21供以習粗方式分別儲存VFQH〜1F7H及 3F6H値、以及170H〜177H及376H値。進一步，位 址解碼器22另具有一通道〇之位元27及一通道1之 位元29供分別致能比較器24、26。此位元27及位 元29分別與資料匯流排連結。當比較器.24被位元27 致能時能比較位址信號値25與第一暫存器2〇之値， 以確認位址信號値25是否落於1F0H〜1F7H及3F0H 範圍內。當比較器26被位元29致能時能比較位址信 號値25與第二暫存器21之値，以確認位址信號値25 是否落於170H〜177H及3 76H範圍內。如比較結果 於信號線241.產生一命中狀態，控制電路23於是利 用位址信號値25轉發一對應的週期給IDE裝置。如 比較結果於信號線261產生一命中.狀態，控制電路？3 於是利用位址信號値25轉發一對應的週期給ipj：裝 置。 於軟體方法方面，本發明於BI0SR0M_18內提 供一段程序，供程式化前述的位元暫存器27 ' 29， 其詳情如下所述。 如第三圖所示，當系統開機（方塊30)後，导IOS 內一些基本測試（POST)執行過程中，本發明提供的 特殊程序即首先於方塊32中偵測系統中是否有另一 ...... 個I D Ε控制器。如果有，於方塊3 6中，經由資料 匯流排28，本發明得致能位元29且失能位元27， 以便致能該與橋缓器I4連接之I D Ε控制器的第1 通道並失能第〇通道。接著，於方塊38，本發明將 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） ^ I n I I J I I I I T I n n --- ^ (請先閲讀背面之注意事項再填寫本頁) 經濟部中央標準局員工消费合作社印製 A7 B7 五、發明説明（_5 ) 於方塊y測得之I D J：控制器的第1 P JI于以失能 並致能其第〇通道。 須明白的是，於方塊36中，經由資料匯流排28， 本發明亦可致能位元27且失能位元29，以便致能該 與橋接器14連接之I D E控制器的第0通道並失能 第1通道。此時於方塊38中，本發明將於方塊32測 得之I D E控制器的第0通道于以失能並致能其第1 通道。 如果於方塊32時未發現另一 I D E控制器，則 本發明得於方塊3 4中致能位元2 7,及/或位元.. 2 9，以 便致能該與橋接器14連接之I D E控制器的第1通 道及/或第〇通道。 完成上述的程序後，系統即能存取此一 IDg卡佔 用的輸出/入埠，而能正確地_作。 當系統運作而發出一個針對系統上mg卡輸出/ 入埠讀或寫週期時，橋接器14之比較電路24及/或比 較電路26即對位址信號値25與暫存器20或2 1的値 進行比較。經由信號線24 1或26 1，控制電路.23即 知悉此一存取週期是否針對該與橋接器14連結之I D E控制器。如是，即轉發一存取週期。例如，當系 統對輸出入埠1F0H發動一寫入週期時，比較器24 會告訴控制器23此一週期屬於與橋接器14連結之I D E控制器，控制器23即對輸出入埠lF〇H轉發一存 取週期。該IDE卡即執行相關的動作。 須說明的是，圖三流程中動作可有許多均等變 本紙張尺度適用中國國家標準（CNS ) A4規格（2丨0'〆297公釐） I--------f <------IT------f (請先閲讀背面之注意事項再填寫本頁) A7 B7五、發明説明（)化，本發明之構想適用於這些均等變化，而被本發明所涵蓋。 I n n _ _ _ _ I I _ I I n n I T I n I I _ _ ^ /J、-口 ^ (請先閱讀背面之注意事項再填寫本頁) 經濟部中央標準局員工消費合作社印製 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） 6Among them, the central processing unit 10 is connected to the main bus / PCI r " inter-bus bridge 12 through the main bus 1, and the PCI bus 2 is connected with standard PCI devices 11, 13, and a PCI / PCI inter-bridge 14 And bridge between PCI bus / ISA bus 16. The P.QJ / PC bridge bridge connector 14 can be connected to the PCI device 17'19. Basic I / O system read-only memory (BIOS ROM) 18 is connected to the PCI / ISA bridge 16 via the ISA bus 3. As is known in the art, the main function of the bridge is to serve as an interface for signals between different buses (Host., PCI, ISA), and forward specific access cycles to the devices on the corresponding bus. If the devices 1.7, I9, etc. connected to the bridge 14 between PCI / Ρ.ς are all standard PCI. Cards, then the system does have plug-and-play capabilities, and the aforementioned loss does not occur at this time. As above. However, when there is an IDE card in the device 17, 19, the access cycle for this IDE card is not .................................... ... actions will occur for the reasons described above. As shown in the second figure, the address decoder 22 of the present invention in the PCI / PCI bridge 14 | | for a first set of registers and a second paper standard for China National Standard Rate (CNS) A4 Specifications (210X297mm) ---------- Γ-4 ------ 1T ------ f (Please read the notes on the back before filling this page) Central Ladder of Ministry of Economic Affairs The quasi-bureau employee consumer cooperative prints A7 B7. V. Description of the invention (4) The set of temporary storage 21 is used to store VFQH ~ 1F7H and 3F6H values, and 170H ~ 177H and 376H values respectively in a rough way. Furthermore, the address decoder 22 further has a channel 27 bit 27 and a channel 1 bit 29 for enabling the comparators 24 and 26, respectively. This bit 27 and bit 29 are respectively connected to the data bus. When the comparator .24 is enabled by bit 27, it can compare the value of the address signal value 25 with the first register 20 to confirm whether the address signal value 25 falls within the range of 1F0H ~ 1F7H and 3F0H. When the comparator 26 is enabled by bit 29, it can compare the value of the address signal value 25 and the second register 21 to confirm whether the address signal value 25 falls within the range of 170H ~ 177H and 3 76H. If the comparison results in a hit state on the signal line 241., the control circuit 23 then uses the address signal value 25 to forward a corresponding period to the IDE device. If the comparison result produces a hit on the signal line 261, the control circuit? 3 So the address signal value 25 is used to forward a corresponding period to ipj: device. In terms of software methods, the present invention provides a program in BI0SR0M_18 for programming the aforementioned bit registers 27'29, the details of which are described below. As shown in the third figure, when the system is turned on (block 30), during the execution of some basic tests (POST) in the IOS, the special program provided by the present invention first detects whether there is another in the system in block 32. .... an ID Ε controller. If yes, in block 36, via data bus 28, the present invention enables bit 29 and disable bit 27, so as to enable the first channel of the ID Ε controller connected to bridge buffer I4 and Disable the 0th channel. Next, at box 38, the present invention applies the paper standard to the Chinese National Standard (CNS) A4 specification (210X297 mm) ^ I n IIJIIIITI nn --- ^ (please read the precautions on the back before filling this page) Ministry of Economic Affairs A7 B7 printed by the Central Bureau of Standards Employees Consumer Cooperative V. Description of the invention (_5) IDJ measured at block y: The first P JI of the controller is disabled and its channel 0 is enabled. It should be understood that in block 36, via the data bus 28, the present invention can also enable bit 27 and disable bit 29, so as to enable the 0th channel of the IDE controller connected to the bridge 14 and Disable the first channel. At this time in block 38, the present invention disables the 0th channel of the ID controller measured at block 32 and enables its 1st channel. If another IDE controller is not found at block 32, the present invention can be enabled in block 34 by bit 27, and / or bit .. 2 9 in order to enable the IDE connected to the bridge 14 Channel 1 and / or Channel 0 of the controller. After completing the above procedure, the system can access the I / O port occupied by this IDg card, and it can operate correctly. When the system operates and issues a read or write cycle for the mg card output / input port on the system, the comparison circuit 24 and / or the comparison circuit 26 of the bridge 14 compares the address signal value 25 with the register 20 or 21 Value comparison. Via the signal line 241 or 261, the control circuit .23 knows whether this access cycle is for the ID controller connected to the bridge 14. If so, an access cycle is forwarded. For example, when the system initiates a write cycle to the I / O port 1F0H, the comparator 24 will tell the controller 23 that this cycle belongs to the IDE controller connected to the bridge 14, and the controller 23 will forward the I / O port lF〇H One access cycle. The IDE card performs related actions. It should be noted that the actions in the process of Figure 3 can have many equal changes. The paper size is applicable to the Chinese National Standard (CNS) A4 specification (2 丨 0'〆297mm) I -------- f <- ----- IT ------ f (Please read the precautions on the back before filling in this page) A7 B7 5. Description of the invention (), the concept of the present invention is applicable to these equal changes, and is Covered. I nn _ _ _ _ II _ II nn ITI n II _ _ ^ / J 、-口 ^ (Please read the notes on the back before filling in this page) Printed by the Ministry of Economic Affairs Central Standards Bureau Employee Consumer Cooperative. The paper size is suitable for China National Standard (CNS) A4 specification (210X297mm) 6