TW302503B - Self-aligned contact process with polysilicon barrier - Google Patents

Abstract

A manufacturing method of integrated circuit, which includes self-aligned contact area formed between two gate structures on semiconductor substrate; in which the above substrate includes buried impurity layer; each gate structure includes first gate oxide, gate formed above gate structure, top gate oxide formed above gate and sidewall spacer formed on the above gate oxide, the above gate and the above top gate oxide; comprises of the following steps: (1) on the above substrate and the above gate structure forming inter-poly oxide; (2) on the above inter-poly oxide forming polysilicon; (3) implanting impurity ion into the above polysilicon; (4) removing one portion of inter-poly oxide and polysilicon between the above gate structure to expose contact area; (5) on the above polysilicon, the above spacer and the above contact area depositing one barrier layer; (6) on the above barrier layer depositing one tungsten metal silicide layer, so as to form electric contact between the above tungsten metal silicide layer and the above self-aligned contact area; (7) patterning the above tungsten metal silicide layer; (8) on the above tungsten metal silicide layer depositing one metal layer and dielectric layer, to form interconnection used as electric contact between the above tungsten metal silicide layer and buried impurity layer in the above contact area, therefore finishing integrated circuit device.

Description

經濟部中央樣準局員工消费合作社印装 3025Q3 A7 _ H7 五、發明说明（/ ) 1.發明之技術領域 本發明是關於含有一層金屬層（M6tal Layer)之半導體 元件的製造方法（Method)。 2 ·發明背景 在半導體積體電路技術領域裡，金屬（Metal)連線是用 來作砂基板（Silicon Substrate)上之元件的電性聯接’例 如，源極、汲極和場效電晶體（Field Effect Transistor ; FET)。通常，金屬（Metal)可以沉積在基 板、介電層和其它結構之上方，例如閘極結構（Gate Structure)等等。最簡單的的方法是沉積金屬之後 (Metal)，再利用微影與電發飽刻技術制定（Patterned) 其圖案以形成金屬連線（Metal Interconnections)。目前 之半導體製程裡，鋁最常被用來作爲金屬連線材料，此外， 耐熔金屬（Refractory Metal)也被用來作爲金屬連線材 料，尤其是鎢金屬（Tungsten)。 爲了能夠更準確使基板上之埋藏雜質區域（Buried Impurity Region)例如源極和汲極，作電性接觸，一種稱爲 『自動對準接觸窗』（Self-Aligned Contact ; SAC)的技 術被廣汎的使用。在接觸窗區域（Contact Area)的附近制 定介電層之圖案再沉積一層金屬層（Metal Layer)以跟源極 /汲極【埋藏雜質區域】等作電性接觸，便形成所謂的『自動 對準接觸窗』。但是，『自動對準接觸窗』技術存在著若干 缺點，例如，金屬（Metal)在接觸窗區域（Contact Area) 之階梯覆蓋能力很差（Poor Step Coverage);另一方面， 金屬（Sletal)直接沉積在基板表面時，所述金屬（Metal) (請先閱讀背面之注意事項再填寫本頁) 裝. 訂 本紙張尺度適用中國國家橾準（CNS ) A4規格（210X297公釐） 經濟部中央揉準局員工消費合作社印製 A7 B7 五、發明説明（）） 會消耗掉一部份的砂基板（Silicon Substrate)，造成【更 深的源極/汲極接面】（Deeper Sour ce/Dra in Junction)。 圖1到圖4是以傳統方法形成『自動對準接觸窗』 (Self-Aligned Contact)的製程剖面圖。首先，參考圖 1 ;在半導體基板上 10 (Semiconductor Substrate)利用 傳統方法形成閘極結構28/30 (Gate Structure)，所述閘 極結構28/30含有閘氧化層16、閘極18、形成在閘極上方 之頂部聞氧化層（Top Gate Oxide)與氧化層側壁子24 (Spacer)。所述【基板10】有兩種不同型態的擴散區 (Diffusions)，即N_擴散區12 (淡摻雜汲極或源極； Lightly Doped Drain or Source)與 N+ 擴散區 14 (重摻 雜汲極或源極；Heavily Doped Drain or Source)。 參考圖2。接著，在元件表面（Device Surface)形成 一層『複晶矽中間氧化層32』（Inter-Poly Oxide) ’此處 所謂的『元件表面』（Device Surface)係包含基板 (Substrate)上之各種薄膜和結構。接著，利用電漿蝕刻技 術去除所述閘極結構28/30之間的一部份所述『複晶矽中間 氧化層32』以露出側壁子24 (Spacer)和【接觸區域 26】，如圖3所示。 接著，在所述『元件表面』形成一層『複晶矽層34』’ 其厚度介於500到600埃之間，如圖4所示’然後’利用 離子佈値技術將磷雜質離子（P31)植入所述『複晶矽層 34』以增加其導電性。『複晶矽層34』沉積在金屬層36 (Metal Layer)和氧化層 24/32 (Oxide Layer)之間以防 (請先閲讀背面之注意事項再填寫本頁) -裝·3025Q3 A7 _ H7 Printed by the Employees ’Consumer Cooperative of the Central Prototype Bureau of the Ministry of Economic Affairs 5. Description of the invention (/) 1. Technical field of the invention The present invention relates to a method of manufacturing a semiconductor element containing a metal layer (M6tal Layer). 2. Background of the invention In the technical field of semiconductor integrated circuits, metal (Metal) wiring is used for electrical connection of components on a sand substrate (Silicon Substrate), for example, source, drain and field effect transistors ( Field Effect Transistor; FET). Generally, metal can be deposited on top of substrates, dielectric layers, and other structures, such as gate structures. The simplest method is to deposit metal (Metal), and then use lithography and electro-saturation technology to formulate (Patterned) its pattern to form metal interconnections (Metal Interconnections). In the current semiconductor manufacturing process, aluminum is most commonly used as a metal wiring material. In addition, refractory metal (Refractory Metal) is also used as a metal wiring material, especially tungsten. In order to make the buried impurity regions (Buried Impurity Region) on the substrate, such as the source and the drain, for electrical contact, a technique called "Self-Aligned Contact" (SAC) is widely used. Pan use. The dielectric layer is patterned near the contact area and a metal layer is deposited to make electrical contact with the source / drain [buried impurity area], etc. Quasi-contact window ". However, the technology of "automatically aligning contact windows" has several shortcomings. For example, the step coverage of the metal in the contact area is very poor (Poor Step Coverage); on the other hand, the metal (Sletal) directly When deposited on the surface of the substrate, the metal (Metal) (please read the precautions on the back before filling out this page). The size of the paper is applicable to the Chinese National Standard (CNS) A4 specification (210X297 mm). A7 B7 printed by the quasi-bureau employee consumer cooperative. V. Description of invention ()) Part of the sand substrate (Silicon Substrate) will be consumed, resulting in [Deeper Sour ce / Dra in Junction] ). Figures 1 to 4 are cross-sectional views of the manufacturing process of forming a "Self-Aligned Contact" by a conventional method. First, refer to FIG. 1; on a semiconductor substrate 10 (Semiconductor Substrate) using a conventional method to form a gate structure 28/30 (Gate Structure), the gate structure 28/30 contains a gate oxide layer 16, gate 18, formed in The top gate oxide and the side wall 24 (Spacer) above the gate. The [substrate 10] has two different types of diffusion regions (Diffusions), namely N_diffusion region 12 (lightly doped drain or source) and N + diffusion region 14 (heavily doped Drain or Source; Heavily Doped Drain or Source). Refer to Figure 2. Next, a "poly-silicon intermediate oxide layer 32" (Inter-Poly Oxide) is formed on the surface of the device (Device Surface). The so-called "device surface" includes various thin films and substrates on the substrate. structure. Next, a part of the "polysilicon intermediate oxide layer 32" between the gate structure 28/30 is removed by plasma etching technology to expose the side walls 24 (Spacer) and [contact area 26], as shown in the figure 3 shown. Next, a layer of "polycrystalline silicon layer 34" is formed on the "device surface" whose thickness is between 500 and 600 angstroms, as shown in FIG. 4 and then "the ion impurity technology is used to remove phosphorus impurity ions (P31) The "polycrystalline silicon layer 34" is implanted to increase its conductivity. "Polycrystalline silicon layer 34" is deposited between the metal layer 36 (Metal Layer) and the oxide layer 24/32 (Oxide Layer) to prevent (please read the precautions on the back before filling in this page)-installed

、1T -丨線 本紙伕尺度適用中國國家標準（CNS > Α4规格（210Χ297公釐）、 1T-丨 Line The size of the paper is applicable to the Chinese national standard (CNS > Α4 specification (210Χ297mm)

經濟部中央標準局貝工消费合作社印製 3G2503 A7 B7 五、發明説明（3) 止【金屬層36】剝落離開所述『元件表面』。所述【金屬層 36】通常是『鎢金屬矽化物』（Tungsten Silicide ; WSix)，並在【接觸區域26】跟源極/汲極14作電性接 觸。上述製程係一種『自動對準』製程（Self-Aligning)， 因爲，所述【金屬層36】連線/【接觸區域26】到源極/汲 極14擴散區是以側壁子24 (Spacer)作爲對準光罩 (Mask)，而不需額外的微影光罩（Lithography Mask) ’ 這消弭了對準誤差較大的微影製程並降低成本。 然而，傳統『自動對準接觸窗』技術確有許多缺點。第一 個缺點是，後續高溫步驟會將重摻雜之N+『複晶矽層34』 (Heavily Doped Polysilicon)的雑質離子驅入『源極/汲 極』，造成【更深的源極/汲極接面】（Deeper Source/Drain Junction)。例如，後續的接觸窗流整溫度 (Flow Temperature)超過90(TC時，【深的源極/汲極接 面】將導至極大的漏電流和元件穿透效應（Device Punchthrough) ° 第二個缺點是，由於所述金屬（Metal)在接觸窗區域 (Contact Area)之階梯覆蓋能力很差（P〇or Step Coverage )，因而昇高了接觸窗電阻値（C〇ntact Resistance)。尤有進者，由於所述『複晶砍層34』佔據了 一部份接觸窗面積，使得接觸窗區域更小，更昇高了接觸窗 電阻値。 Rana等人在美國專利第4985371號掲露了一種形成具 有微細晶粒（Small Grain Size)金屬層的方法’微細晶粒 (請先閱讀背面之注意事項再填寫本頁) ----- 訂--- 線 本紙張尺度適用中國國家標準（CNS ) Μ規格（210X297公釐） 經濟部中央標隼局員工消費合作社印製 A7 B7 五、發明説明（Ιμ) 結構的存在將不會阻止金屬層變成微細的線條圖案。美國專 利第4985371號揭露之方法包含形成多層的金屬層和一種稱 爲【阻止晶粒成長】（Grain Growth Interupt Material) 的材料，而所述【阻止晶粒成長】（Grain Growth Interupt Material)的材料是砂，金屬層貝丨J是錫。Printed by the Beigong Consumer Cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs 3G2503 A7 B7 V. Description of the invention (3) Stop the [metal layer 36] from peeling off the "component surface". The [metal layer 36] is usually "Tungsten Silicide" (WSix), and is in electrical contact with the source / drain 14 in the [contact area 26]. The above process is a "self-aligning" process (Self-Aligning), because the [metal layer 36] connection / [contact area 26] to the source / drain 14 diffusion area is based on the side wall 24 (Spacer) As an alignment mask (Mask), no additional Lithography Mask is needed. This eliminates the lithography process with large alignment errors and reduces costs. However, the traditional "auto-align contact window" technology does have many shortcomings. The first disadvantage is that the subsequent high temperature step will drive the heavily doped N + "polycrystalline silicon layer 34" (Heavily Doped Polysilicon) ion into the "source / drain", resulting in a "deeper source / drain Polar junction] (Deeper Source / Drain Junction). For example, when the subsequent contact window Flow Temperature exceeds 90 (TC, [deep source / drain junction] will lead to a large leakage current and device penetration effect (Device Punchthrough) ° Second The disadvantage is that due to the poor step coverage of the metal in the contact area, the contact resistance is increased (Contact Resistance). In addition, because the "polycrystalline slicing layer 34" occupies a part of the contact window area, the contact window area is smaller and the contact window resistance value is increased. Rana et al. Disclosed in US Patent No. 4,985,371 The method of forming a metal layer with fine grains (Small Grain Size) 'fine grains (please read the precautions on the back before filling in this page) ----- Order --- The size of the line paper is applicable to the Chinese National Standard (CNS ) Μ specifications (210X297 mm) A7 B7 printed by the Employee Consumer Cooperative of the Central Standard Falcon Bureau of the Ministry of Economic Affairs 5. Invention description (Ιμ) The existence of the structure will not prevent the metal layer from becoming a fine line pattern. method It consists of a metal layer forming multiple layers and a material called [Grain Growth Interupt Material], and the material of [Grain Growth Interupt Material] is sand, metal layer 丨 J It is tin.

Schmitz等人在美國專利第4904620號亦揭露了一種形 成『鈦金屬砂化物』（Titanium Disilicide ; TiSi2)的方 法，其中，多層的鈦和矽沉積在基板（Substrate)上，再用 高溫步驟加熱以形成『鈦金屬矽化物』 3·圖示的簡要說明 ， 圖1到圖4是傳統方法形成『自動對準本發明接觸 窗』（Self-Aligned Metal Contact)的製程剖面圖； •圖5到圖8是本發明方法形成『自動對準接觸窗』的 製程剖面圖； 圖9是本發明方法形成『自動對準本發明接觸窗』的平 面俯視圖（Top Down View)。 4.發明之實施例 首先，參考圖5。在半導體基板上10 (Semiconductor Substrate)利用傳統方法形成蘭極結構28/30 (Gate Structure)，所述【基板10】通常是晶格方向（100)之單 晶砂（ilonocrystalline Silicon)，以 P 型單晶政爲 例，其硼離子（Bll)濃度介於5E15到5E17原子/立方公 分之間。當然，也可以在井區（Well )形成具相反導電型態 之積體電路元件。也在所述【基板10】形成閘氧化層16 (Gate Oxide)，而所述閘極結構28/30含有間氧化層 (請先閲讀背面之注意事項再填寫本頁) 丨裝· 訂 i" 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） 經濟部中央標搫局員工消費合作杜印製 A7 B7___ 五、發明説明（七） 16、閘極18、形成在閘極上方之頂部閘氧化層（T〇P Gate Oxide)與形成在所述閘氧化層、頂部閘氧化層20和側壁子 24 (Spacer) 〇 【閘氧化層16】之厚度介於60到200埃之間，【閘 極18】之厚度介於1000到3500埃之間’所述『閘極 18』且被施以磷離子（P31)離子佈値以形成N+閘極，離子 佈値後之雜質離子濃度介於1E18到1E21原子/立方公分之 間。【頂部閘氧化層20】之厚度介於1000到3500埃之 間。側壁子24 (Spacer)則是由二氧化矽組成’其厚度介於 1000到2500埃之間。所述【基板1〇】有兩種不同型態的 擴散區（Diffusions)，即N—擴散區12 (淡慘雜汲極或源 極；Lightly Doped Drain or Source)與 N+ 擴散區 14 (重摻雜汲極或源極；Heavily Doped Drain or Source)，『擴散區12』之雜質離子濃度介於1E17到 1E19原子/立方公分之間，『N+擴散區14』之雜質離子濃 度則介於1E18到1E21原子/立方公分之間。 接著，形成一層『複晶矽中間氧化層32』（Inter-Poly Oxide)，所述『複晶砂中間氧化層32』是用傳統乾氧化技術 (Dry Thermal Oxidation)或濕氧化技術（Wet Thermal Oxidation)低壓化學氣相沉積法（Low Pressure Chemical Vapor Deposition ; LPCVD)形成；例如，可以在溫度介於 700°C到1200°C之間的濕氧環境下形成『複晶砂中間氧化 層32』，所述『複晶矽中間氧化層32』之厚度介於700到 2000埃之間。 接著，在所述『複晶矽中間氧化層32』之上方形成『複 --------------?τ------^试· (讀先閲讀背面之注意事項再填寫本頁) 本紙張尺度適用中國國家橾準（CNS ) Α4规格（210Χ297公釐） 經濟部中央標準局負工消费合作社印裝 A7 B7 五、發明説明（fc) 晶矽層50』，如圖6所示。所述『複晶矽層50』通常是以 矽甲烷（Prolysing Silane)作爲反應氣體之低壓化學氣相 沉積法形成，反應溫度約620°C，厚度介於500到1000埃 之間，理想之厚度約550埃。然後，利用離子佈値技術將鱗 雜質離子（P31)植入所述『複晶矽層50』，其離子佈値劑 量介於1E13到1E15原子/平方公分之間，離子佈値能量貝!ί 介於30到80 kev之間，最後，所述『複晶矽層50』之雜 質離子濃度介於1E18到1E21原子/立方公分之間。 參考圖7。利用電漿鈾刻技術去除一部份的所述接觸窗 區域26 (Contact Area)和側壁子24 (Spacer)之上方的 所述『複晶矽中間氧化層32』與『複晶矽層50』，接著， 沉積一層『障礙層52』（Barrier Layer)，如圖8所示。 所述『障礙層52』可以由『複晶矽』或是『非晶矽』 (Amorphous Silicon)組成’但以『複晶砂』比較理想。所 述『障礙層52』通常是以傳統低壓化學氣相沉積法形成，厚 度介於30到100埃之間，但以50到100埃之間比較理 想，而所述『障礙層52』是利用後續高溫步驟之埋藏N+源 極區域（Buried Source Regions )的擴散 (Interdiffusion)來達到摻雜（Doped)的目的。 接著，在所述『障礙層52』之上方沉積一層『第一金屬 砂化物 54』（First Metal Silicide Layer) ’ 所述『第 一金屬砂化物54』又稱爲『金屬接觸窗層54』。所述『第 一金屬矽化物54』通常是由傳統低壓化學氣相沉積法形成之 『鎢金屬矽化物54』（MetalSilicide;WSix)，其厚度 介於700到3000埃之間，比較理想的厚度1〇〇〇埃。所述 (請先閲讀背面之注意^項再填寫本頁) -裝 訂 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） ⑹如3 Λ7 B7 經濟部中央標準局員工消費合作社印裝 五、發明説明（7) 『鎢金屬矽化物54』之阻値介於4到20 ohms/square之 間。 如圖8圖9所示，係利用傳統電漿蝕刻技術來蝕刻所 述『鎢金屬矽化物54』。接著沉積一層護層56 (Passivation Layer)和金屬層 58 (Metal Layer)，以 連接其它的半導體元件。圖9顯示了圖8之平面俯視圖 (Top Down View)，所述『第一金屬矽化物54』、『金屬 層58』和『汲極或源極14』跟附近的半導體元件作電性接 觸以形成邏輯或記憶體電路。 本發明揭露之方法較之傳統方法有許多優點。第一個優點 是，維持【淺汲極/源極接面】（Shallow Source/Drain Junction);因爲『複晶矽層50』在『接觸區域26』已被去 除所述『障礙層52』形成於『鎢金屬矽化物54』和『源極/ 汲極14』之間，阻止雜質離子從原本『複晶矽層50』擴散 到『源極/汲極14』，因此，能維持【淺汲極/源極接面】。 第二個優點是，由於所述『障礙層52』提供了較佳的金 屬晶粒成長表面（Metal Grain Growing Surface ) ’ 因 此，所述『障礙層52』跟所述『鎢金屬矽化物54』的反應 提供了較佳的砂化反應（Silicidation) ’因而改良了所述 『第一金屬矽化物54』在接觸窗區域（Contact Area)之階 梯覆蓋能力（Step Coverage)。尤有進者，由於所述『第一 金屬矽化物54』跟所述『障礙層52』之間的附著力 (Adhesion)比所述『第一金屬矽化物54』跟傳統氧化層之 間的附著力還要好，因此，所述『障礙層52』防止了在所述 側壁子24 (Spacer)表面之『鎢金屬矽化物54』掀起 0¾ -a (請先閲讀背面之注意事項再填寫本頁)Schmitz et al. Also disclosed a method for forming "Titanium Disilicide" (TiSi2) in U.S. Patent No. 4,904,620, in which multiple layers of titanium and silicon are deposited on a substrate (Substrate) and then heated in a high temperature step to Formation of "titanium metal silicide" 3. Brief description of the illustrations, Figures 1 to 4 are the cross-sectional views of the manufacturing process of forming the "Self-Aligned Metal Contact" (Self-Aligned Metal Contact) by the traditional method; • Figure 5 to Figure 8 is a cross-sectional view of the process of forming the "automatically aligned contact window" by the method of the present invention; FIG. 9 is a top plan view (Top Down View) of the method of the present invention to form the "automatically aligned contact window of the present invention". 4. Embodiment of the invention First, refer to FIG. 5. On the semiconductor substrate 10 (Semiconductor Substrate), a traditional method is used to form a blue-polar structure 28/30 (Gate Structure). The [substrate 10] is usually a single crystal sand (ilonocrystalline Silicon) in the lattice direction (100). As an example of single crystal, its boron ion (Bll) concentration is between 5E15 to 5E17 atoms / cm3. Of course, integrated circuit elements with opposite conductivity types can also be formed in the well area (Well). A gate oxide layer 16 (Gate Oxide) is also formed on the [substrate 10], and the gate structure 28/30 contains an inter-oxide layer (please read the precautions on the back and then fill out this page) 丨 Install · Order i " This paper scale is applicable to the Chinese National Standard (CNS) A4 specification (210X297 mm) A7 B7___ printed by the consumer cooperation of the Central Standardization Bureau of the Ministry of Economic Affairs V. Invention description (VII) 16, gate 18, formed above the gate The thickness of the top gate oxide layer (TOP Gate Oxide) and the gate oxide layer, the top gate oxide layer 20 and the side wall 24 (Spacer) 〇 [gate oxide layer 16] is between 60 and 200 angstroms, [Gate 18] The thickness is between 1000 and 3500 Angstroms. The "gate 18" is applied with phosphorus ion (P31) ion distribution to form an N + gate. The concentration of impurity ions after the ion distribution is Between 1E18 and 1E21 atoms / cm3. [Top gate oxide layer 20] has a thickness between 1000 and 3500 angstroms. The side wall 24 (Spacer) is composed of silicon dioxide and its thickness is between 1000 and 2500 angstroms. The [substrate 1〇] has two different types of diffusion regions (Diffusions), namely N-diffusion region 12 (lightly doped drain or source; Lightly Doped Drain or Source) and N + diffusion region 14 (redoped (Heavily Doped Drain or Source), the concentration of impurity ions in "diffusion zone 12" is between 1E17 to 1E19 atoms / cm3, and the concentration of impurity ions in "N + diffusion zone 14" is between 1E18 to Between 1E21 atoms / cubic centimeter. Next, a layer of "polycrystalline silicon intermediate oxide layer 32" (Inter-Poly Oxide) is formed. The "polycrystalline silicon intermediate oxide layer 32" is a conventional dry oxidation technology (Dry Thermal Oxidation) or wet oxidation technology (Wet Thermal Oxidation) ) Low pressure chemical vapor deposition (LPCVD); for example, the "intermediate oxide layer 32 of polycrystalline sand" can be formed in a wet oxygen environment with a temperature between 700 ° C and 1200 ° C, The thickness of the "polycrystalline silicon intermediate oxide layer 32" is between 700 and 2000 angstroms. Next, form a "multiple --------------? Τ ------ ^ test" above the "multicrystalline silicon intermediate oxide layer 32" (read the back (Notes to fill out this page) This paper standard is applicable to the Chinese National Standard (CNS) Α4 specification (210Χ297 mm) Printed by the National Bureau of Standards of the Ministry of Economic Affairs, the Consumer Cooperative A7 B7 V. Invention description (fc) Crystal silicon layer 50 ,As shown in Figure 6. The "polycrystalline silicon layer 50" is usually formed by low-pressure chemical vapor deposition using silane methane (Prolysing Silane) as the reaction gas. The reaction temperature is about 620 ° C and the thickness is between 500 and 1000 angstroms. About 550 Angstroms. Then, using ion distribution technology to implant scale impurity ions (P31) into the "polycrystalline silicon layer 50", the ion distribution dose is between 1E13 and 1E15 atoms / cm2, and the ion distribution value is energy! Between 30 and 80 kev, and finally, the impurity ion concentration of the "polycrystalline silicon layer 50" is between 1E18 and 1E21 atoms / cm3. Refer to Figure 7. Using plasma uranium etching technology to remove a part of the "polycrystalline silicon intermediate oxide layer 32" and "polycrystalline silicon layer 50" above the contact area 26 (Contact Area) and the side wall 24 (Spacer) Then, deposit a "Barrier Layer 52" (Barrier Layer), as shown in Figure 8. The "barrier layer 52" may be composed of "polycrystalline silicon" or "amorphous silicon" (amorphous silicon), but "polycrystalline sand" is ideal. The "barrier layer 52" is usually formed by a traditional low-pressure chemical vapor deposition method, with a thickness between 30 and 100 angstroms, but it is ideally between 50 and 100 angstroms, and the "barrier layer 52" is used Subsequent high temperature steps of burying N + source region (Buried Source Regions) diffusion (Interdiffusion) to achieve the purpose of doping (Doped). Next, a layer of "First Metal Silicide Layer 54" ("First Metal Silicide Layer") is deposited on top of the "obstacle layer 52". The "First Metal Silicide Layer 54" is also called "Metal Contact Window Layer 54". The "first metal silicide 54" is usually "tungsten metal silicide 54" (MetalSilicide; WSix) formed by a traditional low-pressure chemical vapor deposition method, and its thickness is between 700 and 3000 angstroms, which is an ideal thickness 100 Angstroms. As mentioned (please read the note on the back ^ item first and then fill out this page)-The size of the bound paper is applicable to the Chinese National Standard (CNS) A4 (210X297mm) ⑹ such as 3 Λ7 B7 Printed by the Employees Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs 5. Description of the invention (7) The resistance of "Tungsten Metal Silicide 54" is between 4 and 20 ohms / square. As shown in FIG. 8 to FIG. 9, the conventional plasma etching technique is used to etch the "tungsten metal silicide 54". Then deposit a protective layer 56 (Passivation Layer) and a metal layer 58 (Metal Layer) to connect other semiconductor devices. FIG. 9 shows a top down view of FIG. 8, the "first metal silicide 54", "metal layer 58" and "drain or source electrode 14" make electrical contact with nearby semiconductor devices to Form a logic or memory circuit. The method disclosed by the present invention has many advantages over traditional methods. The first advantage is that [Shallow Source / Drain Junction] is maintained; because the "polycrystalline silicon layer 50" has been removed from the "contact area 26" and the "barrier layer 52" is formed Between "tungsten metal silicide 54" and "source / drain 14", the impurity ions are prevented from diffusing from the original "polycrystalline silicon layer 50" to "source / drain 14", therefore, it can be maintained Pole / source junction]. The second advantage is that since the "barrier layer 52" provides a better metal grain growth surface (Metal Grain Growing Surface) ", the" barrier layer 52 "and the" tungsten metal silicide 54 " The reaction provides a better silicidation reaction (Silicidation) 'thus improving the "first metal silicide 54" in the contact window area (Contact Area) step coverage (Step Coverage). In particular, the adhesion between the "first metal silicide 54" and the "barrier layer 52" is higher than that between the "first metal silicide 54" and the traditional oxide layer. The adhesion is better, so the "barrier layer 52" prevents the "tungsten metal silicide 54" on the surface of the side wall 24 (Spacer) from lifting up 0¾ -a (please read the precautions on the back before filling this page )

本紙張尺度適用中國國家揉準（CNS ) A4規格（210><297公釐） A7 ____B7 五、發明説明（方） (Peel Off)。 努一方面，本發明揭露之方法增加了所述『第一金屬砍 化物54』跟所述【接觸區域26】表面之接觸面積，因此降 低了接觸窗阻値（Contact Resistance);因爲，所述『障 礙層52』比傳統『複晶矽層』之厚度還要薄，這也允許更多 的所述『第一金屬矽化物54』得以跟【接觸區域26】作電 性接觸，因此降低了接觸窗阻値（Contact Resistance)， 己夂善元件表現和良率（Performance & Yield )。 另外，所述『障礙層52』也防止了在所述『鎢金屬矽化 物54』沉積之前之蒸汽淸洗（Vapor Clean Process)所造 成的側壁子24 (Spacer)氧化層被蝕刻的現象，過量的側壁 子24 (Spacer)氧化層被鈾刻掉時，會導至金屬連線跟閘極 18之間的短路。 以上係利用最佳實施例來闡述本發明，而非限制本發 明，並且，熟知半導體技藝之人士皆能明瞭，適當而作些微 的改變及調整，仍將不失本發明之要義所在，亦不脫離本發 明之精神和範圍。 --------{¥------ΪΤ------{.V (請先聞讀背面之注意事項再填寫本頁) 經濟部中央標準局員工消费合作社印裝 本紙張尺度適用中國國家榡準（CNS ) A4规格（210X297公釐〉This paper scale is applicable to China National Standard (CNS) A4 specification (210 > < 297mm) A7 ____B7 5. Description of the invention (square) (Peel Off). On the one hand, the method disclosed in the present invention increases the contact area between the "first metal chop 54" and the surface of the [contact area 26], thus reducing the contact resistance (Contact Resistance); because, "Barrier layer 52" is thinner than the traditional "polycrystalline silicon layer", which also allows more of the "first metal silicide 54" to make electrical contact with [contact area 26], thus reducing Contact Resistance, good performance and yield (Performance & Yield) of components. In addition, the "barrier layer 52" also prevents the side wall 24 (Spacer) oxide layer from being etched due to the vapor washing (Vapor Clean Process) before the deposition of the "tungsten metal silicide 54". When the oxide layer of the side wall 24 (Spacer) is carved away by uranium, it will lead to a short circuit between the metal connection and the gate 18. The above uses the best embodiments to explain the present invention, not to limit the present invention, and those familiar with semiconductor technology can understand that appropriate and slight changes and adjustments will still not lose the essence of the present invention, nor Departs from the spirit and scope of the present invention. -------- {¥ ------ ΪΤ ------ {. V (Please read the precautions on the back first and then fill out this page) Printed by the Staff Consumer Cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs This paper scale is applicable to China National Standard (CNS) A4 specification (210X297mm)

Claims (1)

經濟部中央標隼局貝工消費合作社印製 A8 B8 C8 D8 六、申請專利範圍 1 ·一種積體電路元件的製作方法，所述積體電路元件係包含在半 導體基板上（Semiconductor Substrate)的兩個鬧極結構 (Gate Structure)之間形成自動對準接觸窗區域；而所述基 板（Substrate)包含有埋藏雜質層（Buried Impurity Layer);各個閘極結構含有第一閘氧化層（First Gate Oxide)、形成在閘氧化層上方之閘極、形成在閘極上方之頂部 閘氧化層（Top Gate Oxide)與形成在所述閘氧化層、所述閘 極和所述頂部閘氧化層之側壁（Sidewall)的側壁子 (Spacer);本發明係包含下列步驟： 在所述『基板』和所述『閘極結構』之上方形成『複晶矽中 間氧化層』（Inter-Poly Oxide); 在所述『複晶矽中間氧化層』之上方形成『複晶矽層』； 將雜質離子植入所述『複晶矽層』； 去除所述聞極結構（Gate Structure)之間的一部份『複晶政 中間氧化層』與『複晶矽層』，以露出接觸窗區域（Contact Area) l 在所述『複晶矽層』、所述側壁子（Spacer)和所述『接觸 窗區域』之上方沉積一層『障礙層』（Barrier Layer); 在所述『障礙層』之上方沉積一層『鎢金屬矽化物』 (Tungsten Metal Silicide Layer)，以在所述『鎢金屬砂 化物』跟自動對準之所述『接觸窗區域』之間形成電性接 觸， 制定（Pattern)所述『鎢金屬砂化物』之圓案； 在所述『鎢金屬矽化物』之上方沉積一層金屬層（Metal Layer)和介電層（Dielectric Layer)，以形成連線 (請先閲讀背面之注意事項再填寫本頁) 裝. 訂 i. ! 本紙張尺度適用令國國家捸準（CNS ) A4規格（210X297公釐） 經濟部中央標準局負工消费合作社印装 A8 B8 C8 D8 六、申請專利範圍 (Interconnection)跟所述『鎢金屬矽化物』與所述『接觸 窗區域』內之埋藏雜質層,(Buried Impurity Layer)作電 性接觸，積體電路元件於焉完成。 2·如申請專利範圍第1項所述之製作方法，其中所述『複晶砂 中間氧化層』（Inter-Poly Oxide)，其厚度介於700埃到 2000埃之間。 3·如申請專利範圍第1項所述之製作方法，其中所述『障礙 層』（Barrier Layer)，其厚度介於30埃到1〇〇埃之間。 4·如申請專利範圍第1項所述之製作方法，其中所述『複晶矽 層』，其厚度介於500埃到1000埃之間。 5 _如申請專利範圍第1項所述之製作方法，其中所述『複晶矽 層』被施以磷離子（P31)離子佈値，其離子佈値劑量介於 1E13到1E15原子/平方公分之間。 峰 6·如申請專利範圍第1項所述之製作方法，其中所述『複晶矽 層』之雜質離子濃度介於1E18到1E20原子/立方公分之 間。 7.如申請專利範圍第1項所述之製作方法，其中所述『鎢金屬 砂化物』（Tungsten Metal Silicide Layer)，其厚度介於 700埃到3000埃之間。 8·如申請專利範圍第1項所述之製作方法，其中所述側壁子 (Spacer)是由二氧化砂組成。 9 · 一種積體電路元件的製作方法，所述積體電路元件係包含在半 導體基板上（Semiconductor Substrate)的兩個閘極結構 (Gate Structure)之間形成自動對準接觸窗區域；而所述 『阐極結構』含有側壁子（Spacer);本發明係包含下列步 本紙張尺度適用中國囷家揉率（CNS〉A4規格（210X297公釐） (請先閱讀背面之注意事項再填寫本頁) 訂 經濟部中央橾準局員工消费合作社印製 Α8 Β8 C8 __ D8 六、申請專利範圍 驟： 在所述『基板』和所述『閘極結構』之上方形成『複晶矽 中間氧化層』（Inter-Poly Oxide); 在所述『複晶矽中間氧化層』之上方形成『複晶砂層』； 將雜質離子植入所述『複晶矽層』； 去除所述接觸窗區域內之所述閘極結構（Gate Structure) 之間的一部份『複晶矽中間氧化層』與『複晶矽層』，以露 出接觸窗區域（Contact Area)和所述側壁子（Spacer); 在所述『複晶矽層』、所述側壁子（Spacer)和所述『接 觸窗區域』之上方沉積一層『障礙層』（Barrier Layer); 在所述『障礙層』之上方沉積一層『第一金屬矽化物』 (First Metal Silicide Layer)，以在所述『第一金屬政 化物』跟自動對準之所述『接觸窗區域』之間形成電性接 觸， 制定（Pattern)所述『第一金屬矽化物』之圖案； 在所述『第一金屬矽化物』之上方沉積一層金屬層 (Metal Layer)和介電層（Dielectric Layer)，以形成 連線（Interconnection)跟所述『第一金屬矽化物』作電性 接觸，積體電路元件於焉完成。 10 ·如申請專利範圍第9項所述之製作方法，其中所述基板 (Substrate )含有埋藏雜質層（Buried Impurity Layer)。 11 .如申請專利範圍第9項所述之製作方法，其中所述『閘極 結構』含有第一鬧氧化層（First Gate Oxide)、形成在 『鬧氧化層』上方之複晶砂閘極（Polysilicon Gate)、形 本紙張尺度適用中國國家揉準（CNS ) A4現格（210Χ297公釐） (請先閲讀背面之注意事項再填寫本育) 裝· 訂 8888 ABCD 經濟部中央標準局員工消费合作社印裝 六、申請專利範圍 成在複晶矽閘極上方之頂部閘氧化層（T〇pGate 0xide)與 形成在所述閛氧化層、所述複晶砂閘極和所述頂部閫氧化層 之側壁（s i dewa 11)的側壁子（Spacer ) ° 12 .如申請專利範圍第9項所述之製作方法，其中所述側壁子 (Spacer)是由二氧化砂組成。 13 ·如申請專利範圍第9項所述之製作方法’其中所述『複晶矽 層』被施以磷離子（P31)或砷離子（As75)離子佈値，其 離子佈値劑量介於1E13到1E15原子/平方公分之間，離 子佈値能量則介於30到80 kev之間。 14 ·如申請專利範圍第9項所述之製作方法，其中所述『複晶矽 層』之雜質離子濃度介於1E18到1E21原子/立方公分之 間。 15 ·如申請專利範圍第9項所述之製作方法，其中所述『第一金 屬砂化物』（First Metal Silicide Layer)，是由鎢砂化 物（Tungsten Silicide)組成。 16 ·如申請專利範圍第9項所述之製作方法，其中所述『複晶 砂中間氧化層』（Inter-Poly Oxide)，其厚度介於700 埃到2000埃之間。 Π _如申請專利範圍第9項所述之製作方法，其中所述『障礙 層』（Barrier Layer)，其厚度介於30埃到100埃之 間。 18 ·如申請專利範圍第9項所述之製作方法，其中所述『複晶矽 層』，其厚度介於500埃到1000埃之間。 19 .如申請專利範圍第9項所述之製作方法，其中所述『複晶矽 層』被施以磷離子（P31)離子佈値，其離子佈値劑量介於 (請先閲讀背面之注意事項再填寫本頁) -裝· 訂 J 本紙張尺度逍用中困國家標準（CNS ) A4規格（210X297公釐） A8 B8 C8 D8 六、申請專利範圍 1E13到1E15原子/平方公分之間。 2〇 ·如申請專利範圍第9項所述之製作方法，其中所述『複晶砂 層』之雜質離子濃度介於1E18到1E20原子/立方公分之 間。 21 ·如申請專利範圍第15項所述之製作方法，其中所述『鎢砂 化物』（Metal Silicide)，其厚度介於700埃到3000 埃之間。 (請先閲讀背面之注意事項再填寫本頁) 經濟部中央標準局貝工消費合作社印製 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐）A8 B8 C8 D8 printed by Beigong Consumer Cooperative of the Central Standard Falcon Bureau of the Ministry of Economic Affairs 6. Scope of Patent Application 1 · A method for manufacturing an integrated circuit element, which is composed of two semiconductor substrates (Semiconductor Substrate) The gate structures are automatically aligned between the gate structures; the substrate contains a buried impurity layer; each gate structure contains a first gate oxide layer ), The gate electrode formed above the gate oxide layer, the top gate oxide layer formed above the gate electrode (Top Gate Oxide) and the sidewalls formed on the gate oxide layer, the gate electrode and the top gate oxide layer ( Sidewall); the present invention includes the following steps: forming a "poly-silicon intermediate oxide layer" (Inter-Poly Oxide) above the "substrate" and the "gate structure"; Form a "polycrystalline silicon layer" above the "polycrystalline silicon intermediate oxide layer"; implant impurity ions into the "polycrystalline silicon layer"; remove a portion between the gate structure complex "Government intermediate oxide layer" and "polycrystalline silicon layer" to expose the contact area (Contact Area) l above the "polycrystalline silicon layer", the side wall (Spacer) and the "contact window area" Deposit a layer of "Barrier Layer"; deposit a layer of "Tungsten Metal Silicide Layer" (Tungsten Metal Silicide Layer) above the "Barrier Layer" to automatically align it with the "Tungsten Metal Silicide" Form electrical contact between the "contact window areas" and formulate a round plan for the "tungsten metal sand"; deposit a metal layer (Metal Layer) on top of the "tungsten metal silicide" and Dielectric layer (Dielectric Layer) to form a connection (please read the precautions on the back before filling in this page). Order i.! This paper size is applicable to the national standard of China National Standards (CNS) A4 (210X297mm) A8 B8 C8 D8 printed by the Consumer Labor Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs VI. Patent application (Interconnection) and the buried impurity layer in the "tungsten metal silicide" and the "contact window area", (Buried Impurity Lay er) Make electrical contact, and the integrated circuit element is completed in Yan. 2. The manufacturing method as described in item 1 of the patent application scope, wherein the thickness of the "inter-poly oxide" (Inter-Poly Oxide) is between 700 angstroms and 2000 angstroms. 3. The manufacturing method as described in item 1 of the patent application scope, wherein the thickness of the "Barrier Layer" is between 30 angstroms and 100 angstroms. 4. The manufacturing method as described in item 1 of the patent application scope, wherein the thickness of the "polycrystalline silicon layer" is between 500 angstroms and 1000 angstroms. 5 _ The production method as described in item 1 of the patent application scope, wherein the "polycrystalline silicon layer" is applied with a phosphorus ion (P31) ion distribution value, and the ion distribution dosage is between 1E13 and 1E15 atoms / cm2 between. Peak 6. The manufacturing method as described in item 1 of the patent application scope, wherein the impurity ion concentration of the "polycrystalline silicon layer" is between 1E18 and 1E20 atoms / cm3. 7. The manufacturing method as described in item 1 of the patent application scope, wherein the thickness of the "Tungsten Metal Silicide Layer" is between 700 angstroms and 3000 angstroms. 8. The manufacturing method as described in item 1 of the patent application scope, wherein the side wall (Spacer) is composed of dioxide sand. 9. A method for manufacturing an integrated circuit element, which includes an automatic alignment contact window area formed between two gate structures on a semiconductor substrate (Semiconductor Substrate); and "Analytical Structure" contains a side wall (Spacer); the present invention includes the following steps. The paper size is applicable to the Chinese rubbing rate (CNS> A4 specification (210X297 mm) (please read the precautions on the back and fill in this page) Printed A8 Β8 C8 __ D8 printed by the Employee Consumer Cooperative of the Central Ministry of Economic Affairs of the Ministry of Economic Affairs. Six, the scope of patent application: Form a "polycrystalline silicon intermediate oxide layer" above the "substrate" and the "gate structure" ( Inter-Poly Oxide); forming a "polycrystalline sand layer" above the "polycrystalline silicon intermediate oxide layer"; implanting impurity ions into the "polycrystalline silicon layer"; removing the area in the contact window area Between the gate structure (Gate Structure) part of the "polycrystalline silicon intermediate oxide layer" and "polycrystalline silicon layer" to expose the contact area (Contact Area) and the side wall (Spacer); in the A layer of "Barrier Layer" is deposited above the "polysilicon layer", the side wall (Spacer) and the "contact window area"; a layer of "first metal silicide" is deposited above the "barrier layer" First Metal Silicide Layer ”to form an electrical contact between the“ First Metal Silicide Layer ”and the“ Contact Window Area ”that is automatically aligned, to formulate the“ First Metal Silicide Layer ” Pattern of the "thing"; deposit a metal layer (Metal Layer) and a dielectric layer (Dielectric Layer) on top of the "first metal silicide" to form the connection (Interconnection) with the "first metal silicide" 『For electrical contact, the integrated circuit element is completed in Yan. 10 ･ The manufacturing method as described in item 9 of the patent application scope, wherein the substrate (Substrate) contains a buried impurity layer (Buried Impurity Layer). The manufacturing method described in item 9 of the patent scope, wherein the "gate structure" contains a first gate oxide layer (First Gate Oxide) and a polysilicon gate (Polysilicon Gat) formed above the "nuclear oxide layer" e) The standard paper format is applicable to the Chinese National Standard (CNS) A4 format (210Χ297mm) (please read the precautions on the back before filling in this education). Packing and Ordering 8888 ABCD Printed by the Employee Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs 6. The patent application scope is the top gate oxide layer (T〇pGate 0xide) above the polycrystalline silicon gate and the side walls formed on the oxide oxide layer, the polycrystalline sand gate and the top metal oxide layer. (Si dewa 11) the side wall (Spacer) ° 12. The manufacturing method as described in item 9 of the patent application scope, wherein the side wall (Spacer) is composed of dioxide sand. 13 · The manufacturing method as described in item 9 of the patent application scope, wherein the "polycrystalline silicon layer" is applied with a phosphorus ion (P31) or arsenic ion (As75) ion distribution value, and the ion distribution dosage is between 1E13 To 1E15 atoms / cm2, the ion distribution energy is between 30 and 80 kev. 14. The manufacturing method as described in item 9 of the patent application scope, wherein the impurity ion concentration of the "polycrystalline silicon layer" is between 1E18 and 1E21 atoms / cm3. 15. The production method as described in item 9 of the patent application scope, wherein the "First Metal Silicide Layer" is composed of Tungsten Silicide. 16. The manufacturing method as described in item 9 of the patent application scope, wherein the thickness of the "Inter-Poly Oxide" is between 700 Angstroms and 2000 Angstroms. Π _ The production method as described in item 9 of the patent application scope, wherein the thickness of the "Barrier Layer" is between 30 Angstroms and 100 Angstroms. 18. The manufacturing method as described in item 9 of the patent application scope, wherein the thickness of the "polycrystalline silicon layer" is between 500 angstroms and 1000 angstroms. 19. The manufacturing method as described in item 9 of the patent application scope, wherein the "polycrystalline silicon layer" is applied with a phosphorus ion (P31) ion cloth, and the ion cloth dose is between (please read the note on the back first Please fill in this page for details)-Binding and Ordering J This paper size is used in the national standard (CNS) A4 specification (210X297 mm) A8 B8 C8 D8 6. The patent application range is between 1E13 and 1E15 atoms / square centimeter. 2〇 The manufacturing method as described in item 9 of the patent application scope, wherein the impurity ion concentration of the "polycrystalline sand layer" is between 1E18 and 1E20 atoms / cm3. 21. The manufacturing method as described in item 15 of the patent application scope, wherein the thickness of the "Metal Silicide" is between 700 angstroms and 3000 angstroms. (Please read the precautions on the back before filling out this page) Printed by the Beigong Consumer Cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs This paper scale is applicable to the Chinese National Standard (CNS) A4 specification (210X297 mm)