經濟部中央標準局負工消t合作.社印製 3018^0 A7 _________ B7 五、發明説明（f ) 本發明係直接關於一容許輸出節點過量負突波的半橋 式架構功率電晶體之驅動方法及電路，這個電路亦可應用 於單一矽晶片之類的積體電路上運作。 在功率電晶體的驅動電路中，例如、功率金氧半場效 電晶體（Power M0SFET)驅動的電力配備，功率電晶禮在 切換時經常產生極大的電流，此一大電流結合電路中二極 趙正向迴復特性及漏電感造成的負向暫態效應會在半橋式 輸出節點產生火花信號，這些火花信號對驅動電路具破壞 性且易形成雜訊。 依照上述，本發明主旨在於提供一容許輸出節點過度 負量突波的半橋式架構功率電晶髏之驅動方法與電路。 此外’本發明之另一主旨在於可以將此一電路作在一 片單一積體晶片上。 構成本發明之上述主旨和其它主旨方法之一爲：將第 一個和第二個功率電晶體以半橋式架構聯接、輸出節點接 於兩電晶體間、將這組串聯的電晶體接在第一個電壓源與 一共同電位、提供第二個電壓源、將功率電晶體驅動電路 的本質二極體的陽極之共同接點視爲一端，再將第二個電 壓源接在此端與共同電位之間，如此此端的電壓準位便會 偏移使得二極體在負向暫態時不會發出偏差。這種半橋式 架構允許輸出節點過量負突波。 構成本發明的上述主旨和其它主旨的另一方法爲：將 第一個和第二個功率電晶體以串聯式半橋式架構聯接以允 (請先閱讀背面之注意事項再填寫本頁) 訂 A7 A7 經濟部中央椁準局員工消費合作，壮印製 B7 五、發明説明（卞） 許半橋式架構的電晶體間之輸出節點過量負突波。其串聯 的電晶體係接在第一個電壓源與共同電位之間，這個電路 並包含：每一功率電晶體的驅動電路、將功率電晶體驅動 電路的本質二極趙的陽極之共同接點連接爲一端、再將第 二個電壓源改裝接在此端與共同電位之間，如此此端的電 壓準位便會偏移使得二極體在負向暫態時不會發出偏差。 本發明的上述主旨和其它主旨亦宣告如下：單一晶片 積鍾電路可以允許半橋式架構兩電晶體間之輸出節點過量 負突波的電路組成如下： 將第一個與第二個功率電晶體安排成串聯的半橋式架 構，其輸出接點介於兩電晶體中間； 提供第二個電壓源； 將功率電晶體驅動電路的本質二極體的陽極之共同接 點連耦合爲一端； 再將第二個電壓源改裝接在上述端點與上述共同電位 之間，如此此端的電壓準位便會偏移使得上述的二極體在 負向暫態時不會發出偏差。 本發明的上述主旨和其它主旨亦作另一聲明如下：單 一晶片積體電路允許半橋式架構兩電晶體間之輪出節點過 量負突波，串聯的電晶體係轉接在第一個電壓源與一此 電位之間，此電路並包括： 、 ，、同 每一個功率電晶體的個別驅動電路； 將功率電晶體驅動電路的本質二極體的陽極 點連耗合爲-端； 同接Printed by the Central Standards Bureau of the Ministry of Economic Affairs. 3030 ^ 0 A7 _________ B7. V. Description of the Invention (f) The present invention is directly related to the driving of a half-bridge architecture power transistor that allows excessive negative surges at the output node. Method and circuit. This circuit can also be applied to integrated circuits such as single silicon chips. In the driving circuit of power transistors, for example, the power equipment driven by power MOSFETs, Power transistors often generate extremely large currents during switching. This large current is combined with the second pole in the circuit. The negative transient effect caused by the positive recovery characteristic and the leakage inductance will generate spark signals at the half-bridge output node. These spark signals are destructive to the drive circuit and easily form noise. According to the above, the main purpose of the present invention is to provide a driving method and circuit of a half-bridge architecture power transistor that allows excessive negative surges at the output node. In addition, another aspect of the present invention is that this circuit can be made on a single integrated chip. One of the above-mentioned subject and other subject methods constituting the present invention is: connecting the first and second power transistors in a half-bridge architecture, connecting the output node between the two transistors, and connecting the series of transistors in series The first voltage source and a common potential provide a second voltage source. The common contact of the anode of the essential diode of the power transistor drive circuit is regarded as one end, and then the second voltage source is connected to this end and Between the common potentials, the voltage level at this end will shift so that the diode will not emit deviations in the negative transient state. This half-bridge architecture allows excessive negative surges at the output node. Another method for constructing the above subject and other subjects of the present invention is to connect the first and second power transistors in a series half-bridge structure to allow (please read the precautions on the back before filling this page). A7 A7 Employee consumption cooperation of the Central Bureau of Economic Affairs of the Ministry of Economic Affairs, printing and printing B7. V. Description of Invention (Bian) Excessive negative surges at the output nodes between the transistors of the half-bridge architecture. The series connected transistor system is connected between the first voltage source and the common potential. This circuit also includes: the drive circuit of each power transistor and the common contact of the anode of the power diode drive circuit Connect as one end, and then refit the second voltage source between this end and the common potential, so that the voltage level of this end will shift so that the diode will not emit deviation during the negative transient. The above and other themes of the present invention are also announced as follows: a single chip integrated clock circuit can allow the output node between the two transistors of the half-bridge architecture to have excessive negative surges as follows: The first and second power transistors are composed Arranged in series in a half-bridge architecture, the output contact is between the two transistors; provide a second voltage source; connect the common contact of the anode of the essential diode of the power transistor drive circuit to one end; then The second voltage source is modified and connected between the terminal and the common potential, so that the voltage level of this terminal will be shifted so that the diode will not emit deviation during the negative transient state. The above and other themes of the present invention also make another statement as follows: a single chip integrated circuit allows excessive negative surges in the wheel-out node between two transistors of the half-bridge architecture, and the series-connected transistor system is switched at the first voltage Between the source and this potential, this circuit also includes:,,, and an individual drive circuit for each power transistor; the anode point of the essential diode of the power transistor drive circuit is combined into-terminal; the same connection
(讀先閲讀背面之注意事項再填寫本頁)(Read the precautions on the back before filling in this page)
經濟部中央標準局只工消费合作社印製 A7 B7 五、發明説明（》） --- 再將第二個電壓源改裝接在上迷端點與上述共同電位 之間，如此此端的電壓準位便會偏移使得上述的二極體在 負向暫態時不會發出偏差。 如下對本發明的描述及如附的圖形會使得本發明的特 徵跟優點更加的突出與顯著。 囷式説明： ^ 1(a)顯示安排成半橋式結構的功率金氧半場效電晶 體電路； v囷〗（b)顯示前述人工電路的功率電晶體共同輸出接點 的典型輸出脈沖，圖形中包含一負向的火花； v脣2顯示一典型的半橋式結構的電路，它的界面爲一 1C驅動器以提供信號驅動功率電晶體； v® 3(a)和3(b)爲依照本發明設計的兩種電路安排方式 ’可以允許功率電晶體和驅動電路的輸出接點產生負向火 花而不會造成損害； 顯示圖3(a)或3(b)電路的輸出脈沖，囷中並陳述 本電路發明如何避免驅動器内部二極體順向導通及允許電 路在含有輸出負向突波情形下運作； 顯示一傳统的積體電路驅動器，此電路可以依照 本發明進行修改； \JS6(a)顯示如何將圖3(a)的電路運用在積體電路中； \P6(b)顯示如何將圖3(b)的電路運用在積體電路中。 本紙張尺度场用中阀丨$家標皁（CNS ) 44規格（210X297公货） (請先閱讀背面之注意事項再填寫本頁) 訂 5 經濟部中央標準局負工消费合作社印52 A7 _ B7 -.. . _ ..- __ _____ 五、發明説明（少） 實施例 現在參考囷形1(a)，圖中顯示一典型的半橋式功率電 晶體電路，特別是一组金氧半場效電晶體電路。由電路的 安排可知兩電晶體屬串聯囷騰（totem)極結構，上面的那 顆電晶體10的汲極（drain)接到電壓源VL、下面的那顆電 晶體20的源極（source)接到參考地端、輸出係接到電晶體 10和20間的共同結點且耦連到功率電晶體驅動電路的％腳 ，參考圖2可得到更詳細的資料。 ♦.少圖1(b)所示，半橋式電路的輸出一般均會振盪產生 低於地（com)的電壓，一般高功率電路或高感抗電路的負 向突波均相當高，可能達到數十伏特。 參考圖2 ，半橋式電路的驅動器爲界面晶片25,此晶 片可由國際整流器公司取得，係IR2ll〇，在這樣的一個獨 立的積體晶片25中，^5_玉互巡座皇考ife牴VB的電位差，因 爲供應電位VB亦會低於地端電壓而使得介於和COM間的 本質二極禮22發出偏差。如圖2所示類型的堪動電路中， 一般而言均會存在本質的或寄生的二極體22，在某些情況 下羞· 4極體的順向偏壓會造成極巨大的電流而傷害到二極 渡或電路的-甚它部赞。除了寄生二極體22之外，VDD和COM 間的寄生二極體28與VCC和COM間的寄生二極體30亦存在。 圖5爲一傳統界面晶片25的細部圖。特別的是，囷5仔 細地展示出傳統- 211〇積體電路驅動裝置，這個裝置可 以根據囷3(a)和圖3(b)所示的電路發明修改。 圖5顯示的爲囷2中的積體電路25的功能方塊圖。邏輯 f靖先閱讀背面之注意事項再填寫本頁) 訂 本紙張尺度適用中囚阀家標4<— ( CNS )八4规格（2丨〇y 2y?公#1 .) A7 B7 經濟部中央標準局貝工消費合作社印製 五、發明説明（< )輸入腳10, 11和12經由斯密特觸發器（schlBitt trigge]r) 32X，32Y和32Z接到RS閂32T, 32U和邏輯電路32V與32W， 邏輯電路32V與32W的輸出分別耦連到準位平移電路33八與 33B，準位平移電路331與3邪的輸出用以分別控制上端的 控制輸出腳7與下端的控制輸出腳1。 低壓通道中的準位平移電路33B的輸ά通過延遲電路 26Α與閘電路26Β的一輸入端，閘26Β的輸出係連接到驅動 器輸出金氧半場效電晶體26C與26D的閘極，下面會提到·· 這些電晶體會依邏輯輸入腳與12產生腳1的閘電壓(l OUT)。 囷5電路也包函一低電壓偵測電路27，它可在腳3產生 低電魔·時使閘26B的輸出禁能以避免打開功率金氧半場效 電晶體或腳1的IGBT操作。 高壓通道中的準位平移電路33A的一輸入端接到脈沖 產生器24A，電壓偵測電路27亦接到脈沖產生器24A，當它 偵測到腳3(VCC)低電壓會關閉高壓輸出通道。 脈沖產生器24A有兩個輸出，其一爲輸出立（s)，接到 金氧半場效電晶體24B的閘極’另一爲輸出復立（R)，接到 金氧半場效電晶體24C的閘極。 金氧半場效電晶體24B和24C的源極接地而它們的没極 分別接到電阻24D和24E。 正常操作時，脈沖產生器24A會在金氧半場效電晶體 24B和24C與電阻24D和24E間產生輸出電壓脈沖vset和Vrst 〇 7 (請先閱讀背面之注意事項再填寫本頁) 訂 本紙張尺度適用中國國家標準（CNS ) Λ4規格（：!丨OX2(>7公筇） 經濟部中央標準局，ΛΧ消费合作社印製 301620 A7 B7 五、發明説明（k) 然後，脈沖Vset和Vrst會通過一脈沖滤波器24F ’滅 波器24F的輸出通道接到閂24G的R和S輸入端，閂24G的輪 入端連接到第二個低電壓偵測電路24H，以保證當腳6偵測 到低壓時腳7不會輸出任何信號。 RS閂24G的輸出則是用以打開或關閉驅動器金氧半場 效電晶體241和24J，因此，若閂24G的輸入R爲正則腳7的 輸出爲負，若閂24G的輸入S爲正則脚7的輸出爲正。 如同圖2所示，囷5顯示B與COM之間存在内部二極艘 22 °此外，VDD與COM及VCC與COM間也可發現内部的二椏微 ，請參考圖5的二極體28與30。 囷3(a)與3(b)爲兩個例子用以告訴我們如何可以用一 種比較安全的方式操作半橋式組合的電晶體，使得輸出接 點的負向火花不會傷害到驅動器電路，由這些電路囷可知 如何按照本發明修改電路圖5,使用圖3(a)和3(b)兩電路 的任一均可以增加電晶體1〇和2〇間輸出可容許的負向突波 〇 依照本發明，本質二級體22，28和30，按照囷形所示 它們是一定存在的，其共同陽極接點的電位比驅動器電路 26下方地端還低Vsub的電壓，如圖所示，此飆移電壓供應 源Vsub的極性安排會使得本質二級體22，28和30的陽極對 地的位能爲負電位一 \rsub，這樣的結構在一般的應用中可 以容許輸出VS產生負向脈衝。 電路囷3(a)與3(b)的唯一不同在於其輸入邏輯電路32a 與32b的參考電壓不同，在電路圖3(a)與3(b)中並未顯示界 (請先閲讀背面之注意事項再填寫本頁) 、-° 本紙張尺度適汛中國國家標牟（CNS ) Λ4現格（21()X297公箱） A7 _______B7_____ 五、發明説明) 面電路25的細部囷，要參考細部囷請見囷5，在電路圖3(a) 與3(b)中需要適當的準位偏移電路以提供由輸入電路323與 32b到驅動電路24與26的驅動信號。這些準位偏移電路的 種類可以如同應用序號Πί-〗〗22發明中所描述的那種，在 這褢我們可以同時參考它們。 在電路圖3(a)中，輸入電路32a的基準電位並非爲-VsuY，依此，在電路圖3(a)中，畢位至必要的 ，因爲它可以改變輸入電路32a的輸出的參考準位爲 。準位偏移電路4〇的輸出係耦連到缓衝器41,缓衝器41的 輸出Μ連到準位偏移電路44與42，举位偏移電路42用以搞 二Isjik这JtAiiiXnQIl络並鱼矍复爵下方t路26 ’準路Ml蜞將參考電壓由-Vsub改變成VB以推 fe&iLlfeJ：*蹲 24 〇 輕濟部中央榡隼局員工消赀合作社印繁 (請先閱讀背面之注意事項再填寫本頁) 在電路圖3(b)中，既然輸入電路32b的參考電壓已經 是-Vsub，因此只須要兩個準位偏移電路，其一爲（46)用 以將輸入電路的輸出調整爲參考地端（COM)電壓以推動驅 動器下方電路26，另一爲（48)用以將輸入電路的輸出調整 爲參考驅動器上方電路28的VB端電壓。 因爲電路圖3(a)與3(b)中1«_;&髓22陽趣放赴參考 造農复良在至爲二Isilb ’當VS電壓介於地與-Vsub之間時 二極體並不會順向導通。詳細波形可見圖4，標記爲VS的 輸出其負向脈衡電壓大於-Vsub，故會避免二極體發出偏 差。如此，前述電路圖2中由於内部二極髏發出偏差而產 生的高電流情況將不再發生。 本紙張尺度適州中囡阀孓標準（CNS ) Λ4%格（210X 2们.公费） 301820 A7 B7_ 五、發明説明（f ) V圖6(a)與6(b)顯示如何將圖3(a)與3(b)中對應的部份 電路實際應用在積體電路上，圖6(a)爲圖3(a)的部份電路 而圖6(b)爲圖3(b)的部份電路，兩個電路的結構基本上是 相同的，唯一的不同是不同的電位點接到不同的端點，這 些部份請參考圖6(a)與6(b)。現在我們即將闞述圖6(a)， 爲了簡單起見，囷6(b)將不作進一部的敘述，讀者可借由 比較兩圖形觀察其電位的差異。 應用圖3(a)的電路於單一晶片上時，其高低電壓電路 部份是分開的，圖6(a)爲晶片一部的橫切面，依囷，矽晶 片120含有一P-基座121，之上爲一N-矽磊晶層122，經 由P+下沉區130, 131和132，N—區122被刻分爲高壓區與 低壓區，如此，下沉區130和131可在磊晶層122上定義出 高壓元件區140，其與低壓元件區是分開的，區域140與141 可以具有任意的特性，此外，任何絕緣的技巧均可用於區 域140與141之間。 如圖3(a)中的典型電路24，金氧半場效電晶體驅動電 路由P通道與N通道金氧半場效電晶體組成，這點可以參考 正在t請中的專利，委托人申請编號08/274,012(IR-1131 )，本項發明的應用可同時參考之。圖3(a)中的金氧半場 效電晶體驅動電路的高壓電路作在高壓區14〇中，擴散在 層122的P +接觸區162與163便是代表驅動器元件24的任意 P通道金氧半場效電晶體的汲極與源極，擴散在層122的P 區164形成P型井區，擴散在p型井區接觸區16〇與161 是代表囷3(a)中驅動器元件24的任意N通道金氧半場效電 —____10____ 本紙乐尺度適用中®园家標嗥（CNS ) Λ4規格（2丨0>< 297公筇） ----------!〉------訂------i I (讀先閱讀背面之注意事項再填寫本頁) 經濟部中夹榡率局員工消贤合作枉印製 經濟部中央標準局只工消费合作社印製 A7 B7 —> ____— ----------- " "" — - " 五、發明説明（^ ) 晶體的没極與源極° 、知囷3(a)的電路24也含有低壓部份，此低壓區亦含有 其P通道與N通道金氧半場效電晶體，囷3(a)中驅動器元件 24的金氧半場效電晶體低壓控制電路的圖形可參考區域141 ，N +接觸區125擴散在區域141上且接到電位VI的電極上， 如同高壓區140的擴散層160到164，低壓控制區亦會含有它 自己的低壓電晶體擴散層，只是，低壓控制區的N+與P + 擴散層電極的電位會落在-Vsub與VI之間，這些擴散層即 是代表圖3(a)低壓金氧半場效電晶體的源極與汲極。 N +接觸區126與127擴散於層122中，其電極的電位介 於VB(615V)與VS(600V)之間，P+下沉區 130，131 與 132電 極的電位爲-Vsub，P(-）再鋪裝區150與151將高壓區]4〇 圈起以與低壓區絕緣0 和傳統元件相同地，所有位於矽表層的元件都鋪上一 層介質，例如厚度1.5毫米的低溫矽二氧化物層〗80，所有 表面電極的接觸點滲透到介質層中並連接到未圖示的外接 腳。 囷6(a)完整晶片的上表層會覆蓋一層塑膠外殼π】， 外殼的成份可以是任意合適的絕緣物質，市面上销售的Printed by the Central Standards Bureau of the Ministry of Economic Affairs, only the Consumer Cooperative Society A7 B7 V. Description of the invention (》) --- Then refit the second voltage source between the upper fan terminal and the above common potential, so the voltage level at this terminal It will shift so that the above-mentioned diode will not emit a deviation during the negative transient. The following description of the present invention and accompanying figures will make the features and advantages of the present invention more prominent and significant. Explanation of the formula: ^ 1 (a) shows the power metal oxide half field effect transistor circuit arranged in a half-bridge structure; v 囷〗 (b) shows the typical output pulse of the common output contact of the power transistor of the aforementioned artificial circuit, graphics It contains a negative spark; vlip 2 shows a typical half-bridge structured circuit, and its interface is a 1C driver to provide a signal to drive the power transistor; v® 3 (a) and 3 (b) are in accordance with The two circuit arrangements designed by the present invention can allow the power transistor and the output contact of the drive circuit to generate negative sparks without causing damage; show the output pulses of the circuit of Figure 3 (a) or 3 (b). It also describes how the invention of this circuit can avoid the forward conduction of the internal diode of the driver and allow the circuit to operate in the case of including a negative-going surge; show a traditional integrated circuit driver, this circuit can be modified according to the present invention; \ JS6 ( a) Shows how to use the circuit of Figure 3 (a) in an integrated circuit; \ P6 (b) shows how to use the circuit of Figure 3 (b) in an integrated circuit. This paper standard field valve 丨 $ Home standard soap (CNS) 44 specifications (210X297 public goods) (please read the precautions on the back and then fill out this page). Order 5 Printed by the Ministry of Economic Affairs Central Standards Bureau Negative Work Consumer Cooperative 52 A7 _ B7-.. _ ..- __ _____ V. Description of the invention (less) The embodiment now refers to Fig. 1 (a), which shows a typical half-bridge power transistor circuit, especially a group of metal oxide half-fields Effective transistor circuit. It can be seen from the arrangement of the circuit that the two transistors belong to a series totem pole structure, the drain of the upper transistor 10 is connected to the voltage source VL, and the source of the lower transistor 20 Connected to the reference ground, the output is connected to the common node between the transistors 10 and 20 and is coupled to the% pin of the power transistor drive circuit. Refer to FIG. 2 for more detailed information. ♦ As shown in Figure 1 (b), the output of the half-bridge circuit generally oscillates to produce a voltage lower than ground (com). Generally, the negative surge of a high-power circuit or a high-inductance circuit is quite high, which may be Reach dozens of volts. Referring to FIG. 2, the driver of the half-bridge circuit is the interface chip 25, which can be obtained by International Rectifier Co., Ltd., which is IR2110. In such an independent integrated chip 25, ^ 5_ 玉 互 巡 座 皇考The potential difference of VB, because the supply potential VB will also be lower than the ground voltage, causes a deviation between the essential diode 22 and COM. In the type of circuit shown in Figure 2, generally there will be an essential or parasitic diode 22, in some cases, the forward bias of the 4-pole body will cause a huge current and It hurts to the dipolar crossing or the circuit-even it's a tribute. In addition to the parasitic diode 22, a parasitic diode 28 between VDD and COM and a parasitic diode 30 between VCC and COM also exist. FIG. 5 is a detailed view of a conventional interface wafer 25. In particular, Fig. 5 shows the conventional-211〇 integrated circuit driving device in detail, and this device can be modified according to the circuit invention shown in Fig. 3 (a) and Fig. 3 (b). FIG. 5 shows a functional block diagram of the integrated circuit 25 in FIG. 2. Logic f Jing first read the precautions on the back and then fill out this page) This paper size is applicable to the prisoner house standard 4 < — (CNS) 8 4 specifications (2 丨 〇y 2y? 公 # 1.) A7 B7 Central Ministry of Economic Affairs Printed by the Beigong Consumer Cooperative of the Bureau of Standards 5. Description of invention (<) Input pins 10, 11 and 12 are connected to RS latches 32T, 32U and logic circuits via Schmitt triggers (schlBitt trigge) 32X, 32Y and 32Z 32V and 32W, the outputs of the logic circuits 32V and 32W are respectively coupled to the level shift circuits 33 and 33B, and the output of the level shift circuits 331 and 3 are used to control the upper control output pin 7 and the lower control output pin, respectively. 1. The input of the level shift circuit 33B in the low-voltage channel passes through an input terminal of the delay circuit 26A and the gate circuit 26B, and the output of the gate 26B is connected to the gates of the driver output MOSFETs 26C and 26D. To ... These transistors will generate the gate voltage (l OUT) of pin 1 according to the logic input pin and 12. The circuit 5 also includes a low voltage detection circuit 27, which can disable the output of the gate 26B when pin 3 generates a low voltage to avoid turning on the power MOSFET or pin 1 IGBT operation. An input terminal of the level shift circuit 33A in the high voltage channel is connected to the pulse generator 24A, and the voltage detection circuit 27 is also connected to the pulse generator 24A. When it detects a low voltage at pin 3 (VCC), the high voltage output channel is closed . The pulse generator 24A has two outputs, one of which is the output stand (s), which is connected to the gate of the metal oxide semi-field effect transistor 24B, and the other is the output compound (R) which is connected to the metal oxide half field effect transistor 24C Gate. The source electrodes of the metal oxide half field effect transistors 24B and 24C are grounded and their non-electrodes are connected to the resistors 24D and 24E, respectively. During normal operation, the pulse generator 24A will generate output voltage pulses vset and Vrst between the metal oxide semi-field effect transistors 24B and 24C and the resistors 24D and 24E (please read the precautions on the back before filling in this page) Order this paper The standard is applicable to the Chinese National Standard (CNS) Λ4 specification (!! OX2 (> 7 Gongqiang) Central Bureau of Standards, Ministry of Economic Affairs, 301620 A7 B7 printed by the ΛΧconsumer cooperative. V. Invention description (k) Then, pulse Vset and Vrst meeting The output channel of the wave breaker 24F through a pulse filter 24F is connected to the R and S input terminals of the latch 24G, and the in-turn end of the latch 24G is connected to the second low voltage detection circuit 24H to ensure the detection of the foot 6 When the low voltage is reached, pin 7 will not output any signal. The output of RS latch 24G is used to open or close the driver MOSFETs 241 and 24J. Therefore, if the input R of latch 24G is positive, the output of pin 7 is negative. If the input S of the latch 24G is positive, the output of the pin 7 is positive. As shown in Figure 2, 5 shows that there is an internal diode 22 ° between B and COM. In addition, VDD and COM and VCC and COM can also be found For the internal dichotomy, please refer to diodes 28 and 30 in Figure 5. 囷 3 (a ) And 3 (b) are two examples to show us how to operate the half-bridge combined transistor in a safer way, so that the negative spark of the output contact will not harm the driver circuit. It can be seen how to modify the circuit diagram 5 according to the present invention. Using either circuit of FIGS. 3 (a) and 3 (b) can increase the tolerable negative surge between the transistors 10 and 20. According to the present invention, the essence The secondary bodies 22, 28 and 30, as shown in the figure, they must exist. The potential of the common anode contact is lower than the ground terminal of the driver circuit 26 by a voltage of Vsub. As shown in the figure, this surge voltage supply The polarity arrangement of the source Vsub will make the potential of the anodes of the essential secondary bodies 22, 28, and 30 to the negative potential -rsub, such a structure can allow the output VS to generate negative pulses in general applications. The only difference between (a) and 3 (b) is that the reference voltages of the input logic circuits 32a and 32b are different, and the boundaries are not shown in the circuit diagrams 3 (a) and 3 (b) (please read the precautions on the back before filling in This page),-° This paper scale is suitable for flooding China National Standard Mou CNS) Λ4 present grid (21 () X297 public box) A7 _______B7_____ V. Description of the invention) The details of the surface circuit 25. Please refer to the details of the details of the circuit 25. Please refer to the circuit diagram 3 (a) and 3 (b). To provide a driving signal from the input circuits 323 and 32b to the driving circuits 24 and 26. The types of these level shift circuits can be the same as those described in the application serial number 22-22, and we can refer to them at the same time. In the circuit diagram 3 (a), the reference potential of the input circuit 32a is not -VsuY. Therefore, in the circuit diagram 3 (a), it is necessary to complete the bit because it can change the reference level of the output of the input circuit 32a to . The output of the level shift circuit 40 is coupled to the buffer 41, and the output M of the buffer 41 is connected to the level shift circuits 44 and 42, and the position shift circuit 42 is used to implement two Isjik JtAiiiXnQIl networks. The 26th quasi-channel Ml at the lower part of the monk fisherman ’s complex will change the reference voltage from -Vsub to VB to push the fe & iLlfeJ: * squat 24 〇The employees of the Central Falconry Bureau of the Ministry of Light Economy will be printed by the cooperative (please read first (Notes on the back and then fill in this page) In the circuit diagram 3 (b), since the reference voltage of the input circuit 32b is already -Vsub, only two level shift circuits are needed, one of which is (46) to input The output of the circuit is adjusted to the reference ground (COM) voltage to drive the circuit 26 below the driver, and the other is (48) to adjust the output of the input circuit to the voltage of the VB terminal of the circuit 28 above the reference driver. Because in the circuit diagrams 3 (a) and 3 (b), 1 «_; & marrow 22 Yangqu is put to the reference of the agriculture and agriculture, good for the two Isilb 'when the VS voltage is between the ground and -Vsub diode It will not follow the guide. The detailed waveform can be seen in Figure 4. The output marked as VS has a negative pulse balance voltage greater than -Vsub, so it will avoid the deviation of the diode. In this way, the high current situation caused by the deviation of the internal diode in the aforementioned circuit diagram 2 will no longer occur. The size of this paper is suitable for the state standard (CNS) Λ4% grid (210X 2 people. Public expense) 301820 A7 B7_ V. Description of the invention (f) V Figures 6 (a) and 6 (b) show how to use Figure 3 ( a) Part of the circuit corresponding to 3 (b) is actually applied to the integrated circuit. FIG. 6 (a) is the part of the circuit of FIG. 3 (a) and FIG. 6 (b) is the part of FIG. 3 (b). The structure of the two circuits is basically the same. The only difference is that different potential points are connected to different endpoints. For these parts, please refer to Figures 6 (a) and 6 (b). Now we are going to describe Fig. 6 (a). For simplicity, Fig. 6 (b) will not be included in the description. The reader can observe the difference in potential by comparing the two graphs. When applying the circuit of FIG. 3 (a) on a single chip, the high and low voltage circuit parts are separated. FIG. 6 (a) is a cross section of a part of the chip. The silicon chip 120 includes a P-base 121 , On top of which is an N- silicon epitaxial layer 122, through P + sinking regions 130, 131 and 132, N- region 122 is engraved into a high-voltage region and a low-voltage region, so that the sinking regions 130 and 131 can be epitaxial The layer 122 defines a high-voltage device region 140, which is separate from the low-voltage device region. The regions 140 and 141 can have any characteristics. In addition, any insulation technique can be used between the regions 140 and 141. As shown in the typical circuit 24 in FIG. 3 (a), the metal oxide half field effect transistor driving circuit is composed of a P channel and an N channel metal oxide half field effect transistor. This can be referred to the patent under application, the client applies for the number 08 / 274,012 (IR-1131), the application of this invention can be referred to at the same time. The high voltage circuit of the metal oxide half field effect transistor drive circuit in FIG. 3 (a) is made in the high voltage region 140. The P + contact regions 162 and 163 diffused in the layer 122 are arbitrary P channel metal oxides representing the driver element 24. The drain and source of the half-field effect transistor are diffused in the P region 164 of the layer 122 to form a P-type well region, and the diffusion regions in the p-type well region contact regions 16 and 161 represent any of the driver elements 24 in Fig. 3 (a). N-channel gold-oxygen half field effect electricity —____ 10____ This paper music standard is applicable to ® Garden House Standard (CNS) Λ4 specification (2 丨 0 > < 297 public feast) ----------!〉 --- --- Subscribe ------ i I (Read the precautions on the back and then fill out this page) Printed by the Ministry of Economic Affairs of the Central Bureau of Economic Affairs of the Central Standards Bureau of the Ministry of Economic Affairs A7 B7 — > ____— ----------- " " " —-" Fifth, the description of the invention (^) The crystal's electrode and source pole °, Zhiji 3 (a) The circuit 24 also contains a low-voltage part, and this low-voltage region also contains its P-channel and N-channel metal-oxide half-field transistors. For the graphics of the low-voltage control circuit of the metal-oxide half-field transistor of the driver element 24 in Figure 3 (a), refer to region 141, the N + contact region 125 diffuses on the region 141 and is connected to the electrode of the potential VI. Like the diffusion layers 160 to 164 of the high voltage region 140, the low voltage control region will also contain its own low voltage transistor diffusion layer, but, The potentials of the N + and P + diffusion layer electrodes in the low-voltage control region will fall between -Vsub and VI, and these diffusion layers represent the source and drain of the low-voltage metal-oxide half-effect transistor of Figure 3 (a). The N + contact regions 126 and 127 diffuse in the layer 122, and the potential of their electrodes is between VB (615V) and VS (600V), and the potential of the P + sink regions 130, 131, and 132 is -Vsub, P (- ) Re-paving areas 150 and 151 enclose the high-voltage area] 4 to be insulated from the low-voltage area. As with traditional components, all components on the silicon surface are covered with a layer of dielectric, such as low-temperature silicon dioxide with a thickness of 1.5 mm Layer 80, all the contact points of the surface electrodes penetrate into the dielectric layer and are connected to external pins (not shown).囷 6 (a) The upper surface of the complete chip will be covered with a plastic shell π], the composition of the shell can be any suitable insulating material, commercially available
Nitto MP- 150SG, Nitto MP—180,和Hysol MG15-F品牌 均可。 M6(a)爲圖3(a)的VB與VS間電路的橫切面，囷3(a)VDD 一VSS與VCC-COM之間的電路都可以用相同的方法建立， 這些電路是相似而分離的，對圖3(a)&VDD一vss電路而言 ---- 11 本紙張尺度適用中國阀家標準（CNS ) Λ4规格（2]OX 297公^~~~ -------— (锖先閲讀背面之注意事項再填寫本頁) 、11 A7 B7 經濟部中央標準扃負工消费合作社印製 Λ i、發明説明) 唯一不同的是圖6(a)標記爲VB的點需連接到VCC或VDD，接 VCC或VDD端視考慮的電路爲VCC-COM或VDD-VSS，而圖6 (a)標記爲VS的點需接到COM或VSS。 圖6(b)爲圖3(b)部份電路的實際結構，除了區域125 耦連到VDD外，它和圖6(a)的電路是相同的，區域130, 1幻 和132仍連接至-Vsub。VB- VS電路顯示在圖3(b)中（闲3(b) 的軀動器24)，同樣的建構方法可應用於VCC-COM電路中（ 圈3(b)的驅動器26)，但是圖6(b)標記爲VB的點需連接到 VCC而標記爲VS的點需耦連到COM。 至此，我們已提出一個容許輸出電壓過量負突波而不 會造成任何損害的半橋式結構功率電晶體驅動電路與設計 方法，這個方法的好處之一是可以用建立在如矽晶片上的 單一積體晶片上。舉例而言，它可用在傳统IH2110金氧丰 場效電晶體驅動晶片的設計上。 雖然本發明已有詳細而具體的闞述，在其它的許多方 面它仍有很多明顯的應用，因此，本發明不僅由上述來規 範，同時應由下面的聲明來規範。 •(請先閲讀背面之注意事項再填寫本頁) 丁 本紙张尺度適用中國因家標準（CNS ) Λ4規格（210Χ297公釐） 經濟部中央標準局員工消費合作社印製Nitto MP-150SG, Nitto MP-180, and Hysol MG15-F brands are available. M6 (a) is the cross section of the circuit between VB and VS in Figure 3 (a). The circuit between VDD-VSS and VCC-COM can be established in the same way. These circuits are similar and separated. Yes, for Figure 3 (a) & VDD-vss circuit ---- 11 This paper size is applicable to China Valve Standard (CNS) Λ4 specification (2) OX 297 ^ ~~~ ------ -— (Read the precautions on the back before filling in this page), 11 A7 B7 Printed by the Central Standards Consumer Labor Cooperative of the Ministry of Economic Affairs Λ i, invention description) The only difference is the point marked VB in Figure 6 (a) It needs to be connected to VCC or VDD. Connect the VCC or VDD terminal to the circuit considered as VCC-COM or VDD-VSS, and the point marked VS in Figure 6 (a) needs to be connected to COM or VSS. Fig. 6 (b) is the actual structure of part of the circuit of Fig. 3 (b), except that the region 125 is coupled to VDD, it is the same as the circuit of Fig. 6 (a), and regions 130, 1 and 1 are still connected to -Vsub. The VB-VS circuit is shown in Figure 3 (b) (idle 3 (b) actuator 24), the same construction method can be applied to the VCC-COM circuit (circle 3 (b) driver 26), but the figure 6 (b) The point marked VB needs to be connected to VCC and the point marked VS needs to be coupled to COM. So far, we have proposed a half-bridge structure power transistor drive circuit and design method that allows excessive negative surge of the output voltage without causing any damage. One of the advantages of this method is that it can be used on a single silicon wafer. On the integrated wafer. For example, it can be used in the design of a traditional IH2110 MOSFET driver chip. Although the present invention has been described in detail and in detail, it still has many obvious applications in many other aspects. Therefore, the present invention is regulated not only by the above, but also by the following statement. • (Please read the precautions on the back before filling in this page) Ding This paper size is applicable to the China In-House Standard (CNS) Λ4 specification (210Χ297mm) Printed by the Employee Consumer Cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs
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