DE3684478D1 - GENERATION OF LOCKING CELLS FOR GATE MATRIX IN CMOS TECHNOLOGY. - Google Patents

GENERATION OF LOCKING CELLS FOR GATE MATRIX IN CMOS TECHNOLOGY.

Info

Publication number
DE3684478D1
DE3684478D1 DE8686430057T DE3684478T DE3684478D1 DE 3684478 D1 DE3684478 D1 DE 3684478D1 DE 8686430057 T DE8686430057 T DE 8686430057T DE 3684478 T DE3684478 T DE 3684478T DE 3684478 D1 DE3684478 D1 DE 3684478D1
Authority
DE
Germany
Prior art keywords
generation
cmos technology
series
gate matrix
earth
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE8686430057T
Other languages
German (de)
Inventor
Martine Bonneau
Garrec Jean-Claude Le
Frank Wallart
Gerard Boudon
Pierre Mollier
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Application granted granted Critical
Publication of DE3684478D1 publication Critical patent/DE3684478D1/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
    • H03K3/353—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of field-effect transistors with internal or external positive feedback
    • H03K3/356—Bistable circuits
    • H03K3/356017—Bistable circuits using additional transistors in the input circuit
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
    • H03K3/353—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of field-effect transistors with internal or external positive feedback
    • H03K3/356—Bistable circuits
    • H03K3/356104—Bistable circuits using complementary field-effect transistors
    • H03K3/356113—Bistable circuits using complementary field-effect transistors using additional transistors in the input circuit

Landscapes

  • Design And Manufacture Of Integrated Circuits (AREA)
  • Shift Register Type Memory (AREA)
  • Logic Circuits (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)

Abstract

Disymmetry is produced in the DC mode by increased pmpedance connected in series with the second stage of the latch cell. The series impedances (R31,R32) are connected in the path for parasitic currents between the positive voltage source (Vdd) and earth (Gnd). When the data input (Do) is at logic one, the path to earth from the voltage source of parasitic current is through the first series resistance (R31) and transistor devices (P36,N33,N32). The first series resistance is embodied as a P-type transistor device (P38) of which the gate is earthed.
DE8686430057T 1986-12-30 1986-12-30 GENERATION OF LOCKING CELLS FOR GATE MATRIX IN CMOS TECHNOLOGY. Expired - Fee Related DE3684478D1 (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
EP86430057A EP0273082B1 (en) 1986-12-30 1986-12-30 A new latch cell family in cmos technology gate array

Publications (1)

Publication Number Publication Date
DE3684478D1 true DE3684478D1 (en) 1992-04-23

Family

ID=8196417

Family Applications (1)

Application Number Title Priority Date Filing Date
DE8686430057T Expired - Fee Related DE3684478D1 (en) 1986-12-30 1986-12-30 GENERATION OF LOCKING CELLS FOR GATE MATRIX IN CMOS TECHNOLOGY.

Country Status (4)

Country Link
US (1) US4988893A (en)
EP (1) EP0273082B1 (en)
JP (1) JPH0736509B2 (en)
DE (1) DE3684478D1 (en)

Families Citing this family (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2824706B2 (en) * 1991-09-27 1998-11-18 三菱電機株式会社 Current source circuit and operation method thereof
JPH0685653A (en) * 1992-05-06 1994-03-25 Sgs Thomson Microelectron Inc Receiver circuit provided with bus keeper feature
FR2692072A1 (en) * 1992-06-05 1993-12-10 Sgs Thomson Microelectronics Bistable scale with reset command.
US5311070A (en) * 1992-06-26 1994-05-10 Harris Corporation Seu-immune latch for gate array, standard cell, and other asic applications
US5345195A (en) * 1992-10-22 1994-09-06 United Memories, Inc. Low power Vcc and temperature independent oscillator
US5485323A (en) * 1993-07-14 1996-01-16 International Business Machines Corporation Method and apparatus for moving a disk drive actuator away from a magnetic latch
JPH07307649A (en) * 1994-05-13 1995-11-21 Fujitsu Ltd Electronic device
GB2292855A (en) * 1994-08-31 1996-03-06 Texas Instruments Ltd CMOS latch suitable for low voltage operation
JPH098612A (en) * 1995-06-16 1997-01-10 Nec Corp Latch circuit
JPH11243326A (en) * 1997-12-24 1999-09-07 Nec Corp Static clutch circuit and static logic circuit
JP4397066B2 (en) * 1999-03-24 2010-01-13 日本テキサス・インスツルメンツ株式会社 Latch circuit
JP2001189423A (en) * 1999-12-28 2001-07-10 Sanyo Electric Co Ltd Semiconductor interpreted circuit
WO2006085383A1 (en) * 2005-02-10 2006-08-17 Fujitsu Limited Information providing system and information providing method
KR101064489B1 (en) * 2005-02-12 2011-09-14 삼성전자주식회사 Bus holder with wide range input and wide range output and tolerant input/output bufffer having the same
KR100643498B1 (en) * 2005-11-21 2006-11-10 삼성전자주식회사 Circuit and method for data bus inversion for use in semiconductor memory
WO2008034184A1 (en) 2006-09-22 2008-03-27 Rpo Pty Limited Waveguide configurations for optical touch systems
US10355671B1 (en) * 2018-06-04 2019-07-16 Little Dragon IP Holding LLC Low power flip-flop circiut

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE2339289C2 (en) * 1973-08-02 1975-02-06 Siemens Ag, 1000 Berlin Und 8000 Muenchen Bistable multivibrator with MNOS transistors
JPS59119917A (en) * 1982-12-27 1984-07-11 Toshiba Corp Logical circuit
US4554664A (en) * 1983-10-06 1985-11-19 Sperry Corporation Static memory cell with dynamic scan test latch
JPS60150324A (en) * 1984-01-18 1985-08-08 Nec Corp Field programmable logic array
JPS60150314A (en) * 1984-01-18 1985-08-08 Mitsubishi Electric Corp D flip-flop circuit
US4558237A (en) * 1984-03-30 1985-12-10 Honeywell Inc. Logic families interface circuit and having a CMOS latch for controlling hysteresis
JPS61113319A (en) * 1984-11-07 1986-05-31 Mitsubishi Electric Corp Holding circuit
US4794283A (en) * 1987-05-26 1988-12-27 Motorola, Inc. Edge sensitive level translating and rereferencing CMOS circuitry

Also Published As

Publication number Publication date
US4988893A (en) 1991-01-29
JPH0736509B2 (en) 1995-04-19
EP0273082A1 (en) 1988-07-06
EP0273082B1 (en) 1992-03-18
JPS63175514A (en) 1988-07-19

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee