TW301789B - - Google Patents

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Publication number
TW301789B
TW301789B TW084109292A TW84109292A TW301789B TW 301789 B TW301789 B TW 301789B TW 084109292 A TW084109292 A TW 084109292A TW 84109292 A TW84109292 A TW 84109292A TW 301789 B TW301789 B TW 301789B
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TW
Taiwan
Prior art keywords
dielectric layer
item
layer
line
semiconductor
Prior art date
Application number
TW084109292A
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English (en)
Original Assignee
Texas Instruments Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Publication date
Priority claimed from US08/250,137 external-priority patent/US5527737A/en
Application filed by Texas Instruments Inc filed Critical Texas Instruments Inc
Application granted granted Critical
Publication of TW301789B publication Critical patent/TW301789B/zh

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    • H—ELECTRICITY
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    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
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    • H01L21/02107—Forming insulating materials on a substrate
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    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/02126—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
    • H01L21/02134—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC the material comprising hydrogen silsesquioxane, e.g. HSQ
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    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
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    • H01L21/31612—Deposition of SiO2 on a silicon body
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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Formation Of Insulating Films (AREA)

Description

經濟部中央標準局員工消費合作社印製 A7 B7 五、發明説明（1 ) 本專利申請案爲另一申請案的延序。該案之編號爲 08/250,137，列檔日期爲 05/27/94，明稱"Selective Formation of Low-
Density, L o w - D i e 1 e c t r i c Constant Insulators in Narrow Gaps for Line-to-Line Capacitance Reduction." 可資參考之相關申請案 下列申請案指定予共同之受讓人因此在此列爲參考 編號 列檔日期 T I案例號碼 0 8 / 2 4 7 / 1 9 5 0 5 / 2 0 / 9 4 T I - 1 9 8 4 1 08/246/432 0 5 / 2 0 / 9 4 T I - 1 9 0 7 2 下列申請案與本案同時列檔因此在此亦列爲參考 TI-19179，Gnade等人所有標題爲 Low Dielectric
Constant Layer via Immiscible Sol-Gel Processing T I - 1 9 3 0 5 Havemann等人所有標題爲 Multilevel Interconnect Structure with AirGaps Formed Between Metal Leads 發明領域 本案係有關於半導體製程，特別是在半導體中減低線 至線間電容的半導體製程。 發明背景 半導體廣汎的應用於電子應用中的積體電路，包含高 速電腦及無限電通訊。基本上此積體電路使用多個製在單 4 本紙張尺度適用中國國家標準（CNS ) Α4规格（210Χ297公釐） ---------f -装丨-：-----訂-----線 ·-"0 (請先閱讀背面之注意事項再填寫本頁) 經濟部中央標準局貝工消费合作社印製 A7 __B7 _ 五、發明説明（2 ) 晶矽中的電晶體。現今有多個積體電路包含多個交互連結 用的金屬位準》單一電晶體微晶片可含有上千甚至百萬的 電晶體。因此單一的微晶片亦可含有上 百萬條線以連結電晶體。單裝置的幾何構造縮小而功 能密度增加的時候，不可避免的必需減低線與線之間的電 容。線至線間之電容位在裝置性能爲延遲時間及串音所阻 擾之點。減低這些多階金屬系統的電容將減低RC常數， 串音，及線至線間的功率消散。基本上用於使金屬線之間 互相隔離的材料爲二氧化矽，其爲一熱及化學穩定之材 料。傳統上氧化物蝕刻可用於高方位比（aspect ratio) 之接點。 然而爲熱氧化或化學蒸發沉積所長成的高密度矽之氧 化物的介質常數大小約爲3. 9。1.0之介質常數代表眞 空。在本文中所謂的低介質常數意謂者該値小於3_7。 最近，希望能使用低密度材料如低介質常數的氣凝膠 (aerogel)取代高密度的矽之氧化物。多孔二氧化矽如 氣凝膠的介質常數低至1.2。如此低的介質常數導至RC 延遲時間減低。然而傳統上製造氣凝膠的方法需要超臨界 乾燥步驟，此增加半導體製造的複雜度及成本。 發明槪述 本發明爲在金靥線之間選擇性的形成一低密度低介質 常數之絕緣體的嶄新方法，其可減低線至線之間的電容。 首先多個交互連結的線在半導體中形成。然後介電材料層 5 本紙張尺度適用中國國家標準（CNS ) Α4規格（210Χ297公嫠） ---------{-装------訂-----線 • λ 0 0 < > (請先閲讀背面之注意事項再填寫本頁) 經濟部中央標隼局員工消費合作社印製 A7 B7 五、發明説明（3 ) 覆在半導體及多個交互連結線上其厚度足以充塡連結線之 間的間隙。先將低介質層材料予以烘烤，隨後在高於烘考 的上生溫度中與以固化。經游烘烤及固化，在間隙內的介 質層材料的密度低於上述之互連線及其在開放領域中的密 度。最適合的方法是應用背鈾刻從互連線的頂部移除低介 質層材料。最後在互連線及低介質層材料上沉積一層二氧 化矽。 間隙及開放領域之間的密度差過濾蝕刻法而得到更進 一步的改進，其中在間隙中蝕刻多孔性材料快於在開放領 域中鈾刻少孔性材料。本發明的一項優點爲提供一金屬化 方法可減低線至線之間的電容。本發明的另一項優點爲提 供一金屬化方法可減低串音及功率逸散。本發明的另一項 優點爲在互連線之間提供一介質層層，其介質常數低於高 密度的二氧化矽。 圖形簡述 圖1爲多階互連裝置的方塊圖； 圖2爲本發明互連結構之垂直截面圖； 圖3-4爲一垂直截面圖，顯示圖2之結構中製造的序 歹！1 階段；圖 5 爲（silsesquioxane)H8Si8H12 的分子 結構； 圖 6 爲 HSQ(hydrogen silsesquioxane)的傅氏 轉換紅外線頻譜； 圖7-8爲一垂直截面圖，顯示圖2之結構中製造的序 6 本紙張尺度逋用中國國家標準（CNS ) A4規格（210X297公釐） I I n I I I人—裝I I —訂— I 線 • ··*-· (請先閲讀背面之注意事項再填寫本頁) A7 301789 ___B7_ 五、發明説明（4 ) 列階段； 圖9爲平坦矽晶圓上多孔高密度HSQ的厚度與固化溫 度的函數圖； (請先閱讀背面之注意事項再填寫本萸) 圖1〇爲金氧半導體電容（MOSCAP)及HSQ之線與 線間介質常數與固化溫度的函數圖； 圖11-12爲一垂直截面圖，顯示圖2之結構中製造的 序列階段； 圖13-14爲半導體裝置的截面圖； 圖15爲一梳狀結構中反射係數（Smith圖）的極化圖； 圖16爲抽取容抗（在墊解埋之後）與頻率之間的關係 圖； 圖 17 表示 Hydrogen Silsequioxane 的化學結 構； 圖 18 表示 Hydrogen Silsequioxane 可.能的化 學鍵結； 在圖中除非特別說明否則相同的組件以相同的數字表 示。 較佳實施例之說明 經濟部中央樣準局員工消費合作社印製 圖1爲一裝置的垂直剖面圖，該裝置包含一與金靥互 連線1，2,3,4相平行的接地板5。 由這些互連線1，2,3，4所攜帶電子訊號接受該特別線 路的RC時間常數所影響。在線1的例子中，RC時間常數 的電容元件分爲四個組件。第一電容組件爲電容C12 ’ 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） kl B7 冬」：丨_丨？:、，： 85.19. uni-.^1 五、發明説明（5) 專利申請案第84109292號 ROC Patent Appln. No.84109292 説明書修正頁中文本-附件一 Amended Pages of Specification in Chinese - Encl.I. (民國§5年10月叫日送呈) (Submitted on October ίί/· , 1996) (請先閲讀背面之注意事項再填寫本頁) 其爲線1及2之間的線至線間的電容。第二電容組件 爲電容C 1 3，其爲線1及其下之線3之間的層間的電容。 第三電容組件爲電容C14，其爲線1及其下垂直之線4之 間的層間的電容。第四電容組件爲電容C 1 5 ’其爲線1及 線5之間的線至接地電容。線I-4中每一線的金屬寬度約 爲0 . 3 6 u m。線與線之間的間隙亦約爲〇 . 3 6 U m。金屬線 1 - 4的高度約爲〇 . 6 u m。在金屬線之間的氧化物厚度約 爲0 . 7 u m。圖1結構所模擬的電容示於表丨及表2 » 表1 vl 1.0000000E+00 v2 〇.〇〇〇〇〇〇0E+00 v3 〇.〇〇〇〇〇〇0E+00 v4 〇.〇〇〇〇〇〇0E+00 v5 〇.〇〇〇〇〇〇0E+00 表2
Norm XR P-iter 1 c-iter Ml O.OOOOE+OO n-誤差 p-誤差 電極 電壓 通量 (Coul/mic.) i (電子） (A/micron) U電洞） (A/raicro) (y^ctoio Cll 1.0000E+00 1.0842E-16 O.OOOOE+OO O.OOOOE+OO O.OOOOE+OO C12 0.0000E， -9.1582E-17 O.OOOOE+OO O.OOOOE+OO O.OOOOE+OO C13 0.0000Ε-ΚΧ) -1.0418E-17 0.0000E， O.OOOOE+OO 0.0000Ε-ΚΧ) C14 0.0000E+00 -6.4178E-18 O.OOOOE+OO O.OOOOE+OO O.OOOOE+OO C15 0.0000E+00 -5.5909E-21 O.OOOOE+OO O.OOOOE+OO O.OOOOE+OO 經濟部中央標準局員工消費合作社印製 由表2中可看到線至線間的電容約佔上例中全部電容 的〇 . 8 5。當然該比例將視線至線間的間隙而定》當間隙 減小時，總電容的比例增加。所以減低緊密相隔之互連線 之間的電容對於給地定互連線之總R C延遲時間的影響相 當大》雖然在下文中本發明將使用多階金屬製程加以說 木紙張尺度適用中國國家標準（CNS ) A4規格（210 X 297公釐） 經濟部中央標準局員工消費合作社印製 上* d 9 A7 _ _B7_______ 五、發明説明（6 ) 明，但對於熟習本技術者需知金屬化的階數可改變而 且本發明可等效應用單階金屬裝置。 圖2爲本發明中半導體10上的互連階數。該半導體 10包含一電晶體，及它技術上以知的半導體元件（圖中沒 有顯示）。半導體10亦可包含其他的金屬互連層。在半導 體上形成絕緣體層12以從互連線14a_d中隔離半導體結 構。絕緣體層12可包含一氧化物如二氧化矽。皆接點， 如接點11，延伸過絕緣體12以將互連線14a-c與半導體 10相連。互連線14a-d可由導電材料如鋁或氮化鈦/鋁/ 氮化鈦的多層合金，當然亦可使用其它導電材料。互連線 1 4 a - c之間緊密相隔（例如小於〇 . 5微米），但互連線1 4 c 及14d其間隔更寬（如大於2.0微米）。層20包含低密 度，低介質常數材料且使互連線14a_c彼此之間相隔 離。低密度，低介質常數層20可包含多孔二氧化矽’多 孔砂氧院（siloxane)， 多孔三氧二砂院 (3丨1^"11丨0\3116)或其他其它介質常數小於3.7的多 孔，低密度材料。多孔二氧化矽用於較佳實施例。 低介質常數材料層20置於在電容上含最大衝擊之裝 置區域。因爲緊密間隔互連線上線至線之間的電容對總電 容的貢獻最大，低密度，低介質常數層20可包含多孔二 氧化矽置於互連線14a-c之間。高密渡矽之氧化物18使 用於極多地方（例如互連線14<:及14<1之間）且將互連線 14a-d與相鄰的形成元件如額外的互連層（圖中無示）相 隔離。接通點，如圖中之24，延伸通過二氧化矽層18以 9 本紙張尺度適用中國國家標準（CNS ) A4規格（21 〇 X 297公釐） --------4 |私衣------II------ ^---------------- » Λ . 0*· . (請先閱讀背面之注意事項再填寫本頁) __ 經濟部中央標準局員工消費合作社印製 A7 B7 五、發明説明（7 ) 應用互連線14a-d在需要的地方提供互連。 在互連線之間提供多孔二氧化矽存在一些優點》第 一，因爲低介質常數材料20的介質常數高於高密度二氧 化矽，因此線至線間電容減低。第二，傳統的氧化物蝕刻 用於高方位比接點及通路。第三，在高密度二氧化矽周圍 提供一障礙以防止多孔材料的機械不穩定。第四，二氧化 矽的表面極化以用於照像石板之圖樣。第五，因爲多孔材 料及互連線之間的介面力使多孔結構更形穩定。另外，在 互連線之間的多孔材料在高到700度C下其結構仍然很穩 定。高熱穩定度不緊可使多孔材料可用於層間介質層 (ILD)，且可應用於多金屬介質層。 圖3示電晶體及其他裝置組件（圖中無示）形成之後的 半導體1〇。一或多個互連線亦可在半導體10上形成。在 半導體上形成一或多個互連層。絕緣體丨2及接點11於 半導體1 〇上形成。 現請參可圖4，沉積一金屬層且加以蝕刻以形成互連 線14a-d。爲了簡化起見，圖4中只顯示四條互連線 14a-d。但是需了解互連線線的數目並不受此限制且其 幾合構造亦可爲其他形式。互連線14a_d其垂直厚度的 大小在0 . 5到2 . 0微米之間而水平向的厚度可視設計上的 需要而變動，但基本上其範圍介於〇. 25到1微米。在互 連線14a-d形成之後，一薄層的二氧化矽（圖中無示）可 視需要沉積在結構之表面上。因爲此二氧化矽層爲視需要 決定是否採用，所以在圖中並沒有顯示出來。 10 本紙張尺度適用中國國家樣準（CNS ) A4規格（210X 297公釐） ---------{—裝------訂-----(線 -···* (請先閱讀背面之注意事項再填寫本頁) 經濟部中央標準局員工消費合作社印製 A7 B7 五、發明説明（8 ) 請在參考圖4，一層介質層材料20沉積在結構之表 面，其厚度介於〇. 2至5. 0微米之間。層20所沉積的厚度 足以充塡互連線14a-d之間的區域。層20'可包含織成膠 質懸浮材料如聚二氧一砂院（？0丨）^丨丨564111〇乂&116)， 矽氧烷，或矽酸鹽。 另外層20可包含蒸氣沉積似膠狀材料，如高度氫化 的二氧化矽。甚至"Dow Coming Polysilsequioxane Flowable Oxide "(下文 中稱之爲"可流動氧化物"）可用於較佳實施例中，亦可 使用其它的 hydrigen silsesqui〇xanes(HSQ)。 HSQ之一般公式爲（HSi01.5)2n，此處η等於3至8。 從該式中可看到每一個矽原子對應到1.5個氧原子。圖5 所示者爲多面結構之三氧二矽烷，H8Si8012» 圖6爲HSQ的FTIR頻譜圖。圖中顯示回復溫度與紅 外線吸收度及波數之間的關係。由Si-H及Si-Ο之紅外 線吸收尖峰的改變可得知當回復溫度增加時可重新組合 HSQ的形態》X射線的折射在所有建議的溫度下皆形成 非晶薄麼膜。HSQ展現相當優越的間隙充塡及平面化的 能力，部份原因爲起始材料有相當低的玻璃傳輸溫度（約 2 5 0 度 C )。 現在請參考圖7’圖4中的結構在沉積之後再予烘 烤，基本上烘考溫度介於150度C至300度C之間》烘烤 可從介質層材料層20中將殘餘的溶劑移除，且導至起使 懸浮粒子之間的串聯》另外因爲溶劑的蒸發可在網中產生 多個孔。 本紙張尺度適用中國國家標隼（CNS ) A4規格（210 X297公釐） ---------{ I裝------訂-----(線 ·.*· ·~· (請先閱讀背面之注意事項再填寫本頁) 經濟部中央標準局員工消費合作社印裝 A7 B7 五、發明説明（9) 在圖8中，當溫度高於起始烘烤溫度時該結構回復。 對於層間的絕緣應用，可能需要高的回復溫度（例如大於 5〇〇度C)。在開放場區回復互連線14C-d之間的高密度 絕緣材料20。然而在互連線14a-c之間的材料尙未密 化’仍爲多孔》這可能是因爲互連線的網及側壁之間的交 互作用防止變密所致。因爲多孔的二氧化矽傾向於吸收濕 氣’因此材料需要一層防濕材料覆蓋（如電漿氧化物）。 在HSQ的互連之間產生多孔。在圖9中顯示在平坦的 Si晶圓中密薄膜之量測厚度及多孔性對溫度的效應。由 於密化作用厚度及多孔性隨者溫度的增加而減少》當回復 溫度低於4 0 0度C時，薄膜的多孔性爲1 9 %，且當回復溫 度到達450度C時，薄膜的多孔性減爲約13 %。 爲MOSCAP方法所量測的對應介質常數示於圖10 中。（該値參考熱氧化物K = 3. 96)，線至線之間的電容 量測乃是應用0.5/0. 5um寬度/間隔之疏狀結構。當溫 度從450度C減到300度C時，回復溫度減少，介質常數 減爲約3. 5-2. 7之間，指出在HSQ膜內部的孔數低於有 效介質常數。線至線間電容使用梳狀結構，且所得到的介 質常數見於圖1〇中。與MOSCAP數據相同，互連線間的 介質常數隨著回復溫度之減少而減少。然而對於一給定的 回復溫度其實質上小於MOSCAP ’因此可以知道HSQ膜 間隙的密度小於開放場中者。然而因爲HSQ的機械強度 小於高密度二氧化矽，所以二氧化矽使用於開放場中’而 多孔二氧化矽仍然位在互連線之間。而且頂二氧化矽層及 12 本紙張尺度適用中國國家標準（CNS ) A4規格（2!〇X 297公廣） ---------{—裝------訂-----{ 線 Γ · · · - · (請先閱讀背面之注意事項再填寫本頁) A7 經濟部中央標準局員工消費合作社印製 B7五、發明説明（1 〇) 材料互連側壁可對多孔二氧化矽提供屛障（限制）。 現在請參可圖11，接點路徑24依據傳統的方法經由 二氧化矽層1 8形成圖樣並加以蝕刻。本發明的一優點爲 可使用傳統的接點路徑蝕刻而仍有一較短的RC延遲時 間，此乃由於該密度二氧化矽層留下所需要的路徑，電低 密度多孔二氧化矽用於互連線之間的空間，將產生使線之 R C時間常數減低的效應。最後，蝕刻一金屬層且沉積以 充塡路徑24，而產生圖2的結構。 在圖2之結構形成之後，此程序可重複以形成其他的 金屬互連層，如圖12所示。基本上四個金屬互連層中的 三個可形成。但是本發明仍可用於只含單一或雙金屬互連 或者互連線多於四位階的裝置。 現在請參考圖13，自400度C下經過1小時的處理以 回復可留動氧化物〗6。經由一標準的染色溶解（應用 NH4F及醋酸）經過10秒之後，可將可流動氧化物蝕刻 掉》介於線17-19之間的可流動氧化物密度較低，因此 其蝕刻率低於開放場區域中的可流動氧化物。估計該材 料至少包含20%的孔，且將二氧化矽的介質常數減至低 於3 · 3。 現在請參考圖14，當可流動氧化物在700度C的高溫 下回復時，則在線1 1 - 1 5之間的可流動與開放場區域2 1 中的氧化物相必變得較不密。經由一標準的染色溶解經過 10秒之後，可將氧化物16蝕刻掉。然而在高溫之下的材 料是較不居具多孔性的。此時在可流動16中的多孔性估 --------—裝------訂-----線 '· · ·-· (請先閱讀背面之注意事項再填寫本頁) 本紙張尺度適用中國國家梯準（CNS ) Α4規格（210X297公釐） 〇*ui«d9 經濟部中央標準局員工消費合作社印製 A7 B7 五、發明説明（1 1) 計約爲10%»圖10中亦顯示一保護性蓋層及一較低層的 材料2 0。 另外，圖15及圖16爲此新的多孔層間介質至一 GHz 的高頻響應（回復溫度爲300度C)。圖15爲梳狀結構之 反射係數史密斯的極化座標圖，圖中顯示該結構的行爲接 近一理想的含極小金屬串連電阻的電容。圖16爲（墊已去 除埋入之後）的電納。電納的斜率爲結構的電容，其 1MHz至1GHz之間維持固定，指出在此範圍內介電質並 沒有吸收反應。 另一種更進一步減低HSQ旋上玻璃（spin-on glass)之介質常數的方法爲使用一低分子量的樹脂。低 分子量的材料具有更多的氫配合基，且形成密度較低的薄 膜。具高分子量的材料其氫配合基較少因此籠結構 (cage structure)崩潰，所以變得較不密。低分子量 的HSQ有較多的氫連接在立方體上，因此如圖16中所 示者所產生的結構其孔數較高。現在由
Dow Corning所生產的HSQ平均分子量爲 lOOOOamu 。 已應用有限的孔性比例及改變低介質材料之多孔性的 方法說明本發明的實施例，但需知本發明涵蓋產生低介質 材料之程序及多孔性的不同修改方法。例如在相關的申請 案TI-19072中所說明的多種改變低介質層材料之多孔 性的方法。例如回復溫度’ PH値，黏滯性（由稀釋低介 質層材料而改變）及’外界大氣狀況（如眞空，氮氣，氧 14 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公瘦） ---------{—裝------訂-----(線 . - - i * (請先閲讀背面之注意事項再填寫本頁) A7 B7 五、發明説明（1 2 ) 氣等）可因低介質層的孔性而改變。 另外間隙及開放場之間的密度差可經由浸水蝕刻 (leaching etching)而增加，其中在間隙中蝕刻多孔 材料快於在開放場中蝕刻少孔材料。例如，可經由在材料 中製造一洞且將氣體HF注入洞中以增加多孔性，如此可 完成浸水蝕刻。甚且其它在間隙間的介質層材料中增加多 孔性的方法可參考相關申請案1'1-19179,1'1-1 9 3 0 5 ° 本發明以應用較佳實施例加以說明，但此說明並非用 於限制本發明。對於熟習於本技術者可對上述實施例加以 修訂及更改而不偏離本發明申請專利範圍的精神及關點。 mV' a— 1^1 ·· (請先閱讀背面之注意事項再填寫本頁) 訂 線 經濟部中央標準局員工消费合作社印装 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐）

Claims (1)

  1. 經濟部中央標準局負工消費合作社印裂 A8 B8 C8 D8 六、申請專利範圍 I一種在減低的線至線間電容半導體裝置中製造互連 線的方法，包含： a •在半導體上形成半導體元件； b•在半導體及該半導體元件上覆上一層介質層； c .烘烤該介質層；及 d .將該介質層磨平。 2.如申請專利範圍第1項之方法，其中該方法更包含 在上升溫度中回復該介質層以在該緊密間隔的半導體元件 中形成一介質層體，其密度低於間隔相當遠離之半導體元 件之間的介質層體’且其中該緊密間隔的半導體元件之間 的介質層體其介質常數小於3.7。 3·如申請專利範圍第2項之方法，其中該回復步驟包 含在溫度範圍爲200度C到700度C的爐中回復。 4·如申請專利範圍第1項之方法，其中該方法更包含 在該半導體元件及該介質層之下應用電漿沉積法沉積一氧 化物襯層。 5 .如申請專利範圍第1項之方法，其中該烘烤程序由 熱板執行，其溫度範圍介於室溫到500度C之間。 6 -如申請專利範圍第2項之方法，其中該回復步驟的 溫度範圍爲小於400度C。 7. 申請專利範圍第1項之方法，其中該方法更包含在 該介質層上形成一防濕蓋材料。 8. 如申請專利範圍第1項之方法，其中該方法更包含 在該半導體中的多個半導體元件及開放區中移除該介質 1 6 本紙張尺度適用中國國家標準（CNS ) Α4規格（210X297公釐） --------ί -裝------訂-----一線 . « · · 一- (請先閱讀背面之注意事項再填寫本頁) ABCD 經濟部中央標準局員工消費合作社印製 六、申請專利範圍 層。 9. 如申請專利範圍第1項之方法，其中該平面化步驟 包含化學機械拋光。 10. —種在減低的線至線間電容半導體裝置中製造互 連線的方法，包含： a. 在半導體上形成互連線，及中該第一及第二線之間 隔小於線寬之1. 5倍，而第三及第四線的間隔至少爲三條 線的寬度； b. 在半導體及該多個互連線上覆上一層介質層；及 c .烘烤該介質層。 11. 如申請專利範圍第10項之方法，其中該方法更包 含在上升溫度中回復該介質層以在該第一及第二線之間形 成一介質層體，其密度低於第三及第四線之間的介質層 體，且其中該第一及第二線之間的介質體其介質常數小於 3 . 7 〇 12. 如申請專利範圍第11項之方法，其中該回復步驟 包含在溫度範圍爲200度C到700度C的爐中回復。 13. 如申請專利範圍第1〇項之方法，__其中該方法更包 含蝕刻該介質層以減少第一及第二線之間介質層的密度。 14. 如申請專利範圍第10項之方法，其中形成介質層 的步驟包含織成（spin)介質層。 15_如申請專利範圍第10項之方法，其中該方法更包 含在該半導體中的多個互連線及開放區中移除該介質層。 16.如申請專利範圍第10項之方法，其中該方法更包 ---------{-裝------訂-----卜線 • - *»· (請先閱讀背面之注意事項再填寫本頁) 本紙張尺度適用中國國家樣準（CNS ) A4規格（210X297公釐） 3ϋί739 Α8 Β8 C8 D8 年a c: 申請專利範圍 ί利申請案第84109292號 ROC Patent ΛρρΙη. No.84109292 ,專利範圍修正頁中文本-附件二 Amended Page of Claims in Chinese - Enel II (Submitted on October li/- , 1996) 含在該多個互連線及介質層之間形成一二氧化矽。 I7.如申請專利範圍第15;項之方法，其中該方法更包 含形成接觸路徑其經由該二氧化矽層及介質層至多個互連 線線。 1 8 ·如申請專利範圍第〗〇項之方法，其中該烘烤程序 溫度範圍介於室溫到5 〇 〇度c之間。 1 9 ·如申請專利範圍第1' 1項之方法，其中該回復步驟 的溫度範圍爲小於4 〇 0度C。 20. 如申請專利範圍第10項之方法，其中該方法更包 含在該介質層上形成一防濕蓋材料。 21. —種在減低的線至線間電容半導體裝置中製造互 連線的方法，包含： 請 先 閱 面 之 注 意 奢 層 襯 物1 化 氧 - 積 沉 ;法 件積 元沉 體漿 導電 半用 成應 形上 上件 體元 導體 半導 在半 成該 形在 經濟部中央搮率局員'工消費合作社印^ 成 織 由 經 上 裡 襯 物烘 化板； 氧熱間 該用之 在應 C . 度 c d ο ο 5 層 質 介 該 烤 ;到 層溫 質室 介於 層介 I 圍 上範 覆度 法溫 方其 面 平 呈 .，料 料材 材蓋 蓋濕 濕防 防該 1 使 成光 形拋 上械 層機 質學 介化 該用 在應 第 圍 範 利 專 請 串 如 質 介 該 復 回 中 度 溫 升 上 在 含 包元 更體 法導 方半 該的 中隔 其間 ’密 法緊 方該 之在 項以 1 層 元的 體間 導之 半件 之元 離體 遠導 當半 相的 隔隔 間間 於密 低緊 度該 密中 其其 ， πτ| 體 ’ 質體 介質 1 介 成的 形間 中之 件件 18 本紙张尺度適用中國國家榡準（CNS > Α4規格（210Χ297公釐） 申請專利範圍 於 小 數 常 質 介 其 體 質 介 A8 B8 C8 D8 驟 步 復 回 該 中 其 法 方 之 項 2 2 第 圍 範 利 專 請 甲 如 爲 圍 範 度 溫 在 含 包 C 度 復 回 中 爐 的 C 度 ---------{ 1¾衣-- •* (請先閱讀背面之注意事項再填寫本頁) 訂 線 經濟部中央標準局員工消費合作社印製 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐）
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