經濟部中央棣準局貝工消費合作社印製 298689 at B7 五、發明説明（丨） 發明範圍 本發明係關於類比數位轉換器及其轉換方法，更明確的說，係 關於多級的平行式轉換器，它使用第一轉換級來決定輸入電壓的粗 略範圍，而後續的轉換級再解出類比輸入訊號至更精確的增量。本 發明可應用於視訊及數位訊號處理的領域。 發明背景 類比資料的數位處理和傳輸的應用需要一種技術，將它們的類 比形式轉換成數位的代表方式。習知的類比數位轉換器的種類有： 逐漸逼近式，它產生一個數位輸出，乃使用數位類比轉換器以嘗試 錯誤法產生逼近輸入位準的信號；另外一種是並聯比較器式或快閃 式（FLASH)轉換器，它利用比較多個參考電壓與輸入電壓的關 係，將結果由編碼邏輯輸出，在每次轉換中，數位碼代表最接近輸 入電壓的參考電壓。圖1爲快閃式類比數位轉換器。一般來說，輸 出的部份是由編碼邏輯3〇建立的二進位碼，因此可以提供輸入訊 號η位元的解析度。這種架構通常需要2n個參考電壓10和Μ個比 較器20。當這種形式的轉換器的解析度增加時（輸出的位元數目增 加），設計就會變得很難處理。 爲了要簡化快閃式類比數位轉換器的設計，已知有兩種技術可 以運用。這兩種多級轉換的技術都可以用來完成類比數位的轉換。 在第一種技術裡，如美國專利號53〇2809 (Hosotani等人），美 國專利號5 3 8 9929 (Nayebi等人），美國專利號5 3 5 3 027 (Vorenkamp等人），美國專利號5 3 693 09(Bacrania等人），美 國專利號5 3 879 1 4 (Mangelsdorf)所示，第一級爲快閃式類比數 位轉換的粗略解析度；而具有數位類比轉換器的第二級則調整電壓 比較器的參考電壓來完成解析度更佳的轉換。這兩種轉換的結果再 被編碼成數位輸出位元組，以代表類比輸入電壓的大小。在第二種 技術裡，如美國專利號5 2 9 1 1 9 8 (Dingwall等人），美國專利號 5 2 2 3 8 3 6 (Komutsu)，美國專利號 5400029 (Kobayashi)，美 國專利號473 3 2 1 7 (Dingwall)，美國專利號5 3 493 5 4 (Ho等人） 所示，這種使用多個轉換級的技術，是利用決定邏輯根據前一比較 級的結果，將參考電壓適當的切換到每一級。 以第二種多級轉換的技術爲例，請參考圖2，其爲美國專利號 49〇3〇28(Fukashima)的電路圖，它先產生一組電壓源1，由 本紙張尺度適用中國國家標準（〇呢）八4規格（210/297公|) —2.— ---------——装.-- (请先閱讀背面之注意事項再填寫本買) ίτ A7 _____B7_ 五、發明説明（2 ) vREFBOT(最低値）逐漸增加至vREFTOP(最高値），以建立電壓輸 入（vin)的轉換範圍。一組粗略分域比較器2連接至輸入電壓以及 在分開的區間所建立的Vin的la，lb粗略範圍的一組參考電壓。粗 略分域比較器的輸出5爲控制邏輯與開關單元3的輸入，單元3可以 將一組細微分域比較器4連接至適當的參考電壓的分域範圍1。參 考電壓組la被分成更細微的增量，以建立轉換Vin成爲數位輸出 {〇0,〇1，〇2...，〇11}的最大解析度。當¥111變化時，輸出碼的値或 粗略分域比較器的輸出碼5也跟著改變，而且控制邏輯與開關單元 3也移動細微分域比較器4至下一個分域範圍（從la至lb)。 由於元件選擇及製程漂移的容忍度不同，粗略分域比較器2的 輸出碼5可能是錯誤的。爲了檢查這個錯誤，就需要額外的細微分 域比較器4a及4b，它們將視Vin的大小分別擺在分域la或lb的旁 邊。額外的細微分域比較器4a及4b的輸出碼爲錯誤校正碼7，其與 粗略分域碼5送至輸出編碼邏輯8以決定輸入電壓Vi η的數位輸出代 表碼{〇0,〇1，〇2...〇11}。 經濟部中央標準局員工消費合作社印製 (請先閲讀背面之注意事項再填寫本頁) 利用前面所述的技術，需要兩組誤差檢測電路。而誤差校正功 能在每次細微分域比較器的比較週期時，只會使粗略分域的一邊發 生作用。這種結構消耗額外的功率，並增加實際實施的額外之複雜 度。爲了減少額外比較器的數目，並且簡化實際架構的複雜度，與 本發明同一申請人的已經獲准之專利，證書號爲發明第〇七六八六 四號中提到，如圖3所示，用同一組嵌入式粗略分域比較器140來 達到這些目的。嵌入式粗略分域比較器產生的參考碼，決定細微分 域比較器160的適當參考範圍。由粗略分域比較器，嵌入式粗略分 域比較器，及細微分域比較器得到的碼分別爲17〇，18〇，19〇,再編 碼成數位輸出碼。如何選擇嵌入式粗略分域比較器140的輸入參考 電壓131，是由嵌入式粗略分域選擇邏輯及開關13〇，參考粗略分 域比較器的輸出170來決定。而如何選擇細微分域比較器的參考電 壓，是由細微分域選擇邏輯及開關，參考粗略分域比較器 的輸出170及嵌入式粗.略分域比較器的輸出ISO來決定。 發明摘要 本發明的一個目的是要減少實際實現並聯類比數位轉換器的複 雜度。本發明的另一個目的則是爲了降低功率消耗而將不必要的電 路去除。 (CNS ) A4規格（2丨0X297公釐） 3 — 經濟部中央標準局員工消費合作社印製 A7 B7 五、發明説明（3 ) 圖7說明了此發明的時序圖，在第一個時序週期的前半部7〇5， 粗略類比數位轉換器730及細微類比數位轉換器76〇取樣輸入訊號 73 5及76 5。然後在時序週期710的前半部，粗略類比數位轉換器 比較輸入訊號73 5，此比較740的結果用來決定比較輸入訊號 的粗略數位碼，並且選擇參考電壓給細微類比數位轉換器76〇使 用。在時序週期71〇的後半部，細微類比數位轉換器760可以完成 比較輸入訊號765的動作並可決定細微數位碼，如此可在一個時鐘 週期內決定訊號的數位碼8〇5(結合輸入訊號735的粗略數位碼與 76S之細微數位碼）。在接下來的時序週期715中，粗略類比數位 轉換器730與細微類比數位轉換器760便可取樣下一個輸入訊號 745與7 7 5。所以，第二個細微類比數位轉換器是不需要的。 要完成以上的目的，此二階式類比數位轉換器包含有一個粗略 解析度類比數位轉換器與一個細微解析度類比數位轉換器。一個取 樣與保持電路，週期性的取樣輸入類比電壓，並且保持此取樣電壓 給粗略類比數位轉換器與細微類比數位轉換器使用。一個參考電壓 產生器連接在兩個參考電壓源之間來產生一組參考電壓。 粗略類比數位轉換器連接至取樣的類比輸入訊號。此類比輸入 訊號與一組粗略參考電壓做比較，其結果產生一組粗略數位碼，此 粗略數位碼控制一個參考電壓選擇邏輯裝置去開啓一組參考電壓選 擇開關，用以產生細微參考電壓。 細微類比數位轉換器連接至取樣的類比輸入訊號。此類比輸入 訊號與細微參考電壓作比較，其結果產生一組細微數位碼。 一個輸出編碼裝置將粗略數位碼與細微數位碼作處理，並且修 正粗略數位碼。此輸出數位碼以二進位的方式表示此類比電壓的大 小0 圖式說明 圖1爲說明並聯式或快閃式類比數位轉換器前案技術的電路 圖。 · 圖2爲說明二階式類比數位轉換器前案技術的電路圖。 圖3爲說明嵌入式類比數位轉換器前案技術的電路圖。 圖4爲說明本發明之二階式類比數位轉換器的電路圖。 圖5a-c爲說明本發明中參考電壓產生器的電路圖。 圖6爲說明本發明之細微編碼器的電路圖。 本紙張尺度逋用中國國家標準（CNS ) A4規格（210X297公釐） —— (請先閱讀背面之注意Ϋ項再填寫本頁) 裝. 訂 旅· 經濟部中央樣準局員工消費合作社印製 A7 __B7_ 五、發明説明（斗） 圖7爲說明本發明的轉換週期之時序圖。 發明之詳細說明 在圖4中，類比輸入電壓（Vin) 5 00連接至取樣及保持電路 5 0 5，週期性的對（VU) 5 00取樣，並維持住取樣的類比輸入訊號 電壓5 1 0 » 參考電壓產生器54〇連接在參考電壓源VRB 541與VRT 546之 間。參考電壓產生器54〇可以產生一組參考電壓544，它們從VRB 541至VRT 546逐漸增加。而參考電壓544的增加量可以由下面的 式子決定： (vRT-vRB)/2n ;其中n爲數位輸出碼5 7 5的位元數目。 這些參考電壓544連接至參考電壓開關網路W3。粗略參考電 壓組5 47是由參考電壓544中獲得，並常態接至粗略分域比較器 5 2 0。取樣的類比輸入電壓訊號5 10 與這組粗略參考電壓546比 較，比較的結果爲粗略的溫度尺碼5 2 7(thermometer code)。 (溫度尺碼是一種二進制碼，碼的形成是由連續的數字組成。當碼 增加時，連續的數目也增加，例如： 0000値最低的碼 000 1 0 0 0 1 00 11 0 111 11 11値最高的碼）。 粗略溫度尺碼527連接至參考電壓開關網路，經過處理後，連 接適當的開關選擇線5 4 5。這些開關選擇線5 4 5連接至參考電壓開 關網路，此參考電壓開關網路由一串開關（switch) 5 43所組 成，用來啓動合適的開關5 4 3以連接一組參考電壓5 44，產生細微 參考電壓5 4 9。 · 細微參考電壓5 4 9連接至細微比較器5 3 0。細微比較器5 3 0比較 取樣的類比輸入電壓510與細微參考電壓5 4 9，其結果產生細微溫 度尺碼5 3 7。這些細微溫度尺碼5 3 7經由細微編碼器5 6 0之後產生 細微數位碼5 6 5。 粗略數位碼5 5 5與細微數位碼565被送至輸出編碼邏輯器570。 經此編碼邏輯器轉換成輸出的數位碼5 7 5。輸出數位碼5 7 5是一種 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） —S — „ ^^、訂 線 - * ， (請先閱讀背面之注意事項寫本頁) ( 經濟部中央標準扃負工消費合作社印裝 298689 A7 B7 五、發明説明（y ) 二進位數字，代表類比輸入電壓（Vin) 5 00的大小。數位碼5 7 5可 以被解析成一組二進位數字的最大有效位元。而細微數字碼5 6 5則 被解析爲一組二進位數字的最小有效位元。細微數字碼565也提供 誤差修正因子給最大有效位元。 圖5a說明參考電壓產生器（圖4中的54〇)。參考電壓供應器VRB 541連接至電阻542a，而參考電壓供應器VRT 546連接至電阻 542b。這些串聯電阻5 42形成電壓分壓，在這些串聯電阻542的每 —個連接點上，爲一個參考電壓（圖4中的5 44)。 提供給粗略比較器（圖4中之5 5〇)的參考電壓是由串聯電阻中偶 數行580與奇數行585的交接處所產生。這些參考電壓是直接連接 在粗略比較器上（圖4中之520)。而提供給細微比較器（圖4中之 549)的參考電壓是由各個電阻（圖4中之542)之交接處所產生。這 些連接點是由粗略溫度尺碼5 27與開關選擇邏輯處理網路5 43所決 定。 圖5b中說明了當選擇到參考電壓產生器（圖5a中之540)中的奇 數行5 8 5中的情況，在細微比較器（圖4中之53〇)中的每個比較器 5 3 9透過參考電壓選擇開關（圖4中之5 43 )接至細微參考電壓5 77 ^ 被取樣的輸入電壓Vin 510與細微參考電壓577比較之後，決定細 微溫度尺碼5 3 7，而此溫度尺碼的大小是由取樣的輸入電壓Vi n 5 1〇的大小所決定。細微溫度尺碼5 3 7送到圖4中之細微編碼器5 60 之後，轉成細微數位碼5 9 0。 同理，假若選擇圖5c中之偶數行5 8 0，則細微參考電壓5 7 9連 接至比較器5S9，然後此細微參考電壓與取樣的輸入訊號510比較 之後產生細微溫度尺碼537，細微編碼器5 60根據此細微溫度尺碼 5 3 7，產生細微數位碼5 9 5。 圖6說明了圖4中之細微編碼器5 6〇，如同圖4 —般，細微參考 電壓5 4 9與取樣輸入電壓Vin 510經比較器W5比較之後，產生細 微溫度尺碼。 這些溫度尺碼被送.到反及閘（NAND)陣列600作處理，溫度尺 碼5 3 7中的相鄰兩個位元被連接至反及閘陣列中的一個閘。若此兩 個相鄰位元相等，則反及閘輸出邏輯〇。相反的，若‘相鄰兩位元不 相等，則反及閘輸出邏輯1。由於溫度尺碼537的結構只有一組相 鄰兩位元會不相等，因此，；R有在溫度尺碼537中邏輯〇與邏輯1交 接處反及閘才會輸出1，而其它的反及閘則輸出〇。 在圖6中，ROM編碼器電路的B0，B1,B2(圖6中的610)即爲圖 4細微編.碼器560的輸出。而數位碼選擇電路650控制ROM編碼器 本紙張尺度適用中國國家標準（CNS ) A4規格（2K)X2W公董） -- !〇 - ----------:裝-------訂-----線 (請先閱讀背面之注意事項i 寫本頁) ( 五、發明説明（6 ) A7 B7 TO用相ί 校表衡 m % 章作扰 mr 經濟部中央標準局員工消費合作社印製 來產生圖4中的細微數位碼5 65。數位 1選擇電路6 5 0，是由一些N通 道金氧半電晶體（NMOST'S)所組成，用以產生B0，B1，B2 610的 邏輯値。 假若溫度尺碼5 3 7使得反及閘6〇5產生邏輯1的輸出，貝[J NMOST'S 63 2，63 6和640會處於導通狀態，如果圖4中粗略溫 度尺碼5 27選擇圖6中的奇數分支620，則NMOST'S 63 0和6 3 4會 被啓動，如此，圖4中的細微編碼器5 60之輸出爲100。然而假若 圖4中的粗略溫度尺碼5 2 7選擇圖6中的偶數分支62 5，貝[| NMOST640會被啓動，而圖4中的細微編碼器5 60的輸出爲011。 這些數位碼5 90，5 9 5即是圖4中的細微數位碼5 65。 在圖7中，時序週期700決定了圖4中的取樣與保持電路5 05取 樣訊號的時間，也決定了圖4中粗略比較器520與細微比較器560 作比較的時間。 在時序週期7〇〇中的第一個半週期70 5中，粗略類比數位轉換 器73 0和細微類比數位轉換器取樣輸入訊號73 5和76 5，緊接著在 第二個半時序週期71〇的起始處，粗略類比數位轉換器做比較的動 作740。此比較的結果用來決定圖4中的粗略數位碼5 5 5，及設定 圖4中開關5 43的狀態。同時讓細微類比數位轉換器700比較取樣 訊號510與細微參考電壓5 4 9，這個比較的動作在第二個半時序週 期7 1〇的後半部進行其結果，即是圖4中的細微數位碼5 6 5。此細 微數位碼5 6 5與粗略數位碼5 5 5合倂之後在時序週期7 1 5的前半部 79〇時，被誤差修正電路57〇所修正，而此修正完的位碼5 7 5在時 序週期720時即爲有效的輸出資料1 8 0 5。 在接下來的時序週期715時，粗略類比數位轉換器與細微類比 數位轉換器取樣輸入訊號74 5與77 5，並重複前個時序週期的動 作。在時序週期720時，粗略比較7 5 0與細微比較780完成比較的 動作，並產生粗略數位碼5 5 5與細微數位碼5 6 5。此粗略數位碼 5 5 5與細微數位碼5 6 5合倂之後，在時序週期7 2 5的前半部時被修 正。此修正完的數位碼5 7 5在接下來的時序週期時，即爲有效的輸 出資料2 8 1 0。 此取樣、比較、編碼與修正輸出碼的動作一直重複，使得在時 序週期705與710之後每隔一個時序週期700便產生一組有效的數 位輸出碼。 本發明已特別用較佳實例表示與描述，熟知本領域的技藝者應 當了解，形式或詳細內容上可以有不同的變化，但仍不脫離本發明 的精神與範疇。 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） —η — ^I^---------.灯------ (請先閱讀背面之注意事項再填寫本頁)Printed 298689 at B7 by the Beigong Consumer Cooperative of the Central Bureau of Economic Affairs of the Ministry of Economy V. Description of the Invention (丨) Scope of the Invention The present invention relates to an analog-to-digital converter and its conversion method, more specifically, it relates to multi-level parallel conversion It uses the first conversion stage to determine the rough range of the input voltage, and the subsequent conversion stage solves the analog input signal to a more accurate increment. The invention can be applied to the field of video and digital signal processing. BACKGROUND OF THE INVENTION The application of digital processing and transmission of analog data requires a technique that converts their analog form into a digital representation. The types of conventional analog-to-digital converters are: Gradual approximation, which produces a digital output, which uses a digital-to-analog converter to generate a signal that approximates the input level by trial and error; the other is a parallel comparator or flash (FLASH) converter, which compares the relationship between multiple reference voltages and input voltages, and outputs the results from the coding logic. In each conversion, the digital code represents the reference voltage closest to the input voltage. Figure 1 shows the flash analog-to-digital converter. In general, the output part is a binary code created by the coding logic 30, so it can provide n-bit resolution of the input signal. This architecture usually requires 2n reference voltages 10 and M comparators 20. When the resolution of this type of converter increases (the number of output bits increases), the design becomes difficult to handle. To simplify the design of flash analog-to-digital converters, two techniques are known to be used. Both of these multi-level conversion techniques can be used to complete the conversion of analog digits. In the first technique, such as US Patent No. 53〇2809 (Hosotani et al.), US Patent No. 5 3 8 9929 (Nayebi et al.), US Patent No. 5 3 5 3 027 (Vorenkamp et al.), US Patent No. 5 3 693 09 (Bacrania et al.), US Patent No. 5 3 879 1 4 (Mangelsdorf), the first level is the rough resolution of the flash analog-to-digital conversion; the second level with the digital-to-analog converter is Adjust the reference voltage of the voltage comparator to complete the conversion with better resolution. The results of these two conversions are then encoded into digital output bytes to represent the magnitude of the analog input voltage. In the second technology, such as US Patent No. 5 2 9 1 1 9 8 (Dingwall et al.), US Patent No. 5 2 2 3 8 3 6 (Komutsu), US Patent No. 5400029 (Kobayashi), US Patent No. 473 3 2 1 7 (Dingwall), US Patent No. 5 3 493 5 4 (Ho et al.) As shown in this technique using multiple conversion stages, the reference voltage is used according to the result of the previous comparison stage using decision logic Switch to each level. Taking the second multi-level conversion technology as an example, please refer to FIG. 2, which is a circuit diagram of US Patent No. 49〇3〇28 (Fukashima), which first generates a set of voltage sources 1, and the Chinese standard is applied by this paper scale 〇) 8 4 specifications (210/297 public |) —2.— ---------—— installed .-- (Please read the precautions on the back before filling in this purchase) ίτ A7 _____B7_ V. Description of the invention (2) vREFBOT (lowest value) gradually increases to vREFTOP (highest value) to establish the conversion range of the voltage input (vin). A set of coarse sub-domain comparators 2 is connected to the input voltage and a set of reference voltages for the rough range of Vin la, lb established in separate intervals. The output 5 of the coarse sub-domain comparator is the input of the control logic and the switching unit 3, which can connect a set of fine differential domain comparators 4 to the sub-range 1 of the appropriate reference voltage. The reference voltage group la is divided into finer increments to establish the maximum resolution for converting Vin to digital output {〇0, 〇1, 〇2 ..., 〇11}. When ¥ 111 changes, the value of the output code or the output code 5 of the coarse sub-domain comparator also changes, and the control logic and switching unit 3 also move the fine differential domain comparator 4 to the next sub-domain range (from la to lb ). Due to the different tolerances of component selection and process drift, the output code 5 of the coarsely divided domain comparator 2 may be wrong. In order to check this error, additional fine differential domain comparators 4a and 4b are required, which will be placed beside the domain la or lb depending on the size of Vin, respectively. The output codes of the additional fine differential domain comparators 4a and 4b are error correction codes 7, which are sent to the output coding logic 8 together with the coarse subdomain codes 5 to determine the digital output representative code {〇0, 〇1 of the input voltage Vi η, 〇2 ... 〇11}. Printed by the Employee Consumer Cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs (please read the precautions on the back before filling out this page). Using the technique described above, two sets of error detection circuits are required. However, the error correction function will only make one side of the coarse sub-domain work in each comparison period of the fine differential domain comparator. This structure consumes extra power and adds extra complexity to the actual implementation. In order to reduce the number of additional comparators and simplify the complexity of the actual architecture, the patents granted by the same applicant as the present invention, the certificate number is mentioned in Invention No. 076686, as shown in FIG. 3, The same set of embedded coarse domain comparators 140 are used to achieve these objectives. The reference code generated by the embedded coarse sub-domain comparator determines the appropriate reference range of the fine differential domain comparator 160. The codes obtained by the coarse sub-domain comparator, the embedded coarse sub-domain comparator, and the fine differential sub-domain comparator are respectively 17〇, 18〇, and 19〇, and then encoded into a digital output code. How to select the input reference voltage 131 of the embedded coarse domain comparator 140 is determined by the embedded coarse domain selection logic and the switch 130, with reference to the output 170 of the coarse domain comparator. How to select the reference voltage of the fine differential domain comparator is determined by the fine differential domain selection logic and switch, referring to the output 170 of the coarse sub-domain comparator and the output ISO of the coarse coarse sub-domain comparator. SUMMARY OF THE INVENTION An object of the present invention is to reduce the complexity of actually implementing a parallel analog-to-digital converter. Another object of the present invention is to remove unnecessary circuits in order to reduce power consumption. (CNS) A4 specification (2 丨 0X297mm) 3 — A7 B7 printed by the Employee Consumer Cooperative of the Central Bureau of Standards of the Ministry of Economy V. Description of the invention (3) FIG. 7 illustrates the timing diagram of this invention during the first timing cycle In the first half 705, the rough analog-to-digital converter 730 and the fine analog-to-digital converter 760 sample the input signals 735 and 765. Then in the first half of the timing period 710, the coarse analog digital converter compares the input signal 735. The result of this comparison 740 is used to determine the coarse digital code of the compared input signal, and the reference voltage is selected for use by the fine analog digital converter 76. In the second half of the timing cycle 71〇, the subtle analog-to-digital converter 760 can complete the action of comparing the input signal 765 and can determine the subtle digital code. The rough digital code and the subtle digital code of 76S). In the next timing cycle 715, the coarse analog-to-digital converter 730 and the fine analog-to-digital converter 760 can sample the next input signals 745 and 75. Therefore, the second subtle analog-to-digital converter is not required. To accomplish the above purpose, this second-order analog-to-digital converter includes a coarse-resolution analog-to-digital converter and a fine-resolution analog-to-digital converter. A sample and hold circuit periodically samples the input analog voltage, and holds this sample voltage for use in coarse analog digital converters and fine analog digital converters. A reference voltage generator is connected between two reference voltage sources to generate a set of reference voltages. A rough analog-to-digital converter is connected to the sampled analog input signal. The analog input signal is compared with a set of coarse reference voltages, and as a result a set of coarse digital codes is generated. The coarse digital codes control a reference voltage selection logic device to turn on a set of reference voltage selection switches to generate a fine reference voltage. A fine analog-to-digital converter is connected to the sampled analog input signal. The analog input signal is compared with a subtle reference voltage, and the result is a set of subtle digital codes. An output encoding device processes the coarse digital code and the fine digital code, and corrects the coarse digital code. This output digital code represents the magnitude of this kind of analog voltage in a binary manner. 0 Description of the drawings Figure 1 is a circuit diagram illustrating the prior art technology of a parallel or flash analog digital converter. · Figure 2 is a circuit diagram illustrating the prior art technology of a second-order analog-to-digital converter. FIG. 3 is a circuit diagram illustrating the prior art technology of the embedded analog-to-digital converter. 4 is a circuit diagram illustrating a second-order analog-to-digital converter of the present invention. 5a-c are circuit diagrams illustrating reference voltage generators in the present invention. FIG. 6 is a circuit diagram illustrating the micro encoder of the present invention. The size of this paper is printed in Chinese National Standard (CNS) A4 (210X297mm) —— (please read the note Ϋ on the back and then fill out this page). The book is printed by the Traveling and Consumer Cooperatives of the Central Bureau of Samples of the Ministry of Economic Affairs A7 __B7_ V. Description of the Invention (Bucket) Figure 7 is a timing diagram illustrating the conversion cycle of the present invention. DETAILED DESCRIPTION OF THE INVENTION In FIG. 4, the analog input voltage (Vin) 5 00 is connected to the sample and hold circuit 5 0 5 to periodically sample (VU) 5 00 and maintain the sampled analog input signal voltage 5 1 0 »The reference voltage generator 54 is connected between the reference voltage sources VRB 541 and VRT 546. The reference voltage generator 54 may generate a set of reference voltages 544 that gradually increase from VRB 541 to VRT 546. The increase of the reference voltage 544 can be determined by the following formula: (vRT-vRB) / 2n; where n is the number of bits of the digital output code 5 7 5. These reference voltages 544 are connected to the reference voltage switch network W3. The rough reference voltage group 5 47 is obtained from the reference voltage 544 and is normally connected to the rough sub-domain comparator 5 2 0. The sampled analog input voltage signal 5 10 is compared with this set of rough reference voltages 546. The result of the comparison is a rough temperature code 5 2 7 (thermometer code). (The temperature size is a binary code, and the formation of the code is composed of consecutive numbers. As the code increases, the number of consecutive numbers also increases, for example: 0000 is the lowest code 000 1 0 0 0 1 00 11 0 111 11 11 is the highest value Code). The rough temperature size 527 is connected to the reference voltage switch network. After processing, the appropriate switch selection line 5 4 5 is connected. These switch selection lines 5 4 5 are connected to a reference voltage switch network. The reference voltage switch network is composed of a series of switches 5 43 to activate a suitable switch 5 4 3 to connect a set of reference voltages 5 44. Generate a subtle reference voltage of 5 4 9. · The subtle reference voltage 5 4 9 is connected to the subtle comparator 5 3 0. The subtle comparator 5 3 0 compares the sampled analog input voltage 510 with the subtle reference voltage 5 4 9, which results in subtle temperature size 5 3 7. These minute temperature sizes 5 3 7 pass through the minute encoder 5 6 0 to generate minute digital codes 5 6 5. The coarse digital code 5 5 5 and the fine digital code 565 are sent to the output encoding logic 570. After this coding logic is converted into the output digital code 5 7 5. The output digital code 5 7 5 is a paper standard applicable to the Chinese National Standard (CNS) A4 specification (210X297 mm) —S — „^^, threading-*, (please read the notes on the back to write this page) ( Printed 298689 A7 B7 by the Central Standards Consumer Labor Cooperative of the Ministry of Economic Affairs 5. Description of the invention (y) Binary digits, representing the magnitude of the analog input voltage (Vin) 5 00. The digit code 5 7 5 can be parsed into a set of binary digits The most significant bit of the. The subtle digital code 5 6 5 is parsed into a group of binary digits of the smallest effective bit. The subtle digital code 565 also provides an error correction factor for the most significant bit. Figure 5a illustrates the reference voltage generator (54 in FIG. 4). The reference voltage supplier VRB 541 is connected to the resistor 542a, and the reference voltage supplier VRT 546 is connected to the resistor 542b. These series resistors 542 form a voltage divider, and each of these series resistors 542 One connection point is a reference voltage (5 44 in FIG. 4). The reference voltage provided to the rough comparator (5 5〇 in FIG. 4) is the junction of the even row 580 and the odd row 585 in the series resistor Produce These reference voltages are directly connected to the coarse comparator (520 in Figure 4). The reference voltage provided to the fine comparator (549 in Figure 4) is the junction of various resistors (542 in Figure 4) These connection points are determined by the rough temperature size 5 27 and the switch selection logic processing network 5 43. Figure 5b illustrates the odd rows 5 8 5 when the reference voltage generator (540 in FIG. 5a) is selected In the case of the above, each comparator 5 3 9 in the fine comparator (53〇 in FIG. 4) is connected to the fine reference voltage 5 77 through the reference voltage selection switch (5 43 in FIG. 4) ^ the sampled input After comparing the voltage Vin 510 with the fine reference voltage 577, the fine temperature size 5 3 7 is determined, and the size of this temperature size is determined by the size of the sampled input voltage Vin 5 10. The fine temperature size 5 3 7 is sent to the graph The subtle encoder 5 in 4 is converted into a subtle digital code 5 9 0. Similarly, if the even line 5 8 0 in FIG. 5c is selected, the subtle reference voltage 5 7 9 is connected to the comparator 5S9, and then the subtle The reference voltage is compared with the sampled input signal 510 The fine temperature size 537, the fine encoder 5 60 generates the fine digital code 5 9 5 according to the fine temperature size 5 3 7. FIG. 6 illustrates the fine encoder 5 60 in FIG. 4, as in FIG. 4, the fine reference The voltage 5 4 9 and the sampled input voltage Vin 510 are compared by the comparator W5 to generate fine temperature sizes. These temperature sizes are sent to the NAND array 600 for processing, and the adjacent two of the temperature sizes 5 3 7 One bit is connected to one gate in the inverting gate array. If the two adjacent bits are equal, the output of the gate is logic 0. Conversely, if ‘adjacent two bits are not equal, the gate of the inverter outputs logic 1. Because the structure of the temperature size 537 only has a set of two adjacent two elements that will be unequal, therefore, R will output a 1 at the junction of the logic 0 and logic 1 at the temperature size 537, and the other will be 1, and the other Output 〇. In FIG. 6, B0, B1, and B2 (610 in FIG. 6) of the ROM encoder circuit are the output of the encoder 560 in FIG. The digital code selection circuit 650 controls the ROM encoder. This paper standard is applicable to the Chinese National Standard (CNS) A4 specification (2K) X2W company director)-! 〇- ----------: installed ---- --- booking-line (please read the precautions on the back i write this page first) (V. Description of the invention (6) A7 B7 TO use phase calibration meter balance m% chapter for disturbing mr Central standard of the Ministry of Economic Affairs Printed by the Bureau Staff Consumer Cooperative to produce the fine digital codes 5 65 in Figure 4. The digital 1 selection circuit 6 5 0 is composed of some N-channel metal oxide semi-transistors (NMOST'S) to generate B0, B1, B2 The logic value of 610. If the temperature size 5 3 7 causes the inverting gate 6〇5 to generate a logic 1 output, the [J NMOST'S 63 2, 63 6 and 640 will be in the on state, if the rough temperature size 5 27 in Figure 4 is selected The odd branch 620 in Fig. 6, NMOST'S 63 0 and 6 3 4 will be activated, so, the output of the fine encoder 5 60 in Fig. 4 is 100. However, if the rough temperature size in Fig. 4 5 2 7 selection diagram 6 even number branch 62 5, Bell [| NMOST640 will be activated, and the output of the subtle encoder 5 60 in Figure 4 is 011. These digital codes 5 90, 5 9 5 is in Figure 4 The fine digital code 5 65. In FIG. 7, the timing period 700 determines the time for the sample and hold circuit 5 05 in FIG. 4 to sample the signal, and also determines the time for the rough comparator 520 and the fine comparator 560 in FIG. 4 to compare. In the first half cycle 70 5 of the timing cycle 700, the coarse analog digital converter 73 0 and the fine analog digital converter sample the input signals 73 5 and 76 5 followed by the second half timing cycle 71 At the beginning of 〇, the rough analog-to-digital converter performs a comparison action 740. The result of this comparison is used to determine the rough digital code 5 5 5 in FIG. 4 and set the state of the switch 5 43 in FIG. 4. At the same time, let the analog The digital converter 700 compares the sampling signal 510 with the subtle reference voltage 5 4 9. This comparison is performed in the second half of the second half timing cycle 7 10. The result is the subtle digital code 5 65 in FIG. 4. The combination of the fine digital code 5 6 5 and the coarse digital code 5 5 5 is corrected by the error correction circuit 57 0 in the first half 79〇 of the timing period 7 1 5, and the corrected bit code 5 7 5 is When the timing period is 720, it is valid output data 1 8 0 5. At the next timing cycle 715, the coarse analog-to-digital converter and the fine analog-to-digital converter sample the input signals 74 5 and 77 5 and repeat the actions of the previous timing cycle. At the timing cycle 720, a rough comparison of 7 5 0 and subtle comparison 780 complete the comparison action, and produce rough digital code 5 5 5 and subtle digital code 5 6 5. After the coarse digital code 5 5 5 and the fine digital code 5 6 5 are combined, they are corrected in the first half of the timing period 7 2 5. The corrected digital code 5 7 5 is valid output data 2 8 1 0 in the following timing cycle. The actions of sampling, comparing, encoding, and correcting the output code are repeated all the time, so that a set of valid digital output codes is generated every other time period 700 after the time periods 705 and 710. The present invention has been particularly shown and described with preferred examples. Those skilled in the art should understand that there may be different changes in form or details, but they still do not depart from the spirit and scope of the present invention. This paper scale is applicable to the Chinese National Standard (CNS) A4 specification (210X297mm) —η — ^ I ^ ---------. Lamp ------ (Please read the notes on the back before filling in (This page)