TW202401251A - Method and apparatus for decoding low-density parity-check (ldpc) code - Google Patents

Abstract

The invention is related to a method and an apparatus for decoding low-density parity-check (LDPC) code. The method includes: when detecting a codeword is stored in a static random access memory (SRAM), making an LDPC decoder to enter a first-stage state, in which a check-node calculation circuit calculates a first syndrome corresponding to the codeword; when the first syndrome indicates that the codeword obtained in the first-stage state is incorrect, making the LDPC decoder to enter a second-stage state, in which a variable-node calculation circuit generates variable nodes using a bit flipping algorithm, and the check-node calculation circuit calculates a second syndrome corresponding to the variable nodes; and when the second syndrome indicates that the variable nodes obtained in the second-stage state is incorrect, making the LDPC decoder to repeatedly enter a third-stage state until the decoding is successful, or the iteration number of times of the third-stage state has exceeded a threshold. With the above three-stage configuration for the LDPC decoder, general mechanism would be provided to coordinate with operations performed by the check-node calculation circuit and the variable-node calculation circuit.

Description

低密度奇偶校檢碼的解碼方法及裝置Decoding method and device for low-density parity check code

本發明涉及儲存裝置，尤指一種低密度奇偶校檢碼的解碼方法及裝置。The present invention relates to a storage device, and in particular, to a low-density parity check code decoding method and device.

閃存通常分為NOR閃存與NAND閃存。NOR閃存為隨機存取裝置，中央處理器（Host）可於位址腳位上提供任何存取NOR閃存的位址，並及時地從NOR閃存的資料腳位上獲得儲存於該位址上的資料。相反地，NAND閃存並非隨機存取，而是序列存取。NAND閃存無法像NOR閃存一樣，可以存取任何隨機位址，中央處理器反而需要寫入序列的位元組（Bytes）的值到NAND閃存中，用於定義請求命令（Command）的類型（如，讀取、寫入、抹除等），以及用在此命令上的位址。位址可指向一個頁面（閃存中寫入作業的最小資料塊）或一個區塊（閃存中抹除作業的最小資料塊）。減少從閃存模組讀取資料的過程中的計算資源消耗，一直是影響閃存控制器的整體效能的重要課題。因此，本發明提出一種低密度奇偶校檢碼的解碼方法及裝置，用於減少計算資源的消耗。Flash memory is usually divided into NOR flash memory and NAND flash memory. NOR flash memory is a random access device. The central processor (Host) can provide any address to access the NOR flash memory on the address pin, and obtain the data stored at that address from the data pin of the NOR flash memory in a timely manner. material. In contrast, NAND flash memory does not have random access, but sequential access. NAND flash memory cannot access any random address like NOR flash memory. Instead, the central processor needs to write a sequence of Bytes values into the NAND flash memory to define the type of request command (Command) (such as , read, write, erase, etc.), and the address used on this command. The address can point to a page (the smallest block of data for a write operation in flash memory) or a block (the smallest block of data for an erase operation in flash memory). Reducing the consumption of computing resources in the process of reading data from flash memory modules has always been an important issue that affects the overall performance of flash memory controllers. Therefore, the present invention proposes a low-density parity check code decoding method and device to reduce the consumption of computing resources.

有鑑於此，如何減輕或消除上述相關領域的缺失，實為有待解決的問題。In view of this, how to alleviate or eliminate the deficiencies in the above-mentioned related fields is a problem that needs to be solved.

本說明書涉及一種由低密度奇偶校檢解碼器執行的低密度奇偶校檢碼的解碼方法。所述方法包含以下步驟：當偵測到碼字儲存到靜態隨機存取記憶體時，低密度奇偶校檢（Low-Density Parity-Check，LDPC）解碼器進入第一階段狀態，在所述第一階段狀態中，所述校驗節點計算電路對碼字和奇偶校檢矩陣執行模二乘法以計算出第一校驗子。當第一校驗子指出在第一階段狀態中所獲取的碼字不正確時，LDPC解碼器進入第二階段狀態，在第二階段狀態中，變化節點計算電路依據碼字、相應於碼字的多個第一軟位元和第一校驗子執行位元翻轉演算法以產生多個變化節點，並且計算變化節點的多個第二軟位元；校驗節點計算電路對變化節點和奇偶校檢矩陣執行模二乘法以計算出第二校驗子。當第二校驗子指出在第二階段狀態中產生的變化節點不正確時，LDPC解碼器反覆進入第三階段狀態，直到解碼成功或者第三階段狀態的迭代次數超過閾值為止。在第三階段狀態的每次迭代中，變化節點計算電路依據變化節點、相應於變化節點的第二軟位元和第二校驗子執行位元翻轉演算法以產生多個新的變化節點，並且計算新的變化節點的多個新的第二軟位元；校驗節點計算電路對新的變化節點和奇偶校檢矩陣執行模二乘法以計算出新的第二校驗子。This specification relates to a method of decoding a low-density parity check code performed by a low-density parity check decoder. The method includes the following steps: when it is detected that the codeword is stored in the static random access memory, the low-density parity-check (LDPC) decoder enters the first stage state. In the first-stage state, the check node calculation circuit performs modular square multiplication on the codeword and the parity check matrix to calculate the first syndrome. When the first syndrome indicates that the codeword obtained in the first-stage state is incorrect, the LDPC decoder enters the second-stage state. In the second-stage state, the change node calculation circuit is based on the codeword and corresponds to the codeword. A plurality of first soft bits and a first syndrome perform a bit flip algorithm to generate a plurality of change nodes, and calculate a plurality of second soft bits of the change node; the check node calculation circuit performs a check node calculation circuit on the change node and the parity The check matrix performs modular square multiplication to calculate the second syndrome. When the second syndrome indicates that the changed node generated in the second-stage state is incorrect, the LDPC decoder repeatedly enters the third-stage state until the decoding is successful or the number of iterations of the third-stage state exceeds the threshold. In each iteration of the third stage state, the change node calculation circuit performs a bit flipping algorithm based on the change node, the second soft bit corresponding to the change node, and the second syndrome to generate a plurality of new change nodes, And calculate a plurality of new second soft bits of the new change node; the check node calculation circuit performs a modular square multiplication method on the new change node and the parity check matrix to calculate a new second syndrome.

本說明書另涉及一種低密度奇偶校檢碼的解碼裝置，包含：變化節點計算電路，耦接於靜態隨機存取記憶體；以及校驗節點計算電路，耦接於所述變化節點計算電路。LDPC碼的解碼裝置實施如上所述的低密度奇偶校檢碼的解碼方法。This specification also relates to a low-density parity check code decoding device, which includes: a change node calculation circuit coupled to a static random access memory; and a check node calculation circuit coupled to the change node calculation circuit. The LDPC code decoding device implements the low-density parity check code decoding method described above.

碼字包含使用者資料和LDPC碼。碼字中的每個硬位元對應至少一個第一軟位元，用於指出此硬位元的信心程度，每個變化節點對應至少一個第二軟位元，用於指出此變化節點的信心程度。The codeword contains user information and LDPC code. Each hard bit in the codeword corresponds to at least one first soft bit, which is used to indicate the degree of confidence of this hard bit. Each change node corresponds to at least one second soft bit, which is used to indicate the confidence of this change node. degree.

上述實施例的優點之一，通過如上所述的低密度奇偶校檢解碼器的三階段組態，可提供一般性機制來統合校驗節點計算電路和變化節點計算電路的操作。One of the advantages of the above embodiment is that through the three-stage configuration of the low-density parity check decoder as described above, a general mechanism can be provided to integrate the operations of the check node calculation circuit and the change node calculation circuit.

本發明的其他優點將搭配以下的說明和圖式進行更詳細的解說。Other advantages of the present invention will be explained in more detail in conjunction with the following description and drawings.

以下說明為完成發明的較佳實現方式，其目的在於描述本發明的基本精神，但並不用以限定本發明。實際的發明內容必須參考之後的權利要求範圍。The following description is a preferred implementation manner for completing the invention, and its purpose is to describe the basic spirit of the invention, but is not intended to limit the invention. For the actual invention, reference must be made to the following claims.

必須了解的是，使用於本說明書中的“包含”、“包括”等詞，用以表示存在特定的技術特徵、數值、方法步驟、作業處理、元件以及/或組件，但並不排除可加上更多的技術特徵、數值、方法步驟、作業處理、元件、組件，或以上的任意組合。It must be understood that the words "including" and "include" used in this specification are used to indicate the existence of specific technical features, numerical values, method steps, work processes, components and/or components, but do not exclude the possibility of adding further technical features, values, method steps, processes, components, components, or any combination of the above.

於權利要求中使用如“第一”、“第二”、“第三”等詞是用來修飾權利要求中的元件，並非用來表示之間具有優先順序，前置關係，或者是一個元件先於另一個元件，或者是執行方法步驟時的時間先後順序，僅用來區別具有相同名字的元件。The use of words such as "first", "second" and "third" in the claims is used to modify the elements in the claims, and is not used to indicate that there is a priority, precedence relationship between them, or that they are one element. Prior to another element, or the chronological order in which method steps are performed, it is only used to distinguish elements with the same name.

必須了解的是，當元件描述為“連接”或“耦接”至另一元件時，可以是直接連結、或耦接至其他元件，可能出現中間元件。相反地，當元件描述為“直接連接”或“直接耦接”至另一元件時，其中不存在任何中間元件。使用來描述元件之間關係的其他語詞也可類似方式解讀，例如“介於”相對於“直接介於”，或者是“鄰接”相對於“直接鄰接”等等。It must be understood that when an element is described as being "connected" or "coupled" to another element, it can be directly connected or coupled to the other element, and intervening elements may be present. In contrast, when an element is described as being "directly connected" or "directly coupled" to another element, there are no intervening elements present. Other words used to describe the relationship between elements could be interpreted in a similar fashion, such as "between" versus "directly between," "adjacent" versus "directly adjacent," etc.

參考圖1。電子裝置10包含主機端（Host Side）110、閃存控制器130及閃存模組150，並且閃存控制器130及閃存模組150可合稱為裝置端（Device Side）。電子裝置10可實施於個人電腦、筆記型電腦（Laptop PC）、平板電腦、手機、數位相機、數位攝影機等電子產品之中。主機端110與閃存控制器130的主機介面（Host Interface）131之間可以通用序列匯流排（Universal Serial Bus，USB）、先進技術附著（advanced technology attachment，ATA）、序列先進技術附著（serial advanced technology attachment，SATA）、快速周邊元件互聯（peripheral component interconnect express，PCI-E）、通用快閃記憶儲存（Universal Flash Storage，UFS）、嵌入式多媒體卡（Embedded Multi-Media Card，eMMC）等通訊協定彼此溝通。NAND閃存控制器（NAND Flash Controller，NFC）137的閃存介面（Flash Interface）139與閃存模組150之間可以雙倍資料率（Double Data Rate，DDR）通訊協定彼此溝通，例如，開放NAND快閃（Open NAND Flash Interface，ONFI）、雙倍資料率開關（DDR Toggle）或其他通訊協定。閃存控制器130包含處理單元134，可使用多種方式實施，如使用通用硬體（例如，單一處理器、具平行處理能力的多處理器、圖形處理器或其他具運算能力的處理器），並且在執行軟體以及/或韌體指令時，提供之後描述的功能。處理單元134通過主機介面131接收主機命令，例如讀取命令（Read Command）、寫入命令（Write Command）、丟棄命令（Discard Command）、抹除命令（Erase Command）等，排程並執行這些命令。閃存控制器130另包含隨機存取記憶體（Random Access Memory， RAM）136，可實施為動態隨機存取記憶體（Dynamic Random Access Memory，DRAM）、靜態隨機存取記憶體（Static Random Access Memory，SRAM）或上述兩者的結合，用於配置空間作為資料緩衝區，儲存從主機端110讀取並即將寫入閃存模組150的使用者資料（也可稱為主機資料），以及從閃存模組150讀取並即將輸出給主機端110的使用者資料。隨機存取記憶體136另可儲存執行過程中需要的資料，例如，變數、資料表、主機與閃存位址對照表（Host-to-Flash Address Mapping Table，簡稱H2F表）、閃存與主機位址對照表（Flash-to-Host Address Mapping Table，簡稱F2H表）等。NAND閃存控制器137提供存取閃存模組150時需要的功能，例如命令序列器（Command Sequencer）、低密度奇偶校驗（Low-Density Parity-Check，LDPC）等。Refer to Figure 1. The electronic device 10 includes a host side (Host Side) 110, a flash memory controller 130 and a flash memory module 150, and the flash memory controller 130 and the flash memory module 150 can be collectively referred to as a device side (Device Side). The electronic device 10 can be implemented in electronic products such as personal computers, laptop computers (Laptop PC), tablet computers, mobile phones, digital cameras, and digital video cameras. The host 110 and the host interface (Host Interface) 131 of the flash memory controller 130 can be connected by a Universal Serial Bus (USB), an advanced technology attachment (ATA), or a serial advanced technology attachment (ATA). attachment, SATA), peripheral component interconnect express (PCI-E), Universal Flash Storage (UFS), embedded multi-media card (Embedded Multi-Media Card, eMMC) and other communication protocols are mutually exclusive communication. The flash interface (Flash Interface) 139 of the NAND Flash Controller (NFC) 137 and the flash memory module 150 can communicate with each other using a Double Data Rate (DDR) communication protocol, for example, open NAND flash (Open NAND Flash Interface, ONFI), double data rate switch (DDR Toggle) or other communication protocols. The flash memory controller 130 includes a processing unit 134, which can be implemented in a variety of ways, such as using general-purpose hardware (eg, a single processor, multiple processors with parallel processing capabilities, a graphics processor, or other processors with computing capabilities), and When executing software and/or firmware instructions, the functions described later are provided. The processing unit 134 receives host commands through the host interface 131, such as read command (Read Command), write command (Write Command), discard command (Discard Command), erase command (Erase Command), etc., schedules and executes these commands. . The flash memory controller 130 also includes a random access memory (Random Access Memory, RAM) 136, which can be implemented as a dynamic random access memory (Dynamic Random Access Memory, DRAM) or a static random access memory (Static Random Access Memory, SRAM) or a combination of the above two, is used to configure the space as a data buffer to store user data (also called host data) read from the host 110 and about to be written to the flash memory module 150, and from the flash memory module. The group 150 reads and outputs the user data to the host 110 . The random access memory 136 can also store data needed during execution, such as variables, data tables, host-to-Flash Address Mapping Table (H2F table for short), flash memory and host addresses. Comparison table (Flash-to-Host Address Mapping Table, referred to as F2H table), etc. The NAND flash memory controller 137 provides functions required for accessing the flash memory module 150, such as a command sequencer (Command Sequencer), low-density parity-check (LDPC), etc.

閃存控制器130中可配置共享匯流排架構（Shared Bus Architecture），用於讓元件之間彼此耦接以傳遞資料、位址、控制訊號等，這些元件包含主機介面131、處理單元134、RAM 136、NAND閃存控制器137等。匯流排包含並行的物理線，連接閃存控制器130中兩個以上的組件。共享匯流排是一種共享的傳輸媒體，在任意的時間上，只能有兩個裝置可以使用這些線來彼此溝通，用於傳遞資料。資料及控制訊號能夠在組件間分別沿資料和控制線進行雙向傳播，但另一方面，位址訊號只能沿位址線進行單向傳播。例如，當處理單元134想要讀取RAM 136的特定位址上的資料時，處理單元134在位址線上傳送此位址給RAM 136。接著，此位址的資料會在資料線上回覆給處理單元134。為了完成資料讀取操作，控制訊號會使用控制線進行傳遞。The flash memory controller 130 can be configured with a shared bus architecture (Shared Bus Architecture) for coupling components to each other to transmit data, addresses, control signals, etc. These components include the host interface 131, the processing unit 134, and the RAM 136 , NAND flash memory controller 137, etc. The bus includes parallel physical lines that connect two or more components in the flash memory controller 130 . A shared bus is a shared transmission medium. At any time, only two devices can use these lines to communicate with each other and transfer data. Data and control signals can propagate in both directions between components along data and control lines respectively, but on the other hand, address signals can only propagate in one direction along address lines. For example, when the processing unit 134 wants to read data at a specific address of the RAM 136, the processing unit 134 transmits the address to the RAM 136 on the address line. Then, the data at this address will be returned to the processing unit 134 on the data line. In order to complete the data reading operation, control signals are transmitted using control lines.

閃存模組150提供大量的儲存空間，通常是數百個千兆位元組（Gigabytes，GB），甚至是數個兆兆位元組（Terabytes，TB），用於儲存大量的使用者資料，例如高解析度圖片、影片等。閃存模組150中包含控制電路以及記憶體陣列，記憶體陣列中的記憶單元可組態為單層式單元（Single Level Cells，SLCs）、多層式單元（Multiple Level Cells，MLCs）三層式單元（Triple Level Cells，TLCs）、四層式單元（Quad-Level Cells，QLCs）或上述的任意組合。處理單元134可通過閃存介面139寫入使用者資料到閃存模組150中的指定位址（目的位址），以及從閃存模組150中的指定位址（來源位址）讀取使用者資料。閃存介面139使用數個電子訊號來協調閃存控制器130與閃存模組150間的資料與命令傳遞，包含資料線（Data Line）、時脈訊號（Clock Signal）與控制訊號（Control Signal）。資料線可用於傳遞命令、位址、讀出及寫入的資料；控制訊號線可用於傳遞晶片致能（Chip Enable，CE）、位址提取致能（Address Latch Enable，ALE）、命令提取致能（Command Latch Enable，CLE）、寫入致能（Write Enable，WE）等控制訊號。The flash memory module 150 provides a large amount of storage space, usually hundreds of Gigabytes (GB) or even several Terabytes (TB), for storing large amounts of user data. For example, high-resolution pictures, videos, etc. The flash memory module 150 includes a control circuit and a memory array. The memory cells in the memory array can be configured as single-level cells (Single Level Cells, SLCs) and multi-level cells (Multiple Level Cells, MLCs). (Triple Level Cells, TLCs), Quad-Level Cells (QLCs), or any combination of the above. The processing unit 134 can write user data to a specified address (destination address) in the flash memory module 150 through the flash memory interface 139, and read user data from a specified address (source address) in the flash memory module 150. . The flash memory interface 139 uses several electronic signals to coordinate the transmission of data and commands between the flash memory controller 130 and the flash memory module 150, including data lines (Data Line), clock signals (Clock Signal) and control signals (Control Signal). Data lines can be used to transmit commands, addresses, read and write data; control signal lines can be used to transmit chip enable (Chip Enable, CE), address extraction enable (Address Latch Enable, ALE), command extraction enable Control signals such as Command Latch Enable (CLE) and Write Enable (WE).

參考圖2，閃存模組150中的介面151可包含四個輸出入通道（I/O channels，以下簡稱通道）CH#0至CH#3，每一個通道連接四個NAND閃存單元，例如，通道CH#0連接NAND閃存單元153#0、153#4、153#8及153#12。每個NAND閃存單元可封裝為獨立的芯片（die）。閃存介面139可通過介面151發出致能訊號CE#0至CE#3中的一個來致能NAND閃存單元153#0至153#3、153#4至153#7、153#8至153#11、或153#12至153#15，接著以並行的方式從致能的NAND閃存單元讀取使用者資料，或者寫入使用者資料至致能的NAND閃存單元。所屬技術領域人員可依據系統的需求改變閃存模組150的設計，在閃存模組150中配置更多或更少的通道，和/或將每個通道連接上更多或更少的NAND閃存單元，本發明並不因此受限。Referring to Figure 2, the interface 151 in the flash memory module 150 may include four input/output channels (I/O channels, hereinafter referred to as channels) CH#0 to CH#3, each channel is connected to four NAND flash memory units, for example, channel CH#0 is connected to NAND flash memory cells 153#0, 153#4, 153#8 and 153#12. Each NAND flash memory cell can be packaged as an independent chip (die). The flash memory interface 139 can send one of the enable signals CE#0 to CE#3 through the interface 151 to enable the NAND flash memory units 153#0 to 153#3, 153#4 to 153#7, and 153#8 to 153#11. , or 153#12 to 153#15, and then read user data from the enabled NAND flash memory unit in a parallel manner, or write user data to the enabled NAND flash memory unit. Those skilled in the art can change the design of the flash memory module 150 according to system requirements, configure more or fewer channels in the flash memory module 150, and/or connect each channel to more or fewer NAND flash memory cells. , the present invention is not limited thereby.

NAND閃存控制器137可包含低密度奇偶校檢編碼器（LDPC Encoder），用於依據使用者資料來產生低密度奇偶校檢碼（LDPC Code），其是一種線性的錯誤修正碼（Linear Error Correcting Code）。舉例來說，LDPC碼的產生可使用以下公式表示： MSG _1xn⊙ PCM _{nx (n+m)}= CW _1x(n+m)其中，MSG _1xn代表使用者資料的1列、n行矩陣，PCM _{nx (n+m)}代表n列、(n+m)行奇偶校檢矩陣（Parity Check Matrix），CW _1x(n+m)代表最後產生的碼字（Codeword）的1列、(n+m)行矩陣，⊙代表模2乘法（Modulo 2 Multiplication）。奇偶校檢矩陣可包含類循環（Quasi-Cyclic，QC）結構，並且CW _1x(n+m)中的前n個位元的值等於MSG _1xn的值，而CW _1x(n+m)中的後m個位元的值稱為LDPC碼。舉例如下： 所屬技術領域人員知道可使用習知的奇偶校檢矩陣和高效演算法來產生LDPC碼，例如二階段編碼（2-stage Encoding）等。 The NAND flash memory controller 137 may include a low-density parity check encoder (LDPC Encoder) for generating a low-density parity check code (LDPC Code) based on user data, which is a linear error correction code (Linear Error Correcting Code). For example, the generation of LDPC code can be expressed by the following formula: MSG _1xn ⊙ PCM _{nx (n+m)} = CW _1x(n+m) where MSG _1xn represents a 1-column, n-row matrix of user data, PCM _{nx (n+m)} represents n columns and (n+m) rows Parity Check Matrix, CW _1x(n+m) represents 1 column and (n+m) of the last generated codeword (Codeword) Row matrix, ⊙ represents Modulo 2 Multiplication. The parity check matrix can contain a Quasi-Cyclic (QC) structure, and the value of the first n bits in CW _1x(n+m) is equal to the value of MSG _1xn , while the value of the first n bits in CW _1x(n+m) The value of the last m bits is called the LDPC code. Examples are as follows: Those skilled in the art know that conventional parity check matrices and efficient algorithms can be used to generate LDPC codes, such as two-stage encoding (2-stage Encoding).

NAND閃存控制器137可包含LDPC解碼器（LDPC Decoder）138，用於校驗通過閃存介面139從閃存模組150被讀出的碼字（Codeword，包含使用者資料和LDPC碼）並判斷碼字中是否包含錯誤位元。一旦發現碼字中存在錯誤位元，LDPC解碼器138嘗試回復出正確的碼字，並且從碼字中獲取使用者資料。如果經過預定數目的嘗試，還沒有辦法回復出正確的碼字，則LDPC解碼器138判定此碼字為無法修復錯誤的碼字（Uncorrectable Codeword）。關於LDPC解碼，參考圖3所示的範例(n=3, k=6)LDPC碼。方塊33#0至33#5代表變化節點（Variable Nodes），方塊31#0至31#2代表校驗節點（Check Nodes）。變化節點33#0至33#5中的位元形成碼字，由使用者資料和LDPC碼組成，其中的位元必須滿足圖形限制（Graphical Constrains）。詳細來說，所有連接到一個變化節點的線具有相同的值，並且所有連接到一個校驗節點的加總必須除以二後的餘數為0（也就是說，其加總起來為偶數，或者具有偶數個奇數值）。校驗節點31#0至31#2又可稱為校驗子（Syndrome）。The NAND flash memory controller 137 may include an LDPC decoder (LDPC Decoder) 138 for verifying the codeword (including user information and LDPC code) read from the flash memory module 150 through the flash memory interface 139 and determining the codeword. contains error bits. Once an erroneous bit is found in the codeword, the LDPC decoder 138 attempts to recover the correct codeword and obtains user information from the codeword. If the correct codeword cannot be recovered after a predetermined number of attempts, the LDPC decoder 138 determines that the codeword is an uncorrectable codeword. Regarding LDPC decoding, refer to the example (n=3, k=6) LDPC code shown in Figure 3. Blocks 33#0 to 33#5 represent Variable Nodes, and blocks 31#0 to 31#2 represent Check Nodes. The bits in the change nodes 33#0 to 33#5 form a codeword, which is composed of user data and LDPC code. The bits must meet the graphic constraints (Graphical Constrains). Specifically, all lines connected to a change node have the same value, and the sum of all lines connected to a check node must leave a remainder of 0 when divided by two (that is, they add up to an even number, or has an even number of odd values). Check nodes 31#0 to 31#2 can also be called syndromes (Syndrome).

NAND閃存控制器137還包含靜態隨機存取記憶體（Static Random Access Memory，SRAM）140，用於儲存解碼過程中所需的資料。閃存介面139可儲存從閃存模組150讀取的碼字（又可稱為硬位元）和軟位元在SRAM 140中的指定位址。每個硬位元可對應至少一個軟位元，對應的軟位元用於指出此硬位元的信心程度（Likelihood of Belief）。為了修正碼字中的錯誤位元，SRAM 140還需要配置空間來儲存在解碼過程中的更新後的變化節點以及其對應的軟位元。類似地，每個變化節點可對應至少一個軟位元，對應的軟位元用於指出此變化節點的信心程度。然而，SRAM 140是珍貴的資源，需要妥善的規劃和使用以提高其利用率（Utilization）。The NAND flash memory controller 137 also includes a static random access memory (Static Random Access Memory, SRAM) 140 for storing data required during the decoding process. The flash memory interface 139 can store the code words (also called hard bits) read from the flash memory module 150 and the specified addresses of the soft bits in the SRAM 140 . Each hard bit can correspond to at least one soft bit, and the corresponding soft bit is used to indicate the confidence of the hard bit (Likelihood of Belief). In order to correct the erroneous bits in the codeword, the SRAM 140 also needs configuration space to store the updated changed nodes and their corresponding soft bits during the decoding process. Similarly, each change node may correspond to at least one soft bit, and the corresponding soft bit is used to indicate the degree of confidence of this change node. However, SRAM 140 is a precious resource and requires proper planning and use to improve its utilization.

LDPC解碼器（LDPC Decoder）138包含兩個重要的電路：校驗節點計算電路（Check-node Calculation Circuit）和變化節點計算電路（Variable-node Calculation Circuit）。校驗節點計算電路對碼字或者變化節點，以及奇偶校檢矩陣執行模二乘法以計算出校驗子。變化節點計算電路依據相應於碼字或者變化節點的軟位元，以及校驗子執行習知的位元翻轉演算法（Bit Flipping Algorithm）以產生新的變化節點，並且使用習知的公式來計算新的變化節點的軟位元。然而，校驗節點計算電路和變化節點計算電路的操作之間是相互依賴的，一個電路產生的結果會是另一個電路的輸入，因此，需要一般性機制來統合校驗節點計算電路和變化節點計算電路的操作。LDPC Decoder 138 includes two important circuits: Check-node Calculation Circuit and Variable-node Calculation Circuit. The check node calculation circuit performs modular square multiplication on the codeword or change node, and the parity check matrix to calculate the syndrome. The change node calculation circuit performs a known bit flipping algorithm (Bit Flipping Algorithm) based on the soft bits corresponding to the codeword or change node and the syndrome to generate a new change node, and uses the known formula to calculate The soft bits of the new change node. However, the operations of the check node calculation circuit and the change node calculation circuit are interdependent. The result produced by one circuit will be the input of the other circuit. Therefore, a general mechanism is needed to integrate the check node calculation circuit and the change node. Compute the operation of circuits.

為了統合校驗節點計算電路和變化節點計算電路的操作，本發明實施例提出三階段的LDPC解碼。LDPC解碼器138可視情況進入三階段中的一者，使得其中的校驗節點計算電路和變化節點計算電路據以完成進入階段的操作。詳細來說，當偵測到碼字儲存到靜態隨機存取記憶體140時，LDPC解碼器138進入第一階段狀態。在第一階段狀態中，校驗節點計算電路對碼字和預設的奇偶校檢矩陣執行模二乘法以計算出第一校驗子，其中，碼字包含使用者資料和低密度奇偶校檢碼的多個位元。當第一校驗子指出在第一階段狀態中所獲取的碼字不正確時，LDPC解碼器138進入第二階段狀態。在第二階段狀態中，變化節點計算電路依據碼字、相應於碼字的多個第一軟位元和第一校驗子執行位元翻轉演算法以產生多個變化節點，並且計算變化節點的多個第二軟位元。校驗節點計算電路對變化節點和預設的奇偶校檢矩陣執行模二乘法以計算出第二校驗子。碼字中的每個硬位元對應至少一個第一軟位元，用於指出此硬位元的信心程度。每個變化節點對應至少一個第二軟位元，用於指出此變化節點的信心程度。當第二校驗子指出在第二階段狀態中產生的變化節點不正確時，LDPC解碼器138反覆進入第三階段狀態，直到解碼成功或者第三階段狀態的迭代次數超過閾值為止。在第三階段狀態的每次迭代中，變化節點計算電路依據變化節點、相應於變化節點的第二軟位元和第二校驗子執行位元翻轉演算法以產生多個新的變化節點，並且計算新的變化節點的多個新的第二軟位元。校驗節點計算電路對新的變化節點和奇偶校檢矩陣執行模二乘法以計算出新的第二校驗子。In order to integrate the operations of the check node calculation circuit and the change node calculation circuit, embodiments of the present invention propose a three-stage LDPC decoding. The LDPC decoder 138 can enter one of the three stages according to the situation, so that the check node calculation circuit and the change node calculation circuit therein can complete the operation of entering the stage accordingly. Specifically, when it is detected that the codeword is stored in the static random access memory 140, the LDPC decoder 138 enters the first stage state. In the first stage state, the check node calculation circuit performs modular square multiplication on the codeword and the preset parity check matrix to calculate the first syndrome, where the codeword includes user information and low-density parity check Multiple bits of code. When the first syndrome indicates that the codeword obtained in the first stage state is incorrect, the LDPC decoder 138 enters the second stage state. In the second stage state, the change node calculation circuit performs a bit flipping algorithm according to the codeword, a plurality of first soft bits corresponding to the codeword, and a first syndrome to generate a plurality of change nodes, and calculates the change node multiple second soft bits. The check node calculation circuit performs modular square multiplication on the change node and the preset parity check matrix to calculate the second syndrome. Each hard bit in the codeword corresponds to at least one first soft bit, which is used to indicate the degree of confidence of this hard bit. Each change node corresponds to at least one second soft bit, which is used to indicate the degree of confidence of this change node. When the second syndrome indicates that the changed node generated in the second stage state is incorrect, the LDPC decoder 138 repeatedly enters the third stage state until the decoding is successful or the number of iterations of the third stage state exceeds the threshold. In each iteration of the third stage state, the change node calculation circuit performs a bit flipping algorithm based on the change node, the second soft bit corresponding to the change node, and the second syndrome to generate a plurality of new change nodes, and calculating a plurality of new second soft bits for the new change node. The check node calculation circuit performs modular square multiplication on the new change node and the parity check matrix to calculate a new second syndrome.

在一些實施例中，LDPC解碼器138可包含有限狀態機，用於因應碼字儲存到靜態隨機存取記憶體140的情況時，讓LDPC解碼器138處於第一階段狀態；因應第一校驗子指出在第一階段狀態中所獲取的碼字不正確的情況時，讓LDPC解碼器138處於第二階段狀態；因應第二校驗子指出在第二階段狀態或前一個第三階段中所產生的變化節點不正確的情況時，讓LDPC解碼器138處於第三階段狀態；以及控制進入第三階段狀態的迭代次數不超過閾值。In some embodiments, the LDPC decoder 138 may include a finite state machine, which is used to put the LDPC decoder 138 in the first stage state in response to the situation where the codeword is stored in the static random access memory 140; in response to the first verification When the second checksum indicates that the codeword obtained in the first stage state is incorrect, the LDPC decoder 138 is in the second stage state; in response to the second syndrome indicating that the codeword obtained in the second stage state or the previous third stage is incorrect, the LDPC decoder 138 is in the second stage state. When the generated change node is incorrect, the LDPC decoder 138 is placed in the third stage state; and the number of iterations to control entering the third stage state does not exceed the threshold.

在一些實施例中，閃存介面139可包含軟位元計算電路（Soft-bit Calculation Circuit），用於在從閃存模組150讀取碼字的時候，為碼字中的每個硬位元計算軟位元。因應這種設置，參考圖4所示的NAND閃存控制器137的方塊圖。SRAM 430中可配置四個區域431、433、435和437，用於分別儲存硬位元、硬位元所對應的軟位元、變化節點、變化節點所對應的軟位元。閃存介面139將從閃存模組150讀取的硬位元寫入區域431，並且將計算出來的軟位元寫入區域433。LDPC解碼器410包含有限狀態機（Finite State Machine，FSM）412、多工器413、414、變化節點計算電路416和校驗節點計算電路418。校驗節點計算電路418用於依據區域431中儲存的硬位元或者區域435中儲存的變化節點，以及奇偶校檢矩陣來計算出校驗子。校驗子的產生可使用以下公式表示： PCM _{nx (n+m)}⊙ CW _{( n+m )x 1}= SYD _mx1其中，PCM _{nx (n+m)}代表n列、(n+m)行奇偶校檢矩陣，MSG _(n+m)x1代表碼字的(n+m)列、1行矩陣， SYD _mx1代表校驗子的m列、1行矩陣，⊙代表模2乘法。舉例如下： 由於計算後的校驗子為全”0”，碼字中不包含錯誤位元。如果計算後的校驗子不為全”0”，則碼字中包含錯誤位元。校驗節點計算電路418可輸出硬位元或者變化節點，以及計算出的校驗子至變化節點計算電路416。在一些實施例中，校驗節點計算電路418可依據相應於硬位元或者變化節點的軟位元計算校驗子的可靠度（Reliability of Syndrome），並且將校驗子及其可靠度一併傳送到變化節點計算電路416。 In some embodiments, the flash memory interface 139 may include a soft-bit calculation circuit for calculating each hard bit in the codeword when reading the codeword from the flash memory module 150 . Soft bits. For this arrangement, reference is made to the block diagram of the NAND flash memory controller 137 shown in FIG. 4 . Four areas 431, 433, 435 and 437 can be configured in the SRAM 430 for respectively storing hard bits, soft bits corresponding to the hard bits, change nodes, and soft bits corresponding to the change nodes. The flash memory interface 139 writes the hard bits read from the flash memory module 150 into the area 431 and writes the calculated soft bits into the area 433 . The LDPC decoder 410 includes a finite state machine (Finite State Machine, FSM) 412, multiplexers 413 and 414, a change node calculation circuit 416 and a check node calculation circuit 418. The check node calculation circuit 418 is used to calculate the syndrome based on the hard bits stored in the area 431 or the change nodes stored in the area 435, and the parity check matrix. The generation of the syndrome can be expressed by the following formula: PCM _{nx (n+m)} ⊙ CW _{( n+m )x 1} = SYD _mx1 where, PCM _{nx (n+m)} represents n columns and (n+m) row odd and even Check matrix, MSG _(n+m)x1 represents the (n+m) column, 1-row matrix of the codeword, SYD _mx1 represents the m-column, 1-row matrix of the syndrome, ⊙ represents modulo 2 multiplication. Examples are as follows: Since the calculated syndrome is all "0", the codeword does not contain error bits. If the calculated syndrome is not all "0", the codeword contains erroneous bits. The check node calculation circuit 418 may output hard bits or change nodes, and the calculated syndrome to the change node calculation circuit 416 . In some embodiments, the check node calculation circuit 418 can calculate the reliability of the syndrome (Reliability of Syndrome) based on the soft bits corresponding to the hard bits or the change nodes, and combine the syndrome and its reliability. transmitted to the change node calculation circuit 416.

變化節點計算電路416用於依據從校驗節點計算電路418輸入的校驗子判斷是否需要修正碼字。如果不需要（也就是校驗子為全”0”），則變化節點計算電路416傳送解碼成功的訊息給有限狀態機412。如果需要（也就是校驗子不為全”0”），則變化節點計算電路416傳送解碼失敗的訊息給有限狀態機412，並且根據校驗子、硬位元或者變化節點、相應於硬位元或者變化節點的軟位元，執行習知的位元翻轉演算法，用於將碼字中可能出錯的一個或者多個硬位元或者變化節點進行狀態改變（也就是將”0b0”改變為”0b1”，或者將”0b1”改變為”0b0”）。變化節點計算電路416儲存更新後的變化節點至SRAM 430中的區域435。接著，變化節點計算電路416依據更新後的變化節點使用習知的公式來計算相應於更新後的變化節點的軟位元，並且儲存計算出的軟位元至SRAM 430中的區域437。軟位元可以是對數似然比（Log-likelihood Ratio，LLR）、對數似然比的量化值（Quantization of LLR）等。The change node calculation circuit 416 is used to determine whether the codeword needs to be modified based on the syndrome input from the check node calculation circuit 418. If it is not needed (that is, the syndrome is all “0”), the change node calculation circuit 416 sends a decoding success message to the finite state machine 412 . If necessary (that is, the syndrome is not all "0"), the change node calculation circuit 416 sends a decoding failure message to the finite state machine 412, and calculates the decoding failure information based on the syndrome, the hard bit or the change node, corresponding to the hard bit. The soft bits of the bits or change nodes are executed to perform the conventional bit flip algorithm, which is used to change the state of one or more hard bits or change nodes that may be in error in the codeword (that is, change "0b0" to "0b1", or change "0b1" to "0b0"). The change node calculation circuit 416 stores the updated change node into the area 435 in the SRAM 430 . Then, the change node calculation circuit 416 uses a conventional formula to calculate the soft bits corresponding to the updated change node according to the updated change node, and stores the calculated soft bits to the area 437 in the SRAM 430 . The soft bits can be log-likelihood ratio (Log-likelihood Ratio, LLR), quantization value of log-likelihood ratio (Quantization of LLR), etc.

有限狀態機412使用三個階段來管理LDPC解碼的整個流程，在每個階段中，輸出適當的控制訊號給多工器413、414和變化節點計算電路416，用於驅動這些元件以共同完成LDPC解碼。圖5顯示有限狀態機412的範例狀態轉換。多工器413的輸出端耦接至變化節點計算電路416，並且多工器413的兩個輸入端分別耦接至SRAM 430中的區域431和435。多工器414的輸出端耦接至變化節點計算電路416，並且多工器414的兩個輸入端分別耦接至SRAM 430中的區域433和437。The finite state machine 412 uses three stages to manage the entire process of LDPC decoding. In each stage, appropriate control signals are output to the multiplexers 413, 414 and the change node calculation circuit 416 to drive these components to jointly complete the LDPC Decode. Figure 5 shows example state transitions of finite state machine 412. The output terminal of the multiplexer 413 is coupled to the changing node calculation circuit 416, and the two input terminals of the multiplexer 413 are coupled to areas 431 and 435 in the SRAM 430, respectively. The output terminal of the multiplexer 414 is coupled to the changing node calculation circuit 416, and the two input terminals of the multiplexer 414 are coupled to regions 433 and 437 in the SRAM 430, respectively.

當閃存介面139將硬位元和軟位元分別儲存到區域431和433後，有限狀態機412從等待狀態510進入第一階段狀態531。第一階段可稱為硬位元初始階段。在第一階段中，有限狀態機412發出控制訊號給多工器413以將區域431耦接上變化節點計算電路416，接著，驅動變化節點計算電路416執行第一階段的操作。參考圖6所示的第一階段的資料流示意圖，變化節點計算電路416通過多工器413從區域431讀取硬位元（以符號“sgn”表示），並且將硬位元傳送到校驗節點計算電路418。校驗節點計算電路418依據獲取的硬位元和預設的奇偶校檢矩陣計算校驗子，並且將硬位元和校驗子傳送到變化節點計算電路416。當校驗子為全”0”時，變化節點計算電路416傳送解碼成功的訊息給有限狀態機412，使得有限狀態機412進入解碼成功狀態551。當校驗子不為全”0”時，變化節點計算電路416將硬位元儲存至區域435，並且傳送解碼失敗的訊息給有限狀態機412，使得有限狀態機412進入第二階段狀態532。由於硬位元已經成功儲存到區域435，區域431已經不需要給目前正處理中的碼字使用，因此，區域431可被釋放以儲存從閃存模組150讀出的下一個碼字，從而讓此碼字和下個碼字的解碼能夠並行，提升資料讀取的效率。After the flash memory interface 139 stores the hard bits and soft bits into areas 431 and 433 respectively, the finite state machine 412 enters the first stage state 531 from the waiting state 510 . The first stage can be called the hard bit initialization stage. In the first stage, the finite state machine 412 sends a control signal to the multiplexer 413 to couple the area 431 to the change node calculation circuit 416, and then drives the change node calculation circuit 416 to perform the first stage operation. Referring to the data flow diagram of the first stage shown in Figure 6, the change node calculation circuit 416 reads the hard bits (indicated by the symbol "sgn") from the area 431 through the multiplexer 413, and transmits the hard bits to the checksum Node calculation circuit 418. The check node calculation circuit 418 calculates the syndrome based on the acquired hard bits and the preset parity check matrix, and transmits the hard bits and syndrome to the change node calculation circuit 416 . When the syndrome is all "0", the change node calculation circuit 416 sends a decoding success message to the finite state machine 412, so that the finite state machine 412 enters the decoding success state 551. When the syndrome is not all "0", the change node calculation circuit 416 stores the hard bits in the area 435 and sends a decoding failure message to the finite state machine 412, so that the finite state machine 412 enters the second stage state 532. Since the hard bits have been successfully stored in area 435, area 431 is no longer needed for the codeword currently being processed. Therefore, area 431 can be released to store the next codeword read from the flash memory module 150, thereby allowing The decoding of this codeword and the next codeword can be performed in parallel, improving the efficiency of data reading.

第二階段可稱為軟位元初始和解碼階段，包含解碼的第一次迭代。在第二階段中，有限狀態機412發出控制訊號給多工器413以將區域435連接上變化節點計算電路416，發出控制訊號給多工器414以將區域433耦接上變化節點計算電路416，接著，驅動變化節點計算電路416執行第二階段的操作。參考圖7所示的第二階段的資料流示意圖，變化節點計算電路416通過多工器413從區域435讀取硬位元（以符號“sgn”表示），通過多工器414從區域433讀取軟位元（以符號“mag”表示），依據第一階段計算出來的校驗子、硬位元sgn和軟位元mag，執行習知的位元翻轉演算法，用於更新硬位元sgn成為變化節點sgn’，並且依據更新後的變化節點sgn’使用習知的公式來計算相應的軟位元mag’。接著，變化節點計算電路416傳送變化節點sgn’和相應的軟位元mag’到校驗節點計算電路418。校驗節點計算電路418依據獲取的變化節點sgn’和預設的奇偶校檢矩陣計算校驗子，並且將變化節點sgn’、相應的軟位元mag’和校驗子傳送到變化節點計算電路416。當校驗子為全”0”時，變化節點計算電路416傳送解碼成功的訊息給有限狀態機412，使得有限狀態機412進入解碼成功狀態551。當校驗子不為全”0”時，變化節點計算電路416將變化節點sgn’儲存至區域435，將相應軟位元mag’儲存至區域437，並且傳送解碼失敗的訊息給有限狀態機412，使得有限狀態機412進入第三階段狀態533。由於初始的軟位元已經更新並且成功地儲存到區域437，區域433已經不需要給目前正處理中的碼字使用，因此，區域433可被釋放以讓閃存介面139儲存相應於下一個碼字的軟位元，從而讓此碼字和下個碼字的解碼能夠並行，提升資料讀取的效率。The second phase can be called the soft bit initialization and decoding phase and contains the first iteration of decoding. In the second stage, the finite state machine 412 sends a control signal to the multiplexer 413 to connect the area 435 to the change node calculation circuit 416, and sends a control signal to the multiplexer 414 to couple the area 433 to the change node calculation circuit 416. , then, drive the change node calculation circuit 416 to perform the second stage of operation. Referring to the data flow diagram of the second stage shown in Figure 7, the change node calculation circuit 416 reads the hard bits (indicated by the symbol "sgn") from the area 435 through the multiplexer 413, and reads the hard bits (indicated by the symbol "sgn") from the area 433 through the multiplexer 414. Take the soft bit (represented by the symbol "mag"), and perform the well-known bit flip algorithm based on the syndrome, hard bit sgn and soft bit mag calculated in the first stage to update the hard bit sgn becomes the change node sgn', and the corresponding soft bit mag' is calculated using the conventional formula according to the updated change node sgn'. Next, the change node calculation circuit 416 transmits the change node sgn' and the corresponding soft bit mag' to the check node calculation circuit 418. The check node calculation circuit 418 calculates the syndrome based on the obtained change node sgn' and the preset parity check matrix, and transmits the change node sgn', the corresponding soft bit mag' and the syndrome to the change node calculation circuit 416. When the syndrome is all "0", the change node calculation circuit 416 sends a decoding success message to the finite state machine 412, so that the finite state machine 412 enters the decoding success state 551. When the syndrome is not all "0", the change node calculation circuit 416 stores the change node sgn' in the area 435, stores the corresponding soft bit mag' in the area 437, and sends a decoding failure message to the finite state machine 412 , causing the finite state machine 412 to enter the third stage state 533. Since the initial soft bits have been updated and successfully stored in area 437, area 433 is no longer needed for the codeword currently being processed. Therefore, area 433 can be released to allow the flash memory interface 139 to store the corresponding codeword. of soft bits, so that the decoding of this codeword and the next codeword can be performed in parallel, improving the efficiency of data reading.

第三階段可包含第二次或者以後次數的解碼迭代。此階段會反覆執行，直到解碼成功，或者超過預設次數的迭代還不能解碼成功為止。進入第三階段的一開始，有限狀態機412發出控制訊號給多工器414以將區域437連接上變化節點計算電路416，接著，驅動變化節點計算電路416執行第三階段的操作。參考圖8所示的第三階段的資料流示意圖，變化節點計算電路416通過多工器413從區域435讀取變化節點（以符號“sgn’”表示），通過多工器414從區域437讀取相應的軟位元（以符號“mag’”表示），依據前一個解碼迭代（可存在第二階段或者第三階段之中）計算出來的校驗子、變化節點sgn’和軟位元mag’，執行習知的位元翻轉演算法，用於更新變化節點sgn’成為變化節點sgn”，並且依據更新後的變化節點sgn”使用習知的公式來計算相應的軟位元mag”。接著，變化節點計算電路416傳送變化節點sgn”和相應的軟位元mag”到校驗節點計算電路418。校驗節點計算電路418依據獲取的變化節點sgn”和預設的奇偶校檢矩陣計算校驗子，並且將變化節點sgn”、相應的軟位元mag”和校驗子傳送到變化節點計算電路416。當校驗子為全”0”時，變化節點計算電路416傳送解碼成功的訊息給有限狀態機412，使得有限狀態機412進入解碼成功狀態551。當校驗子不為全”0”時，變化節點計算電路416將變化節點sgn”儲存至區域435，將相應軟位元mag”儲存至區域437，並且傳送解碼失敗的訊息給有限狀態機412，使得有限狀態機412維持在第三階段狀態533，或者進入到解碼錯誤狀態553。The third stage may include the second or subsequent decoding iterations. This phase will be executed repeatedly until decoding is successful, or decoding fails after more than a preset number of iterations. At the beginning of entering the third stage, the finite state machine 412 sends a control signal to the multiplexer 414 to connect the area 437 to the change node calculation circuit 416, and then drives the change node calculation circuit 416 to perform the operation of the third stage. Referring to the data flow diagram of the third stage shown in Figure 8, the change node calculation circuit 416 reads the change node (indicated by the symbol "sgn'") from the area 435 through the multiplexer 413, and reads the change node from the area 437 through the multiplexer 414. Take the corresponding soft bit (represented by the symbol "mag'"), and calculate the syndrome, change node sgn' and soft bit mag based on the previous decoding iteration (can exist in the second or third stage) ', execute the known bit flip algorithm to update the change node sgn' to become the change node sgn", and use the known formula to calculate the corresponding soft bit mag" based on the updated change node sgn". Then , the change node calculation circuit 416 transmits the change node sgn” and the corresponding soft bit mag” to the check node calculation circuit 418. The check node calculation circuit 418 calculates the checksum based on the obtained change node sgn” and the preset parity check matrix. The syndrome is generated, and the change node sgn", the corresponding soft bit mag" and the syndrome are transmitted to the change node calculation circuit 416. When the syndrome is all "0", the change node calculation circuit 416 sends a decoding success message to the finite state machine 412, so that the finite state machine 412 enters the decoding success state 551. When the syndrome is not all “0”, the change node calculation circuit 416 stores the change node sgn” into the area 435, stores the corresponding soft bit mag” into the area 437, and sends a decoding failure message to the finite state machine 412 , causing the finite state machine 412 to remain in the third stage state 533, or enter the decoding error state 553.

當有限狀態機412處於第三階段狀態533並且從變化節點計算電路416獲取解碼失敗的訊息時，有限狀態機412會判斷第三階段的已執行的迭代次數是否超過預設的閾值。如果是，有限狀態機412進入解碼錯誤狀態553。否則，有限狀態機412維持在第三階段狀態533，並且驅動變化節點計算電路416執行第三階段的操作。When the finite state machine 412 is in the third stage state 533 and obtains the decoding failure message from the change node calculation circuit 416, the finite state machine 412 determines whether the number of iterations executed in the third stage exceeds a preset threshold. If so, finite state machine 412 enters decoding error state 553. Otherwise, the finite state machine 412 maintains the third stage state 533 and drives the change node calculation circuit 416 to perform the third stage operation.

在解碼成功狀態551中，有限狀態機412獲取碼字中的使用者資料，儲存使用者資料到RAM 136中的指定位置，並且回覆解碼成功的訊息給處理單元134。In the decoding success state 551, the finite state machine 412 obtains the user data in the codeword, stores the user data in a designated location in the RAM 136, and returns a decoding success message to the processing unit 134.

在解碼錯誤狀態553中，有限狀態機412回覆解碼失敗的訊息給處理單元134，使得理單元134能夠據以判定出現了UECC頁面。In the decoding error state 553, the finite state machine 412 returns a decoding failure message to the processing unit 134, so that the processing unit 134 can determine that a UECC page occurs accordingly.

在另一些實施例中，閃存介面139不包含軟位元計算電路。因應這種設置，圖4所示的NAND閃存控制器137可改為圖9所示的方塊圖。相較於SRAM 430，SRAM 930減少了用以儲存硬位元所對應的軟位元的區域433。相較於LDPC解碼器410，LDPC解碼器910減少了多工器414。有限狀態機912可使用圖5所示的範例狀態轉換來控制整個LDPC解碼的過程。在以上所述的三個階段中，只有第二階段做了些許改變，其餘的技術細節都類似。In other embodiments, the flash memory interface 139 does not include soft bit calculation circuitry. In response to this arrangement, the NAND flash memory controller 137 shown in FIG. 4 can be changed to the block diagram shown in FIG. 9 . Compared with the SRAM 430, the SRAM 930 reduces the area 433 for storing soft bits corresponding to the hard bits. Compared with the LDPC decoder 410, the LDPC decoder 910 has fewer multiplexers 414. The finite state machine 912 can control the entire LDPC decoding process using the example state transition shown in FIG. 5 . Among the three stages mentioned above, only the second stage has made some changes, and the rest of the technical details are similar.

圖10所示的第一階段的資料流示意圖，相似於圖6，因此，第一階段的技術細節可從圖6的說明推導而得，為求簡明不再贅述。The data flow schematic diagram of the first stage shown in Figure 10 is similar to Figure 6. Therefore, the technical details of the first stage can be deduced from the description of Figure 6 and will not be repeated for the sake of simplicity.

在第二階段中，有限狀態機912發出控制訊號給多工器413以將區域435連接上變化節點計算電路916，接著，驅動變化節點計算電路916執行第二階段的操作。參考圖11所示的第二階段的資料流示意圖，變化節點計算電路416通過多工器413從區域435讀取硬位元（以符號“sgn”表示），將軟位元設為預設值（以符號“mag*”表示，例如，全部都強、全部都中等或者全部都弱），依據第一階段計算出來的校驗子、硬位元sgn和預設軟位元mag*，執行習知的位元翻轉演算法，用於更新硬位元sgn成為變化節點sgn’，並且依據更新後的變化節點sgn’使用習知的公式來計算相應的軟位元mag’。接著，變化節點計算電路416傳送變化節點sgn’和相應的軟位元mag’到校驗節點計算電路418。第二階段中的後續技術細節，可參考圖7的相應說明，為求簡明不再贅述。In the second stage, the finite state machine 912 sends a control signal to the multiplexer 413 to connect the area 435 to the change node calculation circuit 916, and then drives the change node calculation circuit 916 to perform the second stage operation. Referring to the data flow diagram of the second stage shown in Figure 11, the change node calculation circuit 416 reads the hard bits (indicated by the symbol "sgn") from the area 435 through the multiplexer 413, and sets the soft bits to the default value. (Indicated by the symbol "mag*", for example, all are strong, all are medium, or all are weak). Based on the syndrome calculated in the first stage, the hard bit sgn and the preset soft bit mag*, the exercise is executed. The well-known bit flip algorithm is used to update the hard bit sgn to become the change node sgn', and use the well-known formula to calculate the corresponding soft bit mag' based on the updated change node sgn'. Next, the change node calculation circuit 416 transmits the change node sgn' and the corresponding soft bit mag' to the check node calculation circuit 418. For subsequent technical details in the second stage, please refer to the corresponding description in Figure 7, and will not be repeated for the sake of simplicity.

圖12所示的第三階段的資料流示意圖，相似於圖8，因此，第三階段的技術細節可從圖8的說明推導而得，為求簡明不再贅述。The data flow schematic diagram of the third stage shown in Figure 12 is similar to Figure 8. Therefore, the technical details of the third stage can be deduced from the description of Figure 8, and will not be repeated for the sake of simplicity.

在另一些實施例中，閃存介面139包含軟位元計算電路，並且LDPC編碼器為一種以零為基礎的差異編碼器（Zero-based Differential Decoder）。因應這種設置，圖4所示的NAND閃存控制器137可改為圖13所示的方塊圖。相較於SRAM 430，SRAM 1330中沒有配置儲存變動節點的區域，取而代之的是在SRAM 1330中配置了儲存翻轉狀態的區域1335。翻轉狀態包含多個位元，每個位元儲存相應硬位元是否翻轉的資訊，例如，”0b1”代表翻轉（也就是改變狀態），”0b0”代表不翻轉（也就是維持原來的狀態）。翻轉狀態初始時為全”0”。LDPC解碼器1310包含有限狀態機1312、互斥或計算器1313、多工器414、變化節點計算電路1316和校驗節點計算電路1318。互斥或計算器1313用於將區域431中儲存的硬位元和區域1335中儲存的翻轉狀態進行互斥或計算，用於產生原始的硬位元或者更新後的變化節點。校驗節點計算電路1318用於依據互斥或計算器1313所輸出的計算結果，以及奇偶校檢矩陣來計算出校驗子。變化節點計算電路1316針對校驗子的判斷及其後續操作、習知的位元翻轉演算法的執行，以及軟位元的計算等技術細節，大致相同於變化節點計算電路416，為求簡明不再贅述。與變化節點計算電路416不同的是，變化節點計算電路1316儲存更新後的翻轉狀態至SRAM 1330中的區域1335。In other embodiments, the flash memory interface 139 includes soft bit calculation circuitry, and the LDPC encoder is a zero-based differential decoder. In response to this arrangement, the NAND flash memory controller 137 shown in FIG. 4 can be changed to the block diagram shown in FIG. 13 . Compared with the SRAM 430, the SRAM 1330 is not configured with an area for storing changed nodes. Instead, the SRAM 1330 is configured with an area 1335 for storing flip states. The flip state contains multiple bits, and each bit stores information about whether the corresponding hard bit is flipped. For example, "0b1" means flipping (that is, changing the state), and "0b0" means not flipping (that is, maintaining the original state) . The flip state is initially all "0". The LDPC decoder 1310 includes a finite state machine 1312, an exclusive OR calculator 1313, a multiplexer 414, a change node calculation circuit 1316 and a check node calculation circuit 1318. The mutual exclusion OR calculator 1313 is used to mutually exclusive or calculate the hard bits stored in the area 431 and the flip state stored in the area 1335 to generate original hard bits or updated change nodes. The check node calculation circuit 1318 is used to calculate the syndrome according to the calculation result output by the mutual exclusive OR calculator 1313 and the parity check matrix. The change node calculation circuit 1316 is roughly the same as the change node calculation circuit 416 in terms of the syndrome judgment and subsequent operations, the execution of the conventional bit flipping algorithm, and the calculation of soft bits. Again. Different from the change node calculation circuit 416, the change node calculation circuit 1316 stores the updated flip state to the area 1335 in the SRAM 1330.

有限狀態機1312使用三個階段來管理LDPC解碼的整個流程，在每個階段中，輸出適當的控制訊號給多工器1314和變化節點計算電路1316，用於驅動這些元件以共同完成LDPC解碼。有限狀態機1312可使用圖5所示的範例狀態轉換來控制整個LDPC解碼的過程。The finite state machine 1312 uses three stages to manage the entire process of LDPC decoding. In each stage, appropriate control signals are output to the multiplexer 1314 and the change node calculation circuit 1316 to drive these components to jointly complete the LDPC decoding. The finite state machine 1312 can control the entire LDPC decoding process using the example state transition shown in FIG. 5 .

在第一階段中，有限狀態機1312驅動變化節點計算電路1316執行第一階段的操作。參考圖14所示的第一階段的資料流示意圖，變化節點計算電路1316通過互斥或計算器1313讀取硬位元（以符號“sgn”表示），並且將硬位元傳送到校驗節點計算電路1318。校驗節點計算電路1318依據獲取的硬位元和預設的奇偶校檢矩陣計算校驗子，並且將校驗子傳送到變化節點計算電路1316。在這裡需要注意的是，校驗節點計算電路1318並不將硬位元傳送給變化節點計算電路1316。當校驗子為全”0”時，變化節點計算電路1316傳送解碼成功的訊息給有限狀態機1312，使得有限狀態機1312進入解碼成功狀態551。當校驗子不為全”0”時，變化節點計算電路1316將硬位元儲存至區域435，並且傳送解碼失敗的訊息給有限狀態機1312，使得有限狀態機1312進入第二階段狀態532。在這裡需要注意的是，由於硬位元一直需要被使用，因此區域431不能被釋放。In the first stage, the finite state machine 1312 drives the change node calculation circuit 1316 to perform the operation of the first stage. Referring to the data flow diagram of the first stage shown in Figure 14, the change node calculation circuit 1316 reads the hard bit (indicated by the symbol "sgn") through the mutex or calculator 1313, and transmits the hard bit to the check node Computing circuit 1318. The check node calculation circuit 1318 calculates the syndrome based on the obtained hard bits and the preset parity check matrix, and transmits the syndrome to the change node calculation circuit 1316. It should be noted here that the check node calculation circuit 1318 does not transmit the hard bits to the change node calculation circuit 1316. When the syndrome is all "0", the change node calculation circuit 1316 sends a decoding success message to the finite state machine 1312, so that the finite state machine 1312 enters the decoding success state 551. When the syndrome is not all "0", the change node calculation circuit 1316 stores the hard bits in the area 435 and sends a decoding failure message to the finite state machine 1312, so that the finite state machine 1312 enters the second stage state 532. It should be noted here that area 431 cannot be released because the hard bits always need to be used.

參考圖15所示的第二階段的資料流示意圖，在第二階段中，有限狀態機1312發出控制訊號給多工器1314以將區域433連接上變化節點計算電路1316，接著，驅動變化節點計算電路1316執行第二階段的操作。參考圖13所示的第二階段的資料流示意圖，變化節點計算電路1316通過多工器1314從區域433讀取軟位元（以符號“mag”表示），依據第一階段計算出來的校驗子、預設硬位元（預設為全”0”，以符號“sgn*”表示，也就是以預設值暫代區域431中儲存的實際硬位元）和軟位元mag，執行習知的位元翻轉演算法，用於更新硬位元sgn成為變化節點sgn’（此時的變化節點包含了錯誤模式，Error Pattern），計算硬位元sgn和變化節點sgn’之間的差異以產生翻轉狀態（以符號“flp’”表示），並且依據更新後的變化節點sgn’使用習知的公式來計算相應的軟位元mag’。接著，變化節點計算電路1316傳送變化節點sgn’和相應的軟位元mag’到校驗節點計算電路1318。校驗節點計算電路1318依據獲取的變化節點sgn’和預設的奇偶校檢矩陣計算校驗子，並且將變化節點sgn’、相應的軟位元mag’和校驗子傳送到變化節點計算電路1316。由於變化節點sgn’是錯誤模式，因此，變化節點計算電路1316獲取校驗子不為全”0”的結果，將翻轉狀態flp’儲存至區域1335，將相應軟位元mag’儲存至區域437，並且傳送解碼失敗的訊息給有限狀態機1312，使得有限狀態機1312進入第三階段狀態533。由於初始的軟位元已經更新並且成功地儲存到區域437，區域433已經不需要給目前正處理中的碼字使用，因此，區域433可被釋放以讓閃存介面139儲存相應於下一個碼字的軟位元。Referring to the data flow diagram of the second stage shown in Figure 15, in the second stage, the finite state machine 1312 sends a control signal to the multiplexer 1314 to connect the area 433 to the change node calculation circuit 1316, and then drives the change node calculation Circuit 1316 performs the second phase of operation. Referring to the data flow diagram of the second stage shown in Figure 13, the change node calculation circuit 1316 reads the soft bits (represented by the symbol "mag") from the area 433 through the multiplexer 1314, and based on the checksum calculated in the first stage sub, default hard bits (the default is all "0", represented by the symbol "sgn*", that is, the actual hard bits stored in area 431 are temporarily replaced by the default value) and soft bit mag, execute the exercise The well-known bit flip algorithm is used to update the hard bit sgn to become the change node sgn' (the change node at this time contains the error pattern, Error Pattern), calculate the difference between the hard bit sgn and the change node sgn' to A flip state (represented by the symbol "flp'") is generated, and the corresponding soft bit mag' is calculated using the well-known formula based on the updated change node sgn'. Next, the change node calculation circuit 1316 transmits the change node sgn' and the corresponding soft bit mag' to the check node calculation circuit 1318. The check node calculation circuit 1318 calculates the syndrome based on the obtained change node sgn' and the preset parity check matrix, and transmits the change node sgn', the corresponding soft bit mag' and the syndrome to the change node calculation circuit 1316. Since the change node sgn' is an error mode, the change node calculation circuit 1316 obtains the result that the syndrome is not all "0", stores the flip state flp' in the area 1335, and stores the corresponding soft bit mag' in the area 437 , and sends a decoding failure message to the finite state machine 1312, so that the finite state machine 1312 enters the third stage state 533. Since the initial soft bits have been updated and successfully stored in area 437, area 433 is no longer needed for the codeword currently being processed. Therefore, area 433 can be released to allow the flash memory interface 139 to store the corresponding codeword. of soft bits.

第三階段可包含第二次或者以後次數的解碼迭代。此階段會反覆執行，直到解碼成功，或者超過預設次數的迭代還不能解碼成功為止。進入第三階段的一開始，有限狀態機1312發出控制訊號給多工器1314以將區域437連接上變化節點計算電路1316，接著，驅動變化節點計算電路1316執行第三階段的操作。參考圖16所示的第三階段的資料流示意圖，變化節點計算電路1316從互斥或計算器1313獲取變化節點（以符號“sgn’”表示），通過多工器1314從區域437讀取相應的軟位元（以符號“mag’”表示），依據前一個解碼迭代（可存在第二階段或者第三階段之中）計算出來的校驗子、變化節點sgn’和軟位元mag’，執行習知的位元翻轉演算法，用於更新變化節點sgn’成為變化節點sgn” ，計算硬位元sgn和變化節點sgn”之間的差異以產生新的翻轉狀態（以符號“flp’’”表示），並且依據更新後的變化節點sgn”使用習知的公式來計算相應的軟位元mag”。接著，變化節點計算電路1316傳送變化節點sgn”和相應的軟位元mag”到校驗節點計算電路1318。校驗節點計算電路1318依據獲取的變化節點sgn”和預設的奇偶校檢矩陣計算校驗子，並且將變化節點sgn”、相應的軟位元mag”和校驗子傳送到變化節點計算電路1316。當校驗子為全”0”時，變化節點計算電路1316傳送解碼成功的訊息給有限狀態機1312，使得有限狀態機1312進入解碼成功狀態551。當校驗子不為全”0”時，變化節點計算電路1316將翻轉狀態flp”儲存至區域1335，將相應軟位元mag”儲存至區域437，並且傳送解碼失敗的訊息給有限狀態機1312，使得有限狀態機1312維持在第三階段狀態533，或者進入到解碼錯誤狀態553。The third stage may include the second or subsequent decoding iterations. This phase will be executed repeatedly until decoding is successful, or decoding fails after more than a preset number of iterations. At the beginning of the third stage, the finite state machine 1312 sends a control signal to the multiplexer 1314 to connect the area 437 to the change node calculation circuit 1316, and then drives the change node calculation circuit 1316 to perform the operation of the third stage. Referring to the data flow schematic diagram of the third stage shown in Figure 16, the change node calculation circuit 1316 obtains the change node (represented by the symbol "sgn'") from the mutual exclusive OR calculator 1313, and reads the corresponding data from the area 437 through the multiplexer 1314. The soft bits (represented by the symbol "mag'") are based on the syndrome, change node sgn' and soft bit mag' calculated in the previous decoding iteration (which can exist in the second or third stage), Execute the well-known bit flip algorithm for updating the change node sgn' to become the change node sgn", and calculate the difference between the hard bit sgn and the change node sgn" to generate a new flip state (with the symbol "flp'' ” represents), and uses the commonly known formula to calculate the corresponding soft bit mag “based on the updated change node sgn”. Next, the change node calculation circuit 1316 transmits the change node sgn″ and the corresponding soft bit mag″ to the check node calculation circuit 1318. The check node calculation circuit 1318 calculates the syndrome based on the obtained change node sgn" and the preset parity check matrix, and transmits the change node sgn", the corresponding soft bit mag" and the syndrome to the change node calculation circuit 1316. When the syndrome is all "0", the change node calculation circuit 1316 sends a decoding success message to the finite state machine 1312, causing the finite state machine 1312 to enter the decoding success state 551. When the syndrome is not all "0" When Stage state 533, or entering decoding error state 553.

雖然圖1、圖2、圖4、圖9、圖13中包含了以上描述的元件，但不排除在不違反發明的精神下，使用更多其他的附加元件，以達成更佳的技術效果。Although Figures 1, 2, 4, 9, and 13 include the above-described elements, it does not rule out the use of more other additional elements to achieve better technical effects without violating the spirit of the invention.

雖然本發明使用以上實施例進行說明，但需要注意的是，這些描述並非用以限縮本發明。相反地，此發明涵蓋了熟習此技藝人士顯而易見的修改與相似設置。所以，申請權利要求範圍須以最寬廣的方式解釋來包含所有顯而易見的修改與相似設置。Although the present invention is described using the above embodiments, it should be noted that these descriptions are not intended to limit the present invention. On the contrary, this invention covers modifications and similar arrangements which will be obvious to one skilled in the art. Therefore, the scope of the claims of the application must be interpreted in the broadest manner to include all obvious modifications and similar arrangements.

10:電子裝置 110:主機端 130:閃存控制器 131:主機介面 134:處理單元 136:隨機存取記憶體 137:NAND閃存控制器 138:LDPC解碼器 139:閃存介面 140:靜態隨機存取記憶體 150:閃存模組 151:介面 153#0~153#15:NAND閃存單元 CH#0~CH#3:通道 CE#0~CE#3:致能訊號 31#0~31#2:校驗節點 33#0~33#5:變化節點 410:LDPC編碼器 412:有限狀態機 413,414:多工器 416:變化節點計算電路 418:校驗節點計算電路 430:靜態隨機存取記憶體 431,433,435,437:靜態隨機存取記憶體中的區域 510,531~533,551~553:狀態 910:LDPC編碼器 912:有限狀態機 916:變化節點計算電路 930:靜態隨機存取記憶體 1310:LDPC編碼器 1312:有限狀態機 1313:互斥或計算器 1314:多工器 1316:變化節點計算電路 1318:校驗節點計算電路 1330:靜態隨機存取記憶體 1335:靜態隨機存取記憶體中的區域 10: Electronic devices 110: Host side 130:Flash controller 131:Host interface 134: Processing unit 136: Random access memory 137:NAND flash memory controller 138:LDPC decoder 139:Flash memory interface 140: Static random access memory 150:Flash memory module 151:Interface 153#0~153#15: NAND flash memory unit CH#0~CH#3: Channel CE#0~CE#3: enable signal 31#0~31#2: Verification node 33#0~33#5: Change nodes 410:LDPC encoder 412:Finite state machine 413,414:Mux 416: Change node calculation circuit 418: Check node calculation circuit 430: Static random access memory 431,433,435,437: Areas in static random access memory 510,531~533,551~553: Status 910:LDPC encoder 912:Finite state machine 916: Change node calculation circuit 930: Static random access memory 1310:LDPC encoder 1312:Finite state machine 1313:mutex or calculator 1314:Multiplexer 1316: Change node calculation circuit 1318: Check node calculation circuit 1330: Static random access memory 1335: Area in static random access memory

圖1為依據本發明實施例的電子裝置的系統架構圖。FIG. 1 is a system architecture diagram of an electronic device according to an embodiment of the present invention.

圖2為依據本發明實施例的閃存模組的示意圖。FIG. 2 is a schematic diagram of a flash memory module according to an embodiment of the present invention.

圖3為依據本發明實施例的範例LDPC碼的示意圖。FIG. 3 is a schematic diagram of an example LDPC code according to an embodiment of the present invention.

圖4為依據本發明實施例的NAND閃存控制器的方塊圖。FIG. 4 is a block diagram of a NAND flash memory controller according to an embodiment of the present invention.

圖5為依據本發明實施例的有限狀態機的狀態轉換的示意圖。FIG. 5 is a schematic diagram of state transition of a finite state machine according to an embodiment of the present invention.

圖6為依據本發明實施例的相應於圖4的硬體架構的第一階段的資料流示意圖。FIG. 6 is a schematic diagram of the data flow in the first stage corresponding to the hardware architecture of FIG. 4 according to an embodiment of the present invention.

圖7為依據本發明實施例的相應於圖4的硬體架構的第二階段的資料流示意圖。FIG. 7 is a schematic diagram of the data flow in the second stage corresponding to the hardware architecture of FIG. 4 according to an embodiment of the present invention.

圖8為依據本發明實施例的相應於圖4的硬體架構的第三階段的資料流示意圖。FIG. 8 is a schematic diagram of the data flow in the third stage corresponding to the hardware architecture of FIG. 4 according to an embodiment of the present invention.

圖9為依據本發明實施例的NAND閃存控制器的方塊圖。FIG. 9 is a block diagram of a NAND flash memory controller according to an embodiment of the present invention.

圖10為依據本發明實施例的相應於圖9的硬體架構的第一階段的資料流示意圖。FIG. 10 is a schematic diagram of the data flow corresponding to the first stage of the hardware architecture of FIG. 9 according to an embodiment of the present invention.

圖11為依據本發明實施例的相應於圖9的硬體架構的第二階段的資料流示意圖。FIG. 11 is a schematic diagram of the data flow corresponding to the second stage of the hardware architecture of FIG. 9 according to an embodiment of the present invention.

圖12為依據本發明實施例的相應於圖9的硬體架構的第三階段的資料流示意圖。FIG. 12 is a schematic diagram of the data flow corresponding to the third stage of the hardware architecture of FIG. 9 according to an embodiment of the present invention.

圖13為依據本發明實施例的NAND閃存控制器的方塊圖。FIG. 13 is a block diagram of a NAND flash memory controller according to an embodiment of the present invention.

圖14為依據本發明實施例的相應於圖13的硬體架構的第一階段的資料流示意圖。FIG. 14 is a schematic diagram of the data flow corresponding to the first stage of the hardware architecture of FIG. 13 according to an embodiment of the present invention.

圖15為依據本發明實施例的相應於圖13的硬體架構的第二階段的資料流示意圖。FIG. 15 is a data flow diagram corresponding to the second stage of the hardware architecture of FIG. 13 according to an embodiment of the present invention.

圖16為依據本發明實施例的相應於圖13的硬體架構的第三階段的資料流示意圖。FIG. 16 is a data flow diagram corresponding to the third stage of the hardware architecture of FIG. 13 according to an embodiment of the present invention.

510,531~533,551~553:狀態 510,531~533,551~553: status

Claims (14)

一種低密度奇偶校檢碼的解碼方法，由低密度奇偶校檢解碼器執行，其中，所述低密度奇偶校檢解碼器包含變化節點計算電路和校驗節點計算電路，所述方法包含： 當偵測到碼字儲存到靜態隨機存取記憶體時，所述低密度奇偶校檢解碼器進入第一階段狀態，在所述第一階段狀態中，所述校驗節點計算電路對所述碼字和奇偶校檢矩陣執行模二乘法以計算出第一校驗子，其中，所述碼字包含使用者資料和低密度奇偶校檢碼； 當所述第一校驗子指出在所述第一階段狀態中所獲取的所述碼字不正確時，所述低密度奇偶校檢解碼器進入第二階段狀態，在所述第二階段狀態中，所述變化節點計算電路依據所述碼字、相應於所述碼字的多個第一軟位元和所述第一校驗子執行位元翻轉演算法以產生多個變化節點，並且計算所述變化節點的多個第二軟位元；所述校驗節點計算電路對所述變化節點和所述奇偶校檢矩陣執行模二乘法以計算出第二校驗子，其中，所述碼字中的每個硬位元對應至少一個所述第一軟位元，用於指出此硬位元的信心程度，每個所述變化節點對應至少一個所述第二軟位元，用於指出此變化節點的信心程度；以及 當所述第二校驗子指出在所述第二階段狀態中產生的所述變化節點不正確時，所述低密度奇偶校檢解碼器反覆進入第三階段狀態，直到解碼成功或者所述第三階段狀態的迭代次數超過閾值為止，在所述第三階段狀態的每次迭代中，所述變化節點計算電路依據所述變化節點、相應於所述變化節點的所述第二軟位元和所述第二校驗子執行位元翻轉演算法以產生多個新的變化節點，並且計算所述新的變化節點的多個新的第二軟位元；所述校驗節點計算電路對所述新的變化節點和所述奇偶校檢矩陣執行模二乘法以計算出新的第二校驗子。 A decoding method of low-density parity check codes, executed by a low-density parity check decoder, wherein the low-density parity check decoder includes a change node calculation circuit and a check node calculation circuit, and the method includes: When it is detected that the codeword is stored in the static random access memory, the low-density parity check decoder enters the first stage state. In the first stage state, the check node calculation circuit calculates the The codeword and the parity check matrix perform modular square multiplication to calculate the first syndrome, wherein the codeword includes user information and a low-density parity check code; When the first syndrome indicates that the codeword obtained in the first stage state is incorrect, the low density parity check decoder enters the second stage state. In the second stage state , the change node calculation circuit performs a bit flipping algorithm according to the codeword, a plurality of first soft bits corresponding to the codeword, and the first syndrome to generate a plurality of change nodes, and Calculate a plurality of second soft bits of the change node; the check node calculation circuit performs a modular square multiplication method on the change node and the parity check matrix to calculate a second syndrome, wherein, Each hard bit in the codeword corresponds to at least one first soft bit, used to indicate the degree of confidence of this hard bit, and each change node corresponds to at least one said second soft bit, used to indicate Indicate the degree of confidence in this change node; and When the second syndrome indicates that the changed node generated in the second stage state is incorrect, the low-density parity check decoder repeatedly enters the third stage state until decoding is successful or the third stage state is reached. Until the number of iterations of the three-stage state exceeds the threshold, in each iteration of the third-stage state, the change node calculation circuit calculates the change node according to the change node, the second soft bit corresponding to the change node and The second syndrome executes a bit flipping algorithm to generate a plurality of new change nodes, and calculates a plurality of new second soft bits of the new change nodes; the check node calculation circuit calculates the The new change node and the parity check matrix perform modular square multiplication to calculate a new second syndrome. 如請求項1所述的低密度奇偶校檢碼的解碼方法，其中，所述低密度奇偶校檢解碼器包含有限狀態機，所述低密度奇偶校檢碼的解碼方法包含： 所述有限狀態機因應所述碼字儲存到所述靜態隨機存取記憶體的情況時，讓所述低密度奇偶校檢解碼器處於所述第一階段狀態； 所述有限狀態機因應所述第一校驗子指出在所述第一階段狀態中所獲取的所述碼字不正確的情況時，讓所述低密度奇偶校檢解碼器處於所述第二階段狀態； 所述有限狀態機因應所述第二校驗子指出在所述第二階段狀態或前一個所述第三階段狀態中所產生的所述變化節點不正確的情況時，讓所述低密度奇偶校檢解碼器處於所述第三階段狀態；以及 所述有限狀態機控制進入所述第三階段狀態的所述迭代次數不超過所述閾值。 The decoding method of low-density parity check code as described in request item 1, wherein the low-density parity check decoder includes a finite state machine, and the decoding method of low-density parity check code includes: The finite state machine causes the low-density parity check decoder to be in the first stage state in response to the situation where the codeword is stored in the static random access memory; The finite state machine causes the low-density parity check decoder to be in the second state in response to the first syndrome indicating that the codeword obtained in the first stage state is incorrect. stage status; When the finite state machine indicates that the change node generated in the second stage state or the previous third stage state is incorrect in response to the second syndrome, the low-density parity The check decoder is in the third stage state; and The finite state machine controls the number of iterations to enter the third stage state not to exceed the threshold. 如請求項1所述的低密度奇偶校檢碼的解碼方法，其中，所述碼字經由閃存介面從閃存模組中被讀取並且被儲存到所述靜態隨機存取記憶體。The decoding method of low-density parity check code as claimed in claim 1, wherein the codeword is read from the flash memory module through a flash memory interface and stored in the static random access memory. 如請求項1所述的低密度奇偶校檢碼的解碼方法，其中，所述低密度奇偶校檢解碼器包含有限狀態機、第一多工器和第二多工器，所述第一多工器的輸出端耦接至所述變化節點計算電路，所述第一多工器的二個輸入端分別耦接至所述靜態隨機存取記憶體中的第一區域和第二區域，所述第二多工器的輸出端耦接至所述變化節點計算電路，所述第二多工器的二個輸入端分別耦接至所述靜態隨機存取記憶體中的第三區域和第四區域，所述碼字經由閃存介面從閃存模組被讀取並且被儲存到所述第一區域，所述閃存介面產生相應於所述碼字的所述第一軟位元，並且所述第一軟位元被儲存到所述第三區域，所述低密度奇偶校檢碼的解碼方法包含： 在所述第一階段狀態中，所述有限狀態機發出第一控制訊號給所述第一多工器以將所述第一區域耦接至所述變化節點計算電路，以及驅動所述變化節點計算電路執行第一階段的操作，所述變化節點計算電路通過所述第一多工器從所述第一區域讀取所述碼字，傳送所述碼字給所述校驗節點計算電路，從所述校驗節點計算電路獲取所述第一校驗子，依據所述第一校驗子傳送解碼成功或者解碼失敗的訊息給所述有限狀態機，以及儲存所述碼字至所述第二區域； 在所述第二階段狀態中，所述有限狀態機發出第二控制訊號給所述第二多工器以將所述第三區域耦接至所述變化節點計算電路，以及驅動所述變化節點計算電路執行第二階段的操作，所述變化節點計算電路通過所述第二多工器從所述第三區域讀取所述第一軟位元，傳送所述變化節點給所述校驗節點計算電路，從所述校驗節點計算電路獲取所述第二校驗子，依據所述第二校驗子傳送解碼成功或者解碼失敗的訊息給所述有限狀態機，儲存所述變化節點至所述第二區域，以及儲存所述第二軟位元至所述第四區域； 在所述第三階段狀態的每次迭代中，所述有限狀態機發出第三控制訊號給所述第一多工器以將所述第二區域耦接至所述變化節點計算電路，發出第四控制訊號給所述第二多工器以將所述第四區域耦接至所述變化節點計算電路，所述變化節點計算電路通過所述第一多工器從所述第二區域讀取所述變化節點，通過所述第二多工器從所述第四區域讀取相應於所述變化節點的所述第二軟位元，傳送所述新的變化節點給所述校驗節點計算電路，從所述校驗節點計算電路獲取所述新的第二校驗子，依據所述新的第二校驗子傳送解碼成功或者解碼失敗的訊息給所述有限狀態機，儲存所述新的變化節點至所述第二區域，以及儲存所述新的第二軟位元至所述第四區域。 The decoding method of low-density parity check code as described in request item 1, wherein the low-density parity check decoder includes a finite state machine, a first multiplexer and a second multiplexer, and the first multiplexer The output end of the multiplexer is coupled to the change node calculation circuit, and the two input ends of the first multiplexer are respectively coupled to the first area and the second area in the static random access memory, so The output terminal of the second multiplexer is coupled to the change node calculation circuit, and the two input terminals of the second multiplexer are respectively coupled to the third area and the third area in the static random access memory. four areas, the codeword is read from the flash memory module via a flash memory interface and stored in the first area, the flash memory interface generates the first soft bit corresponding to the codeword, and the The first soft bit is stored in the third area, and the decoding method of the low-density parity check code includes: In the first phase state, the finite state machine sends a first control signal to the first multiplexer to couple the first region to the change node calculation circuit and drive the change node The calculation circuit performs the operation of the first stage, the change node calculation circuit reads the codeword from the first area through the first multiplexer, and transmits the codeword to the check node calculation circuit, Obtain the first syndrome from the check node calculation circuit, transmit a decoding success or decoding failure message to the finite state machine according to the first syndrome, and store the codeword in the third Second area; In the second phase state, the finite state machine sends a second control signal to the second multiplexer to couple the third region to the change node calculation circuit and drive the change node The calculation circuit performs the second phase operation. The change node calculation circuit reads the first soft bits from the third area through the second multiplexer and transmits the change node to the check node. The calculation circuit obtains the second syndrome from the check node calculation circuit, sends a decoding success or decoding failure message to the finite state machine according to the second syndrome, and stores the changed node in the the second area, and storing the second soft bits in the fourth area; In each iteration of the third phase state, the finite state machine sends a third control signal to the first multiplexer to couple the second region to the change node calculation circuit, and sends a third control signal to the first multiplexer. Four control signals to the second multiplexer to couple the fourth region to the change node calculation circuit, the change node calculation circuit reads from the second area through the first multiplexer The change node reads the second soft bit corresponding to the change node from the fourth area through the second multiplexer, and transmits the new change node to the check node for calculation A circuit that obtains the new second syndrome from the check node calculation circuit, transmits a decoding success or decoding failure message to the finite state machine according to the new second syndrome, and stores the new change node to the second area, and store the new second soft bit to the fourth area. 如請求項4所述的低密度奇偶校檢碼的解碼方法，包含： 在所述碼字儲存至所述第二區域後，釋放所述第一區域；以及 在所述第二軟位元儲存至所述第四區域後，釋放所述第三區域。 The decoding method of low-density parity check code as described in request item 4 includes: After the codeword is stored in the second area, releasing the first area; and After the second soft bit is stored in the fourth area, the third area is released. 如請求項1所述的低密度奇偶校檢碼的解碼方法，其中，所述低密度奇偶校檢解碼器包含有限狀態機、多工器，所述多工器的輸出端耦接至所述變化節點計算電路，所述多工器的二個輸入端分別耦接至所述靜態隨機存取記憶體中的第一區域和第二區域，所述碼字經由閃存介面從閃存模組被讀取並且被儲存到所述第一區域，所述低密度奇偶校檢碼的解碼方法包含： 在所述第一階段狀態中，所述有限狀態機發出第一控制訊號給所述多工器以將所述第一區域耦接至所述變化節點計算電路，以及驅動所述變化節點計算電路執行第一階段的操作，所述變化節點計算電路通過所述多工器從所述第一區域讀取所述碼字，傳送所述碼字給所述校驗節點計算電路，從所述校驗節點計算電路獲取所述第一校驗子，依據所述第一校驗子傳送解碼成功或者解碼失敗的訊息給所述有限狀態機，以及儲存所述碼字至所述第二區域； 在所述第二階段狀態中，所述有限狀態機驅動所述變化節點計算電路執行第二階段的操作，所述變化節點計算電路以預設值當作所述第一軟位元，傳送所述變化節點給所述校驗節點計算電路，從所述校驗節點計算電路獲取所述第二校驗子，依據所述第二校驗子傳送解碼成功或者解碼失敗的訊息給所述有限狀態機，儲存所述變化節點至所述第二區域，以及儲存所述第二軟位元至第三區域；以及 在所述第三階段狀態的每次迭代中，所述有限狀態機發出第二控制訊號給所述多工器以將所述第二區域耦接至所述變化節點計算電路，所述變化節點計算電路通過所述多工器從所述第二區域讀取所述變化節點，從所述第三區域讀取相應於所述變化節點的所述第二軟位元，傳送所述新的變化節點給所述校驗節點計算電路，從所述校驗節點計算電路獲取所述新的第二校驗子，依據所述新的第二校驗子傳送解碼成功或者解碼失敗的訊息給所述有限狀態機，儲存所述新的變化節點至所述第二區域，以及儲存所述新的第二軟位元至所述第三區域。 The decoding method of low-density parity check code as described in claim 1, wherein the low-density parity check decoder includes a finite state machine and a multiplexer, and the output end of the multiplexer is coupled to the Change node calculation circuit, the two input terminals of the multiplexer are respectively coupled to the first area and the second area in the static random access memory, the codeword is read from the flash memory module through the flash memory interface is retrieved and stored in the first area. The decoding method of the low-density parity check code includes: In the first stage state, the finite state machine sends a first control signal to the multiplexer to couple the first region to the change node calculation circuit and drive the change node calculation circuit To perform the operation of the first stage, the change node calculation circuit reads the codeword from the first area through the multiplexer, transmits the codeword to the check node calculation circuit, and reads the codeword from the check node calculation circuit. The check node calculation circuit obtains the first syndrome, transmits a decoding success or decoding failure message to the finite state machine according to the first syndrome, and stores the codeword in the second area; In the second stage state, the finite state machine drives the change node calculation circuit to perform the second stage operation. The change node calculation circuit uses the preset value as the first soft bit to transmit all the The change node is given to the check node calculation circuit, the second syndrome is obtained from the check node calculation circuit, and a message of successful decoding or failure of decoding is sent to the finite state according to the second syndrome. a machine, storing the change node to the second area, and storing the second soft bit to a third area; and In each iteration of the third phase state, the finite state machine sends a second control signal to the multiplexer to couple the second region to the change node calculation circuit, and the change node The computing circuit reads the change node from the second area through the multiplexer, reads the second soft bit corresponding to the change node from the third area, and transmits the new change The node provides the check node calculation circuit, obtains the new second syndrome from the check node calculation circuit, and transmits a decoding success or decoding failure message to the check node based on the new second syndrome. A finite state machine stores the new changed node in the second area, and stores the new second soft bit in the third area. 如請求項6所述的低密度奇偶校檢碼的解碼方法，包含： 在所述碼字儲存至所述第二區域後，釋放所述第一區域。 The decoding method of low-density parity check code as described in request item 6 includes: After the codeword is stored in the second area, the first area is released. 如請求項1所述的低密度奇偶校檢碼的解碼方法，其中，所述低密度奇偶校檢解碼器包含有限狀態機、互斥或計算器、多工器，所述多工器的輸出端耦接至所述變化節點計算電路，所述多工器的二個輸入端分別耦接至所述靜態隨機存取記憶體中的第三區域和第四區域，所述碼字經由閃存介面從閃存模組被讀取並且被儲存到所述靜態隨機存取記憶體中的所述第一區域，所述靜態隨機存取記憶體中的所述第二區域儲存翻轉狀態，所述翻轉狀態初始為全”0”，所述閃存介面產生相應於所述碼字的所述第一軟位元，所述第一軟位元被儲存到所述第三區域，所述互斥或計算器對所述第一區域中的所述碼字和所述第二區域中的所述翻轉狀態進行互斥或計算並且輸出計算結果至所述變化節點計算電路，所述低密度奇偶校檢碼的解碼方法包含： 在所述第一階段狀態中，所述有限狀態機驅動所述變化節點計算電路執行第一階段的操作，所述變化節點計算電路從所述互斥或計算器獲取所述碼字，傳送所述碼字給所述校驗節點計算電路，從所述校驗節點計算電路獲取所述第一校驗子，以及依據所述第一校驗子傳送解碼成功或者解碼失敗的訊息給所述有限狀態機； 在所述第二階段狀態中，所述有限狀態機發出控制訊號給所述多工器以將所述第三區域耦接至所述變化節點計算電路，以及驅動所述變化節點計算電路執行第二階段的操作，所述變化節點計算電路將所述碼字當作全”0”，通過所述多工器從所述第三區域讀取所述第一軟位元，計算所述碼字和所述變化節點間的差異以產生所述翻轉狀態，傳送所述變化節點給所述校驗節點計算電路，從所述校驗節點計算電路獲取所述第二校驗子，依據所述第二校驗子傳送解碼成功或者解碼失敗的訊息給所述有限狀態機，儲存所述翻轉狀態至所述第二區域，以及儲存所述第二軟位元至所述第四區域； 在所述第三階段狀態的每次迭代中，所述有限狀態機發出第二控制訊號給所述多工器以將所述第四區域耦接至所述變化節點計算電路，所述變化節點計算電路從所述互斥或計算器獲取所述變化節點，通過所述多工器從所述第四區域讀取相應於所述變化節點的所述第二軟位元，計算所述碼字和所述新的變化節點間的差異以產生新的翻轉狀態，傳送所述新的變化節點給所述校驗節點計算電路，從所述校驗節點計算電路獲取所述新的第二校驗子，依據所述新的第二校驗子傳送解碼成功或者解碼失敗的訊息給所述有限狀態機，儲存所述新的翻轉狀態至所述第二區域，以及儲存所述新的第二軟位元至所述第四區域。 The decoding method of low-density parity check code as described in request item 1, wherein the low-density parity check decoder includes a finite state machine, a mutex or calculator, and a multiplexer, and the output of the multiplexer The terminal is coupled to the change node calculation circuit, the two input terminals of the multiplexer are respectively coupled to the third area and the fourth area in the static random access memory, and the codeword passes through the flash memory interface. is read from the flash memory module and stored into the first area in the static random access memory, the second area in the static random access memory stores a flip state, the flip state Initially all "0", the flash memory interface generates the first soft bit corresponding to the codeword, the first soft bit is stored in the third area, the mutex or calculator Perform mutual exclusion or calculation on the codeword in the first area and the flip state in the second area and output the calculation result to the change node calculation circuit. The low-density parity check code Decoding methods include: In the first stage state, the finite state machine drives the change node calculation circuit to perform the first stage operation. The change node calculation circuit obtains the codeword from the mutex or calculator and transmits the describe the codeword to the check node calculation circuit, obtain the first syndrome from the check node calculation circuit, and transmit a decoding success or decoding failure message to the finite element according to the first syndrome state machine; In the second stage state, the finite state machine sends a control signal to the multiplexer to couple the third region to the change node calculation circuit, and drive the change node calculation circuit to execute the first In the second-stage operation, the change node calculation circuit treats the codeword as all "0", reads the first soft bit from the third area through the multiplexer, and calculates the codeword and the difference between the change nodes to generate the flip state, transmit the change node to the check node calculation circuit, obtain the second syndrome from the check node calculation circuit, according to the first The second syndrome transmits a decoding success or decoding failure message to the finite state machine, stores the flip state in the second area, and stores the second soft bit in the fourth area; In each iteration of the third phase state, the finite state machine sends a second control signal to the multiplexer to couple the fourth region to the change node calculation circuit, the change node The calculation circuit obtains the change node from the mutex or calculator, reads the second soft bit corresponding to the change node from the fourth area through the multiplexer, and calculates the codeword and the difference between the new change node to generate a new flip state, transmit the new change node to the check node calculation circuit, and obtain the new second check from the check node calculation circuit Submit, transmit decoding success or decoding failure information to the finite state machine according to the new second syndrome, store the new flip state in the second area, and store the new second software bit to the fourth area. 如請求項8所述的低密度奇偶校檢碼的解碼方法，包含： 在所述第二軟位元儲存至所述第四區域後，釋放所述第三區域。 The decoding method of low-density parity check code as described in request item 8 includes: After the second soft bit is stored in the fourth area, the third area is released. 一種低密度奇偶校檢碼的解碼裝置，包含： 變化節點計算電路，耦接於靜態隨機存取記憶體；以及 校驗節點計算電路，耦接於所述變化節點計算電路， 其中，當偵測到碼字儲存到所述靜態隨機存取記憶體時，所述低密度奇偶校檢碼的解碼裝置進入第一階段狀態，在所述第一階段狀態中，所述校驗節點計算電路對所述碼字和奇偶校檢矩陣執行模二乘法以計算出第一校驗子，其中，所述碼字包含使用者資料和低密度奇偶校檢碼； 當所述第一校驗子指出在所述第一階段狀態中所獲取的所述碼字不正確時，所述低密度奇偶校檢碼的解碼裝置進入第二階段狀態，在所述第二階段狀態中，所述變化節點計算電路依據所述碼字、相應於所述碼字的多個第一軟位元和所述第一校驗子執行位元翻轉演算法以產生多個變化節點，並且計算所述變化節點的多個第二軟位元；所述校驗節點計算電路對所述變化節點和所述奇偶校檢矩陣執行模二乘法以計算出第二校驗子，其中，所述碼字中的每個硬位元對應至少一個所述第一軟位元，用於指出此硬位元的信心程度，每個所述變化節點對應至少一個所述第二軟位元，用於指出此變化節點的信心程度；以及 當所述第二校驗子指出在所述第二階段狀態中產生的所述變化節點不正確時，所述低密度奇偶校檢碼的解碼裝置反覆進入第三階段狀態，直到解碼成功或者所述第三階段狀態的迭代次數超過閾值為止，在所述第三階段狀態的每次迭代中，所述變化節點計算電路依據所述變化節點、相應於所述變化節點的所述第二軟位元和所述第二校驗子執行位元翻轉演算法以產生多個新的變化節點，並且計算所述新的變化節點的多個新的第二軟位元；所述校驗節點計算電路對所述新的變化節點和所述奇偶校檢矩陣執行模二乘法以計算出新的第二校驗子。 A decoding device for low-density parity check codes, including: a change node calculation circuit coupled to the static random access memory; and a check node calculation circuit coupled to the change node calculation circuit, Wherein, when it is detected that the codeword is stored in the static random access memory, the decoding device of the low-density parity check code enters the first stage state. In the first stage state, the check The node calculation circuit performs modular square multiplication on the codeword and the parity check matrix to calculate the first syndrome, wherein the codeword includes user information and a low-density parity check code; When the first syndrome indicates that the codeword obtained in the first stage state is incorrect, the decoding device of the low-density parity check code enters the second stage state. In the stage state, the change node calculation circuit performs a bit flipping algorithm based on the codeword, a plurality of first soft bits corresponding to the codeword, and the first syndrome to generate a plurality of change nodes. , and calculate a plurality of second soft bits of the change node; the check node calculation circuit performs a modular square multiplication on the change node and the parity check matrix to calculate a second syndrome, where, Each hard bit in the codeword corresponds to at least one first soft bit, which is used to indicate the degree of confidence of this hard bit, and each change node corresponds to at least one second soft bit, The degree of confidence used to indicate this change node; and When the second checksum indicates that the changed node generated in the second stage state is incorrect, the decoding device of the low-density parity check code repeatedly enters the third stage state until the decoding is successful or the Until the number of iterations of the third stage state exceeds the threshold, in each iteration of the third stage state, the change node calculation circuit is based on the change node and the second soft bit corresponding to the change node. The check node calculation circuit performs a bit flipping algorithm on the element and the second syndrome to generate a plurality of new change nodes, and calculates a plurality of new second soft bits of the new change node; the check node calculation circuit A modular square method is performed on the new changed node and the parity check matrix to calculate a new second syndrome. 如請求項10所述的低密度奇偶校檢碼的解碼裝置，包含： 有限狀態機，用於因應所述碼字儲存到所述靜態隨機存取記憶體的情況時，讓所述低密度奇偶校檢碼的解碼裝置處於所述第一階段狀態；因應所述第一校驗子指出在所述第一階段狀態中所獲取的所述碼字不正確的情況時，讓所述低密度奇偶校檢的解碼裝置處於所述第二階段狀態；因應所述第二校驗子指出在所述第二階段狀態或前一個所述第三階段狀態中所產生的所述變化節點不正確的情況時，讓所述低密度奇偶校檢的解碼裝置處於所述第三階段狀態；以及控制進入所述第三階段狀態的所述迭代次數不超過所述閾值。 The decoding device for low-density parity check codes as described in claim 10 includes: A finite state machine is used to put the decoding device of the low-density parity check code in the first stage state in response to the situation where the codeword is stored in the static random access memory; in response to the first When the syndrome indicates that the codeword obtained in the first stage state is incorrect, the low-density parity check decoding device is placed in the second stage state; in response to the second stage check, When the syndrome indicates that the change node generated in the second stage state or the previous third stage state is incorrect, the low-density parity check decoding device is placed in the third stage. state; and controlling the number of iterations to enter the third stage state not to exceed the threshold. 如請求項10所述的低密度奇偶校檢碼的解碼裝置，包含： 有限狀態機； 第一多工器，包含第一輸出端耦接至所述變化節點計算電路，以及二個第一輸入端分別耦接至所述靜態隨機存取記憶體中的第一區域和第二區域；以及 第二多工器，包含第二輸出端耦接至所述變化節點計算電路，以及二個第二輸入端分別耦接至所述靜態隨機存取記憶體中的第三區域和第四區域， 其中，所述碼字經由閃存介面從閃存模組被讀取並且被儲存到所述第一區域， 其中，所述閃存介面產生相應於所述碼字的所述第一軟位元，並且所述第一軟位元被儲存到所述第三區域， 其中，在所述第一階段狀態中，所述有限狀態機發出第一控制訊號給所述第一多工器以將所述第一區域耦接至所述變化節點計算電路，以及驅動所述變化節點計算電路執行第一階段的操作，所述變化節點計算電路通過所述第一多工器從所述第一區域讀取所述碼字，傳送所述碼字給所述校驗節點計算電路，從所述校驗節點計算電路獲取所述第一校驗子，依據所述第一校驗子傳送解碼成功或者解碼失敗的訊息給所述有限狀態機，以及儲存所述碼字至所述第二區域，使得所述第一區域能夠被釋放； 其中，在所述第二階段狀態中，所述有限狀態機發出第二控制訊號給所述第二多工器以將所述第三區域耦接至所述變化節點計算電路，以及驅動所述變化節點計算電路執行第二階段的操作，所述變化節點計算電路通過所述第二多工器從所述第三區域讀取所述第一軟位元，傳送所述變化節點給所述校驗節點計算電路，從所述校驗節點計算電路獲取所述第二校驗子，依據所述第二校驗子傳送解碼成功或者解碼失敗的訊息給所述有限狀態機，儲存所述變化節點至所述第二區域，以及儲存所述第二軟位元至所述第四區域，使得所述第三區域能夠被釋放， 其中，在所述第三階段狀態的每次迭代中，所述有限狀態機發出第三控制訊號給所述第一多工器以將所述第二區域耦接至所述變化節點計算電路，發出第四控制訊號給所述第二多工器以將所述第四區域耦接至所述變化節點計算電路，所述變化節點計算電路通過所述第一多工器從所述第二區域讀取所述變化節點，通過所述第二多工器從所述第四區域讀取相應於所述變化節點的所述第二軟位元，傳送所述新的變化節點給所述校驗節點計算電路，從所述校驗節點計算電路獲取所述新的第二校驗子，依據所述新的第二校驗子傳送解碼成功或者解碼失敗的訊息給所述有限狀態機，儲存所述新的變化節點至所述第二區域，以及儲存所述新的第二軟位元至所述第四區域。 The decoding device for low-density parity check codes as described in claim 10 includes: finite state machine; A first multiplexer, including a first output terminal coupled to the change node calculation circuit, and two first input terminals respectively coupled to the first area and the second area in the static random access memory; as well as A second multiplexer includes a second output terminal coupled to the change node calculation circuit, and two second input terminals coupled to the third area and the fourth area in the static random access memory, wherein the codeword is read from the flash memory module via a flash memory interface and stored in the first area, wherein the flash memory interface generates the first soft bit corresponding to the codeword, and the first soft bit is stored in the third area, Wherein, in the first stage state, the finite state machine sends a first control signal to the first multiplexer to couple the first region to the change node calculation circuit, and drive the The change node calculation circuit performs the first stage of operation. The change node calculation circuit reads the codeword from the first area through the first multiplexer and transmits the codeword to the check node for calculation. A circuit that obtains the first syndrome from the check node calculation circuit, transmits a decoding success or decoding failure message to the finite state machine according to the first syndrome, and stores the codeword in the The second area enables the first area to be released; Wherein, in the second stage state, the finite state machine sends a second control signal to the second multiplexer to couple the third region to the change node calculation circuit, and drive the The change node calculation circuit performs the second stage of operation. The change node calculation circuit reads the first soft bits from the third area through the second multiplexer and transmits the change node to the calibration A check node calculation circuit obtains the second syndrome from the check node calculation circuit, transmits a decoding success or decoding failure message to the finite state machine according to the second syndrome, and stores the changed node to the second area, and storing the second soft bits to the fourth area so that the third area can be released, Wherein, in each iteration of the third stage state, the finite state machine sends a third control signal to the first multiplexer to couple the second region to the change node calculation circuit, Sending a fourth control signal to the second multiplexer to couple the fourth region to the change node calculation circuit, the change node calculation circuit transmits data from the second region to the first multiplexer through the first multiplexer. Read the change node, read the second soft bit corresponding to the change node from the fourth area through the second multiplexer, and transmit the new change node to the verification The node calculation circuit obtains the new second syndrome from the check node calculation circuit, sends a decoding success or decoding failure message to the finite state machine according to the new second syndrome, and stores all the decoding information. The new change node is added to the second area, and the new second soft bit is stored in the fourth area. 如請求項10所述的低密度奇偶校檢碼的解碼裝置，包含： 有限狀態機；以及 多工器，包含輸出端耦接至所述變化節點計算電路，以及二個輸入端分別耦接至所述靜態隨機存取記憶體中的第一區域和第二區域， 其中，碼字經由閃存介面從閃存模組被讀取並且被儲存到所述第一區域， 其中，在所述第一階段狀態中，所述有限狀態機發出第一控制訊號給所述多工器以將所述第一區域耦接至所述變化節點計算電路，以及驅動所述變化節點計算電路執行第一階段的操作，所述變化節點計算電路通過所述多工器從所述第一區域讀取所述碼字，傳送所述碼字給所述校驗節點計算電路，從所述校驗節點計算電路獲取所述第一校驗子，依據所述第一校驗子傳送解碼成功或者解碼失敗的訊息給所述有限狀態機，儲存所述碼字至所述第二區域，使得所述第一區域能夠被釋放， 其中，在所述第二階段狀態中，所述有限狀態機驅動所述變化節點計算電路執行第二階段的操作，所述變化節點計算電路以預設值當作所述第一軟位元，傳送所述變化節點給所述校驗節點計算電路，從所述校驗節點計算電路獲取所述第二校驗子，依據所述第二校驗子傳送解碼成功或者解碼失敗的訊息給所述有限狀態機，儲存所述變化節點至所述第二區域，以及儲存所述第二軟位元至第三區域， 其中，在所述第三階段狀態的每次迭代中，所述有限狀態機發出第二控制訊號給所述多工器以將所述第二區域耦接至所述變化節點計算電路，所述變化節點計算電路通過所述多工器從所述第二區域讀取所述變化節點，從所述第三區域讀取相應於所述變化節點的所述第二軟位元，傳送所述新的變化節點給所述校驗節點計算電路，從所述校驗節點計算電路獲取所述新的第二校驗子，依據所述新的第二校驗子傳送解碼成功或者解碼失敗的訊息給所述有限狀態機，儲存所述新的變化節點至所述第二區域，以及儲存所述新的第二軟位元至所述第三區域。 The decoding device for low-density parity check codes as described in claim 10 includes: Finite state machines; and A multiplexer, including an output terminal coupled to the change node calculation circuit, and two input terminals respectively coupled to the first area and the second area in the static random access memory, wherein the codeword is read from the flash memory module via the flash memory interface and stored in the first area, Wherein, in the first stage state, the finite state machine sends a first control signal to the multiplexer to couple the first region to the change node calculation circuit and drive the change node The calculation circuit performs the operation of the first stage. The change node calculation circuit reads the codeword from the first area through the multiplexer, transmits the codeword to the check node calculation circuit, and obtains the codeword from the check node calculation circuit. The check node calculation circuit obtains the first syndrome, transmits a decoding success or decoding failure message to the finite state machine according to the first syndrome, and stores the codeword in the second area, enabling said first area to be released, Wherein, in the second stage state, the finite state machine drives the change node calculation circuit to perform the second stage operation, and the change node calculation circuit uses a preset value as the first soft bit, Send the changed node to the check node calculation circuit, obtain the second syndrome from the check node calculation circuit, and send a decoding success or decoding failure message to the second syndrome according to the second syndrome a finite state machine, storing the change node in the second area, and storing the second soft bit in a third area, Wherein, in each iteration of the third stage state, the finite state machine sends a second control signal to the multiplexer to couple the second region to the change node calculation circuit, and the The change node calculation circuit reads the change node from the second area through the multiplexer, reads the second soft bit corresponding to the change node from the third area, and transmits the new The changed node is given to the check node calculation circuit, the new second syndrome is obtained from the check node calculation circuit, and a message of decoding success or decoding failure is sent to the check node calculation circuit according to the new second syndrome. The finite state machine stores the new changed node in the second area, and stores the new second soft bit in the third area. 如請求項10所述的低密度奇偶校檢碼的解碼裝置，包含： 有限狀態機； 互斥或計算器；以及 多工器，包含輸出端耦接至所述變化節點計算電路，以及二個輸入端分別耦接至所述靜態隨機存取記憶體中的第三區域和第四區域， 其中，所述碼字經由閃存介面從閃存模組被讀取並且被儲存到所述靜態隨機存取記憶體中的所述第一區域， 其中，所述靜態隨機存取記憶體中的所述第二區域儲存翻轉狀態，所述翻轉狀態初始為全”0”， 其中，所述閃存介面產生相應於所述碼字的所述第一軟位元，所述第一軟位元被儲存到所述第三區域， 其中，所述互斥或計算器對所述第一區域中的所述碼字和所述第二區域中的所述翻轉狀態進行互斥或計算並且輸出計算結果至所述變化節點計算電路， 其中，在所述第一階段狀態中，所述有限狀態機驅動所述變化節點計算電路執行第一階段的操作，所述變化節點計算電路從所述互斥或計算器獲取所述碼字，傳送所述碼字給所述校驗節點計算電路，從所述校驗節點計算電路獲取所述第一校驗子，以及依據所述第一校驗子傳送解碼成功或者解碼失敗的訊息給所述有限狀態機， 其中，在所述第二階段狀態中，所述有限狀態機發出控制訊號給所述多工器以將所述第三區域耦接至所述變化節點計算電路，以及驅動所述變化節點計算電路執行第二階段的操作，所述變化節點計算電路將所述碼字當作全”0”，通過所述多工器從所述第三區域讀取所述第一軟位元，計算所述碼字和所述變化節點間的差異以產生所述翻轉狀態，傳送所述變化節點給所述校驗節點計算電路，從所述校驗節點計算電路獲取所述第二校驗子，依據所述第二校驗子傳送解碼成功或者解碼失敗的訊息給所述有限狀態機，儲存所述翻轉狀態至所述第二區域，以及儲存所述第二軟位元至所述第四區域， 其中，在所述第三階段狀態的每次迭代中，所述有限狀態機發出第二控制訊號給所述多工器以將所述第四區域耦接至所述變化節點計算電路，所述變化節點計算電路從所述互斥或計算器獲取所述變化節點，通過所述多工器從所述第四區域讀取相應於所述變化節點的所述第二軟位元，計算所述碼字和所述新的變化節點間的差異以產生新的翻轉狀態，傳送所述新的變化節點給所述校驗節點計算電路，從所述校驗節點計算電路獲取所述新的第二校驗子，依據所述新的第二校驗子傳送解碼成功或者解碼失敗的訊息給所述有限狀態機，儲存所述新的翻轉狀態至所述第二區域，以及儲存所述新的第二軟位元至所述第四區域。 The decoding device for low-density parity check codes as described in claim 10 includes: finite state machine; mutex or calculator; and A multiplexer, including an output terminal coupled to the change node calculation circuit, and two input terminals respectively coupled to the third area and the fourth area in the static random access memory, wherein the codeword is read from the flash memory module via a flash memory interface and stored in the first area in the static random access memory, Wherein, the second area in the static random access memory stores a flip state, and the flip state is initially all "0", wherein the flash memory interface generates the first soft bit corresponding to the codeword, and the first soft bit is stored in the third area, wherein the mutual exclusion OR calculator performs mutual exclusion OR calculation on the codeword in the first area and the flip state in the second area and outputs the calculation result to the change node calculation circuit, Wherein, in the first stage state, the finite state machine drives the change node calculation circuit to perform the first stage operation, and the change node calculation circuit obtains the codeword from the mutex or calculator, Send the codeword to the check node calculation circuit, obtain the first syndrome from the check node calculation circuit, and send a decoding success or decoding failure message to the check node according to the first syndrome. Describe the finite state machine, Wherein, in the second stage state, the finite state machine sends a control signal to the multiplexer to couple the third region to the change node calculation circuit, and drive the change node calculation circuit To perform the second phase operation, the change node calculation circuit treats the codeword as all "0", reads the first soft bit from the third area through the multiplexer, and calculates the The difference between the codeword and the change node is used to generate the flip state, the change node is transmitted to the check node calculation circuit, and the second syndrome is obtained from the check node calculation circuit, according to the The second syndrome transmits a decoding success or decoding failure message to the finite state machine, stores the flip state in the second area, and stores the second soft bit in the fourth area, Wherein, in each iteration of the third stage state, the finite state machine sends a second control signal to the multiplexer to couple the fourth region to the change node calculation circuit, and the The change node calculation circuit obtains the change node from the mutex or calculator, reads the second soft bit corresponding to the change node from the fourth area through the multiplexer, and calculates the The difference between the codeword and the new change node is used to generate a new flip state, transmitting the new change node to the check node calculation circuit, and obtaining the new second second value from the check node calculation circuit. syndrome, transmit a decoding success or decoding failure message to the finite state machine according to the new second syndrome, store the new flip state in the second area, and store the new third two soft bits to the fourth region.

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