TW202348818A - Laminated structure, semiconductor device and method for producing the same - Google Patents

Laminated structure, semiconductor device and method for producing the same Download PDF

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TW202348818A
TW202348818A TW112109208A TW112109208A TW202348818A TW 202348818 A TW202348818 A TW 202348818A TW 112109208 A TW112109208 A TW 112109208A TW 112109208 A TW112109208 A TW 112109208A TW 202348818 A TW202348818 A TW 202348818A
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Taiwan
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laminated structure
semiconductor
semiconductor device
type semiconductor
buffer layer
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TW112109208A
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Chinese (zh)
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木島健
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日商蓋亞尼克斯股份有限公司
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Abstract

An objective of this invention is to provide a laminated structure having excellent crystallinity, a semiconductor device, and a producing method capable of obtaining these in an industrially advantageous manner. This invention provides a method for producing semiconductor devices including Schottky barrier diode (SBD), Junction barrier Schottky diode (JBS), Merged-PiN Schottky barrier diode (MPS), metal semiconductor field effect transistors (MESFETs), high electron mobility transistors (HEMTs), metal oxide semiconductor field effect transistors (MOSFETs), static induction transistor (SIT), Junction Field Effect Transistor (JFET), an insulated gate bipolar transistor (IGBT), light emitting diode (LED) or a combination thereof by laminating a buffer layer containing a conductive crystal film containing a nitride or oxynitride of Hf and/or Zr on a semiconductor crystal substrate; and laminating an epitaxial film made of a compound semiconductor directly or via another layer on the buffer layer.

Description

積層構造體、半導體裝置及其製造方法 Multilayer structure, semiconductor device and manufacturing method thereof

本發明係關於一種積層構造體、半導體裝置及其製造方法。 The present invention relates to a laminated structure, a semiconductor device, and a manufacturing method thereof.

以往，使藍寶石(sapphire)基板上晶體成長氮化鎵的異質磊晶生長(heteroepitaxial growth)製程等一直被研討著。然而，由於熱膨脹率的不同及晶格不匹配的問題，所以不容易形成高品質的磊晶膜(epitaxial film)，存在著磊晶膜的形成步驟複雜且高度/精緻化的問題，並且關係到成本增加等問題。 In the past, heteroepitaxial growth processes for growing gallium nitride crystals on sapphire substrates have been studied. However, due to differences in thermal expansion rates and lattice mismatch, it is not easy to form a high-quality epitaxial film. There are problems with the formation steps of the epitaxial film being complicated and highly/refined, and related to Increased costs and other issues.

近年來，經調整的實質上適合於磊晶層的熱膨脹率(CTE)後的磊晶用基板(例如專利文獻1)一直被研討著。然而，上述的磊晶用基板的製作步驟複雜且高度/精緻化，完全達不到根本性地解決問題，而且，存在著進行磊晶用基板的剝離後，在進行表面處理之後進行研磨，而且必須進行連接電極等問題。因此，期待著能夠容易地形成氮化鎵等化合物半導體的磊晶膜，而且也能夠容易地製造半導體裝置的對策。 In recent years, epitaxial substrates whose thermal expansion coefficient (CTE) has been adjusted to be substantially suitable for the epitaxial layer have been studied (for example, Patent Document 1). However, the manufacturing steps of the above-mentioned substrate for epitaxy are complicated and highly refined, and cannot fundamentally solve the problem. Moreover, after peeling off the substrate for epitaxy, there is a need to perform surface treatment and then polish. Problems such as connecting electrodes must be made. Therefore, measures are expected to make it possible to easily form an epitaxial film of a compound semiconductor such as gallium nitride and to easily manufacture a semiconductor device.

[先前技術文獻] [Prior technical literature]

[專利文獻] [Patent Document]

專利文獻1：日本特開2020-161833號公報 Patent Document 1: Japanese Patent Application Publication No. 2020-161833

本發明之目的為提供具有優異的結晶性的積層構造體、半導體特性優異的半導體裝置及能夠獲得工業上有利的上述的具有優異的結晶性的積層構造體、半導體特性優異的半導體裝置的製造方法。 An object of the present invention is to provide a laminated structure having excellent crystallinity, a semiconductor device having excellent semiconductor properties, and a method for manufacturing a laminated structure having excellent crystallinity and a semiconductor device having excellent semiconductor properties that can be industrially advantageous. .

本發明的發明人等為了達成上述目的而精進研究後的結果，發覺到在要將緩衝層積層於半導體晶體基板上，直接或隔著其他層而在前述緩衝層上積層由化合物半導體構成的磊晶膜時，當使用Hf及/或Zr的氮化物或氮氧化物的結晶作為前述緩衝層，就會容易地獲得良好品質的導電性結晶膜、前述導電性結晶膜可用於作為緩衝層、能夠容易地形成由高品質的化合物半導體構成的磊晶膜等，而且發覺到依據上述的積層構造體也能夠將所形成的導電性結晶膜使用於電極層等、能夠容易地製造半導體裝置等各種現象的認知，以致於察覺到前述積層構造體為能夠一併解決以往問題的積層構造體。 As a result of intensive research in order to achieve the above object, the inventors of the present invention found that in order to laminate a buffer layer on a semiconductor crystal substrate, a compound semiconductor composed of a compound semiconductor must be layered directly on the buffer layer or via another layer. In the case of a crystal film, when a crystal of Hf and/or Zr nitride or oxynitride is used as the buffer layer, a good quality conductive crystal film can be easily obtained. The conductive crystal film can be used as a buffer layer. It was discovered that epitaxial films and the like made of high-quality compound semiconductors can be easily formed, and the conductive crystalline film formed can also be used for electrode layers and the like based on the above-mentioned multilayer structure, and semiconductor devices can be easily manufactured, etc. cognition, so that he realized that the aforementioned multilayer structure was a multilayer structure that could solve all the problems of the past.

再者，本發明的發明人等在獲得上述的認知後，進一步重複地研討之後終於完成本發明。 Furthermore, after the inventors of the present invention obtained the above-mentioned knowledge, they conducted further repeated studies and finally completed the present invention.

亦即，本發明係有關以下的發明。 That is, the present invention relates to the following invention.

[1]一種積層構造體，係直接或隔著其他層而在緩衝層上積層有由化合物半導體構成的磊晶膜者，前述緩衝層係包含導電性結晶膜，而該導電性結晶膜係含有Hf及/或Zr的氮化物或氮氧化物。 [1] A laminated structure in which an epitaxial film composed of a compound semiconductor is laminated on a buffer layer directly or via another layer, the buffer layer containing a conductive crystal film, and the conductive crystal film containing Nitride or nitrogen oxide of Hf and/or Zr.

[2]如前述[1]所述的積層構造體，其中，前述導電性結晶膜係含有HfN。 [2] The laminated structure according to the above [1], wherein the conductive crystal film contains HfN.

[3]如前述[1]或[2]所述的積層構造體，其中，前述磊晶膜係具有立方晶體構造。 [3] The laminated structure according to [1] or [2] above, wherein the epitaxial film has a cubic crystal structure.

[4]如前述[1]至[3]中任一者所述的積層構造體，其中，前述化合物半導體係為寬能隙半導體(wide bandgap semiconductor)。 [4] The laminated structure according to any one of [1] to [3] above, wherein the compound semiconductor is a wide bandgap semiconductor.

[5]如前述[1]至[4]中任一者所述的積層構造體，其中，前述化合物半導體係為氮化物半導體。 [5] The laminated structure according to any one of [1] to [4] above, wherein the compound semiconductor is a nitride semiconductor.

[6]如前述[1]至[5]中任一者所述的積層構造體，其中，前述緩衝層係直接或隔著其他層而積層在半導體單晶體基板上。 [6] The laminated structure according to any one of [1] to [5] above, wherein the buffer layer is laminated on the semiconductor single crystal substrate directly or via another layer.

[7]如前述[6]所述的積層構造體，其中，前述緩衝層係藉由晶體成長而積層在前述半導體單晶體基板上。 [7] The laminated structure according to the above [6], wherein the buffer layer is laminated on the semiconductor single crystal substrate by crystal growth.

[8]如前述[6]或[7]所述的積層構造體，其中，前述半導體單晶體基板係為Si基板。 [8] The laminated structure according to the above [6] or [7], wherein the semiconductor single crystal substrate is a Si substrate.

[9]一種半導體裝置，係包含積層構造體者，且前述積層構造體係為如前述[1]至[8]中任一者所述的積層構造體。 [9] A semiconductor device including a multilayer structure, wherein the multilayer structure system is the multilayer structure according to any one of the above [1] to [8].

[10]如前述[9]所述的半導體裝置，其中，前述半導體裝置係立式裝置。 [10] The semiconductor device according to the above [9], wherein the semiconductor device is a vertical device.

[11]如前述[9]或[10]所述的半導體裝置，其中，前述半導體裝置係蕭特基屏障二極體(SBD：Schottky barrier diode)、接面位障蕭特基二極體(JBS：Junction barrier Schottky diode)、合併式PiN蕭特基二極體(MPS：Merged-PiN Schottky barrier diode)、金屬半導體場效電晶體(MESFET)、高電子移動率電晶體(HEMT)、金屬氧化物半導體場效應電晶體(MOSFET)、靜電感應電晶體(SIT)、接面場效電晶體(JFET)、絕緣閘雙極電晶體(IGBT)、發光二極體(LED)或其等的組合。 [11] The semiconductor device according to [9] or [10] above, wherein the semiconductor device is a Schottky barrier diode (SBD) or a junction barrier Schottky diode (SBD). JBS: Junction barrier Schottky diode), Merged PiN Schottky diode (MPS: Merged-PiN Schottky barrier diode), Metal Semiconductor Field Effect Transistor (MESFET), High Electron Mobility Transistor (HEMT), Metal Oxide Physical semiconductor field effect transistor (MOSFET), electrostatic induction transistor (SIT), junction field effect transistor (JFET), insulating gate bipolar transistor (IGBT), light emitting diode (LED) or a combination thereof.

[12]一種積層構造體的製造方法，係在半導體晶體基板上積層緩衝層，且直接或隔著其他層而在前述緩衝層上積層有由化合物半導體構成的磊晶膜者，前述緩衝層係包含導電性結晶膜，而該導電性結晶膜係含有Hf及/或Zr的氮化物或氮氧化物。 [12] A method of manufacturing a laminated structure in which a buffer layer is laminated on a semiconductor crystal substrate, and an epitaxial film composed of a compound semiconductor is laminated on the buffer layer directly or via another layer, and the buffer layer is It contains a conductive crystal film, and the conductive crystal film contains nitride or nitride oxide of Hf and/or Zr.

[13]如前述[12]所述的積層構造體的製造方法，其中，前述半導體單晶體基板係為Si基板，前述化合物半導體係為氮化物半導體。 [13] The method for manufacturing a laminated structure according to the above [12], wherein the semiconductor single crystal substrate is a Si substrate and the compound semiconductor is a nitride semiconductor.

[14]一種半導體裝置的製造方法，係使用積層構造體者，前述積層構造體係為如前述[1]至[8]中任一者所述的積層構造體。 [14] A method of manufacturing a semiconductor device using a laminated structure, and the laminated structure system is the laminated structure described in any one of [1] to [8] above.

[15]一種系統，係包含半導體裝置者，前述半導體裝置係為如前述[9]至[11]中任一者所述的半導體裝置。 [15] A system including a semiconductor device as described in any one of [9] to [11] above.

本發明的積層構造體及半導體裝置具有優異的結晶性，依據本發明的製造方法，可達成能夠獲得工業上有利的前述積層構造體及半導體裝置的功效。 The laminated structure and semiconductor device of the present invention have excellent crystallinity, and according to the manufacturing method of the present invention, the effect of obtaining the aforementioned laminated structure and semiconductor device that is industrially advantageous can be achieved.

1:磊晶膜(化合物半導體) 1: Epitaxial film (compound semiconductor)

5:氧化膜/緩衝層 5:Oxide film/buffer layer

9:晶體基板 9: Crystal substrate

101:n型半導體層 101: n-type semiconductor layer

101a:n-型半導體層 101a:n - type semiconductor layer

101b:n+型半導體層 101b: n + type semiconductor layer

102:p型半導體層 102: p-type semiconductor layer

104:絕緣體層 104:Insulator layer

105a:蕭特基電極 105a: Schottky electrode

105b:歐姆電極 105b: Ohmic electrode

106:保護環 106:Protective ring

111a:n-型半導體層 111a:n - type semiconductor layer

111b:n+型半導體層 111b: n + type semiconductor layer

114:半絕緣體層 114: Semi-insulator layer

115a:閘極電極 115a: Gate electrode

115b:源極電極 115b: Source electrode

115c:汲極電極 115c: Drain electrode

118:緩衝層118 118: Buffer layer 118

119:晶體基板 119:Crystal substrate

121a:能帶較寬的n型半導體層 121a: N-type semiconductor layer with wider energy band

121b:能帶較窄的n型半導體層 121b: n-type semiconductor layer with narrow energy band

121c:n+型半導體層 121c: n + type semiconductor layer

123:電子通過層 123:Electron passing layer

124:半絕緣體層 124: Semi-insulator layer

125a:閘極電極 125a: Gate electrode

125b:源極電極 125b: Source electrode

125c:汲極電極 125c: Drain electrode

128:緩衝層 128:Buffer layer

129:晶體基板 129:Crystal substrate

131a:n-型半導體層 131a:n - type semiconductor layer

131b:第一n+型半導體層 131b: First n + type semiconductor layer

131c:第二n+型半導體層 131c: Second n + type semiconductor layer

132:p型半導體層 132: p-type semiconductor layer

132a:p+型半導體層 132a: p + type semiconductor layer

134:閘極絕緣膜 134: Gate insulation film

135a:閘極電極 135a: Gate electrode

135b:源極電極 135b: Source electrode

135c:汲極電極 135c: Drain electrode

141a:n-型半導體層 141a:n - type semiconductor layer

141b:第一n+型半導體層 141b: First n + type semiconductor layer

141c:第二n+型半導體層 141c: Second n + type semiconductor layer

142:p型半導體層 142: p-type semiconductor layer

145a:閘極電極 145a: Gate electrode

145b:源極電極 145b: Source electrode

145c:汲極電極 145c: Drain electrode

151:n型半導體層 151: n-type semiconductor layer

151a:n-型半導體層 151a:n - type semiconductor layer

151b:n+型半導體層 151b: n + type semiconductor layer

152:p型半導體層 152: p-type semiconductor layer

154:閘極絕緣膜 154: Gate insulation film

155a:閘極電極 155a: Gate electrode

155b:射極電極 155b: Emitter electrode

155c:集極電極 155c: Collector electrode

161:n型半導體層 161: n-type semiconductor layer

162:p型半導體層 162: p-type semiconductor layer

163:發光層 163: Luminous layer

165a:第一電極 165a: first electrode

165b:第二電極 165b: Second electrode

167:透光性電極 167: Translucent electrode

1101a至1101b:金屬源 1101a to 1101b: Metal source

1102a至1102h:接地 1102a to 1102h: Ground

1103a至1103b:ICP電極 1103a to 1103b: ICP electrode

1104a至1104b:截止濾波器 1104a to 1104b: Cutoff filter

1105a至1105b:DC電源 1105a to 1105b: DC power supply

1106a至1106b:RF電源 1106a to 1106b: RF power supply

1107a至1107b:燈 1107a to 1107b: Lamp

1108:Ar源 1108:Ar source

1109:反應性氣體源 1109: Reactive gas source

1110:電源 1110:Power supply

1111:基板保持器 1111:Substrate holder

1112:基板 1112:Substrate

1113:截止濾波器 1113: Cutoff filter

1114:ICP環 1114:ICP ring

1115:真空槽 1115: Vacuum tank

1116:旋轉軸 1116:Rotation axis

圖1係示意性地顯示本發明的積層構造體之適合的實施型態之一例的圖。 FIG. 1 is a diagram schematically showing an example of a suitable embodiment of the laminated structure of the present invention.

圖2係用以說明在本發明的積層構造體的製造方法中的緩衝層形成步驟的示意圖。 FIG. 2 is a schematic diagram for explaining the buffer layer formation step in the manufacturing method of the laminated structure of the present invention.

圖3係示意性地顯示本發明的半導體裝置(SBD)之適合的實施型態之一例的圖。 FIG. 3 is a diagram schematically showing an example of a suitable embodiment of the semiconductor device (SBD) of the present invention.

圖4係示意性地顯示本發明的半導體裝置(JBS)之適合的實施型態之一例的圖。 FIG. 4 is a diagram schematically showing an example of a suitable implementation mode of the semiconductor device (JBS) of the present invention.

圖5係示意性地顯示本發明的半導體裝置(MESFET)之適合的實施型態之一例的圖。 FIG. 5 is a diagram schematically showing an example of a suitable implementation mode of the semiconductor device (MESFET) of the present invention.

圖6係示意性地顯示本發明的半導體裝置(HEMT)之適合的實施型態之一例的圖。 FIG. 6 is a diagram schematically showing an example of a suitable implementation mode of the semiconductor device (HEMT) of the present invention.

圖7係示意性地顯示本發明的半導體裝置(MOSFET)之適合的實施型態之一例的圖。 FIG. 7 is a diagram schematically showing an example of a suitable implementation mode of the semiconductor device (MOSFET) of the present invention.

圖8係示意性地顯示本發明的半導體裝置(SIT)之適合的實施型態之一例的圖。 FIG. 8 is a diagram schematically showing an example of a suitable embodiment of the semiconductor device (SIT) of the present invention.

圖9係示意性地顯示本發明的半導體裝置(JFET)之適合的實施型態之一例的圖。 FIG. 9 is a diagram schematically showing an example of a suitable implementation mode of the semiconductor device (JFET) of the present invention.

圖10係示意性地顯示本發明的半導體裝置(IGBT)之適合的實施型態之一例的圖。 FIG. 10 is a diagram schematically showing an example of a suitable embodiment of the semiconductor device (IGBT) of the present invention.

圖11係示意性地顯示本發明的半導體裝置(LED)之適合的實施型態之一例的圖。 FIG. 11 is a diagram schematically showing an example of a suitable embodiment of the semiconductor device (LED) of the present invention.

圖12係示意性地顯示電源系統之適合的實施型態之一例的圖。 FIG. 12 is a diagram schematically showing an example of a suitable implementation form of the power supply system.

圖13係示意性地顯示系統裝置之適合的一例的圖。 FIG. 13 is a diagram schematically showing a suitable example of the system device.

圖14係示意性地顯示電源裝置之電源電路圖之適合的一例的圖。 FIG. 14 is a diagram schematically showing a suitable example of the power supply circuit diagram of the power supply device.

圖15係示意性地顯示在實施例中適合地使用的成膜裝置的圖。 FIG. 15 is a diagram schematically showing a film-forming apparatus suitably used in Examples.

本發明的積層構造體的特點在於：直接或隔著其他層而在緩衝層上積層有由化合物半導體構成的磊晶膜者，前述緩衝層係包含導電性結晶膜，而該導電性結晶膜係含有Hf及/或Zr的氮化物或氮氧化物。圖1顯示前述積層構造體之適合的例子，圖1的積層構造體係在晶體基板9上積層有緩衝層5，而且在前述緩衝層5上積層有由化合物半導體構成的磊晶膜1。此外，本說明書中，「膜」及「層」的各用語係可依據各種情形或因應狀況而相互替代。 The laminated structure of the present invention is characterized in that an epitaxial film composed of a compound semiconductor is laminated on a buffer layer directly or through another layer, the buffer layer includes a conductive crystal film, and the conductive crystal film is Nitride or nitrogen oxide containing Hf and/or Zr. FIG. 1 shows a suitable example of the above-mentioned laminated structure. In the laminated structure system of FIG. 1, a buffer layer 5 is laminated on a crystal substrate 9, and an epitaxial film 1 composed of a compound semiconductor is laminated on the buffer layer 5. In addition, in this specification, the terms "film" and "layer" may be replaced by each other according to various circumstances or situations.

本發明的積層構造體較佳為例如圖2所示，使用以利用氮之公知的晶體成長手段而在晶體基板9上形成緩衝層5。前述晶體成長手段可為公知的手段，也可為氣相晶體成長手段及液相晶體成長手段之其中任一晶體成長手段。在作為前述晶體成長手段方面可舉出有例如蒸鍍法、CVD(化學氣相沉積)法、濺射法等。在本發明中，較佳為形成前述緩衝層5後，使用前述晶體成長手段將由化合物半導體構成的磊晶膜形成在前述緩衝層上，如此一來，藉由形成前述磊晶膜而如圖1所示的方式前述緩衝層沿晶體成長方向轉變而在與前述磊晶膜的界面形成山谷構造，藉由該山谷構造，能夠容易地獲得結晶性優異的良好品質的前述磊晶膜。 A preferred example of the laminated structure of the present invention is as shown in FIG. 2 , in which the buffer layer 5 is formed on the crystal substrate 9 using a known crystal growth method using nitrogen. The aforementioned crystal growth means may be a publicly known means, or may be any one of a vapor phase crystal growth means and a liquid phase crystal growth means. Examples of the crystal growth means include vapor deposition, CVD (chemical vapor deposition), and sputtering. In the present invention, it is preferable that after the buffer layer 5 is formed, an epitaxial film composed of a compound semiconductor is formed on the buffer layer using the crystal growth means. In this way, by forming the epitaxial film, as shown in FIG. 1 In the mode shown, the buffer layer changes along the crystal growth direction to form a valley structure at the interface with the epitaxial film. With this valley structure, the epitaxial film of good quality and excellent in crystallinity can be easily obtained.

前述晶體基板(以下也簡稱為「基板」)之基板材料等只要是不會阻礙本發明的目的就不特別地限定，也可為公知的晶體基板。也可為有機化合物，亦可為無機化合物。在本發明中，前述晶體基板較佳為含有無機化合物。在本發明中，前述基板較佳為表面的一部分或全部具有結晶者，更佳為晶體成長側之主表面的全部或一部分具有結晶的晶體基板者，最佳為晶體成長側之主表面的全部具有結晶的晶體基板者。前述結晶只要是不會阻礙本發明的目的就不特別地限定，晶體結構等也不特別地限定，也可為立方晶系、正方晶系、三方晶系、六 方晶系、斜方晶系及單斜晶系等其中任一晶體結構，然而在本發明中，較佳為立方晶系的晶體結構，更佳為沿(100)或(200)取向的結晶。再者，前述晶體基板也可具有偏移角，在前述偏移角方面可舉出例如0.2°至12.0°的偏移角等。在此所稱的「偏移角」乃指基板表面與晶體成長面所形成的角度。前述基板形狀為板狀，只要是構成前述絕緣膜的支撐體就不特別地限定。也可為絕緣體基板，亦可為半導體基板，然而在本發明中，前述基板較佳為Si基板，更佳為結晶性Si基板，最佳為沿(100)取向的結晶性Si基板。此外，在作為前述基板材料方面，在Si基板之外可舉出有例如屬於元素週期表第3族至第15族的一種或兩種以上的金屬或該等金屬的氧化物等。前述基板的形狀不特別地限定而可為大致圓形狀(例如圓形、橢圓形等)，也可為多角形狀(例如三角形、正方形、長方形、五角形、六角形、七角形、八角形、九角形等)，能夠適合地使用各種形狀。 The substrate material of the crystal substrate (hereinafter also referred to as "substrate") is not particularly limited as long as it does not hinder the object of the present invention, and it may be a known crystal substrate. It may also be an organic compound or an inorganic compound. In the present invention, the crystal substrate preferably contains an inorganic compound. In the present invention, the aforementioned substrate is preferably a crystal substrate having crystals on part or all of its surface, more preferably all or part of the main surface on the crystal growth side, and most preferably the entire main surface on the crystal growth side. Having a crystalline substrate. The aforementioned crystal is not particularly limited as long as it does not hinder the object of the present invention, and the crystal structure is not particularly limited either. It may be a cubic crystal system, a tetragonal crystal system, a trigonal crystal system, or a hexagonal crystal system. Any crystal structure such as cubic system, orthorhombic system or monoclinic system. However, in the present invention, the crystal structure of cubic system is preferred, and the crystal structure along (100) or (200) orientation is more preferred. . Furthermore, the crystal substrate may have an offset angle. Examples of the offset angle include an offset angle of 0.2° to 12.0°. The "offset angle" referred to here refers to the angle formed by the substrate surface and the crystal growth surface. The shape of the substrate is not particularly limited as long as it is a plate-like shape and forms a support for the insulating film. It may be an insulator substrate or a semiconductor substrate. However, in the present invention, the aforementioned substrate is preferably a Si substrate, more preferably a crystalline Si substrate, and most preferably a crystalline Si substrate along the (100) orientation. Examples of the substrate material include, in addition to the Si substrate, one or two or more metals belonging to Group 3 to Group 15 of the periodic table of elements, or oxides of these metals. The shape of the substrate is not particularly limited and may be a substantially circular shape (such as a circle, an ellipse, etc.) or a polygonal shape (such as a triangle, a square, a rectangle, a pentagon, a hexagon, a heptagon, an octagon, or a nonagonal shape). etc.), various shapes can be used appropriately.

再者，在本發明中，前述晶體基板較佳為具有平坦面者，然而前述晶體基板之較佳者也可為表面的一部分或全部具有凹凸形狀。前述具有凹凸形狀的晶體基板只要是表面的一部分或全部形成有由凹部或凸部所構成的凹凸部即可，前述凹凸部只要是由由凹部或凸部所構成者就不特別地限定，可為由凸部所構成的凹凸部，也可為由凹部所構成的凹凸部，也可為由凸部及凹部所構成的凹凸部。再者，前述凹凸部也可由規律的凸部或凹部所形成，亦可由不規律的凸部或凹部所形成。在本發明中，前述凹凸部較佳為周期性地形成者，更佳為周期性且規律性地圖案化者。前述凹凸部的形狀不特別地限定，可舉出有例如條紋狀、點狀、網眼狀或隨機狀等，然而在本發明中，較佳為點狀或條紋狀，而以點狀為更佳。再者，凹凸部為周期性且規律性地圖案化時，前述凹凸部的圖案形狀較佳為三角形、四角形(例如正方形、長方形或梯形等)、五角形或六角形等多角 形狀、圓形、橢圓狀等形狀。此外，凹凸部形成點狀時，較佳為將點狀的晶格形狀設成例如正方晶格、斜方晶格、三角晶格、六角晶格等晶格形狀，更佳為設成三角晶格的晶格形狀。前述凹凸部的凹部或凸部的剖面形狀不特別地限定，然而可舉出有匚字形、U字形、倒U字形、波紋形或三角形、四角形(例如正方形、長方形或梯形等)、五角形或六角形等多角形狀。此外，前述晶體基板的厚度不特別地限定，然而較佳為50至2000μm，更佳為100至1000μm。 Furthermore, in the present invention, the crystal substrate preferably has a flat surface. However, the crystal substrate may preferably have a concave and convex shape on part or all of its surface. The crystal substrate having an uneven shape is not particularly limited as long as the uneven portions composed of concave portions or convex portions are formed on part or all of the surface. The concave-convex portion may be composed of a convex portion, the concave-convex portion may be composed of a concave portion, or the concave-convex portion may be composed of a convex portion and a concave portion. Furthermore, the aforementioned concave and convex parts may also be formed by regular convex parts or concave parts, or may be formed by irregular convex parts or concave parts. In the present invention, the concave and convex portions are preferably formed periodically, and more preferably are patterned periodically and regularly. The shape of the uneven portions is not particularly limited, and examples thereof include striped, dotted, mesh, or random shapes. However, in the present invention, dotted or striped shapes are preferred, and dotted shapes are more preferred. good. Furthermore, when the concave and convex portions are patterned periodically and regularly, the pattern shape of the concave and convex portions is preferably a polygonal shape such as a triangle, a quadrangle (such as a square, a rectangle or a trapezoid, etc.), a pentagon or a hexagon. Shapes, circles, ovals, etc. In addition, when the uneven portions are formed into point shapes, it is preferable that the point-like lattice shape be a lattice shape such as a square lattice, an orthorhombic lattice, a triangular lattice, or a hexagonal lattice, and more preferably a triangular lattice shape. The lattice shape of the lattice. The cross-sectional shape of the concave or convex portions of the concave and convex portions is not particularly limited, but examples thereof include U-shaped, U-shaped, inverted U-shaped, corrugated or triangular, quadrangular (for example, square, rectangular or trapezoidal, etc.), pentagonal or hexagonal. Angular and other polygonal shapes. In addition, the thickness of the crystal substrate is not particularly limited, but is preferably 50 to 2000 μm, more preferably 100 to 1000 μm.

前述緩衝層只要是包含導電性結晶膜，而該導電性結晶膜含有Hf及/或Zr的氮化物或氮氧化物就不特別地限定，然而在本發明中，前述導電性結晶膜較佳為含有HfN及/或ZrN者，更佳為含有HfN者。藉由前述導電性結晶膜含有HfN，即使是由二層以上晶體成長來形成前述磊晶膜時，在每種情況下，都能夠產生轉變以進一步提高磊晶膜的結晶性。再者，前述導電性結晶膜較佳為具有立方晶體構造者，更佳為含有沿(100)或(200)取向的結晶者。前述緩衝層能夠以例如350℃至700℃且使用Hf源及/或Zr源以及氮氣而以濺鍍法等公知的晶體成長手段適合地形成於前述晶體基板上。再者，前述緩衝層也可包含有混晶(也可稱為「混合晶體」)膜。前述混晶膜只要是由混晶所構成的結晶膜就不特別地限定，而在作為前述混晶方面，除了Hf及/或Zr的氮化物或氮氧化物之外，更可含有例如選自Ti、Al、Y及Ce之一種或兩種以上的氮化物或氮氧化物等的混晶等。依據上述適合的混晶，不僅能夠達到更優化前述緩衝層的應力緩和效果，而且能夠達到更優化前述磊晶膜的膜質。 The buffer layer is not particularly limited as long as it contains a conductive crystal film, and the conductive crystal film contains a nitride or nitride oxide of Hf and/or Zr. However, in the present invention, the conductive crystal film is preferably Those containing HfN and/or ZrN are more preferably those containing HfN. Since the conductive crystal film contains HfN, even when the epitaxial film is formed by growing two or more crystal layers, in each case, transformation can occur to further improve the crystallinity of the epitaxial film. Furthermore, the conductive crystal film preferably has a cubic crystal structure, and more preferably contains crystals along the (100) or (200) orientation. The buffer layer can be suitably formed on the crystal substrate by a known crystal growth means such as sputtering using an Hf source and/or a Zr source and nitrogen gas at, for example, 350°C to 700°C. Furthermore, the buffer layer may also include a mixed crystal (also referred to as "mixed crystal") film. The mixed crystal film is not particularly limited as long as it is a crystal film composed of mixed crystals. As the mixed crystal, in addition to nitrides or nitride oxides of Hf and/or Zr, it may further contain, for example, selected from the group consisting of Mixed crystals of one or more nitrides or nitrogen oxides of Ti, Al, Y and Ce, etc. According to the above-mentioned suitable mixed crystal, not only the stress relaxation effect of the buffer layer can be further optimized, but also the film quality of the epitaxial film can be further optimized.

前述磊晶膜只要是由化合物半導體構成的晶體成長膜就不特別地限定。前述化合物半導體也不特別地限定，而可為公知的化合物半導體。在作為前述化合物半導體方面，可舉出有例如氮化物半導體、碳化物半導體(例如SiC 等)、氧化物半導體、InP或GaAs等。在本發明中，前述化合物半導體較佳為寬能隙半導體，更佳為氮化物半導體。在作為前述氮化物半導體方面，可舉出有例如III-V族半導體(氮化鋁(AlN))、氮化鎵(GaN)、氮化銦(InN)等)、或氮化硼(BN)等。在本發明中，前述磊晶膜較佳為具有立方晶體構造，更較為由立方晶半導體構成的晶體成長膜。在作為立方晶半導體方面，可舉出有例如c-BN、c-AlN、c-GaN、c-InN、c-SiC、GaAs、AlAs、InAs、GaP、AlP、InP或其等的混晶半導體等。 The epitaxial film is not particularly limited as long as it is a crystal growth film composed of a compound semiconductor. The aforementioned compound semiconductor is not particularly limited and may be a known compound semiconductor. Examples of the compound semiconductor include nitride semiconductors, carbide semiconductors (such as SiC etc.), oxide semiconductor, InP or GaAs, etc. In the present invention, the compound semiconductor is preferably a wide bandgap semiconductor, more preferably a nitride semiconductor. Examples of the nitride semiconductor include III-V semiconductors (aluminum nitride (AlN)), gallium nitride (GaN), indium nitride (InN), etc.), or boron nitride (BN). wait. In the present invention, the epitaxial film preferably has a cubic crystal structure, and is more preferably a crystal growth film composed of a cubic crystal semiconductor. Examples of cubic crystal semiconductors include c-BN, c-AlN, c-GaN, c-InN, c-SiC, GaAs, AlAs, InAs, GaP, AlP, InP, and mixed crystal semiconductors thereof. wait.

依據以上的方式所獲得的積層構造體能夠依照一般方法保持原有狀態或依據所希望而進一步進行加工等以使用於半導體裝置。在本發明中，能夠將前述積層構造體中的前述緩衝層適合地使用於前述半導體裝置的歐姆性的(ohmic)接合用或電子釋出用的電極或緩衝層，而且能夠將前述積層構造體中的前述磊晶膜適合地使用於前述半導體裝置的半導體層。再者，將前述積層構造體使用於半導體裝置時，也能夠以維持原狀的方式使用於半導體裝置，而且也可以在形成其他層(例如絕緣體層、半絕緣體層、導體層、半導體層、緩衝層或其他中間層等)等之後使用。再者，在前述半導體裝置中也可使用公知的剝離手段來剝離前述晶體基板。 The laminated structure obtained in the above manner can be kept as it is according to general methods or further processed as desired to be used in a semiconductor device. In the present invention, the buffer layer in the laminated structure can be suitably used as an electrode or buffer layer for ohmic bonding or electron emission of the semiconductor device, and the laminated structure can be used The epitaxial film is suitably used for the semiconductor layer of the semiconductor device. Furthermore, when the above-described laminated structure is used in a semiconductor device, it can be used in the semiconductor device as it is, and other layers (such as insulator layers, semi-insulator layers, conductor layers, semiconductor layers, buffer layers) can also be formed. or other intermediate layers, etc.) before use. Furthermore, in the semiconductor device, a known peeling means may be used to peel off the crystal substrate.

前述半導體裝置只要是不會阻礙本發明的目的就不特別地限定，也可為公知的半導體裝置。可以為立式裝置，也可以為橫式裝置，然而在本發明中，前述半導體裝置較佳為立式裝置。在作為前述半導體裝置方面，可舉出例如二極體或電晶體等，更具體為例如以蕭特基屏障二極體(SBD：Schottky barrier diode)、接面位障蕭特基二極體(JBS：Junction barrier Schottky diode)、高電子移動率電晶體(HEMT)、金屬半導體場效電晶體(MESFET)、金屬氧化物半導體場效應電晶體(MOSFET)、靜電感應電晶體(SIT)、接面場效電晶體(JFET)、絕緣閘雙 極電晶體(IGBT)、發光二極體(LED)或其等的組合為適合的例子。 The aforementioned semiconductor device is not particularly limited as long as it does not hinder the object of the present invention, and may be a known semiconductor device. It may be a vertical device or a horizontal device. However, in the present invention, the semiconductor device is preferably a vertical device. Examples of the aforementioned semiconductor devices include diodes, transistors, and the like. More specifically, examples include Schottky barrier diodes (SBDs) and junction barrier Schottky diodes (SBDs). JBS: Junction barrier Schottky diode), high electron mobility transistor (HEMT), metal semiconductor field effect transistor (MESFET), metal oxide semiconductor field effect transistor (MOSFET), electrostatic induction transistor (SIT), junction field Effective transistor (JFET), insulated gate double IGBTs, LEDs, or combinations thereof are suitable examples.

以下，使用圖式來說明將前述積層構造體適合地使用於半導體裝置，更具體為將前述積層構造體中的前述緩衝層適合地使用於前述半導體裝置的歐姆性的接合用或電子釋出用的電極或緩衝層，而且能夠將前述積層構造體中的前述磊晶膜適合地使用於前述半導體裝置的半導體層時之適合的例子，然而本發明並不限定於這些例子。此外，以下要例示的半導體裝置中，只要是不會阻礙本發明的目的，也可更包含其他層(例如絕緣體層、半絕緣體層、導體層、半導體層、緩衝層或其他中間層等)等，再者，也可適切地省去晶體基板、緩衝層(buffer layer)等。 Hereinafter, the drawings will be used to explain how the laminated structure is suitably used in a semiconductor device, and more specifically, how the buffer layer in the laminated structure is suitably used for ohmic bonding or electron emission of the semiconductor device. An electrode or a buffer layer, and the epitaxial film in the multilayer structure can be suitably used as a semiconductor layer of the semiconductor device. However, the present invention is not limited to these examples. In addition, the semiconductor device to be exemplified below may further include other layers (such as insulator layers, semi-insulator layers, conductor layers, semiconductor layers, buffer layers or other intermediate layers, etc.) as long as they do not hinder the object of the present invention. , Furthermore, the crystal substrate, buffer layer, etc. can also be omitted appropriately.

(SBD) (SBD)

圖3顯示本發明之蕭特基屏障二極體(SBD)的一例。圖3的SBD具有n型半導體層101、n-型半導體層101a、n+型半導體層101b、絕緣體層104、蕭特基電極105a及歐姆電極105b。 FIG. 3 shows an example of the Schottky barrier diode (SBD) of the present invention. The SBD of FIG. 3 includes an n-type semiconductor layer 101, an n - type semiconductor layer 101a, an n + -type semiconductor layer 101b, an insulator layer 104, a Schottky electrode 105a, and an ohmic electrode 105b.

蕭特基電極等電極的材料可為公知的電極材料，在作為前述電極材料方面，可舉出例如Al、Mo、Co、Zr、Sn、Nb、Fe、Cr、Ta、Ti、Au、Pt、V、Mn、Ni、Cu、Hf、W、Ir、Zn、In、Pd、Nd或Ag等金屬或這些金屬的合金、氧化錫、氧化鋅、氧化銦、氧化銦錫(ITO)、氧化鋅銦(IZO)等金屬氧化物導電膜、聚苯胺、聚噻吩或聚吡咯等有機導電性化合物、或這些化合物的混合物等。 The material of electrodes such as Schottky electrodes can be known electrode materials. Examples of the electrode materials include Al, Mo, Co, Zr, Sn, Nb, Fe, Cr, Ta, Ti, Au, Pt, Metals such as V, Mn, Ni, Cu, Hf, W, Ir, Zn, In, Pd, Nd or Ag or alloys of these metals, tin oxide, zinc oxide, indium oxide, indium tin oxide (ITO), zinc indium oxide Metal oxide conductive films such as (IZO), organic conductive compounds such as polyaniline, polythiophene or polypyrrole, or mixtures of these compounds, etc.

電極的形成能夠藉由例如真空蒸鍍法或濺鍍法等公知的手段來進行。更具體為例如要形成蕭特基電極時，進行由Mo構成的層與由Al構成的層的積層，對於由Mo構成的層及由Al構成的層能夠藉由進行運用了光微影術(photolithography)而成的圖案來進行。 The electrodes can be formed by known means such as vacuum evaporation or sputtering. More specifically, for example, when forming a Schottky electrode, a layer composed of Mo and a layer composed of Al are laminated. The layer composed of Mo and the layer composed of Al can be formed by using photolithography ( photolithography).

在作為絕緣體層104的材料方面可舉出例如GaO、AlGaO、InAlGaO、AlInZnGaO4、AlN、Hf2O3、SiN、SiON、Al2O3、MgO、GdO、SiO2或Si3N4等。絕緣體層104係設於n-型半導體層101a與蕭特基電極105a之間。絕緣體層的形成能夠藉由例如濺鍍法、真空蒸鍍法或CVD(化學氣相沉積)法或等公知的手段來進行。 Examples of the material of the insulator layer 104 include GaO, AlGaO, InAlGaO, AlInZnGaO 4 , AlN, Hf 2 O 3 , SiN, SiON, Al 2 O 3 , MgO, GdO, SiO 2 or Si 3 N 4 . The insulator layer 104 is provided between the n - type semiconductor layer 101a and the Schottky electrode 105a. The insulating layer can be formed by, for example, sputtering, vacuum evaporation, CVD (chemical vapor deposition), or other known means.

在圖3的SBD被施加反向偏壓的情形下，由於空乏層(未圖示)會擴展於n型半導體層101中，所以構成高耐壓的SBD。再者，被施加順向偏壓的情形下，電子會從歐姆電極105b往蕭特基電極105a流動。如此一來，使用有前述半導體構造的SBD在高耐壓及大電流用方面優異，切換速度也快速，在耐壓性及可靠度方面也優異，而且，在絕緣特性方面也優異，且具有較高的電流控制性。 When a reverse bias voltage is applied to the SBD in FIG. 3 , a depletion layer (not shown) expands in the n-type semiconductor layer 101 , thereby forming a high withstand voltage SBD. Furthermore, when a forward bias voltage is applied, electrons flow from the ohmic electrode 105b to the Schottky electrode 105a. As a result, the SBD using the aforementioned semiconductor structure is excellent in high withstand voltage and large current use, has a fast switching speed, is also excellent in withstand voltage and reliability, is also excellent in insulation characteristics, and has a relatively high High current controllability.

(JBS) (JBS)

圖4顯示本發明的適合的實施型態之一的接面位障蕭特基二極體(JBS)。圖4的半導體裝置具有n型半導體層101、n-型半導體層101a、n+型半導體層101b、p型半導體層102、蕭特基電極105a、歐姆電極105b及保護環(guard ring)106。含有n-型半導體層101a、設於前述n-型半導體層101a上且與n-型半導體層101a之間可形成蕭特基屏障的蕭特基電極105a、以及設於蕭特基電極105a與n-型半導體層101a之間且能夠在與n-型半導體層101a之間形成比蕭特基電極105a之蕭特基屏障的屏障高度(barrier height)更大屏障高度的蕭特基屏障的p型半導體層102。此外，p型半導體層102被埋設於n-型半導體層101a中。在本發明中，較佳為p型半導體層102係依一定間隔方式來設置，更佳為在前述蕭特基電極105a的兩端與n-型半導體層101a之間各自設有p型半導體層102。藉由上述各種較佳的型態，能夠以熱穩定性及密接性方面更優異，更減少漏電流，而且耐壓等半導體特性方面更優異的 方式構成JBS。 FIG. 4 shows a junction barrier Schottky diode (JBS) which is one of the suitable embodiments of the present invention. The semiconductor device of FIG. 4 includes an n-type semiconductor layer 101, an n - type semiconductor layer 101a, an n + -type semiconductor layer 101b, a p-type semiconductor layer 102, a Schottky electrode 105a, an ohmic electrode 105b, and a guard ring 106. It includes an n - type semiconductor layer 101a, a Schottky electrode 105a disposed on the n - type semiconductor layer 101a and capable of forming a Schottky barrier between the n - type semiconductor layer 101a, and a Schottky electrode 105a disposed between the Schottky electrode 105a and the n-type semiconductor layer 101a. p between the n -type semiconductor layer 101a and capable of forming a Schottky barrier with a barrier height greater than the barrier height of the Schottky barrier of the Schottky electrode 105a with the n -type semiconductor layer 101a type semiconductor layer 102. In addition, the p-type semiconductor layer 102 is buried in the n - type semiconductor layer 101a. In the present invention, it is preferable that the p-type semiconductor layers 102 are arranged at certain intervals, and it is more preferable that a p-type semiconductor layer is provided between both ends of the Schottky electrode 105a and the n - type semiconductor layer 101a. 102. With the above-mentioned various preferred forms, JBS can be constructed in a manner that is more excellent in terms of thermal stability and adhesion, reduces leakage current, and is more excellent in semiconductor characteristics such as withstand voltage.

(MESFET) (MESFET)

圖5顯示本發明的金屬半導體場效電晶體(MESFET)的一例。圖5的MESFET具有n-型半導體層111a、n+型半導體層111b、緩衝層(buffer layer)118、晶體基板119、半絕緣體層114、閘極電極115a、源極電極115b及汲極電極115c。 FIG. 5 shows an example of the metal semiconductor field effect transistor (MESFET) of the present invention. The MESFET of Figure 5 has an n - type semiconductor layer 111a, an n + type semiconductor layer 111b, a buffer layer 118, a crystal substrate 119, a semi-insulator layer 114, a gate electrode 115a, a source electrode 115b and a drain electrode 115c. .

閘極電極、源極電極及汲極電極的材料可為公知的電極材料，在作為前述電極材料方面可舉出例如Al、Mo、Co、Zr、Sn、Nb、Fe、Cr、Ta、Ti、Au、Pt、V、Mn、Ni、Cu、Hf、W、Ir、Zn、In、Pd、Nd或Ag等金屬或這些金屬的合金、氧化錫、氧化鋅、氧化銦、氧化銦錫(ITO)、氧化鋅銦(IZO)等金屬氧化物導電膜、聚苯胺、聚噻吩或聚吡咯等有機導電性化合物、或這些化合物的混合物等。閘極電極、源極電極及汲極電極的形成能夠藉由例如真空蒸鍍法或濺鍍法等公知的手段來進行。 The gate electrode, source electrode and drain electrode may be made of known electrode materials. Examples of the electrode materials include Al, Mo, Co, Zr, Sn, Nb, Fe, Cr, Ta, Ti, Metals such as Au, Pt, V, Mn, Ni, Cu, Hf, W, Ir, Zn, In, Pd, Nd or Ag or alloys of these metals, tin oxide, zinc oxide, indium oxide, indium tin oxide (ITO) , metal oxide conductive films such as indium zinc oxide (IZO), organic conductive compounds such as polyaniline, polythiophene or polypyrrole, or mixtures of these compounds. The gate electrode, source electrode and drain electrode can be formed by known means such as vacuum evaporation or sputtering.

半絕緣體層114只要是以半絕緣體所構成即可，在作為前述半絕緣體方面可舉出例如含有半絕緣體摻雜物者或未經摻雜處理者等。 The semi-insulating layer 114 only needs to be composed of a semi-insulating material. Examples of the semi-insulating material include those containing a semi-insulating dopant or those without a doping treatment.

圖5的MESFET由於在閘極電極下形成良好的空乏層，所以能夠有效地控制從汲極電極流到源極電極的電流。 Since the MESFET in Figure 5 forms a good depletion layer under the gate electrode, it can effectively control the current flowing from the drain electrode to the source electrode.

(HEMT) (HEMT)

圖6顯示本發明的高電子移動率電晶體(HEMT)的一例。圖6的HEMT具有能帶較寬的n型半導體層121a、能帶較窄的n型半導體層121b、n+型半導體層121c、電子通過層123、半絕緣體層124、閘極電極125a、源極電極125b、汲極電極125c、緩衝層128及晶體基板129。 FIG. 6 shows an example of the high electron mobility transistor (HEMT) of the present invention. The HEMT of FIG. 6 has an n-type semiconductor layer 121a with a wide energy band, an n-type semiconductor layer 121b with a narrow energy band, an n + -type semiconductor layer 121c, an electron passage layer 123, a semi-insulator layer 124, a gate electrode 125a, and a source. electrode 125b, drain electrode 125c, buffer layer 128 and crystal substrate 129.

閘極電極、源極電極及汲極電極的材料可以分別為公知的電極材 料，在作為前述電極材料方面可舉出例如Al、Mo、Co、Zr、Sn、Nb、Fe、Cr、Ta、Ti、Au、Pt、V、Mn、Ni、Cu、Hf、W、Ir、Zn、In、Pd、Nd或Ag等金屬或這些金屬的合金、氧化錫、氧化鋅、氧化銦、氧化銦錫(ITO)、氧化鋅銦(IZO)等金屬氧化物導電膜、聚苯胺、聚噻吩或聚吡咯等有機導電性化合物、或這些化合物的混合物等。閘極電極、源極電極及汲極電極的形成能夠藉由例如真空蒸鍍法或濺鍍法等公知的手段來進行。 The materials of the gate electrode, source electrode and drain electrode can respectively be well-known electrode materials. Examples of the aforementioned electrode materials include Al, Mo, Co, Zr, Sn, Nb, Fe, Cr, Ta, Ti, Au, Pt, V, Mn, Ni, Cu, Hf, W, Ir, Metals such as Zn, In, Pd, Nd or Ag or alloys of these metals, metal oxide conductive films such as tin oxide, zinc oxide, indium oxide, indium tin oxide (ITO), indium zinc oxide (IZO), polyaniline, poly Organic conductive compounds such as thiophene or polypyrrole, or mixtures of these compounds. The gate electrode, source electrode and drain electrode can be formed by known means such as vacuum evaporation or sputtering.

此外，閘極電極下的n型半導體層至少以能帶較寬的層121a與較窄的層121b所構成，半絕緣體層124只要是以半絕緣體構成即可，在作為前述半絕緣體方面可舉出例如含有半絕緣體摻雜物者或未經摻雜處理者等。形成在半絕緣體層124上的電子通過層123在例如以應用屬於氮化物半導體的GaN作為半導體時，能夠使用i(故意．無摻雜(intentionally．undoped))-GaN等。 In addition, the n-type semiconductor layer under the gate electrode is composed of at least a wider energy band layer 121a and a narrower layer 121b. The semi-insulator layer 124 only needs to be composed of a semi-insulator. Examples of the aforementioned semi-insulator include Examples include those containing semi-insulating dopants or those without doping treatment. The electron passage layer 123 formed on the semi-insulating layer 124 may use i (intentionally undoped)-GaN or the like when GaN, which is a nitride semiconductor, is used as the semiconductor.

圖6的HEMT由於在閘極電極下形成良好的空乏層，所以能夠有效地控制從汲極電極流到源極電極的電流。再者，在本發明中，進一步藉由設成凹槽構造而能夠顯現常閉型(normally-off)。 Since the HEMT in Figure 6 forms a good depletion layer under the gate electrode, it can effectively control the current flowing from the drain electrode to the source electrode. Furthermore, in the present invention, a normally-off type can be achieved by further forming a groove structure.

(MOSFET) (MOSFET)

圖7顯示本發明的半導體裝置為MOSFET時的一例。圖7顯示具有n-型半導體層131a、第一n+型半導體層131b、第二n+型半導體層131c、p型半導體層132、p+型半導體層132a、閘極絕緣膜134、閘極電極135a、源極電極135b及汲極電極135c的金屬氧化物半導體場效應電晶體(MOSFET)之適合的一例。此外，p+型半導體層132a可為p型半導體層，也可為與p型半導體層132相同。 FIG. 7 shows an example when the semiconductor device of the present invention is a MOSFET. 7 shows an n - type semiconductor layer 131a, a first n + type semiconductor layer 131 b, a second n + type semiconductor layer 131 c, a p type semiconductor layer 132, a p + type semiconductor layer 132 a, a gate insulating film 134, and a gate electrode. A suitable example of the electrode 135a, the source electrode 135b and the drain electrode 135c is a metal oxide semiconductor field effect transistor (MOSFET). In addition, the p + -type semiconductor layer 132 a may be a p-type semiconductor layer, or may be the same as the p-type semiconductor layer 132 .

在由前述導電性結晶膜構成的汲極電極135c上形成有例如厚度100nm至100μm的n+型半導體層131b，在前述n+型半導體層131b上形成例如厚度 100nm至100μm的n-型半導體層131a。 An n + -type semiconductor layer 131 b having a thickness of, for example, 100 nm to 100 μm is formed on the drain electrode 135 c made of the conductive crystal film, and an n − -type semiconductor layer having a thickness of, for example, 100 nm to 100 μm is formed on the n + -type semiconductor layer 131 b. 131a.

再者，在前述n-型半導體層131a及前述p型半導體層132內形成有達到前述n-型半導體層131a之中途為止之深度的複數個溝槽。在前述溝槽內藉由例如10nm至1μm厚度的閘極絕緣膜134而埋入並形成閘極電極135a。 Furthermore, a plurality of trenches are formed in the n - type semiconductor layer 131a and the p - type semiconductor layer 132 to a depth reaching the middle of the n-type semiconductor layer 131a. The gate electrode 135a is embedded and formed in the trench by a gate insulating film 134 having a thickness of, for example, 10 nm to 1 μm.

在圖7的MOSFET為導通(on)狀態下，當對前述源極電極135b與前述汲極電極135c之間施加電壓，而對前述閘極電極135a施予相對於前述源極電極135b為正的電壓時，就會在前述n-型半導體層131a的側表面形成通道層，電力會注入前述n-型半導體層而成為導通(turn-on)。在關斷(off)狀態下，藉由將前述閘極電極的電壓設成0V，無法形成通道層，形成以空乏層充滿n-型半導體層的狀態而成為關斷(turn-off)。 When the MOSFET in FIG. 7 is in the on state, when a voltage is applied between the source electrode 135b and the drain electrode 135c, a positive voltage is applied to the gate electrode 135a relative to the source electrode 135b. When the voltage is applied, a channel layer is formed on the side surface of the n - type semiconductor layer 131a, and power is injected into the n - type semiconductor layer to become turn-on. In the off state, by setting the voltage of the gate electrode to 0V, the channel layer cannot be formed, and the n - type semiconductor layer is filled with the depletion layer, thereby becoming turn-off.

圖7的MOSFET係在n-型半導體層131a、p型半導體層132及n+型半導體層131c的預定區域設蝕刻遮罩(etching mask)，將前述蝕刻遮罩設為遮罩，進而藉由反應性離子蝕刻法等進行異向性蝕刻(anisotropic etching)以形成從前述n+型半導體層131c表面達到前述n-型半導體層131a之中途為止之深度的溝槽。接著，使用熱氧化法、真空蒸鍍法、濺射法、CVD法等公知的手段在前述溝槽的側面及底面形成例如50nm至1μm厚度的閘極絕緣膜134之後，使用CVD法、真空蒸鍍法、濺射法將例如聚矽等閘極電極材料形成在前述溝槽達n-型半導體層的厚度以下。 The MOSFET of FIG. 7 is provided with an etching mask (etching mask) in predetermined areas of the n - type semiconductor layer 131 a, the p type semiconductor layer 132 and the n + type semiconductor layer 131 c. The aforementioned etching mask is used as a mask, and further by Anisotropic etching is performed using a reactive ion etching method or the like to form a trench with a depth extending from the surface of the n + -type semiconductor layer 131 c to the middle of the n − -type semiconductor layer 131 a. Next, a gate insulating film 134 having a thickness of, for example, 50 nm to 1 μm is formed on the side and bottom surfaces of the trenches using known means such as thermal oxidation method, vacuum evaporation method, sputtering method, CVD method, etc., and then using CVD method, vacuum evaporation method, etc. The gate electrode material, such as polysilicon, is formed in the trench by plating or sputtering methods up to the thickness of the n - type semiconductor layer.

接著，藉由使用真空蒸鍍法、濺射法、CVD法等公知的手段在n+型半導體層131c上形成源極電極135b而能夠製造功率金氧半場效電晶體(Power MOSFET)。此外，源極電極的電極材料可為公知的電極材料，在作為前述電極材料方面，可舉出例如Al、Mo、Co、Zr、Sn、Nb、Fe、Cr、Ta、Ti、Au、Pt、 V、Mn、Ni、Cu、Hf、W、Ir、Zn、In、Pd、Nd或Ag等金屬或這些金屬的合金、氧化錫、氧化鋅、氧化銦、氧化銦錫(ITO)、氧化鋅銦(IZO)等金屬氧化物導電膜、聚苯胺、聚噻吩或聚吡咯等有機導電性化合物、或這些化合物的混合物等。 Next, a power metal oxide semi-field effect transistor (Power MOSFET) can be manufactured by forming the source electrode 135b on the n + -type semiconductor layer 131c using known means such as vacuum evaporation, sputtering, and CVD. In addition, the electrode material of the source electrode may be a known electrode material. Examples of the electrode material include Al, Mo, Co, Zr, Sn, Nb, Fe, Cr, Ta, Ti, Au, Pt, Metals such as V, Mn, Ni, Cu, Hf, W, Ir, Zn, In, Pd, Nd or Ag or alloys of these metals, tin oxide, zinc oxide, indium oxide, indium tin oxide (ITO), zinc indium oxide Metal oxide conductive films such as (IZO), organic conductive compounds such as polyaniline, polythiophene or polypyrrole, or mixtures of these compounds, etc.

與以往的溝槽型MOSFET比較，以上述方式所獲得的MOSFET係在耐壓性方面更優異者。此外，圖7係顯示溝槽型的立式MOSFET的例子，然而在本發明中不限定於此方式，能夠適用於各種MOSFET的型態。例如，也可將圖7的溝槽的深度下挖達到n-型半導體層131a之底面為止的深度以降低串聯電阻(series resistance)。 Compared with conventional trench-type MOSFETs, the MOSFET obtained in the above manner has superior voltage resistance. In addition, FIG. 7 shows an example of a trench-type vertical MOSFET. However, the present invention is not limited to this form and can be applied to various types of MOSFETs. For example, the depth of the trench in FIG. 7 may be dug down to the depth of the bottom surface of the n - type semiconductor layer 131a to reduce series resistance.

(SIT) (SIT)

圖8顯示本發明的半導體裝置為SIT時的一例。圖8的SIT具有n-型半導體層141a、n+型半導體層141b及141c、閘極電極145a、源極電極145b及汲極電極145c。 FIG. 8 shows an example when the semiconductor device of the present invention is a SIT. The SIT of FIG. 8 has an n − -type semiconductor layer 141 a, n + -type semiconductor layers 141 b and 141 c, a gate electrode 145 a, a source electrode 145 b, and a drain electrode 145 c.

在由導電性結晶膜構成的汲極電極145c上形成有例如厚度100nm至100μm的n+型半導體層141b，在前述n+型半導體層141b上形成有例如厚度100nm至100μm的n-型半導體層141a。再者，在前述n-型半導體層141a上形成有n+型半導體層141c，在前述n+型半導體層141c上形成有源極電極145b。 An n + -type semiconductor layer 141 b having a thickness of, for example, 100 nm to 100 μm is formed on the drain electrode 145 c made of a conductive crystal film, and an n − -type semiconductor layer having a thickness of, for example, 100 nm to 100 μm is formed on the n + -type semiconductor layer 141 b. 141a. Furthermore, an n + -type semiconductor layer 141 c is formed on the n − -type semiconductor layer 141 a, and a source electrode 145 b is formed on the n + -type semiconductor layer 141 c.

再者，在前述n-型半導體層141a內形成有貫穿前述n+型半導體層141c且達到n-型半導體層141a之中途的深度為止之深度的複數個溝槽。在前述溝槽內的n-型半導體層上形成有閘極電極145a。 Furthermore, a plurality of trenches penetrating the n + -type semiconductor layer 141 c and reaching a depth halfway through the n - -type semiconductor layer 141 a are formed in the n - -type semiconductor layer 141 a. A gate electrode 145a is formed on the n - type semiconductor layer in the trench.

在圖8的SIT為導通狀態下，當對前述源極電極145b與前述汲極電極145c之間施加電壓，而對前述閘極電極145a施予相對於前述源極電極145b為正的電壓時，就會在前述n-型半導體層141a內形成通道層，電力會注入前述n-型半導體層而成為導通(turn-on)。在關斷(off)狀態下，藉由將前述閘極電極的電壓設成0V， 變得無法形成通道層，形成以空乏層充滿n-型半導體層的狀態而成為關斷(turn-off)。 When the SIT in FIG. 8 is in the on state, when a voltage is applied between the source electrode 145b and the drain electrode 145c, and a positive voltage is applied to the gate electrode 145a with respect to the source electrode 145b, A channel layer will be formed in the n - type semiconductor layer 141a, and power will be injected into the n - type semiconductor layer to become turn-on. In the off state, by setting the voltage of the gate electrode to 0V, the channel layer cannot be formed, and the n - type semiconductor layer is filled with the depletion layer, thereby becoming turn-off. .

在圖8所示的SIT的製造上能夠使用公知的手段。例如，與上述的MOSFET的製造步驟同樣地在n-型半導體層141a及n+型半導體層141c的預定區域設蝕刻遮罩，將前述蝕刻遮罩設為遮罩，藉由反應性離子蝕刻法等進行異向性蝕刻以形成從前述n+型半導體層141c表面達到前述n-型半導體層之中途為止之深度的溝槽。接著，使用CVD法、真空蒸鍍法、濺射法等將例如聚矽等閘極電極材料在前述溝槽形成n-型半導體層的厚度以下。然後，藉由使用真空蒸鍍法、濺射法、CVD法等公知的手段分別在n+型半導體層141c上形成源極電極145b，在n+型半導體層141b上形成汲極電極145c，能夠製造圖8所示的SIT。 Well-known means can be used for manufacturing the SIT shown in FIG. 8 . For example, in the same manner as the above-mentioned MOSFET manufacturing steps, an etching mask is provided in a predetermined area of the n - type semiconductor layer 141 a and the n + type semiconductor layer 141 c, and the etching mask is used as a mask, and the reactive ion etching method is used. Anisotropic etching is performed to form a trench with a depth ranging from the surface of the n + -type semiconductor layer 141 c to the middle of the n − -type semiconductor layer. Next, a gate electrode material such as polysilicon is formed in the trench by using a CVD method, a vacuum evaporation method, a sputtering method, or the like to have a thickness equal to or less than the thickness of the n - type semiconductor layer. Then, the source electrode 145b is formed on the n + -type semiconductor layer 141 c and the drain electrode 145 c is formed on the n + -type semiconductor layer 141 b using known means such as vacuum evaporation, sputtering, and CVD. The SIT shown in Figure 8 was manufactured.

此外，源極電極的電極材料可為公知的電極材料，在作為前述電極材料方面，可舉出例如Al、Mo、Co、Zr、Sn、Nb、Fe、Cr、Ta、Ti、Au、Pt、V、Mn、Ni、Cu、Hf、W、Ir、Zn、In、Pd、Nd或Ag等金屬或這些金屬的合金、氧化錫、氧化鋅、氧化銦、氧化銦錫(ITO)、氧化鋅銦(IZO)等金屬氧化物導電膜、聚苯胺、聚噻吩或聚吡咯等有機導電性化合物、或這些化合物的混合物等。 In addition, the electrode material of the source electrode may be a known electrode material. Examples of the electrode material include Al, Mo, Co, Zr, Sn, Nb, Fe, Cr, Ta, Ti, Au, Pt, Metals such as V, Mn, Ni, Cu, Hf, W, Ir, Zn, In, Pd, Nd or Ag or alloys of these metals, tin oxide, zinc oxide, indium oxide, indium tin oxide (ITO), zinc indium oxide Metal oxide conductive films such as (IZO), organic conductive compounds such as polyaniline, polythiophene or polypyrrole, or mixtures of these compounds, etc.

圖9顯示具有n-型半導體層141a、第一n+型半導體層141b、第二n+型半導體層141c、p型半導體層142、閘極電極145a、源極電極145b及汲極電極145c的接面場效電晶體(JFET)之適合的一例。 FIG. 9 shows a semiconductor device having an n − -type semiconductor layer 141 a, a first n + -type semiconductor layer 141 b, a second n + -type semiconductor layer 141 c, a p-type semiconductor layer 142 , a gate electrode 145 a, a source electrode 145 b and a drain electrode 145 c. A suitable example is junction field effect transistor (JFET).

圖10顯示具有n型半導體層151、n-型半導體層151a、n+型半導體層151b、p型半導體層152、閘極絕緣膜154、閘極電極155a、射極電極155b及集極電極155c的絕緣閘雙極電晶體(IGBT)之適合的一例。 FIG. 10 shows an n-type semiconductor layer 151, an n - type semiconductor layer 151a, an n + -type semiconductor layer 151b, a p-type semiconductor layer 152, a gate insulating film 154, a gate electrode 155a, an emitter electrode 155b and a collector electrode 155c. A suitable example is the insulated gate bipolar transistor (IGBT).

(LED) (LED)

圖11顯示本發明之半導體裝置為發光二極體(LED)時的一例。圖11的半導體發光元件係在第二電極165b上具有n型半導體層161，在n型半導體層161積層有發光層163。然後，在發光層163上積層有p型半導體層162。在p型半導體層162上具有可供發光層163產生的光透過的透光性電極167，在透光性電極167上積層有第一電極165a。此外，圖11的半導體發光元件也可以為在除了電極部分以外處以保護層覆蓋。 FIG. 11 shows an example when the semiconductor device of the present invention is a light emitting diode (LED). The semiconductor light-emitting element of FIG. 11 has an n-type semiconductor layer 161 on the second electrode 165b, and a light-emitting layer 163 is laminated on the n-type semiconductor layer 161. Then, the p-type semiconductor layer 162 is laminated on the light-emitting layer 163 . The p-type semiconductor layer 162 is provided with a translucent electrode 167 through which light generated by the light-emitting layer 163 can pass, and a first electrode 165a is laminated on the translucent electrode 167 . In addition, the semiconductor light-emitting element of FIG. 11 may be covered with a protective layer except for the electrode portion.

在作為透光性電極的材料方面可舉出含有銦(In)或鈦(Ti)的氧化物的導電性材料等。更具體而言，可舉出例如In2O3、ZnO、SnO2、Ga2O3、TiO2、CeO2或這些氧化物的兩種以上的混晶或摻雜於這些氧化物後者等。藉由濺鍍等公知的手段設有這些材料而能夠形成透光性電極。再者，也可於形成透光性電極之後進行以透光性電極之透明化為目的的熱退火(thermal annealing)。 Examples of materials for the translucent electrode include conductive materials containing oxides of indium (In) or titanium (Ti). More specifically, examples thereof include In 2 O 3 , ZnO, SnO 2 , Ga 2 O 3 , TiO 2 , CeO 2 , mixed crystals of two or more of these oxides, or the latter doped with these oxides. These materials can be provided by known means such as sputtering to form a translucent electrode. Furthermore, thermal annealing (thermal annealing) for the purpose of making the translucent electrode transparent may be performed after forming the translucent electrode.

依據圖11的半導體發光元件，將第一電極165a設為正極，將第二電極165b設為負極，藉由此兩者而對p型半導體層162、發光層163及n型半導體層161流通電極以使發光層163發光。 According to the semiconductor light-emitting element of FIG. 11 , the first electrode 165 a is set as the positive electrode, and the second electrode 165 b is set as the negative electrode. Through these two electrodes, the p-type semiconductor layer 162 , the light-emitting layer 163 and the n-type semiconductor layer 161 are connected. So that the light-emitting layer 163 emits light.

在作為第一電極165a的材料方面，可舉出例如Al、Mo、Co、Zr、Sn、Nb、Fe、Cr、Ta、Ti、Au、Pt、V、Mn、Ni、Cu、Hf、W、Ir、Zn、In、Pd、Nd或Ag等金屬或這些金屬的合金、氧化錫、氧化鋅、氧化銦、氧化銦錫(ITO)、氧化鋅銦(IZO)等金屬氧化物導電膜、聚苯胺、聚噻吩或聚吡咯等有機導電性化合物、或這些化合物的混合物等。電極的形成法不特別地限定，能夠依照考量與前述材料的相容性而從印刷方法、噴塗法、塗佈法等濕式方法、真空蒸鍍法、濺射法、離子鍍法等物理方法、CVD、電漿CVD法等化學方法等之中經適切地選擇的方法來形成。 Examples of the material of the first electrode 165a include Al, Mo, Co, Zr, Sn, Nb, Fe, Cr, Ta, Ti, Au, Pt, V, Mn, Ni, Cu, Hf, W, Metals such as Ir, Zn, In, Pd, Nd or Ag or alloys of these metals, metal oxide conductive films such as tin oxide, zinc oxide, indium oxide, indium tin oxide (ITO), zinc indium oxide (IZO), etc., polyaniline , organic conductive compounds such as polythiophene or polypyrrole, or mixtures of these compounds. The formation method of the electrode is not particularly limited, and can be selected from printing methods, wet methods such as spraying methods and coating methods, and physical methods such as vacuum evaporation methods, sputtering methods, and ion plating methods, taking into account compatibility with the aforementioned materials. , CVD, plasma CVD and other chemical methods, etc., are formed by an appropriately selected method.

本發明的半導體裝置不僅以上記述的事項，可以更使用公知的手段適合地使用作為功率模塊、反向器(inverter；也稱為「逆變器」)或轉換器(converter)等半導體裝置，而且，作為半導體裝置可適用於使用例如電源裝置的半導體系統。此外，前述電源裝置能夠以使用公知的手段而將前述半導體裝置連接於配線圖案等的方式來製作。圖12顯示電源系統的例子。圖12係使用複數個前述電源裝置與控制電路以構成電源系統。前述電源系統如圖13所示，能夠與電子電路組合以使用於系統裝置。此外，圖14顯示電源裝置的電源電路圖的一例。圖14顯示由功率電路與控制電路構成的電源裝置的電源電路，藉由反向器(以MOSFETA至D構成)以高頻將DC電壓轉換至AC後，以變壓器實施絕緣及變壓，以整流MOSFET(A至B’)整流後，以DCL(平滑用線圈L1,L2)與電容器進行平滑而輸出直流電壓。此時以電壓比較器將輸出電壓與基準電壓比較，以使成為所希望的輸出電壓的方式利用PWM(脈波寬度調變)控制電路來控制反向器及整流MOSFET。 In addition to the matters described above, the semiconductor device of the present invention can be suitably used as a semiconductor device such as a power module, an inverter (also called "inverter"), or a converter using known means. , as a semiconductor device, it is applicable to a semiconductor system using, for example, a power supply device. In addition, the power supply device can be manufactured by connecting the semiconductor device to a wiring pattern or the like using known means. Figure 12 shows an example of a power supply system. Figure 12 shows a power supply system using a plurality of the aforementioned power supply devices and control circuits. The aforementioned power supply system, as shown in FIG. 13 , can be combined with an electronic circuit and used in a system device. In addition, FIG. 14 shows an example of a power supply circuit diagram of the power supply device. Figure 14 shows the power circuit of a power supply device composed of a power circuit and a control circuit. After converting DC voltage to AC at high frequency through an inverter (composed of MOSFETA to D), a transformer is used to insulate and transform the voltage for rectification. After MOSFET (A to B') is rectified, it is smoothed by DCL (smoothing coils L1, L2) and a capacitor to output a DC voltage. At this time, a voltage comparator compares the output voltage with a reference voltage, and a PWM (Pulse Width Modulation) control circuit is used to control the inverter and rectifier MOSFET so that the output voltage becomes a desired output voltage.

[實施例] [Example]

(實施例1) (Example 1)

以RIE(反應離子蝕刻)處理Si基板(100)的晶體成長面側，使用氮且利用蒸鍍法使蒸鍍源的金屬(Hf、Zr)與氮熱反應，以於Si基板上形成由結晶性氮化物構成的結晶膜。可得知藉由XPS(X射線光電子能譜儀)所獲得的結晶膜含有各自具有立方晶體構造的HfN、ZrN。再者，藉由四端子法(四端點測量技術)針對所獲得的結晶膜進行調查瞭解之下，係具有良好的導電性。接著，藉由濺鍍法在結晶膜上形成GaN膜作為半導體膜。藉由XPS可得知所獲得的半導體膜為c-GaN單結晶膜。再者，利用剖面STEM(掃描穿透式電子顯微鏡)像觀察界面時，可得知朝向晶體 成長方向變形，形成相互相鄰的頂點及底點所形成的角各自不同的山谷構造，緩衝層在半導體膜形成時顯現良好的應力緩和性。此外，利用X射線結晶晶格像觀察所獲得的半導體膜時，即為無缺陷之大面積的半導體膜，可得知本發明之積層構造體的結晶性良好。 The crystal growth surface side of the Si substrate (100) is treated with RIE (reactive ion etching), using nitrogen and using an evaporation method to thermally react the metal (Hf, Zr) of the evaporation source with the nitrogen to form a crystal on the Si substrate. A crystalline film composed of nitrides. It is found that the crystal film obtained by XPS (X-ray photoelectron spectroscopy) contains HfN and ZrN each having a cubic crystal structure. Furthermore, the obtained crystal film was investigated by the four-terminal method (four-terminal measurement technology) and found to have good conductivity. Next, a GaN film is formed as a semiconductor film on the crystal film by a sputtering method. From XPS, it was found that the obtained semiconductor film was a c-GaN single crystal film. Furthermore, when the interface is observed using cross-sectional STEM (Scanning Transmission Electron Microscope) images, it can be seen that the orientation of the crystal The growth direction is deformed to form a valley structure in which the angles formed by adjacent peaks and bottoms are different, and the buffer layer exhibits good stress relaxation properties when the semiconductor film is formed. In addition, when the obtained semiconductor film was observed using an X-ray crystal lattice image, it was found to be a large-area semiconductor film without defects, indicating that the laminated structure of the present invention has good crystallinity.

圖15顯示在實施例1使用的蒸鍍成膜裝置。圖15的蒸鍍成膜裝置於坩堝至少具有金屬源1101a至1101b、接地1102a至1102h、ICP(感應耦合式電漿)電極1103a至1103b、截止濾波器(cut filter)1104a至1104b、DC電源1105a至1105b、RF電源1106a至1106b、燈1107a至1107b、Ar源1108、反應性氣體源1109、電源1110、基板保持器1111、基板1112、截止濾波器1113、ICP環1114、真空槽1115及旋轉軸1116。此外，圖15的ICP電極1103a至1103b具有朝基板1112之中心側彎曲而成的大致凹面形狀或拋物線形狀。 FIG. 15 shows the vapor deposition film forming apparatus used in Example 1. The vapor deposition film forming apparatus of FIG. 15 has at least metal sources 1101a to 1101b, grounds 1102a to 1102h, ICP (inductively coupled plasma) electrodes 1103a to 1103b, cut filters 1104a to 1104b, and DC power supply 1105a in the crucible. to 1105b, RF power supplies 1106a to 1106b, lamps 1107a to 1107b, Ar source 1108, reactive gas source 1109, power supply 1110, substrate holder 1111, substrate 1112, cutoff filter 1113, ICP ring 1114, vacuum chamber 1115 and rotation shaft 1116. In addition, the ICP electrodes 1103a to 1103b in FIG. 15 have a substantially concave shape or a parabolic shape that is bent toward the center side of the substrate 1112.

如圖15所示，將基板1112卡止於基板保持器1111上，接著，使用電源1110與旋轉機構(未圖示)使旋轉軸1116旋轉以使基板1112旋轉，再者，藉由燈1107a至1107b將基板1112加熱，藉由真空泵(未圖示)將真空槽1115內予以排氣而設成真空或減壓下。其後，從Ar源1108將Ar氣體導入真空槽1115內，利用DC電源1105a至1105b、RF電源1106a至1106b、ICP電極1103a至1103b、截止濾波器1104a至1104b及接地1102a至1102h於基板1112上形成氬電漿，藉此，進行基板1112之表面的潔淨化。 As shown in FIG. 15 , the substrate 1112 is locked on the substrate holder 1111 , and then the power supply 1110 and the rotating mechanism (not shown) are used to rotate the rotating shaft 1116 to rotate the substrate 1112 , and further, the lamp 1107 a is used to rotate the rotating shaft 1116 . 1107b. The substrate 1112 is heated, and the vacuum chamber 1115 is evacuated by a vacuum pump (not shown) to bring it to a vacuum or reduced pressure. Thereafter, Ar gas is introduced into the vacuum chamber 1115 from the Ar source 1108, and is placed on the substrate 1112 using DC power supplies 1105a to 1105b, RF power supplies 1106a to 1106b, ICP electrodes 1103a to 1103b, cutoff filters 1104a to 1104b and grounds 1102a to 1102h. Argon plasma is formed, whereby the surface of the substrate 1112 is cleaned.

將Ar氣體導入真空槽1115內之同時並且利用反應性氣體源1109導入反應性氣體。此時，藉由反覆進行屬於加熱燈(lamp heater)的燈1107a至1107b的開(on)及關(off)，構成能夠形成更良質的晶體成長膜。 Ar gas is introduced into the vacuum chamber 1115 and at the same time, the reactive gas is introduced using the reactive gas source 1109 . At this time, by repeatedly turning on and off the lamps 1107a to 1107b belonging to the lamp heater, a crystal growth film of higher quality can be formed.

[產業利用性] [Industrial Applicability]

本發明的積層構造體能夠使用於半導體(例如化學半導體電子裝置等)、電子零件暨電性設備零件、光學暨電子照相關聯裝置、工業構件等所有的領域，惟更適合使用於半導體裝置。 The laminated structure of the present invention can be used in all fields such as semiconductors (such as chemical semiconductor electronic devices, etc.), electronic parts and electrical equipment parts, optical and electrophotographic related devices, industrial components, etc., but is more suitable for use in semiconductor devices.

1:磊晶膜(化合物半導體) 1: Epitaxial film (compound semiconductor)

5:氧化膜 5:Oxide film

9:晶體基板 9: Crystal substrate

Claims (15)

一種積層構造體，係直接或隔著其他層而在緩衝層上積層有由化合物半導體構成的磊晶膜者，前述緩衝層係包含導電性結晶膜，而該導電性結晶膜係含有Hf及/或Zr的氮化物或氮氧化物。 A laminated structure in which an epitaxial film composed of a compound semiconductor is laminated on a buffer layer directly or through other layers, the buffer layer includes a conductive crystal film, and the conductive crystal film contains Hf and/or Or Zr nitrides or nitrogen oxides. 如請求項1所述之積層構造體，其中，前述導電性結晶膜係含有HfN。 The laminated structure according to claim 1, wherein the conductive crystal film contains HfN. 如請求項1或2所述之積層構造體，其中，前述磊晶膜係具有立方晶體構造。 The laminated structure according to claim 1 or 2, wherein the epitaxial film has a cubic crystal structure. 如請求項1至3中任一項所述之積層構造體，其中，前述化合物半導體係為寬能隙半導體。 The laminated structure according to any one of claims 1 to 3, wherein the compound semiconductor is a wide bandgap semiconductor. 如請求項1至4中任一項所述之積層構造體，其中，前述化合物半導體係為氮化物半導體。 The laminated structure according to any one of claims 1 to 4, wherein the compound semiconductor is a nitride semiconductor. 如請求項1至5中任一項所述之積層構造體，其中，前述緩衝層係直接或隔著其他層而積層在半導體單晶體基板上。 The laminated structure according to any one of claims 1 to 5, wherein the buffer layer is laminated on the semiconductor single crystal substrate directly or through other layers. 如請求項6所述之積層構造體，其中，前述緩衝層係藉由晶體成長而積層在前述半導體單晶體基板上。 The laminated structure according to claim 6, wherein the buffer layer is laminated on the semiconductor single crystal substrate by crystal growth. 如請求項6或7所述之積層構造體，其中，前述半導體單晶體基板係為Si基板。 The laminated structure according to claim 6 or 7, wherein the semiconductor single crystal substrate is a Si substrate. 一種半導體裝置，係包含積層構造體者，且前述積層構造體係為如請求項1至8中任一項所述的積層構造體。 A semiconductor device including a laminated structure, wherein the laminated structure system is the laminated structure according to any one of claims 1 to 8. 如請求項9所述之半導體裝置，其中，前述半導體裝置係立式裝置。 The semiconductor device according to claim 9, wherein the semiconductor device is a vertical device. 如請求項9或10所述之半導體裝置，其中，前述半導體裝置係蕭特基屏障二極體(SBD)、接面位障蕭特基二極體(JBS)、合併式PiN蕭特基二極體(MPS)、金屬半導體場效電晶體(MESFET)、高電子移動率電晶體(HEMT)、金屬氧化物半導體場效應電晶體(MOSFET)、靜電感應電晶體(SIT)、接面場效電晶體(JFET)、絕緣閘雙極電晶體(IGBT)、發光二極體(LED)或其等的組合。 The semiconductor device according to claim 9 or 10, wherein the aforementioned semiconductor device is a Schottky barrier diode (SBD), a junction barrier Schottky diode (JBS), or a combined PiN Schottky diode. Polar body (MPS), metal semiconductor field effect transistor (MESFET), high electron mobility transistor (HEMT), metal oxide semiconductor field effect transistor (MOSFET), electrostatic induction transistor (SIT), junction field effect transistor Crystal (JFET), Insulated Gate Bipolar Transistor (IGBT), Light Emitting Diode (LED) or a combination thereof. 一種積層構造體的製造方法，係在半導體晶體基板上積層緩衝層，且直接或隔著其他層而在前述緩衝層上積層有由化合物半導體構成的磊晶膜者，前述緩衝層係包含導電性結晶膜，而該導電性結晶膜係含有Hf及/或Zr的氮化物或氮氧化物。 A method of manufacturing a laminated structure in which a buffer layer is laminated on a semiconductor crystal substrate, and an epitaxial film composed of a compound semiconductor is laminated on the buffer layer directly or through other layers, and the buffer layer contains a conductive A crystalline film, and the conductive crystalline film contains nitrides or oxynitrides of Hf and/or Zr. 如請求項12所述之積層構造體的製造方法，前述半導體單晶體基板係為Si基板，前述化合物半導體係為氮化物半導體。 The method of manufacturing a laminated structure according to claim 12, wherein the semiconductor single crystal substrate is a Si substrate, and the compound semiconductor is a nitride semiconductor. 一種半導體裝置的製造方法，係使用積層構造體者，前述積層構造體係為如請求項1至8中任一項所述的積層構造體。 A method of manufacturing a semiconductor device using a laminated structure, and the laminated structure system is the laminated structure according to any one of claims 1 to 8. 一種系統，係包含半導體裝置者，前述半導體裝置係為如請求項9至11中任一項所述的半導體裝置。 A system including a semiconductor device, the semiconductor device being the semiconductor device according to any one of claims 9 to 11.
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