TW202334468A - Field effect transistor, method for producing same, and sputtering target for production of field effect transistor - Google Patents
Field effect transistor, method for producing same, and sputtering target for production of field effect transistor Download PDFInfo
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- effect transistor
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Classifications
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- C—CHEMISTRY; METALLURGY
- C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
- C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
- C23C14/00—Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material
- C23C14/06—Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material characterised by the coating material
- C23C14/08—Oxides
-
- C—CHEMISTRY; METALLURGY
- C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
- C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
- C23C14/00—Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material
- C23C14/22—Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material characterised by the process of coating
- C23C14/34—Sputtering
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/20—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy
- H01L21/2003—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy characterised by the substrate
- H01L21/2015—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy characterised by the substrate the substrate being of crystalline semiconductor material, e.g. lattice adaptation, heteroepitaxy
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
Abstract
Description
本發明係關於一種場效電晶體及其製造方法。又，本發明係關於一種場效電晶體製造用濺鍍靶材。The invention relates to a field effect transistor and a manufacturing method thereof. Furthermore, the present invention relates to a sputtering target for field effect transistor manufacturing.
於平板顯示器(以下亦稱為「FPD」)所使用之薄膜電晶體(以下亦稱為「TFT」)之技術領域中，隨著FPD高功能化，In-Ga-Zn複合氧化物(以下亦稱為「IGZO」)所代表之氧化物半導體代替先前之非晶矽逐漸受到關注，並逐漸實用化。IGZO具有表現出較高之場效遷移率及較低之漏電流之優點。近年來，隨著FPD進一步高功能化，提出一種表現出較IGZO所表現出之場效遷移率更高之場效遷移率之材料。In the technical field of thin film transistors (hereinafter also referred to as "TFT") used in flat panel displays (hereinafter also referred to as "FPD"), as FPDs become more functional, In-Ga-Zn composite oxides (hereinafter also referred to as Oxide semiconductors represented by "IGZO" (called "IGZO") have gradually attracted attention and become practical instead of the previous amorphous silicon. IGZO has the advantages of exhibiting higher field effect mobility and lower leakage current. In recent years, as FPDs have become more highly functional, a material has been proposed that exhibits a higher field effect mobility than that exhibited by IGZO.
作為FPD之一種之可撓性顯示器因具有較薄、較輕、較柔軟等功能而可廣泛地開展應用，因此近年來受到關注。尤其是顯示元件使用有機EL(Electroluminescence，電致發光)之可撓性有機EL顯示器(OLED)由於無需背光裝置，故原理上適合用作可撓性顯示器。As a type of FPD, flexible displays have attracted attention in recent years because they are thinner, lighter, and softer and can be widely used. In particular, flexible organic EL displays (OLEDs) that use organic EL (Electroluminescence) as display elements do not require a backlight device, so they are in principle suitable for use as flexible displays.
作為構成可撓性顯示器之重要構件之一，可例舉具有柔軟性之基材。作為可撓性顯示器所使用之基材，聚對苯二甲酸乙二酯及聚萘二甲酸乙二酯等塑膠膜較薄且輕量，並且柔軟性優異，故較為適合。然而，塑膠膜於耐熱性方面存在問題。為了於基材上形成TFT，於成膜後需要進行後退火處理以改善電特性，但於使用塑膠膜之類的耐熱性較低之基材之情形時，必須於低溫下進行後退火處理。然而，若於低溫下對包含IGZO之膜進行後退火處理，則該膜會發生低電阻化，從而難以作為半導體發揮功能。因此，於專利文獻1中，提出一種於IGZO系氧化物半導體薄膜之製造中不會因低溫下之後退火處理而發生低電阻化之技術。 先前技術文獻 專利文獻 One of the important components constituting a flexible display is a flexible base material. As substrates for flexible displays, plastic films such as polyethylene terephthalate and polyethylene naphthalate are suitable because they are thin, lightweight, and have excellent flexibility. However, plastic films have problems with heat resistance. In order to form a TFT on a substrate, post-annealing treatment is required after film formation to improve the electrical characteristics. However, when a substrate with low heat resistance such as a plastic film is used, post-annealing treatment must be performed at a low temperature. However, if a film containing IGZO is post-annealed at a low temperature, the resistance of the film becomes low, making it difficult to function as a semiconductor. Therefore, Patent Document 1 proposes a technology that does not cause low resistance due to subsequent annealing at low temperatures during the production of an IGZO-based oxide semiconductor thin film. Prior technical literature patent documents
專利文獻1：日本專利特開2012-049209號Patent document 1: Japanese Patent Application No. 2012-049209
根據專利文獻1所記載之技術，即便在低溫下進行後退火處理亦防止IGZO系薄膜發生低電阻化，但後退火處理後之薄膜因其場效遷移率較低，故不足以將該薄膜用作用以驅動上述OLED之半導體。 因此，本發明之課題在於提供一種可消除上述先前技術所具有之各種缺點之場效電晶體及其製造方法。 According to the technology described in Patent Document 1, even if the post-annealing treatment is performed at low temperature, the IGZO-based thin film is prevented from becoming low in resistance. However, the field-effect mobility of the film after the post-annealing treatment is low, so it is not sufficient for use in this film. Semiconductor used to drive the above-mentioned OLED. Therefore, the object of the present invention is to provide a field effect transistor and a manufacturing method thereof that can eliminate various shortcomings of the above-mentioned prior art.
本發明提供一種場效電晶體，其具備具有250℃以下之玻璃轉移溫度之基材或可撓性配線板所使用之基材、及設置於該基材上之氧化物半導體層，且 上述氧化物半導體層含有包含銦(In)元素、鋅(Zn)元素及添加元素(X)之氧化物， 添加元素(X)為選自鉭(Ta)元素、鍶(Sr)元素及鈮(Nb)元素中之至少1種元素， 各元素之原子比同時滿足式(1)至(3)(式中之X設為上述添加元素之含有比之總和)。 0.4≦(In＋X)/(In＋Zn＋X)≦0.8 (1) 0.2≦Zn/(In＋Zn＋X)≦0.6 (2) 0.001≦X/(In＋Zn＋X)≦0.015 (3) The present invention provides a field effect transistor, which includes a base material having a glass transition temperature of 250° C. or lower or a base material used for a flexible wiring board, and an oxide semiconductor layer provided on the base material, and The above-mentioned oxide semiconductor layer contains an oxide including indium (In) element, zinc (Zn) element and additional element (X), The additional element (X) is at least one element selected from the group consisting of tantalum (Ta) element, strontium (Sr) element and niobium (Nb) element, The atomic ratio of each element satisfies formulas (1) to (3) at the same time (X in the formula is set to the sum of the content ratios of the above-mentioned added elements). 0.4≦(In＋X)/(In＋Zn＋X)≦0.8 (1) 0.2≦Zn/(In＋Zn＋X)≦0.6 (2) 0.001≦X/(In＋Zn＋X)≦0.015 (3)
又，本發明提供一種場效電晶體之製造方法，其具有如下步驟：使用含有包含銦(In)元素、鋅(Zn)元素及添加元素(X)之氧化物之濺鍍靶材(添加元素(X)為選自鉭(Ta)元素、鍶(Sr)元素及鈮(Nb)元素中之至少1種元素)，於氧濃度為21 vol%以上49 vol%以下之環境下，對可撓性配線板所使用之基材或具有250℃以下之玻璃轉移溫度之基材進行濺鍍，形成源自上述靶材之氧化物半導體，且 於50℃以上250℃以下之溫度下對上述氧化物半導體進行退火處理。 Furthermore, the present invention provides a method for manufacturing a field effect transistor, which has the following steps: using a sputtering target containing an oxide containing an indium (In) element, a zinc (Zn) element, and an additional element (X) (the additional element (X) is at least one element selected from the group consisting of tantalum (Ta) element, strontium (Sr) element and niobium (Nb) element), in an environment with an oxygen concentration of 21 vol% or more and 49 vol% or less, for flexible The base material used for the flexible wiring board or the base material having a glass transition temperature below 250°C is sputtered to form an oxide semiconductor derived from the above target material, and The above-mentioned oxide semiconductor is annealed at a temperature of not less than 50°C and not more than 250°C.
進而，本發明提供一種場效電晶體之製造用濺鍍靶材，其係如下濺鍍靶材：含有包含銦(In)元素、鋅(Zn)元素及添加元素(X)之氧化物， 添加元素(X)為選自鉭(Ta)元素、鍶(Sr)元素及鈮(Nb)元素中之至少1種元素， 各元素之原子比同時滿足式(1)至(3)；且 該場效電晶體具備氧化物半導體層，該氧化物半導體層設置於可撓性配線板所使用之基材或具有250℃以下之玻璃轉移溫度之基材上且源自上述濺鍍靶材。 0.4≦(In＋X)/(In＋Zn＋X)≦0.8 (1) 0.2≦Zn/(In＋Zn＋X)≦0.6 (2) 0.001≦X/(In＋Zn＋X)≦0.015 (3) Furthermore, the present invention provides a sputtering target for manufacturing field effect transistors, which is a sputtering target containing an oxide including indium (In) element, zinc (Zn) element and additional element (X), The additional element (X) is at least one element selected from the group consisting of tantalum (Ta) element, strontium (Sr) element and niobium (Nb) element, The atomic ratio of each element satisfies formulas (1) to (3) at the same time; and This field effect transistor has an oxide semiconductor layer, and the oxide semiconductor layer is provided on a base material used for a flexible wiring board or a base material having a glass transition temperature of 250° C. or lower and is derived from the above-mentioned sputtering target. 0.4≦(In＋X)/(In＋Zn+X)≦0.8 (1) 0.2≦Zn/(In＋Zn＋X)≦0.6 (2) 0.001≦X/(In＋Zn＋X)≦0.015 (3)
以下，基於本發明之較佳之實施方式對其進行說明。本發明係關於一種場效電晶體(以下亦稱為「FET」)。本發明之FET係具備基材、及設置於該基材上之氧化物半導體層而構成。 如下所述，本發明之FET較佳為藉由包括如下步驟之方法製造：藉由濺鍍法，於基材上形成氧化物半導體層；及形成氧化物半導體層後，進行後退火以改善電特性。通常於形成氧化物半導體層後進行後退火之情形時，先前之氧化物半導體層必須於高溫下進行處理，故耐熱性較低之基材會變形或熔融，因此無法作為元件發揮功能。然而，根據本發明，即便在使用耐熱性不夠高之材料、例如可撓性配線板所使用之材料、或玻璃轉移溫度較低之材料(例如具有250℃以下之玻璃轉移溫度之材料)作為基材之情形時，於藉由濺鍍形成膜後，可以相對較低之溫度進行退火，故亦可形成氧化物半導體層。 Hereinafter, the preferred embodiments of the present invention will be described. The present invention relates to a field effect transistor (hereinafter also referred to as "FET"). The FET of the present invention includes a base material and an oxide semiconductor layer provided on the base material. As described below, the FET of the present invention is preferably manufactured by a method including the following steps: forming an oxide semiconductor layer on a substrate by sputtering; and after forming the oxide semiconductor layer, post-annealing is performed to improve the electrical conductivity. characteristic. Usually, when post-annealing is performed after forming an oxide semiconductor layer, the previous oxide semiconductor layer must be processed at high temperatures. Therefore, the base material with low heat resistance may be deformed or melted, and therefore cannot function as a device. However, according to the present invention, even if a material with insufficient heat resistance, such as a material used for a flexible wiring board, or a material with a low glass transition temperature (for example, a material with a glass transition temperature of 250° C. or lower) is used as the base, In the case of materials, after the film is formed by sputtering, it can be annealed at a relatively low temperature, so that an oxide semiconductor layer can also be formed.
於圖1中，模式性地示出本發明之FET之一實施方式。再者，該圖所示之構造之FET係本發明之實施方式之一例，當然本發明之FET並不限定於該圖所示之構造之FET。 該圖所示之FET1形成於基材10之一面。於基材10之一面配置有通道層20、源極電極30及汲極電極31，且以覆蓋該等之方式形成有閘極絕緣膜40。於閘極絕緣膜40上配置有閘極電極50。而且，於最上部配置有保護層60。於具有該構造之FET1中，例如通道層20由氧化物半導體層構成。因此，本發明中所謂之「設置於基材上之氧化物半導體層」包括如下兩種情形：(i)經由與基材之表面相接地設置之另一個或兩個以上之層設置有氧化物半導體層；及(ii)與基材之表面相接地設置有氧化物半導體層。 In FIG. 1 , one embodiment of the FET of the present invention is schematically shown. Furthermore, the FET having the structure shown in the figure is an example of the embodiment of the present invention. Of course, the FET of the present invention is not limited to the FET having the structure shown in the figure. The FET 1 shown in this figure is formed on one side of the base material 10 . The channel layer 20, the source electrode 30 and the drain electrode 31 are arranged on one surface of the base material 10, and a gate insulating film 40 is formed to cover them. The gate electrode 50 is arranged on the gate insulating film 40 . Furthermore, a protective layer 60 is arranged on the uppermost part. In the FET 1 having this structure, the channel layer 20 is composed of an oxide semiconductor layer, for example. Therefore, the so-called "oxide semiconductor layer provided on the substrate" in the present invention includes the following two situations: (i) An oxide semiconductor layer is provided through another or two or more layers in contact with the surface of the substrate; a physical semiconductor layer; and (ii) an oxide semiconductor layer is provided in contact with the surface of the substrate.
本發明之FET中之氧化物半導體層(以下，亦將本發明之FET中之氧化物半導體層適當地稱為「本發明之氧化物半導體層」)含有包含銦(In)元素、鋅(Zn)元素及添加元素(X)之氧化物。添加元素(X)包含選自鉭(Ta)元素、鍶(Sr)元素及鈮(Nb)元素中之至少一種元素。本發明之氧化物半導體層包含In、Zn及添加元素(X)作為構成其之金屬元素，亦可於不損及本發明之效果之範圍內，除包含該等元素以外還刻意地或不可避免地包含微量元素。作為微量元素，例如可例舉下述有機添加物中所含之元素或靶材製造時所混入之球磨機等之介質原料。作為本發明之氧化物半導體層中所含之微量元素，例如可例舉：Fe、Cr、Ni、Al、Si、W、Zr、Na、Mg、K、Ca、Ti、Y、Ga、Sn、Ba、La、Ce、Pr、Nd、Pm、Sm、Eu、Gd、Tb、Dy、Ho、Er、Tm、Yb、Lu及Pb等。相對於本發明之氧化物半導體層所含之包含In、Zn及X之氧化物之合計質量，其等之含量分別通常較佳為100質量ppm(以下亦稱為「ppm」)以下，更佳為80 ppm以下，進而較佳為50 ppm以下。該等微量元素之合計量較佳為500 ppm以下，更佳為300 ppm以下，進而較佳為100 ppm以下。於本發明之氧化物半導體層中包含微量元素之情形時，上述合計質量中亦包括微量元素之質量。The oxide semiconductor layer in the FET of the present invention (hereinafter, the oxide semiconductor layer in the FET of the present invention will also be appropriately referred to as the "oxide semiconductor layer of the present invention") contains elements including indium (In), zinc (Zn) ) element and oxides of added element (X). The additional element (X) includes at least one element selected from the group consisting of tantalum (Ta) element, strontium (Sr) element and niobium (Nb) element. The oxide semiconductor layer of the present invention contains In, Zn and the additive element (X) as its constituent metal elements. It may also contain In, Zn and the additive element (X) in addition to these elements, deliberately or unavoidably, within the scope that does not impair the effects of the present invention. Ground contains trace elements. Examples of trace elements include elements contained in the organic additives described below or media materials such as ball mills that are mixed during target production. Examples of trace elements contained in the oxide semiconductor layer of the present invention include: Fe, Cr, Ni, Al, Si, W, Zr, Na, Mg, K, Ca, Ti, Y, Ga, Sn, Ba, La, Ce, Pr, Nd, Pm, Sm, Eu, Gd, Tb, Dy, Ho, Er, Tm, Yb, Lu and Pb, etc. Relative to the total mass of the oxides including In, Zn, and It is 80 ppm or less, and it is more preferable that it is 50 ppm or less. The total amount of these trace elements is preferably 500 ppm or less, more preferably 300 ppm or less, and still more preferably 100 ppm or less. When the oxide semiconductor layer of the present invention contains a trace element, the above-mentioned total mass also includes the mass of the trace element.
就本發明之FET之性能提昇之方面而言，本發明之氧化物半導體層較佳為構成其之金屬元素、即In、Zn及X之原子比處於特定範圍內。 具體而言，In及X較佳為滿足以下式(1)所表示之原子比(式中之X設為上述添加元素之含有比之總和；以下，式(2)及(3)中亦相同)。 0.4≦(In＋X)/(In＋Zn＋X)≦0.8 (1) Zn較佳為滿足以下式(2)所表示之原子比。 0.2≦Zn/(In＋Zn＋X)≦0.6 (2) X較佳為滿足以下式(3)所表示之原子比。 0.001≦X/(In＋Zn＋X)≦0.015 (3) In terms of improving the performance of the FET of the present invention, the oxide semiconductor layer of the present invention preferably has an atomic ratio of the metal elements constituting it, that is, In, Zn, and X, within a specific range. Specifically, In and ). 0.4≦(In＋X)/(In＋Zn+X)≦0.8 (1) Zn preferably satisfies the atomic ratio represented by the following formula (2). 0.2≦Zn/(In＋Zn＋X)≦0.6 (2) X preferably satisfies the atomic ratio represented by the following formula (3). 0.001≦X/(In＋Zn＋X)≦0.015 (3)
藉由使氧化物半導體層中之In、Zn及X之原子比同時滿足上述式(1)至(3)，本發明之FET會表現出較高之場效遷移率、較低之漏電流及接近0 V之臨界電壓。就使該等優點更顯著之觀點而言，In及X進而較佳為滿足下述式(1-2)至(1-6)。 0.43≦(In＋X)/(In＋Zn＋X)≦0.79 (1-2) 0.48≦(In＋X)/(In＋Zn＋X)≦0.78 (1-3) 0.53≦(In＋X)/(In＋Zn＋X)≦0.75 (1-4) 0.54≦(In＋X)/(In＋Zn＋X)≦0.74 (1-5) 0.58≦(In＋X)/(In＋Zn＋X)≦0.70 (1-6) By making the atomic ratios of In, Zn and X in the oxide semiconductor layer simultaneously satisfy the above formulas (1) to (3), the FET of the present invention will exhibit higher field effect mobility, lower leakage current and The critical voltage is close to 0 V. From the viewpoint of making these advantages more remarkable, In and X further preferably satisfy the following formulas (1-2) to (1-6). 0.43≦(In＋X)/(In＋Zn＋X)≦0.79 (1-2) 0.48≦(In＋X)/(In＋Zn＋X)≦0.78 (1-3) 0.53≦(In＋X)/(In＋Zn＋X)≦0.75 (1-4) 0.54≦(In＋X)/(In＋Zn＋X)≦0.74 (1-5) 0.58≦(In+X)/(In+Zn+X)≦0.70 (1-6)
就與上述同樣之觀點而言，Zn進而較佳為滿足下述式(2-2)至(2-6)，X進而較佳為滿足下述式(3-2)至(3-5)。From the same viewpoint as above, it is further preferred that Zn satisfies the following formulas (2-2) to (2-6), and X further preferably satisfies the following formulas (3-2) to (3-5). .
0.21≦Zn/(In＋Zn＋X)≦0.57 (2-2) 0.22≦Zn/(In＋Zn＋X)≦0.52 (2-3) 0.25≦Zn/(In＋Zn＋X)≦0.47 (2-4) 0.26≦Zn/(In＋Zn＋X)≦0.46 (2-5) 0.30≦Zn/(In＋Zn＋X)≦0.42 (2-6) 0.0015≦X/(In＋Zn＋X)≦0.013 (3-2) 0.002＜X/(In＋Zn＋X)≦0.012 (3-3) 0.0025≦X/(In＋Zn＋X)≦0.010 (3-4) 0.003≦X/(In＋Zn＋X)≦0.009 (3-5) 0.21≦Zn/(In＋Zn＋X)≦0.57 (2-2) 0.22≦Zn/(In＋Zn＋X)≦0.52 (2-3) 0.25≦Zn/(In＋Zn＋X)≦0.47 (2-4) 0.26≦Zn/(In＋Zn＋X)≦0.46 (2-5) 0.30≦Zn/(In＋Zn+X)≦0.42 (2-6) 0.0015≦X/(In＋Zn+X)≦0.013 (3-2) 0.002＜X/(In＋Zn+X)≦0.012 (3-3) 0.0025≦X/(In+Zn+X)≦0.010 (3-4) 0.003≦X/(In＋Zn+X)≦0.009 (3-5)
如上所述，添加元素(X)使用選自Ta、Sr及Nb中之1種以上。該等元素可分別單獨使用，或者亦可組合2種以上使用。尤其是，就本發明之FET之綜合性能之觀點、及製造藉由濺鍍法製造氧化物半導體層時所使用之濺鍍靶材上之經濟性的方面而言，較佳為使用Ta作為添加元素(X)。 該等添加元素中，就充分發揮本發明所期望之效果之方面而言，較佳為使用Ta、Sr及Nb中之任一種，特佳為僅使用Ta或Nb，尤佳為僅使用Ta。但是亦可使用Ta、Sr及Nb這3種。 As mentioned above, as the additional element (X), one or more types selected from Ta, Sr, and Nb are used. These elements can be used individually, or two or more types can be used in combination. In particular, from the viewpoint of the overall performance of the FET of the present invention and the economical aspect of manufacturing a sputtering target used when manufacturing an oxide semiconductor layer by a sputtering method, it is preferable to use Ta as an additive. element(X). Among these additive elements, in order to fully exert the desired effects of the present invention, it is preferable to use any one of Ta, Sr and Nb, particularly preferably to use only Ta or Nb, and even more preferably to use only Ta. However, three types, namely Ta, Sr and Nb, can also be used.
就進一步提高由本發明之靶材形成之氧化物半導體元件之場效遷移率的方面、及表現出接近0 V之臨界電壓之方面而言，本發明之FET較佳為除滿足上述(1)至(3)之關係以外，In與X之原子比還滿足以下式(4)。 0.970≦In/(In＋X)≦0.999 (4) In order to further improve the field effect mobility of the oxide semiconductor device formed from the target material of the present invention and to exhibit a critical voltage close to 0 V, the FET of the present invention is preferably one that satisfies the above-mentioned (1) to In addition to the relationship (3), the atomic ratio of In and X also satisfies the following formula (4). 0.970≦In/(In＋X)≦0.999(4)
根據式(4)可知，於本發明之FET中，藉由使用相對於In之量為極少量之X，FET之場效遷移率提高。該情況係由本發明人首次發現。From equation (4), it can be seen that in the FET of the present invention, by using a very small amount of X relative to the amount of In, the field effect mobility of the FET is improved. This situation was discovered for the first time by the present inventor.
就本發明之FET之場效遷移率進一步提高之觀點、及表現出接近0 V之臨界電壓之觀點而言，In與X之原子比進而較佳為滿足以下式(4-2)至(4-4)。 0.980≦In/(In＋X)≦0.997 (4-2) 0.990≦In/(In＋X)≦0.995 (4-3) 0.990＜In/(In＋X)≦0.993 (4-4) From the perspective of further improving the field-effect mobility of the FET of the present invention and exhibiting a critical voltage close to 0 V, the atomic ratio of In and -4). 0.980≦In/(In＋X)≦0.997 (4-2) 0.990≦In/(In＋X)≦0.995 (4-3) 0.990＜In/(In＋X)≦0.993 (4-4)
本發明之FET中之氧化物半導體層包含In、Zn、添加元素X及氧，除此以外亦可包含其他元素，但就FET之場效遷移率進一步提高之觀點而言，上述氧化物半導體層較佳為包含In、Zn、添加元素X及氧，且剩餘部分由不可避免之雜質構成。The oxide semiconductor layer in the FET of the present invention contains In, Zn, additional elements Preferably, it contains In, Zn, additional elements X and oxygen, and the remainder consists of unavoidable impurities.
本發明之氧化物半導體層所含之各金屬之比率例如藉由X射線光電子光譜法(XPS：X-Ray Photoelectron Spectroscopy)、或ICP(Inductively Coupled Plasma，感應耦合電漿)發射光譜測定進行測定。The ratio of each metal contained in the oxide semiconductor layer of the present invention is measured, for example, by X-ray photoelectron spectroscopy (XPS: X-Ray Photoelectron Spectroscopy) or ICP (Inductively Coupled Plasma, inductively coupled plasma) emission spectrometry.
就因該FET之傳輸特性良好而使FPD高功能化之方面而言，較佳為本發明之FET之場效遷移率之值較大。詳細而言，本發明之TFT之場效遷移率(cm 2/Vs)較佳為20 cm 2/Vs以上，更佳為30 cm 2/Vs以上，進而較佳為50 cm 2/Vs以上，進而更佳為60 cm 2/Vs以上，進而更佳為70 cm 2/Vs以上，進而更佳為80 cm 2/Vs以上，特佳為100 cm 2/Vs以上。場效遷移率之值越大，則就FPD高功能化之方面而言越佳，若場效遷移率高達200 cm 2/Vs左右，則可獲得充分令人滿意之程度之性能。 就進一步提高場效遷移率之觀點而言，本發明之FET中之氧化物半導體層較佳為具有非晶結構。 From the perspective of improving the functionality of the FPD due to the good transmission characteristics of the FET, it is preferable that the field effect mobility of the FET of the present invention is large. Specifically, the field effect mobility (cm 2 /Vs) of the TFT of the present invention is preferably 20 cm 2 /Vs or more, more preferably 30 cm 2 /Vs or more, and further preferably 50 cm 2 /Vs or more. More preferably, it is 60 cm 2 /Vs or more, still more preferably 70 cm 2 /Vs or more, still more preferably 80 cm 2 /Vs or more, and particularly preferably 100 cm 2 /Vs or more. The larger the value of the field effect mobility, the better in terms of high functionality of the FPD. If the field effect mobility is as high as about 200 cm 2 /Vs, sufficiently satisfactory performance can be obtained. From the viewpoint of further improving the field effect mobility, the oxide semiconductor layer in the FET of the present invention preferably has an amorphous structure.
本發明之FET中之基材包含可撓性配線板所使用之材料，或者包含具有250℃以下之玻璃轉移溫度之材料。就可使用本發明之FET而容易地製造例如可撓性顯示器之方面而言，有利的是使用包含該等材料之基材。 作為構成基材之材料，較佳為樹脂基材，例如可例舉選自由聚酯系高分子、矽酮系高分子、丙烯酸系高分子、聚烯烴系高分子、及該等之共聚物所組成之群中之一種或兩種以上。又，該等樹脂基材更佳為包含具有250℃以下之玻璃轉移溫度之材料。該等材料例如具有膜之形態。 The base material in the FET of the present invention includes materials used for flexible wiring boards, or materials with a glass transition temperature of 250° C. or lower. To the extent that the FETs of the present invention can be used to easily manufacture, for example, flexible displays, it is advantageous to use substrates containing these materials. The material constituting the base material is preferably a resin base material, and examples thereof include those selected from the group consisting of polyester polymers, silicone polymers, acrylic polymers, polyolefin polymers, and copolymers thereof. One or more than two types of groups. Furthermore, the resin base material preferably contains a material having a glass transition temperature of 250° C. or lower. These materials have the form of a film, for example.
作為構成基材之材料之具體例，可例舉：聚萘二甲酸乙二酯(PEN)、聚對苯二甲酸乙二酯(PET)、聚苯硫醚(PPS)、聚醚醚酮(PEEK)、聚苯乙烯(PS)、聚醚碸(PES)、聚碳酸酯(PC)、三乙醯纖維素(TAC)、聚對苯二甲酸丁二酯(PBT)、聚矽烷(polysilane)、聚矽氧烷(polysiloxane)、聚矽氮烷(polysilazane)、聚碳矽烷(polycarbosilane)、聚丙烯酸酯(polyacrylate)、聚甲基丙烯酸酯(polymethacrylate)、聚丙烯酸甲酯(polymethylacrylate)、聚丙烯酸乙酯(polyethylacrylate)、聚甲基丙烯酸乙酯(polyethylmetacrylate)、環烯烴共聚物(COC)、環烯烴聚合物(COP)、聚乙烯(PE)、聚丙烯(PP)、聚甲基丙烯酸甲酯(PMMA)、聚縮醛(POM)、聚四氟乙烯(PTFE)、聚氯乙烯(PVC)、聚偏二氟乙烯(PVDF)、全氟烷基高分子(PFA)及苯乙烯-丙烯腈共聚物(SAN)等。該等材料可單獨使用一種，或者可組合兩種以上使用。Specific examples of the material constituting the base material include polyethylene naphthalate (PEN), polyethylene terephthalate (PET), polyphenylene sulfide (PPS), polyether ether ketone ( PEEK), polystyrene (PS), polyether styrene (PES), polycarbonate (PC), triacetyl cellulose (TAC), polybutylene terephthalate (PBT), polysilane (polysilane) , polysiloxane, polysilazane, polycarbosilane, polyacrylate, polymethacrylate, polymethylacrylate, polyacrylic acid Ethyl ester (polyethylmetacrylate), polyethylmethacrylate (polyethylmetacrylate), cyclic olefin copolymer (COC), cyclic olefin polymer (COP), polyethylene (PE), polypropylene (PP), polymethyl methacrylate (PMMA), polyacetal (POM), polytetrafluoroethylene (PTFE), polyvinyl chloride (PVC), polyvinylidene fluoride (PVDF), perfluoroalkyl polymer (PFA) and styrene-acrylonitrile Copolymer (SAN), etc. One type of these materials may be used alone, or two or more types may be used in combination.
根據本發明，藉由利用使用下述靶材之濺鍍法，使氧化物半導體層形成於基材上，即便為包含可撓性配線板所使用之材料，換言之耐熱性不夠充分高之材料的基材，亦可順利形成場效遷移率較高之氧化物半導體層。就該觀點而言，作為基材，可使用包含玻璃轉移溫度較佳為250℃以下、更佳為200℃以下、進而較佳為180℃以下之材料的基材。另一方面，就於退火步驟中保持最低限度之耐熱性之觀點而言，構成基材之材料之玻璃轉移溫度典型地較佳為0℃以上，更佳為25℃以上，進而較佳為80℃以上，進而更佳為85℃以上，進而更佳為90℃以上。基材之玻璃轉移溫度之測定方法如下所述。According to the present invention, an oxide semiconductor layer is formed on a base material by utilizing a sputtering method using the following target material, even if it includes a material used for a flexible wiring board, in other words, a material whose heat resistance is not sufficiently high. The substrate can also smoothly form an oxide semiconductor layer with higher field effect mobility. From this point of view, as the base material, a base material containing a material whose glass transition temperature is preferably 250°C or lower, more preferably 200°C or lower, and further preferably 180°C or lower can be used. On the other hand, from the viewpoint of maintaining minimum heat resistance during the annealing step, the glass transition temperature of the material constituting the base material is typically preferably 0°C or higher, more preferably 25°C or higher, and further preferably 80°C. ° C or higher, more preferably 85 ° C or higher, further preferably 90 ° C or higher. The method for measuring the glass transition temperature of the base material is as follows.
[玻璃轉移溫度之測定法] 於本發明中，玻璃轉移溫度係依照JIS-K-7121-1987(塑膠之轉移溫度測定方法)並藉由DTA(Differential Thermal Analysis，示差熱分析)法而求出。典型地使用NETZSCH公司製造之STA 2500 Regulus等作為測定裝置，測定中間點玻璃轉移溫度。 [Measurement method of glass transition temperature] In the present invention, the glass transition temperature is determined by the DTA (Differential Thermal Analysis) method in accordance with JIS-K-7121-1987 (Measurement of Transition Temperature of Plastics). Typically, STA 2500 Regulus manufactured by NETZSCH is used as a measuring device to measure the midpoint glass transition temperature.
就提高可撓性之觀點而言，本發明之FET中之基材之厚度較佳為1 μm以上500 μm以下，更佳為1 μm以上300 μm以下，進而較佳為1 μm以上100 μm以下。 就同樣之觀點而言，本發明之FET中之基材之熱膨脹係數較佳為5 ppm/℃以上80 ppm/℃以下，更佳為5 ppm/℃以上50 ppm/℃以下，進而較佳為5 ppm/℃以上20 ppm/℃以下。 From the viewpoint of improving flexibility, the thickness of the substrate in the FET of the present invention is preferably 1 μm or more and 500 μm or less, more preferably 1 μm or more and 300 μm or less, and still more preferably 1 μm or more and 100 μm or less. . From the same viewpoint, the thermal expansion coefficient of the base material in the FET of the present invention is preferably 5 ppm/°C or more and 80 ppm/°C or less, more preferably 5 ppm/°C or more and 50 ppm/°C or less, and still more preferably 5 ppm/°C or more and 50 ppm/°C or less. Above 5 ppm/℃ and below 20 ppm/℃.
根據本發明，亦提供一種具備本發明之FET之半導體裝置。於本說明書中，半導體裝置係藉由利用半導體特性可發揮功能之所有裝置，例如光電裝置、半導體電路及電子機器均為半導體裝置。本發明之半導體裝置尤其可用作FPD所使用之薄膜電晶體。According to the present invention, a semiconductor device including the FET of the present invention is also provided. In this specification, semiconductor devices are all devices that can function by utilizing semiconductor characteristics. For example, optoelectronic devices, semiconductor circuits, and electronic machines are all semiconductor devices. The semiconductor device of the present invention can especially be used as a thin film transistor used in FPD.
其次，對本發明之FET之適宜之製造方法進行說明。本發明之FET可使用公知之光微影法而製造，尤其是於製造本發明之氧化物半導體層之情形時，可使用下述濺鍍靶材，於以下條件下進行濺鍍。 關於濺鍍法，例如可使用DC(Direct Current，直流)濺鍍法。 濺鍍時之基材之溫度例如可設定為10℃以上250℃以下。又，亦可於不超過基材之玻璃轉移溫度之基材溫度下進行濺鍍。 濺鍍時之極限真空度例如可設定為未達0.001 Pa。 作為濺鍍氣體(環境)，例如可使用Ar與O 2之混合氣體。於此情形時，濺鍍氣體中之O 2氣體濃度可設定為21 vol%以上49 vol%以下，尤其可設定為22 vol%以上45 vol%以下。藉由將O 2氣體濃度設定於該範圍內，可使濺鍍層順利地半導體化。 濺鍍氣壓例如可設定為0.1 Pa以上3 Pa以下。 濺鍍功率例如可設定為0.1 W/cm 2以上10 W/cm 2以下。 Next, a suitable manufacturing method of the FET of the present invention will be described. The FET of the present invention can be manufactured using a known photolithography method. Especially when manufacturing the oxide semiconductor layer of the present invention, the following sputtering target can be used and sputtering can be performed under the following conditions. Regarding the sputtering method, for example, DC (Direct Current) sputtering method can be used. The temperature of the base material during sputtering can be set, for example, to 10°C or more and 250°C or less. Alternatively, sputtering may be performed at a substrate temperature that does not exceed the glass transition temperature of the substrate. The ultimate vacuum degree during sputtering can be set to less than 0.001 Pa, for example. As the sputtering gas (environment), for example, a mixed gas of Ar and O2 can be used. In this case, the O 2 gas concentration in the sputtering gas can be set to 21 vol% or more and 49 vol% or less, especially 22 vol% or more and 45 vol% or less. By setting the O 2 gas concentration within this range, the sputtered layer can be smoothly converted into a semiconductor. The sputtering gas pressure can be set to 0.1 Pa or more and 3 Pa or less, for example. The sputtering power can be set to, for example, 0.1 W/cm 2 or more and 10 W/cm 2 or less.
藉由在以上條件下進行濺鍍，即便為包含耐熱性不夠高之材料之基材，亦可於其上順利地製造氧化物半導體層。By performing sputtering under the above conditions, an oxide semiconductor layer can be successfully produced on a substrate including a material with insufficient heat resistance.
藉由濺鍍法形成氧化物半導體層後，較佳為對該氧化物半導體層進行退火處理。退火處理之目的在於對該氧化物半導體層賦予所期望之性能。出於該目的，退火處理之溫度較佳為50℃以上250℃以下，更佳為80℃以上200℃以下，進而較佳為100℃以上180℃以下，進而更佳為100℃以上150℃以下。退火處理之時間較佳為1分鐘以上180分鐘以下，更佳為2分鐘以上120分鐘以下，進而較佳為3分鐘以上60分鐘以下。退火環境較佳為包含大氣壓之氧環境等。 對氧化物半導體層之退火處理可於形成該氧化物半導體層後立即進行。或者，亦可於形成氧化物半導體層後進而形成一個或兩個以上之其他層，其後進行退火處理。 After the oxide semiconductor layer is formed by sputtering, the oxide semiconductor layer is preferably annealed. The purpose of the annealing treatment is to impart desired properties to the oxide semiconductor layer. For this purpose, the temperature of the annealing treatment is preferably not less than 50°C and not more than 250°C, more preferably not less than 80°C and not more than 200°C, still more preferably not less than 100°C and not more than 180°C, still more preferably not less than 100°C and not more than 150°C. . The time of the annealing treatment is preferably not less than 1 minute and not more than 180 minutes, more preferably not less than 2 minutes and not more than 120 minutes, and still more preferably not less than 3 minutes and not more than 60 minutes. The annealing environment is preferably an oxygen environment including atmospheric pressure. The annealing treatment of the oxide semiconductor layer can be performed immediately after forming the oxide semiconductor layer. Alternatively, one or two or more other layers may be formed after the oxide semiconductor layer is formed, and then annealed.
於藉由濺鍍法製造本發明之氧化物半導體層之情形時，理論上，濺鍍所使用之靶材之組成直接反映在氧化物半導體層之組成中。即，形成源自靶材之氧化物半導體層。因此，為了形成具有上述組成之本發明之氧化物半導體層，可使用含有包含銦(In)元素、鋅(Zn)元素及添加元素(X)之氧化物之濺鍍靶材(添加元素(X)為選自鉭(Ta)元素、鍶(Sr)元素及鈮(Nb)元素中之至少1種元素)。即，該濺鍍靶材適宜地用於製造具備如下氧化物半導體層之FET，該氧化物半導體層設置於可撓性配線板所使用之基材或具有250℃以下之玻璃轉移溫度之基材上且源自該濺鍍靶材。於以下說明中，亦將FET製造用濺鍍靶材適當地稱為「本發明之靶材」。When the oxide semiconductor layer of the present invention is manufactured by sputtering, theoretically, the composition of the target used for sputtering is directly reflected in the composition of the oxide semiconductor layer. That is, an oxide semiconductor layer derived from the target material is formed. Therefore, in order to form the oxide semiconductor layer of the present invention having the above composition, a sputtering target containing an oxide containing an indium (In) element, a zinc (Zn) element and an additional element (X) can be used (the additional element (X) ) is at least one element selected from the group consisting of tantalum (Ta) element, strontium (Sr) element and niobium (Nb) element). That is, this sputtering target is suitably used for manufacturing an FET having an oxide semiconductor layer provided on a base material used for a flexible wiring board or a base material having a glass transition temperature of 250° C. or lower. on and derived from the sputtering target. In the following description, the sputtering target for FET manufacturing will also be appropriately referred to as "the target of the present invention".
具體而言，可使用各元素之原子比同時滿足以下式(1)至(3)之FET製造用濺鍍靶材(式中之X設為上述添加元素之含有比之總和)。 0.4≦(In＋X)/(In＋Zn＋X)≦0.8 (1) 0.2≦Zn/(In＋Zn＋X)≦0.6 (2) 0.001≦X/(In＋Zn＋X)≦0.015 (3) Specifically, a sputtering target for FET manufacturing in which the atomic ratio of each element satisfies the following formulas (1) to (3) can be used (X in the formula is the sum of the content ratios of the above-mentioned added elements). 0.4≦(In＋X)/(In＋Zn＋X)≦0.8 (1) 0.2≦Zn/(In＋Zn＋X)≦0.6 (2) 0.001≦X/(In＋Zn＋X)≦0.015 (3)
上述FET製造用濺鍍靶材較佳為構成該靶材之各元素之原子比進而滿足式(4)。 0.970≦In/(In＋X)≦0.999 (4) The sputtering target for FET manufacturing is preferably such that the atomic ratio of each element constituting the target satisfies formula (4). 0.970≦In/(In＋X)≦0.999 (4)
上述式(1)～(4)之較佳之範圍與對於本發明之氧化物半導體層於上文敍述之範圍、即式(1-2)至(4-4)相同。The preferred ranges of the above formulas (1) to (4) are the same as the ranges described above for the oxide semiconductor layer of the present invention, that is, the formulas (1-2) to (4-4).
如上所述，本發明之靶材含有包含In、Zn及X之氧化物。該氧化物可為In之氧化物、Zn之氧化物或X之氧化物。或者，該氧化物可為選自由In、Zn及X所組成之群中之任意2種以上元素之複合氧化物。作為複合氧化物之具體例，可例舉：In-Zn複合氧化物、Zn-Ta複合氧化物、In-Ta複合氧化物、In-Nb複合氧化物、Zn-Nb複合氧化物、In-Sr複合氧化物、Zn-Sr複合氧化物、In-Zn-Ta複合氧化物、In-Zn-Nb複合氧化物、In-Zn-Sr複合氧化物等，但並不限於該等。As mentioned above, the target material of the present invention contains an oxide containing In, Zn and X. The oxide may be an oxide of In, an oxide of Zn or an oxide of X. Alternatively, the oxide may be a composite oxide of two or more elements selected from the group consisting of In, Zn, and X. Specific examples of the composite oxide include In-Zn composite oxide, Zn-Ta composite oxide, In-Ta composite oxide, In-Nb composite oxide, Zn-Nb composite oxide, and In-Sr. Composite oxide, Zn-Sr composite oxide, In-Zn-Ta composite oxide, In-Zn-Nb composite oxide, In-Zn-Sr composite oxide, etc., but are not limited to these.
就提高該靶材之密度及強度且降低電阻之觀點而言，本發明之靶材尤佳為包含作為In之氧化物之In 2O 3相及作為In與Zn之複合氧化物之Zn 3In 2O 6相。關於本發明之靶材包含In 2O 3相及Zn 3In 2O 6相，可根據藉由以本發明之靶材為對象之X射線繞射(以下亦稱為「XRD」)測定是否觀察到In 2O 3相及Zn 3In 2O 6相來進行判斷。再者，本發明中之In 2O 3相可包含微量Zn元素。 From the viewpoint of increasing the density and strength of the target material and reducing the electrical resistance, the target material of the present invention is particularly preferably composed of an In 2 O 3 phase which is an oxide of In and Zn 3 In which is a composite oxide of In and Zn. 2 O 6 phase. The target material of the present invention contains the In 2 O 3 phase and the Zn 3 In 2 O 6 phase. Whether or not the target material is observed can be measured by X-ray diffraction (hereinafter also referred to as "XRD") using the target material of the present invention as an object. To judge the In 2 O 3 phase and Zn 3 In 2 O 6 phase. Furthermore, the In 2 O 3 phase in the present invention may contain trace amounts of Zn element.
詳細而言，於使用CuKα射線作為X射線源之XRD測定中，In 2O 3相於2θ＝30.38°以上30.78°以下之範圍內觀察到主峰。Zn 3In 2O 6相於2θ＝34.00°以上34.40°以下之範圍內觀察到主峰。 Specifically, in the XRD measurement using CuKα rays as the X-ray source, the main peak of the In 2 O 3 phase was observed in the range of 2θ=30.38° to 30.78°. The main peak of the Zn 3 In 2 O 6 phase is observed in the range from 2θ=34.00° to 34.40°.
進而，於本發明之靶材中，較佳為In 2O 3相及Zn 3In 2O 6相兩者中均包含添加元素(X)。尤其是，若於靶材整體中均質地分散包含添加元素(X)，則於由本發明之靶材形成之氧化物半導體中均勻地包含添加元素(X)，從而可獲得均質之氧化物半導體膜。關於In 2O 3相及Zn 3In 2O 6相兩者中均包含添加元素(X)，例如可藉由能量分散型X射線光譜法(以下亦稱為「EDX」)等進行測定。 Furthermore, in the target material of the present invention, it is preferable that both the In 2 O 3 phase and the Zn 3 In 2 O 6 phase contain the additional element (X). In particular, if the additional element (X) is dispersed and contained uniformly throughout the target material, the additional element (X) will be uniformly contained in the oxide semiconductor formed from the target material of the present invention, and a homogeneous oxide semiconductor film can be obtained. . The addition element (X) contained in both the In 2 O 3 phase and the Zn 3 In 2 O 6 phase can be measured, for example, by energy dispersive X-ray spectroscopy (hereinafter also referred to as "EDX").
於藉由XRD測定於本發明之靶材中觀察到In 2O 3相之情形時，就提高本發明之靶材之密度及強度且降低電阻之方面而言，較佳為In 2O 3相之晶粒之尺寸滿足特定範圍。詳細而言，In 2O 3相之晶粒之尺寸較佳為3.0 μm以下，更佳為2.7 μm以下，進而較佳為2.5 μm以下。晶粒之尺寸越小越佳，下限值並無特別限定，通常為0.1 μm以上。 When the In 2 O 3 phase is observed in the target material of the present invention by XRD measurement, the In 2 O 3 phase is preferred in terms of increasing the density and strength of the target material of the present invention and reducing the resistance. The size of the grains satisfies a specific range. Specifically, the size of the crystal grains of the In 2 O 3 phase is preferably 3.0 μm or less, more preferably 2.7 μm or less, further preferably 2.5 μm or less. The smaller the size of the crystal grains, the better. The lower limit is not particularly limited, but is usually 0.1 μm or more.
於藉由XRD測定於本發明之靶材中觀察到Zn 3In 2O 6相之情形時，就提高本發明之靶材之密度及強度且降低電阻之方面而言，較佳為Zn 3In 2O 6相之晶粒之尺寸亦滿足特定範圍。詳細而言，Zn 3In 2O 6相之晶粒之尺寸較佳為3.9 μm以下，更佳為3.5 μm以下，進而較佳為3.0 μm以下，進而更佳為2.5 μm以下，進而更佳為2.3 μm以下，特佳為2.0 μm以下，尤佳為1.9 μm以下。晶粒之尺寸越小越佳，下限值並無特別限定，通常為0.1 μm以上。 When the Zn 3 In 2 O 6 phase is observed in the target material of the present invention by XRD measurement, Zn 3 In is preferred in terms of improving the density and strength of the target material of the present invention and reducing the resistance. The size of the crystal grains of the 2 O 6 phase also satisfies a specific range. Specifically, the size of the crystal grains of the Zn 3 In 2 O 6 phase is preferably 3.9 μm or less, more preferably 3.5 μm or less, further preferably 3.0 μm or less, still more preferably 2.5 μm or less, still more preferably 2.3 μm or less, particularly preferably 2.0 μm or less, particularly preferably 1.9 μm or less. The smaller the size of the crystal grains, the better. The lower limit is not particularly limited, but is usually 0.1 μm or more.
為了將In 2O 3相之晶粒之尺寸及Zn 3In 2O 6相之晶粒之尺寸設定於上述範圍內，例如可藉由下述方法製造靶材。 In 2O 3相之晶粒之尺寸及Zn 3In 2O 6相之晶粒之尺寸係藉由利用掃描式電子顯微鏡(以下亦稱為「SEM」)觀察本發明之靶材而進行測定。具體之測定方法將於下述實施例中進行詳細敍述。 In order to set the size of the crystal grains of the In 2 O 3 phase and the size of the crystal grains of the Zn 3 In 2 O 6 phase within the above ranges, for example, the target material can be manufactured by the following method. The size of the crystal grains of the In 2 O 3 phase and the size of the crystal grains of the Zn 3 In 2 O 6 phase are measured by observing the target material of the present invention using a scanning electron microscope (hereinafter also referred to as "SEM"). The specific measurement method will be described in detail in the following examples.
本發明之靶材包含In、Zn、添加元素X及氧，除此以外亦可包含其他元素，但就使用上述靶材製造之FET之場效遷移率進一步提高之觀點而言，上述靶材較佳為包含In、Zn、添加元素X及氧，且剩餘部分由不可避免之雜質構成。The target material of the present invention contains In, Zn, additional element Preferably, it contains In, Zn, additional elements X and oxygen, and the remainder is composed of unavoidable impurities.
其次，對本發明之靶材之適宜之製造方法進行說明。於本製造方法中，使作為靶材之原料之氧化物粉末成形為規定形狀而獲得成形體，對該成形體進行煅燒，藉此獲得由燒結體所構成之靶材。為了獲得成形體，可採用該技術領域中迄今為止已知之方法，例如澆鑄成形法。就可製造緻密之靶材之方面而言，尤佳為採用CIP(Cold Isostatic Pressing，冷均壓)成形法。Next, a suitable manufacturing method of the target material of the present invention will be described. In this manufacturing method, an oxide powder as a raw material of a target material is molded into a predetermined shape to obtain a molded body, and the molded body is fired to obtain a target material composed of a sintered body. To obtain a shaped body, methods hitherto known in this technical field, such as cast molding, can be used. In terms of producing dense target materials, it is particularly preferable to use the CIP (Cold Isostatic Pressing) forming method.
於CIP成形法中，對與澆鑄成形法中所使用之漿料同樣之漿料進行噴霧乾燥而獲得乾燥粉末。將所獲得之乾燥粉末填充於模具中進行CIP成形。In the CIP molding method, the same slurry as that used in the cast molding method is spray-dried to obtain dry powder. The obtained dry powder is filled into a mold for CIP molding.
以該方式獲得成形體後，繼而對其進行煅燒。成形體之煅燒通常可於含氧環境中進行。尤其於大氣環境中進行煅燒較為簡便。煅燒溫度較佳為1200℃以上1600℃以下，更佳為1300℃以上1500℃以下，進而較佳為1350℃以上1450℃以下。煅燒時間較佳為1小時以上100小時以下，更佳為2小時以上50小時以下，進而較佳為3小時以上30小時以下。升溫速度較佳為5℃/小時以上500℃/小時以下，更佳為10℃/小時以上200℃/小時以下，進而較佳為20℃/小時以上100℃/小時以下。After the shaped body is obtained in this manner, it is subsequently calcined. Calcination of the shaped body can usually be carried out in an oxygen-containing environment. In particular, it is easier to calcine in an atmospheric environment. The calcination temperature is preferably from 1200°C to 1600°C, more preferably from 1300°C to 1500°C, and further preferably from 1350°C to 1450°C. The calcination time is preferably from 1 hour to 100 hours, more preferably from 2 hours to 50 hours, and still more preferably from 3 hours to 30 hours. The temperature rise rate is preferably 5°C/hour or more and 500°C/hour or less, more preferably 10°C/hour or more and 200°C/hour or less, and still more preferably 20°C/hour or more and 100°C/hour or less.
於成形體之煅燒中，就促進燒結及產生緻密靶材之觀點而言，較佳為於煅燒過程中將產生In與Zn之複合氧化物、例如Zn 5In 2O 8之相之溫度維持一定時間。詳細而言，於原料粉末中包含In 2O 3粉及ZnO粉之情形時，隨著升溫，其等發生反應而產生Zn 5In 2O 8之相，其後變成Zn 4In 2O 7之相，再變成Zn 3In 2O 6之相。尤其就產生Zn 5In 2O 8之相時體積擴散而促進緻密化之方面而言，較佳為確實地產生Zn 5In 2O 8之相。就此種觀點而言，於煅燒之升溫過程中，較佳為將溫度於1000℃以上1250℃以下之範圍內維持一定時間，更佳為將溫度於1050℃以上1200℃以下之範圍內維持一定時間。所維持之溫度不一定限於特定一點之溫度，亦可為具有某種程度之幅度之溫度範圍。具體而言，於將選自1000℃以上1250℃以下之範圍中之特定溫度設為T(℃)時，例如可為T±10℃，較佳為T±5℃，更佳為T±3℃，進而較佳為T±1℃，只要包含於1000℃以上1250℃以下之範圍內即可。維持該溫度範圍之時間較佳為1小時以上40小時以下，進而較佳為2小時以上20小時以下。 In the calcination of the shaped body, from the viewpoint of promoting sintering and producing a dense target material, it is preferable to maintain a constant temperature during the calcination process in which a composite oxide of In and Zn, such as Zn 5 In 2 O 8 , is produced. time. Specifically, when the raw material powder contains In 2 O 3 powder and ZnO powder, they react with each other as the temperature rises to produce a phase of Zn 5 In 2 O 8 , which then becomes a phase of Zn 4 In 2 O 7 . phase, and then becomes the phase of Zn 3 In 2 O 6 . In particular, in terms of promoting densification by volume diffusion when the Zn 5 In 2 O 8 phase is generated, it is preferable to reliably generate the Zn 5 In 2 O 8 phase. From this point of view, during the temperature rise process of calcination, it is better to maintain the temperature in the range of above 1000°C and below 1250°C for a certain period of time, and more preferably to maintain the temperature in the range of above 1050°C and below 1200°C for a certain period of time. . The temperature maintained is not necessarily limited to the temperature at a specific point, but can also be a temperature range with a certain degree of amplitude. Specifically, when T (℃) is a specific temperature selected from the range of 1000°C to 1250°C, for example, it may be T±10°C, preferably T±5°C, and more preferably T±3. °C, and more preferably T±1 °C, as long as it is included in the range of 1000°C or more and 1250°C or less. The time to maintain this temperature range is preferably from 1 hour to 40 hours, and more preferably from 2 hours to 20 hours.
以該方式所獲得之靶材可藉由研削加工等加工為規定尺寸。藉由將其接合於基材，可獲得濺鍍靶。靶材之形狀並無特別限制，可採用先前公知之形狀，例如平板型及圓筒形等。The target material obtained in this way can be processed into a specified size by grinding or the like. By bonding it to a base material, a sputtering target can be obtained. The shape of the target is not particularly limited, and previously known shapes can be used, such as flat plate and cylindrical shape.
以上，基於本發明之較佳之實施方式對其進行了說明，但本發明並不限於上述實施方式。As mentioned above, the present invention has been described based on the preferred embodiments, but the present invention is not limited to the above-mentioned embodiments.
關於上述實施方式，本發明進而揭示以下場效電晶體及其製造方法、以及場效電晶體製造用濺鍍靶材。 [1]一種場效電晶體，其具備具有250℃以下之玻璃轉移溫度之基材、及設置於該基材上之氧化物半導體層，且 上述氧化物半導體層含有包含銦(In)元素、鋅(Zn)元素及添加元素(X)之氧化物， 添加元素(X)為選自鉭(Ta)元素、鍶(Sr)元素及鈮(Nb)元素中之至少1種元素， 各元素之原子比同時滿足式(1)至(3)(式中之X設為上述添加元素之含有比之總和)。 0.4≦(In＋X)/(In＋Zn＋X)≦0.8 (1) 0.2≦Zn/(In＋Zn＋X)≦0.6 (2) 0.001≦X/(In＋Zn＋X)≦0.015 (3) Regarding the above embodiments, the present invention further discloses the following field effect transistor, its manufacturing method, and a sputtering target for field effect transistor manufacturing. [1] A field effect transistor including a base material having a glass transition temperature of 250° C. or lower, and an oxide semiconductor layer provided on the base material, and The above-mentioned oxide semiconductor layer contains an oxide including indium (In) element, zinc (Zn) element and additional element (X), The additional element (X) is at least one element selected from the group consisting of tantalum (Ta) element, strontium (Sr) element and niobium (Nb) element, The atomic ratio of each element satisfies formulas (1) to (3) at the same time (X in the formula is set to the sum of the content ratios of the above-mentioned added elements). 0.4≦(In＋X)/(In＋Zn＋X)≦0.8 (1) 0.2≦Zn/(In＋Zn＋X)≦0.6 (2) 0.001≦X/(In＋Zn＋X)≦0.015 (3)
[2]一種場效電晶體，其具備可撓性配線板所使用之基材、及設置於該基材上之氧化物半導體層，且 上述氧化物半導體層含有包含銦(In)元素、鋅(Zn)元素及添加元素(X)之氧化物， 添加元素(X)為選自鉭(Ta)元素、鍶(Sr)元素及鈮(Nb)元素中之至少1種元素， 各元素之原子比同時滿足式(1)至(3)(式中之X設為上述添加元素之含有比之總和)。 0.4≦(In＋X)/(In＋Zn＋X)≦0.8 (1) 0.2≦Zn/(In＋Zn＋X)≦0.6 (2) 0.001≦X/(In＋Zn＋X)≦0.015 (3) [3]如[1]或[2]所記載之場效電晶體，其中上述添加元素(X)為鉭(Ta)元素或鈮(Nb)元素。 [4]如[3]所記載之場效電晶體，其中上述添加元素(X)為鉭(Ta)元素。 [5]如[1]至[4]中任一項所記載之場效電晶體，其中構成上述氧化物半導體層之各元素之原子比進而滿足式(4)。 0.970≦In/(In＋X)≦0.999 (4) [6]如[1]至[5]中任一項所記載之場效電晶體，其中上述場效電晶體之場效遷移率為20 cm 2/Vs以上。 [2] A field effect transistor having a base material used for a flexible wiring board and an oxide semiconductor layer provided on the base material, and the oxide semiconductor layer contains an element including indium (In), zinc (Zn) element and the oxide of the added element (X), the added element (X) is at least one element selected from the group consisting of tantalum (Ta) element, strontium (Sr) element and niobium (Nb) element, atoms of each element The ratio satisfies formulas (1) to (3) at the same time (X in the formula is set to the sum of the content ratios of the above-mentioned added elements). 0.4≦(In＋X)/(In＋Zn＋X)≦0.8 (1) 0.2≦Zn/(In＋Zn＋X)≦0.6 (2) 0.001≦X/(In＋Zn＋X)≦0.015 (3) [3] As shown in [1] or [2] The field effect transistor described above, wherein the above-mentioned added element (X) is tantalum (Ta) element or niobium (Nb) element. [4] The field effect transistor according to [3], wherein the added element (X) is tantalum (Ta). [5] The field effect transistor according to any one of [1] to [4], wherein the atomic ratio of each element constituting the oxide semiconductor layer further satisfies the formula (4). 0.970≦In/(In＋X)≦0.999 (4) [6] The field effect transistor as described in any one of [1] to [5], wherein the field effect mobility of the above field effect transistor is 20 cm 2 /Vs or above.
[7]如[6]所記載之場效電晶體，其中上述場效電晶體之場效遷移率為30 cm 2/Vs以上。 [8]如[7]所記載之場效電晶體，其中上述場效電晶體之場效遷移率為50 cm 2/Vs以上。 [9]如[1]至[8]中任一項所記載之場效電晶體，其中上述基材係聚萘二甲酸乙二酯(PEN)、聚對苯二甲酸乙二酯(PET)、聚苯硫醚(PPS)、聚醚醚酮(PEEK)、聚苯乙烯(PS)、聚醚碸(PES)、聚碳酸酯(PC)、三乙醯纖維素(TAC)、環烯烴聚合物(COP)。 [10]一種場效電晶體之製造方法，其具有如下步驟：使用含有包含銦(In)元素、鋅(Zn)元素及添加元素(X)之氧化物之濺鍍靶材(添加元素(X)為選自鉭(Ta)元素、鍶(Sr)元素及鈮(Nb)元素中之至少1種元素)，於氧濃度為21 vol%以上49 vol%以下之環境下，對可撓性配線板所使用之基材或具有250℃以下之玻璃轉移溫度之基材進行濺鍍，形成源自上述靶材之氧化物半導體，且 於50℃以上250℃以下之溫度下對上述氧化物半導體進行退火處理。 [11]如[10]所記載之製造方法，其中上述添加元素(X)為鉭(Ta)元素或鈮(Nb)元素。 [7] The field effect transistor according to [6], wherein the field effect mobility of the field effect transistor is 30 cm 2 /Vs or more. [8] The field effect transistor according to [7], wherein the field effect mobility of the field effect transistor is 50 cm 2 /Vs or more. [9] The field effect transistor according to any one of [1] to [8], wherein the base material is polyethylene naphthalate (PEN) or polyethylene terephthalate (PET) , polyphenylene sulfide (PPS), polyether ether ketone (PEEK), polystyrene (PS), polyether sulfide (PES), polycarbonate (PC), triacetyl cellulose (TAC), cyclic olefin polymerization Object (COP). [10] A method of manufacturing a field effect transistor, which has the following steps: using a sputtering target containing an oxide containing an indium (In) element, a zinc (Zn) element, and an additional element (X) (the additional element (X) ) is at least one element selected from the group consisting of tantalum (Ta) element, strontium (Sr) element and niobium (Nb) element), in an environment with an oxygen concentration of 21 vol% or more and 49 vol% or less, for flexible wiring The base material used for the plate or the base material having a glass transition temperature of 250°C or less is sputtered to form an oxide semiconductor derived from the above target material, and the above oxide semiconductor is processed at a temperature of 50°C or more and 250°C or less. Annealing treatment. [11] The manufacturing method according to [10], wherein the additional element (X) is a tantalum (Ta) element or a niobium (Nb) element.
[12]如[11]所記載之製造方法，其中上述添加元素(X)為鉭(Ta)元素。 [13]如[10]至[12]中任一項所記載之製造方法，其中上述靶材中之各元素之原子比同時滿足式(1)至(3)(式中之X設為上述添加元素之含有比之總和)。 0.4≦(In＋X)/(In＋Zn＋X)≦0.8 (1) 0.2≦Zn/(In＋Zn＋X)≦0.6 (2) 0.001≦X/(In＋Zn＋X)≦0.015 (3) [14]一種場效電晶體之製造用濺鍍靶材，其係如下濺鍍靶材：含有包含銦(In)元素、鋅(Zn)元素及添加元素(X)之氧化物， 添加元素(X)為選自鉭(Ta)元素、鍶(Sr)元素及鈮(Nb)元素中之至少1種元素， 各元素之原子比同時滿足式(1)至(3)；且 該場效電晶體具備氧化物半導體層，該氧化物半導體層設置於可撓性配線板所使用之基材或具有250℃以下之玻璃轉移溫度之基材上且源自上述濺鍍靶材。 0.4≦(In＋X)/(In＋Zn＋X)≦0.8 (1) 0.2≦Zn/(In＋Zn＋X)≦0.6 (2) 0.001≦X/(In＋Zn＋X)≦0.015 (3) [15]如[14]所記載之濺鍍靶材，其中上述添加元素(X)為鉭(Ta)元素或鈮(Nb)元素。 [16]如[15]所記載之濺鍍靶材，其中上述添加元素(X)為鉭(Ta)元素。 [12] The manufacturing method according to [11], wherein the additional element (X) is tantalum (Ta). [13] The manufacturing method as described in any one of [10] to [12], wherein the atomic ratio of each element in the target material simultaneously satisfies the formulas (1) to (3) (X in the formula is set to the above Add the sum of the content ratios of the elements). 0.4≦(In＋X)/(In＋Zn＋X)≦0.8 (1) 0.2≦Zn/(In＋Zn＋X)≦0.6 (2) 0.001≦X/(In＋Zn＋X)≦0.015 (3) [14] A sputtering target for manufacturing field effect transistors, which is the following sputtering target: containing an oxide containing indium (In) element, zinc (Zn) element and additional element (X), The additional element (X) is at least one element selected from the group consisting of tantalum (Ta) element, strontium (Sr) element and niobium (Nb) element, The atomic ratio of each element satisfies formulas (1) to (3) at the same time; and This field effect transistor has an oxide semiconductor layer, and the oxide semiconductor layer is provided on a base material used for a flexible wiring board or a base material having a glass transition temperature of 250° C. or lower and is derived from the above-mentioned sputtering target. 0.4≦(In＋X)/(In＋Zn＋X)≦0.8 (1) 0.2≦Zn/(In＋Zn＋X)≦0.6 (2) 0.001≦X/(In＋Zn＋X)≦0.015 (3) [15] The sputtering target material according to [14], wherein the added element (X) is tantalum (Ta) element or niobium (Nb) element. [16] The sputtering target material according to [15], wherein the added element (X) is a tantalum (Ta) element.
[17]如[14]至[16]中任一項所記載之場效電晶體之製造用濺鍍靶材，其中上述場效電晶體之製造用濺鍍靶材包含In 2O 3相及Zn 3In 2O 6相。 [18]如[17]所記載之場效電晶體之製造用濺鍍靶材，其中In 2O 3相及Zn 3In 2O 6相兩者中均包含添加元素(X)。 [19]如[17]或[18]所記載之場效電晶體之製造用濺鍍靶材，其中In 2O 3相之晶粒之尺寸為0.1 μm以上3.0 μm以下，且 Zn 3In 2O 6相之晶粒之尺寸為0.1 μm以上3.9 μm以下。 [20]一種半導體裝置，其使用如[1]至[9]中任一項所記載之場效電晶體。 實施例 [17] The sputtering target for manufacturing field effect transistors according to any one of [14] to [16], wherein the sputtering target for manufacturing field effect transistors contains an In 2 O 3 phase and Zn 3 In 2 O 6 phase. [18] The sputtering target for manufacturing a field effect transistor according to [17], wherein both the In 2 O 3 phase and the Zn 3 In 2 O 6 phase contain the additive element (X). [19] The sputtering target for manufacturing field effect transistors as described in [17] or [18], wherein the size of the crystal grains of the In 2 O 3 phase is 0.1 μm or more and 3.0 μm or less, and Zn 3 In 2 The size of the crystal grains of the O 6 phase is from 0.1 μm to 3.9 μm. [20] A semiconductor device using the field effect transistor according to any one of [1] to [9]. Example
以下，藉由實施例對本發明更詳細地進行說明。然而，本發明之範圍並不限於該實施例。Hereinafter, the present invention will be described in more detail through examples. However, the scope of the present invention is not limited to this embodiment.
[實施例1] 以In、Zn及Ta之原子比成為以下表1所示之值之方式，將In 2O 3粉末、ZnO粉末、及Ta 2O 5粉末製成靶材，使用該靶材，藉由光微影法製作圖1所示之FET1。 於FET1之製作中，使用聚萘二甲酸乙二酯膜(東洋紡股份有限公司製造之Teonex(註冊商標))(玻璃轉移溫度：155℃)作為基材10。使用DC濺鍍裝置，於基材10上成膜Mo薄膜作為源極電極30及汲極電極31，使用藉由上述方法所獲得之靶材，於下述條件下進行濺鍍成膜，成膜為厚度約30 nm之通道層20。 ・成膜裝置：DC濺鍍裝置 Tokki股份有限公司製造之SML-464 ・極限真空度：未達1×10 -4Pa ・濺鍍氣體：Ar/O 2混合氣體 ・濺鍍氣壓：0.4 Pa ・O 2氣體濃度：如以下表1所示。 ・基材溫度：室溫 ・濺鍍功率：3 W/cm 2繼而，於下述條件下，成膜SiO x薄膜作為閘極絕緣膜40。 ・成膜裝置：電漿CVD(Chemical Vapor Deposition，化學氣相沈積)裝置 Samco股份有限公司製造之PD-2202L ・成膜氣體：SiH 4/N 2O/N 2混合氣體 ・成膜壓力：110 Pa ・基材溫度：150℃ 繼而，使用上述DC濺鍍裝置，成膜Mo薄膜作為閘極電極50。 使用上述電漿CVD裝置，成膜SiO x薄膜作為保護層60。最後，於150℃下實施退火處理。退火處理之時間設為60分鐘。以該方式製造FET1。 藉由X射線光電子光譜法(XPS：X-Ray Photoelectron Spectroscopy)，確認到所獲得之FET1中之通道層20之組成與靶材之組成相同(以下實施例及比較例中亦相同)。XPS係可測定藉由對試樣表面照射X射線而產生之光電子能量，分析試樣之構成元素及其電子狀態的測定方法。因此，表1所示之各元素之組成於通道層20及靶材中相同。 [Example 1] In 2 O 3 powder, ZnO powder, and Ta 2 O 5 powder were made into targets so that the atomic ratio of In, Zn, and Ta became the values shown in Table 1 below, and the targets were used. , the FET1 shown in Figure 1 is produced by photolithography. In the production of FET 1, a polyethylene naphthalate film (Teonex (registered trademark) manufactured by Toyobo Co., Ltd.) (glass transition temperature: 155°C) was used as the base material 10. Using a DC sputtering device, a Mo thin film is formed on the substrate 10 as the source electrode 30 and the drain electrode 31. Using the target obtained by the above method, sputtering is performed under the following conditions to form the film. It is a channel layer 20 with a thickness of about 30 nm.・Film forming device: DC sputtering device SML-464 manufactured by Tokki Co., Ltd. ・Ultimate vacuum degree: less than 1×10 -4 Pa ・Sputtering gas: Ar/O 2 mixed gas ・Sputtering gas pressure: 0.4 Pa ・O2 gas concentration: as shown in Table 1 below.・Substrate temperature: room temperature ・Sputtering power: 3 W/cm 2 Next, under the following conditions, a SiO x thin film is formed as the gate insulating film 40 .・Film forming device: Plasma CVD (Chemical Vapor Deposition, chemical vapor deposition) device PD-2202L manufactured by Samco Co., Ltd. ・Film forming gas: SiH 4 /N 2 O/N 2 mixed gas ・Film forming pressure: 110 Pa ・Substrate temperature: 150° C. Next, the above-mentioned DC sputtering device was used to form a Mo thin film as the gate electrode 50 . Using the plasma CVD apparatus described above, a SiO x thin film is formed as the protective layer 60 . Finally, annealing treatment is performed at 150°C. The annealing treatment time was set to 60 minutes. FET1 is manufactured in this way. Through X-ray photoelectron spectroscopy (XPS: X-Ray Photoelectron Spectroscopy), it was confirmed that the composition of the channel layer 20 in the obtained FET 1 was the same as that of the target material (the same is true in the following examples and comparative examples). XPS is a measurement method that can measure the photoelectron energy generated by irradiating X-rays on the surface of a sample and analyze the constituent elements and their electronic states of the sample. Therefore, the compositions of each element shown in Table 1 are the same in the channel layer 20 and the target material.
[實施例2至12及比較例1至15] 以實施例1中In、Zn及Ta、或In、Zn及Nb之原子比成為以下表1及表2所示之值之方式，將各原料粉末混合而製造靶材。又，於以下表1及表2所示之條件下進行濺鍍。除該等以外，以與實施例1相同之方式獲得FET1。 [Examples 2 to 12 and Comparative Examples 1 to 15] In Example 1, each raw material powder was mixed so that the atomic ratio of In, Zn, and Ta, or In, Zn, and Nb became the value shown in Table 1 and Table 2 below, and a target was manufactured. Moreover, sputtering was performed under the conditions shown in Table 1 and Table 2 below. Except for these, FET1 was obtained in the same manner as in Example 1.
[評價1] 對實施例及比較例中所獲得之靶材進行SEM觀察，藉由如下方法測定In 2O 3相之晶粒之尺寸及Zn 3In 2O 6相之晶粒之尺寸。將其等之結果示於以下表1及表2中。 使用日立高新技術製造之掃描式電子顯微鏡SU3500，對靶材之表面進行SEM觀察，並且進行結晶之組成相或結晶形狀之評價。 具體而言，使用金剛砂紙#180、#400、#800、#1000、#2000，對將靶材切斷所獲得之切斷面階段性地進行研磨，最後進行拋光研磨而精加工成鏡面。對鏡面精加工面進行SEM觀察。於結晶形狀之評價中，以倍率1000倍，對87.5 μm×125 μm之範圍之BSE-COMP(Backscattered Electron-Compositional，背散射電子成分)圖像隨機拍攝10個視野而獲得SEM圖像。 藉由圖像處理軟體：ImageJ 1.51k(http://imageJ.nih.gov/ij/，提供來源：美國國立衛生研究所(NIH：National Institutes of Health))，對所獲得之SEM圖像進行解析。具體程序如下。 於1100℃下對SEM圖像拍攝時所使用之樣品實施1小時熱蝕刻，進行SEM觀察，藉此獲得圖2所示之出現晶界之圖像。對於所獲得之圖像，首先沿著In 2O 3相(圖2中看起來較白之區域A)之晶界進行描繪。於所有描繪完成後，實施粒子解析(Analyze→Analyze Particles)，獲得各粒子之面積。其後，根據所獲得之各粒子之面積計算出等面積圓直徑。將10個視野中所計算出之所有粒子之等面積圓直徑之算術平均值設為In 2O 3相之晶粒之尺寸。繼而，沿著Zn 3In 2O 6相之晶界進行描繪，同樣地實施解析，獲得各粒子之面積，根據所獲得之各粒子之面積計算出等面積圓直徑。將10個視野中所計算出之所有粒子之等面積圓直徑之算術平均值設為Zn 3In 2O 6相之晶粒之尺寸。 又，對熱蝕刻前之無晶界之BSE-COMP圖像進行粒子解析，藉此計算出總面積中之In 2O 3相之面積之比率。將10個視野中所計算出之所有粒子之該等之算術平均值設為In 2O 3相面積率。又，自100減去In 2O 3相面積率，藉此計算出Zn 3In 2O 6相面積率。 [Evaluation 1] SEM observation was performed on the target materials obtained in the Examples and Comparative Examples, and the size of the crystal grains of the In 2 O 3 phase and the size of the crystal grains of the Zn 3 In 2 O 6 phase were measured by the following method. The results are shown in Table 1 and Table 2 below. The scanning electron microscope SU3500 manufactured by Hitachi High-Tech was used to conduct SEM observation of the surface of the target, and the composition phase or crystal shape of the crystal was evaluated. Specifically, the cut surface obtained by cutting the target material was ground in stages using emery paper #180, #400, #800, #1000, and #2000, and finally polished and polished to a mirror surface. SEM observation was performed on the mirror-finished surface. In the evaluation of the crystal shape, 10 visual fields of BSE-COMP (Backscattered Electron-Compositional) images in the range of 87.5 μm × 125 μm were randomly taken at a magnification of 1000 times to obtain SEM images. Using image processing software: ImageJ 1.51k (http://imageJ.nih.gov/ij/, source: National Institutes of Health (NIH: National Institutes of Health)), the obtained SEM images were processed parse. The specific procedures are as follows. The sample used for taking the SEM image was thermally etched at 1100°C for 1 hour, and SEM observation was performed to obtain the image of grain boundaries as shown in Figure 2. For the obtained image, first trace along the grain boundaries of the In 2 O 3 phase (the whiter-looking area A in Figure 2). After all drawings are completed, perform particle analysis (Analyze→Analyze Particles) to obtain the area of each particle. Thereafter, the equal-area circle diameter is calculated based on the obtained area of each particle. The arithmetic mean of the equal-area circle diameters of all particles calculated in 10 fields of view is set as the size of the crystal grains of the In 2 O 3 phase. Next, the grain boundaries of the Zn 3 In 2 O 6 phase were drawn and analyzed in the same manner to obtain the area of each particle. The diameter of an equal-area circle was calculated based on the obtained area of each particle. The arithmetic mean of the equal-area circle diameters of all particles calculated in 10 fields of view is set as the size of the crystal grains of the Zn 3 In 2 O 6 phase. Furthermore, particle analysis was performed on the BSE-COMP image without grain boundaries before thermal etching to calculate the area ratio of the In 2 O 3 phase in the total area. The arithmetic mean of all particles calculated in 10 fields of view was set as the In 2 O 3 phase area ratio. Furthermore, the In 2 O 3 phase area ratio was subtracted from 100 to calculate the Zn 3 In 2 O 6 phase area ratio.
[評價2] 對實施例及比較例中所獲得之FET1進行汲極電壓Vd＝5 V下之傳輸特性之測定。所測定之傳輸特性係場效遷移率μ(cm 2/Vs)、SS(Subthreshold Swing，次臨界擺動)值(V/dec)及臨界電壓Vth(V)。傳輸特性係利用Agilent Technologies股份有限公司製造之半導體器件分析儀B1500A進行測定。將測定結果示於表1及表2中。再者，雖未示於表中，但本發明人藉由XRD測定確認到，各實施例中所獲得之FET1之通道層20為非晶結構。 場效遷移率係於MOSFET(Metal-Oxide-Semiconductor Field-Effect Transistor，金屬氧化物半導體場效電晶體)動作之飽和區域中根據汲極電壓一定時汲極電流相對於閘極電壓之變化求出的通道遷移率，值越大則傳輸特性越良好。 SS值係於臨界電壓附近使汲極電流上升1位數所需之閘極電壓，值越小則傳輸特性越良好。 臨界電壓係對汲極電極施加正電壓且對閘極電極施加正負任一電壓時汲極電流流動而成為1 nA之情形時的電壓，值較佳為接近0 V。詳細而言，更佳為-2 V以上，進而較佳為-1 V以上，進而更佳為0 V以上。又，更佳為3 V以下，進而較佳為2 V以下，進而更佳為1 V以下。具體而言，更佳為-2 V以上3 V以下，進而較佳為-1 V以上2 V以下，進而更佳為0 V以上1 V以下。 [Evaluation 2] The transmission characteristics at the drain voltage Vd = 5 V were measured for the FET 1 obtained in the Example and the Comparative Example. The measured transmission characteristics are field-effect mobility μ (cm 2 /Vs), SS (Subthreshold Swing, sub-critical swing) value (V/dec) and threshold voltage Vth (V). The transmission characteristics were measured using a semiconductor device analyzer B1500A manufactured by Agilent Technologies Co., Ltd. The measurement results are shown in Table 1 and Table 2. Furthermore, although not shown in the table, the inventors confirmed through XRD measurement that the channel layer 20 of the FET 1 obtained in each example has an amorphous structure. The field-effect mobility is calculated based on the change of the drain current relative to the gate voltage when the drain voltage is constant in the saturation region of MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor) operation. The channel mobility of , the larger the value, the better the transmission characteristics. The SS value is the gate voltage required to increase the drain current by one digit near the critical voltage. The smaller the value, the better the transfer characteristics. The critical voltage is the voltage at which the drain current flows and becomes 1 nA when a positive voltage is applied to the drain electrode and a positive or negative voltage is applied to the gate electrode. The value is preferably close to 0 V. Specifically, it is more preferably -2 V or more, still more preferably -1 V or more, and still more preferably 0 V or more. Moreover, it is more preferably 3 V or less, still more preferably 2 V or less, still more preferably 1 V or less. Specifically, it is more preferably -2 V or more and 3 V or less, further preferably -1 V or more and 2 V or less, and still more preferably 0 V or more and 1 V or less.
[表1]
[表2]
根據表1及表2所示之結果可知，各實施例中所獲得之FET1於可撓性配線板所使用之基材或具有250℃以下之玻璃轉移溫度之基材上表現出優異之傳輸特性。另一方面，於比較例中，場效遷移率μ、臨界電壓Vth、SS值均不良，無法獲得良好之傳輸特性。「不良」意指通道層導體化或絕緣化，無法獲得良好之傳輸特性，而無法作為場效電晶體發揮功能。 再者，雖未示於表中，但本發明人藉由EDX測定確認到，於實施例之靶材中，In 2O 3相及Zn 3In 2O 6相兩者中均包含添加元素(X)。 [產業上之可利用性] According to the results shown in Table 1 and Table 2, it can be seen that the FET 1 obtained in each example exhibits excellent transmission characteristics on a substrate used for a flexible wiring board or a substrate with a glass transition temperature of 250° C. or lower. . On the other hand, in the comparative example, the field effect mobility μ, threshold voltage Vth, and SS value were all poor, and good transmission characteristics could not be obtained. "Bad" means that the channel layer is conductive or insulated, cannot obtain good transmission characteristics, and cannot function as a field effect transistor. Furthermore, although it is not shown in the table, the inventors confirmed through EDX measurement that in the targets of the examples, both the In 2 O 3 phase and the Zn 3 In 2 O 6 phase contained additional elements ( X). [Industrial availability]
根據本發明，提供一種雖形成於耐熱性較低之基材上但具有較高之場效遷移率之場效電晶體及其製造方法。又，根據本發明，提供一種適於製造此種場效電晶體之濺鍍靶材。 若使用本發明之靶材進行濺鍍，則較使用先前之靶材之情形，即便在濺鍍後於低溫下進行後退火處理，亦可具有較高之場效遷移率，故可抑制產生不表現出充分之場效遷移率之不良品，進而可減少廢棄物之產生。即，可減少該等廢棄物處理中之能量成本。又，低溫下之後退火步驟本身亦可減少製造時之能量成本。可達成天然資源之可持續管理及有效利用、以及脫碳(碳中和)化。 According to the present invention, a field effect transistor having a high field effect mobility formed on a substrate with low heat resistance and a manufacturing method thereof are provided. Furthermore, according to the present invention, a sputtering target suitable for manufacturing such a field effect transistor is provided. If the target material of the present invention is used for sputtering, compared with the case of using the previous target material, even if the post-annealing treatment is performed at a low temperature after sputtering, it can still have a higher field effect mobility, so the generation of inaccuracies can be suppressed. Defective products that exhibit sufficient field efficiency mobility can reduce waste generation. That is, the energy cost in waste treatment can be reduced. In addition, the subsequent annealing step itself at low temperature can also reduce the energy cost of manufacturing. Sustainable management and effective utilization of natural resources, as well as decarbonization (carbon neutrality) can be achieved.
1:FET 10:基材 20:通道層 30:源極電極 31:汲極電極 40:閘極絕緣膜 50:閘極電極 60:保護層 1:FET 10:Substrate 20: Channel layer 30: Source electrode 31: Drain electrode 40: Gate insulation film 50: Gate electrode 60:Protective layer
圖1係表示本發明之場效電晶體之構造之模式圖。 圖2係實施例1中所獲得之靶材之掃描式電子顯微鏡圖像。 FIG. 1 is a schematic diagram showing the structure of the field effect transistor of the present invention. Figure 2 is a scanning electron microscope image of the target obtained in Example 1.
1:FET 1:FET
10:基材 10:Substrate
20:通道層 20: Channel layer
30:源極電極 30: Source electrode
31:汲極電極 31: Drain electrode
40:閘極絕緣膜 40: Gate insulation film
50:閘極電極 50: Gate electrode
60:保護層 60:Protective layer
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Also Published As
| Publication number | Publication date |
|---|---|
| JPWO2023145497A1 (en) | 2023-08-03 |
| JP7364824B1 (en) | 2023-10-18 |
| WO2023145497A1 (en) | 2023-08-03 |
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