TW202331950A - Wiring board and method for manufacturing same - Google Patents
Wiring board and method for manufacturing same Download PDFInfo
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- TW202331950A TW202331950A TW111143916A TW111143916A TW202331950A TW 202331950 A TW202331950 A TW 202331950A TW 111143916 A TW111143916 A TW 111143916A TW 111143916 A TW111143916 A TW 111143916A TW 202331950 A TW202331950 A TW 202331950A
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- 238000004519 manufacturing process Methods 0.000 title claims description 32
- 238000000034 method Methods 0.000 title description 51
- 239000003990 capacitor Substances 0.000 claims abstract description 49
- 238000005530 etching Methods 0.000 claims abstract description 40
- 239000010410 layer Substances 0.000 claims description 389
- 239000000758 substrate Substances 0.000 claims description 51
- 239000012790 adhesive layer Substances 0.000 claims description 41
- 230000015572 biosynthetic process Effects 0.000 abstract description 21
- 238000009713 electroplating Methods 0.000 abstract description 13
- 238000000059 patterning Methods 0.000 abstract description 2
- 238000007747 plating Methods 0.000 description 29
- 239000011521 glass Substances 0.000 description 23
- 239000010408 film Substances 0.000 description 22
- PXHVJJICTQNCMI-UHFFFAOYSA-N nickel Substances [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 21
- 229920002120 photoresistant polymer Polymers 0.000 description 20
- 239000010949 copper Substances 0.000 description 19
- 229910052751 metal Inorganic materials 0.000 description 19
- 239000002184 metal Substances 0.000 description 19
- 229910052802 copper Inorganic materials 0.000 description 18
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 15
- 229910052759 nickel Inorganic materials 0.000 description 11
- 238000004544 sputter deposition Methods 0.000 description 11
- 239000010936 titanium Substances 0.000 description 11
- 229910052719 titanium Inorganic materials 0.000 description 9
- 239000003513 alkali Substances 0.000 description 8
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 7
- 239000000654 additive Substances 0.000 description 7
- 239000004020 conductor Substances 0.000 description 7
- 239000000463 material Substances 0.000 description 7
- 239000007864 aqueous solution Substances 0.000 description 6
- 238000007772 electroless plating Methods 0.000 description 5
- 229910052741 iridium Inorganic materials 0.000 description 5
- 239000000243 solution Substances 0.000 description 5
- 229910016570 AlCu Inorganic materials 0.000 description 3
- -1 AlSiCu Inorganic materials 0.000 description 3
- 229910000789 Aluminium-silicon alloy Inorganic materials 0.000 description 3
- 229910000881 Cu alloy Inorganic materials 0.000 description 3
- 229910001030 Iron–nickel alloy Inorganic materials 0.000 description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 3
- 229910052782 aluminium Inorganic materials 0.000 description 3
- 238000003486 chemical etching Methods 0.000 description 3
- 238000005229 chemical vapour deposition Methods 0.000 description 3
- 229910052804 chromium Inorganic materials 0.000 description 3
- 239000011248 coating agent Substances 0.000 description 3
- 238000000576 coating method Methods 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 229910052750 molybdenum Inorganic materials 0.000 description 3
- 229910052763 palladium Inorganic materials 0.000 description 3
- 229910052697 platinum Inorganic materials 0.000 description 3
- 239000011347 resin Substances 0.000 description 3
- 229920005989 resin Polymers 0.000 description 3
- 229910052707 ruthenium Inorganic materials 0.000 description 3
- 229910052721 tungsten Inorganic materials 0.000 description 3
- VYZAMTAEIAYCRO-UHFFFAOYSA-N Chromium Chemical compound [Cr] VYZAMTAEIAYCRO-UHFFFAOYSA-N 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 238000004040 coloring Methods 0.000 description 2
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 2
- 229910052737 gold Inorganic materials 0.000 description 2
- 239000010931 gold Substances 0.000 description 2
- 238000009413 insulation Methods 0.000 description 2
- 238000007733 ion plating Methods 0.000 description 2
- GKOZUEZYRPOHIO-UHFFFAOYSA-N iridium atom Chemical compound [Ir] GKOZUEZYRPOHIO-UHFFFAOYSA-N 0.000 description 2
- 238000003475 lamination Methods 0.000 description 2
- 239000007788 liquid Substances 0.000 description 2
- 238000001451 molecular beam epitaxy Methods 0.000 description 2
- 230000003287 optical effect Effects 0.000 description 2
- 230000002093 peripheral effect Effects 0.000 description 2
- 229910052703 rhodium Inorganic materials 0.000 description 2
- 239000010948 rhodium Substances 0.000 description 2
- MHOVAHRLVXNVSD-UHFFFAOYSA-N rhodium atom Chemical compound [Rh] MHOVAHRLVXNVSD-UHFFFAOYSA-N 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 229910000679 solder Inorganic materials 0.000 description 2
- 239000010409 thin film Substances 0.000 description 2
- 238000001771 vacuum deposition Methods 0.000 description 2
- BPQQTUXANYXVAA-UHFFFAOYSA-N Orthosilicate Chemical compound [O-][Si]([O-])([O-])[O-] BPQQTUXANYXVAA-UHFFFAOYSA-N 0.000 description 1
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 238000006124 Pilkington process Methods 0.000 description 1
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- NINIDFKCEFEMDL-UHFFFAOYSA-N Sulfur Chemical compound [S] NINIDFKCEFEMDL-UHFFFAOYSA-N 0.000 description 1
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 1
- GWEVSGVZZGPLCZ-UHFFFAOYSA-N Titan oxide Chemical compound O=[Ti]=O GWEVSGVZZGPLCZ-UHFFFAOYSA-N 0.000 description 1
- 230000005856 abnormality Effects 0.000 description 1
- 230000002411 adverse Effects 0.000 description 1
- 238000000149 argon plasma sintering Methods 0.000 description 1
- JRPBQTZRNDNNOP-UHFFFAOYSA-N barium titanate Chemical compound [Ba+2].[Ba+2].[O-][Ti]([O-])([O-])[O-] JRPBQTZRNDNNOP-UHFFFAOYSA-N 0.000 description 1
- 229910002113 barium titanate Inorganic materials 0.000 description 1
- 229910052797 bismuth Inorganic materials 0.000 description 1
- JCXGWMGPZLAOME-UHFFFAOYSA-N bismuth atom Chemical compound [Bi] JCXGWMGPZLAOME-UHFFFAOYSA-N 0.000 description 1
- 239000005388 borosilicate glass Substances 0.000 description 1
- AOWKSNWVBZGMTJ-UHFFFAOYSA-N calcium titanate Chemical compound [Ca+2].[O-][Ti]([O-])=O AOWKSNWVBZGMTJ-UHFFFAOYSA-N 0.000 description 1
- 239000003638 chemical reducing agent Substances 0.000 description 1
- 238000013329 compounding Methods 0.000 description 1
- 239000000470 constituent Substances 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000001627 detrimental effect Effects 0.000 description 1
- 238000003280 down draw process Methods 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 239000011133 lead Substances 0.000 description 1
- 238000007500 overflow downdraw method Methods 0.000 description 1
- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 description 1
- BPUBBGLMJRNUCC-UHFFFAOYSA-N oxygen(2-);tantalum(5+) Chemical compound [O-2].[O-2].[O-2].[O-2].[O-2].[Ta+5].[Ta+5] BPUBBGLMJRNUCC-UHFFFAOYSA-N 0.000 description 1
- 230000000149 penetrating effect Effects 0.000 description 1
- 230000035515 penetration Effects 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 239000006089 photosensitive glass Substances 0.000 description 1
- 238000007372 rollout process Methods 0.000 description 1
- 239000010980 sapphire Substances 0.000 description 1
- 229910052594 sapphire Inorganic materials 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 238000002791 soaking Methods 0.000 description 1
- VEALVRVVWBQVSL-UHFFFAOYSA-N strontium titanate Chemical compound [Sr+2].[O-][Ti]([O-])=O VEALVRVVWBQVSL-UHFFFAOYSA-N 0.000 description 1
- 239000011593 sulfur Substances 0.000 description 1
- 229910052717 sulfur Inorganic materials 0.000 description 1
- 229910001936 tantalum oxide Inorganic materials 0.000 description 1
- OGIDPMRJRNCKJF-UHFFFAOYSA-N titanium oxide Inorganic materials [Ti]=O OGIDPMRJRNCKJF-UHFFFAOYSA-N 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01G—CAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES, LIGHT-SENSITIVE OR TEMPERATURE-SENSITIVE DEVICES OF THE ELECTROLYTIC TYPE
- H01G4/00—Fixed capacitors; Processes of their manufacture
- H01G4/30—Stacked capacitors
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/16—Printed circuits incorporating printed electric components, e.g. printed resistor, capacitor, inductor
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Manufacturing & Machinery (AREA)
- Parts Printed On Printed Circuit Boards (AREA)
Abstract
Description
本發明係有關於一種配線基板及其製造方法。The present invention relates to a wiring substrate and a manufacturing method thereof.
將玻璃材料用作芯板的多層配線基板(以下稱為「玻璃電路板」等)大多被用作為中介層(interposer)。在這些多層配線基板中，有時會在基板內部形成薄膜電容器，作為被動電路的一部分，前述薄膜電容器具有藉由下部電極層與上部電極層夾持介電質之MIM(Metal Insulator Metal，金屬絕緣層金屬)構造。Multilayer wiring boards (hereinafter referred to as "glass boards", etc.) using glass materials as core boards are often used as interposers. In these multilayer wiring boards, thin film capacitors are sometimes formed inside the board. As part of the passive circuit, the thin film capacitors have a MIM (Metal Insulator Metal, Metal Insulated Metal) that sandwiches a dielectric between the lower electrode layer and the upper electrode layer. layer metal) structure.
在專利文獻1中，揭示了「一種配線基板，具備：基板，具有絕緣表面；第1導電層，係配置於前述基板上，包含有第1部分及第2部分，前述第1部分具有第1厚度，前述第2部分具有比該第1厚度更薄的第2厚度，且與該第1部分鄰接；第1絕緣層，係以自與前述第2部分隔開的方式配置於前述第1部分上；及第2導電層，相對於前述第1絕緣層而配置於與前述第1部分相反側」。 [先前技術文獻] [專利文獻] In Patent Document 1, it is disclosed that "a wiring substrate includes: a substrate having an insulating surface; a first conductive layer disposed on the substrate and comprising a first part and a second part, the first part having a first thickness, the aforementioned second portion has a second thickness thinner than the first thickness, and is adjacent to the first portion; the first insulating layer is disposed on the aforementioned first portion in a manner to be separated from the aforementioned second portion and the second conductive layer are arranged on the opposite side to the first part with respect to the first insulating layer. [Prior Art Literature] [Patent Document]
專利文獻1：國際公開第2019/244382號Patent Document 1: International Publication No. 2019/244382
[發明欲解決之課題][Problem to be solved by the invention]
在絕緣基板上形成MIM電容器時，首先設置第1種子層，使用第1種子層藉由鍍敷等設置第1導電層，將此作為電容器之下部電極。接著，在該下部電極之上方設置絕緣層，進而使用第2種子層及第2種子層藉由電鍍更在絕緣層之上方設置第2導電層，來作為上部電極。 在如此之第1導電層－絕緣層－第2導電層之電容器中，一般來說在導電層與介電質層中熱膨脹係數有所不同，因此在電容器會有產生應力應變的情形。 因此，在專利文獻1中揭示為了緩和MIM之第1導電層中之應力，在第1導電層與第1絕緣層之境界附近設置階梯差。 When forming a MIM capacitor on an insulating substrate, firstly, a first seed layer is provided, and a first conductive layer is provided by plating or the like using the first seed layer, and this is used as the lower electrode of the capacitor. Next, an insulating layer is provided on the lower electrode, and a second conductive layer is further provided on the insulating layer by electroplating using the second seed layer and the second seed layer, as an upper electrode. In such a first conductive layer-insulating layer-second conductive layer capacitor, generally speaking, the coefficient of thermal expansion is different between the conductive layer and the dielectric layer, so stress and strain may occur in the capacitor. Therefore, Patent Document 1 discloses that in order to relax the stress in the first conductive layer of the MIM, a step is provided near the boundary between the first conductive layer and the first insulating layer.
惟，在使用種子層來形成下部電極或上部電極之電容器中，由於種子層之膜厚薄，因此容易產生側邊蝕刻。接著，使用濺鍍等之方法在已產生側邊蝕刻的部位上形成第2種子層，因此極有可能使第2種子層無法完全地形成。 於是，本發明中，以提供一種例如不會在種子層產生側邊蝕刻之配線基板及其製造技術為目的。 [用以解決課題之手段] However, in a capacitor in which a lower electrode or an upper electrode is formed using a seed layer, side etching tends to occur because the film thickness of the seed layer is thin. Next, the second seed layer is formed on the portion where the side etching has occurred by a method such as sputtering, so there is a high possibility that the second seed layer cannot be completely formed. Therefore, an object of the present invention is to provide a wiring board that does not cause side etching in the seed layer, and its manufacturing technique, for example. [Means to solve the problem]
為了解決上述之課題，本發明一代表性的配線基板之製造方法為，前述配線基板包含：表面具有絕緣性之基板；配置於前述基板上之第1種子層；配置於前述種子層上方之第1導電層；配置於前述第1導電層上方之第1絕緣層；配置於前述第1絕緣層上方之第2種子層；及配置於前述第2種子層上方之第2導電層， 於前述配線基板中，藉由蝕刻將前述第1種子層圖案化之步驟是使用於至少1個方向上寬度比前述第1導電層更大之蝕刻遮罩，來進行蝕刻。 In order to solve the above-mentioned problems, a representative method of manufacturing a wiring board according to the present invention is that the wiring board includes: a substrate having an insulating surface; a first seed layer arranged on the substrate; and a first seed layer arranged above the seed layer. 1 conductive layer; a first insulating layer disposed above the first conductive layer; a second seed layer disposed above the first insulating layer; and a second conductive layer disposed above the second seed layer, In the above wiring board, the step of patterning the first seed layer by etching is performed by using an etching mask having a width larger than that of the first conductive layer in at least one direction.
又，為解決上述課題，一個代表性的本發明之配線基板為，在包含 表面具有絕緣性之基板及以下(1)至(5)之層的配線基板中： (1)配置於前述基板上之第1種子層； (2)配置於前述第1種子層上方之第1導電層； (3)配置於前述第1導電層上方之第1絕緣層； (4)配置於前述第1絕緣層上方之第2種子層；及 (5)配置於前述第2種子層上方之第2導電層， 前述(1)至(5)之層係構成MIM電容器， 在將寬度比前述MIM電容器中之第1導電層更大之前述MIM電容器中之前述第1種子層在水平方向上之寬度設為b，前述第1導電層在水平方向上之寬度設為a的情況下，a及b係滿足以下的數式(2)： 50nm≦(b-a)/2≦50μm ･･･(2) [發明之效果] Furthermore, in order to solve the above-mentioned problems, a typical wiring board of the present invention is composed of Substrates with insulating surfaces and wiring substrates with layers (1) to (5) below: (1) The first seed layer arranged on the aforementioned substrate; (2) The first conductive layer arranged above the aforementioned first seed layer; (3) The first insulating layer arranged above the aforementioned first conductive layer; (4) the second seed layer arranged above the first insulating layer; and (5) the second conductive layer arranged above the aforementioned second seed layer, The layers of the aforementioned (1) to (5) constitute a MIM capacitor, In the MIM capacitor whose width is larger than that of the first conductive layer in the MIM capacitor, the width of the first seed layer in the horizontal direction is b, and the width of the first conductive layer in the horizontal direction is a In the case of , a and b satisfy the following formula (2): 50nm≦(b-a)/2≦50μm ･･･(2) [Effect of Invention]
依據本發明，可以提供一種不會在種子層產生側邊蝕刻之配線基板及其製造方法。 上述以外的課題、構成及效果係透過以下用以實施的形態中之說明可明瞭。 According to the present invention, it is possible to provide a wiring board which does not cause side etching in a seed layer and a manufacturing method thereof. Problems, configurations, and effects other than those described above will be clarified by the description in the following embodiments for implementation.
[用以實施發明的形態][Mode for Carrying Out the Invention]
以下，參考圖式說明作為本發明之對象之基本構造、習知例之製造方法、本發明之第1實施形態、第2實施形態等。另，本發明並未因該等揭示而受限。又，在圖式之記載中對相同部分附上相同符號來表示。 在具有相同或同樣功能之構成要素為有複數個的情況，有時會對相同符號附上不同的附加符號來說明。又，在沒有必要區別該等複數個構成要素時，有時會省略附加符號來說明。 關於圖式中所示之各構成要素之位置、大小、形狀、範圍等，為了容易理解發明，有時不會顯示實際的位置、大小、形狀、範圍等。因此，本發明未必受限於圖式所揭示之位置、大小、形狀、範圍等。 Hereinafter, the basic structure which is the object of this invention, the manufacturing method of a conventional example, the 1st embodiment, the 2nd embodiment etc. of this invention are demonstrated with reference to drawings. In addition, the present invention is not limited by these disclosures. In addition, in description of drawings, the same code|symbol is attached|subjected and shown to the same part. When there are plural components having the same or similar function, the same symbols may be described with different additional symbols. In addition, when it is not necessary to distinguish these plural constituent elements, the reference numerals may be omitted for description. Regarding the position, size, shape, range, etc. of each component shown in the drawings, the actual position, size, shape, range, etc. may not be shown in order to facilitate understanding of the invention. Therefore, the present invention is not necessarily limited to the positions, sizes, shapes, ranges, etc. disclosed in the drawings.
另，在本揭示中，所謂的「面」不僅板狀構件之面，針對板狀構件所包含之層，有時亦指在與板狀構件之面略平行的層之間的界面。又，所謂的「上面」、「下面」意指在圖示有板狀構件或板狀構件所包含之層時顯示在圖式上之上方或者下方的面。另，針對「上面」、「下面」，有時亦稱為「第1面」、「第2面」。In addition, in the present disclosure, the so-called "surface" is not only the surface of the plate-shaped member, but may also mean the interface between layers that are approximately parallel to the surface of the plate-shaped member with respect to the layers included in the plate-shaped member. In addition, "upper side" and "lower side" mean a surface shown above or below the drawing when a plate-shaped member or a layer included in the plate-shaped member is shown in the drawing. Also, "upper side" and "lower side" are sometimes referred to as "first side" and "second side".
又，所謂的「側面」意指板狀構件或板狀構件所包含之層中的面或層之厚度的部分。再者，有時會將面的一部分及側面合起來稱為「端部」。 又，所謂的「上方」意指在將板狀構件或層水平地載置時之垂直上方的方向。再者，針對「上方」及與此相反的「下方」，有時將該等稱為「Z軸正向」、「Z軸負向」，針對水平方向，有時稱為「X軸方向」、「Y軸方向」。 In addition, the term "side" refers to a surface of a plate-shaped member or a layer included in a plate-shaped member or a part of the thickness of a layer. In addition, a part of a surface and a side surface may be collectively referred to as an "end". In addition, the term "upper" means a vertically upper direction when a plate-like member or layer is placed horizontally. Furthermore, "upper" and the opposite "lower" are sometimes referred to as "Z-axis positive direction" and "Z-axis negative direction", and the horizontal direction is sometimes referred to as "X-axis direction". , "Y axis direction".
又，所謂的「平面形狀」、「平面視角」意指：從上方，也就是說從z軸之正向朝負向來辨識面或層時之形狀。再者，所謂的「截面形狀」、「截面視角」意指：在特定的方向上切斷板狀構件或層時從水平方向辨識時之形狀。 再者，所謂的「中心部」意指：不是面或層的周邊部，而是中心部。再者，所謂的「中心方向」意指：從面或層之周邊部朝向面或層之平面形狀當中之中心的方向。 Also, the so-called "plane shape" and "plane view angle" mean: the shape of a surface or layer when viewed from above, that is, from the positive direction of the z-axis toward the negative direction. In addition, the so-called "cross-sectional shape" and "cross-sectional view angle" mean the shape seen from the horizontal direction when a plate-like member or layer is cut in a specific direction. In addition, the so-called "central part" means not the peripheral part of the surface or the layer, but the central part. Furthermore, the so-called "central direction" means the direction from the peripheral portion of the surface or layer toward the center of the planar shape of the surface or layer.
[基本構造] 首先，參考圖1說明本發明之製造方法之具有MIM電容器作為前提之配線基板的基本構造。 圖1是配線基板之剖面圖，前述配線基板包含：表面具有絕緣性之基板1、配置於前述基板1上之第1種子層3、配置於前述第1種子層3上方之第1導電層4、配置於前述第1導電層4上方之第1絕緣層6、配置於前述第1絕緣層6上方之第2種子層8、及配置於前述第2種子層8上方之第2導電層9。 在圖1之配線基板中，第1導電層4成為MIM之下部電極，第1絕緣層6成為MIM之介電質層，第2導電層9成為MIM之上部電極，在基板1上構成MIM電容器。 [basic structure] First, the basic structure of a wiring board having a MIM capacitor as a premise of the manufacturing method of the present invention will be described with reference to FIG. 1 . Fig. 1 is a cross-sectional view of a wiring substrate. The wiring substrate includes: a substrate 1 with an insulating surface, a first seed layer 3 disposed on the substrate 1, and a first conductive layer 4 disposed above the first seed layer 3. , the first insulating layer 6 disposed above the first conductive layer 4 , the second seed layer 8 disposed above the first insulating layer 6 , and the second conductive layer 9 disposed above the second seed layer 8 . In the wiring substrate shown in FIG. 1 , the first conductive layer 4 becomes the lower electrode of the MIM, the first insulating layer 6 becomes the dielectric layer of the MIM, and the second conductive layer 9 becomes the upper electrode of the MIM, forming a MIM capacitor on the substrate 1 .
＜各要素之說明＞ 以下，詳細說明本發明之製造方法之作為前提之MIM電容器之各要素之材質、形狀等。 (基板) 基板1宜將具有光穿透性之透明的玻璃作為材料者。玻璃的成分或者玻璃所含有之各成分之配合比率，進而玻璃之製造方法並無特別限制。 例如，以玻璃來說，可列舉出無鹼玻璃、鹼玻璃、硼矽酸玻璃、石英玻璃、藍寶石玻璃、感光性玻璃等，亦可使用以矽酸鹽作為主要成分之任一種玻璃材料。 再者，亦可使用其他常說的玻璃材料。惟，在本揭示之基板1安裝半導體使用的情況，宜使用無鹼玻璃。 又，玻璃基板的厚度宜為1mm以下，但考慮玻璃之貫通孔形成製程之容易性或製造時之操作性，較佳為0.1mm以上、且0.8mm以下。 ＜Description of each element＞ Hereinafter, the material, shape, etc. of each element of the MIM capacitor which is a premise of the manufacturing method of the present invention will be described in detail. (substrate) The substrate 1 is preferably made of transparent glass with light penetration. There are no particular limitations on the components of the glass, the compounding ratio of each component contained in the glass, and the method of manufacturing the glass. For example, glass includes non-alkali glass, alkali glass, borosilicate glass, quartz glass, sapphire glass, photosensitive glass, etc. Any glass material containing silicate as a main component can also be used. Furthermore, other glass materials that are commonly used can also be used. However, in the case where the substrate 1 of the present disclosure is mounted with a semiconductor, it is preferable to use alkali-free glass. Also, the thickness of the glass substrate is preferably 1 mm or less, but it is preferably 0.1 mm or more and 0.8 mm or less in consideration of the ease of the glass through-hole forming process and the ease of manufacture.
以玻璃基板之製造方法來說，可舉出浮式(float)法、下拉(down-draw)法、熔融(fusion)法、上拉(up-draw))法、輥出(roll-out)法等，可以使用藉由任一方法所製得之玻璃材料，不限於本實施形態。玻璃的線膨脹係數係-1ppm/K以上且15.0ppm/K以下為佳。 其理由為：在-1ppm/K以下時，就很難選定玻璃材料本身，不能廉價製造。另一方面，在15.0ppm/K以上時，與其他層之間熱膨脹係數的差異很大，可靠性降低。又，在基板1安裝矽晶片時，使與矽晶片連接之連接可靠性降低。 另，玻璃的線膨脹係數希望較佳為0.5ppm/K以上且8.0ppm/K以下、更佳為1.0ppm/K以上且4.0ppm/K以下。 在玻璃基板亦可事先形成抗反射膜或IR截止濾光片等功能膜。又，亦可賦予強度、賦予抗靜電、賦予著色、紋理(texture)控制等之功能。以該等功能膜的例子來說，關於強度賦予，可舉出硬塗膜，關於抗靜電賦予，可舉出抗靜電膜，關於著色，可舉出光學濾波膜，關於紋理控制，可舉出抗眩光膜、光散射膜等，但不在此限。對該等功能膜之形成方法來說，可使用蒸鍍、濺鍍法、濕式等之成膜技術。 For the manufacturing method of the glass substrate, there are float method, down-draw method, fusion method, up-draw method, roll-out method, etc. method, etc., the glass material produced by any method can be used, and it is not limited to this embodiment. The linear expansion coefficient of glass is preferably -1 ppm/K or more and 15.0 ppm/K or less. The reason is that when it is -1ppm/K or less, it is difficult to select the glass material itself, and it cannot be manufactured at low cost. On the other hand, when it is 15.0 ppm/K or more, the difference in thermal expansion coefficient with other layers becomes large, and reliability falls. Also, when the silicon chip is mounted on the substrate 1, the connection reliability with the silicon chip is lowered. In addition, the coefficient of linear expansion of glass is preferably from 0.5 ppm/K to 8.0 ppm/K, more preferably from 1.0 ppm/K to 4.0 ppm/K. Functional films such as an anti-reflection film or an IR cut filter may also be formed on the glass substrate in advance. In addition, functions such as strength, antistatic, coloring, and texture control can also be imparted. Taking the example of these functional films as an example, hard coating film can be mentioned for strength imparting, antistatic film can be mentioned for antistatic imparting, optical filter film can be mentioned for coloring, and optical filter film can be mentioned for texture control. Anti-glare film, light-scattering film, etc., but not limited thereto. For the formation method of such functional films, film formation techniques such as vapor deposition, sputtering, and wet methods can be used.
(第1種子層) 構成第1種子層3之金屬層是在半加成工法中形成配線用當中，作為電解電鍍之供電層來作用。 設置在基板1之正上方及形成基板1的貫通孔內壁之種子金屬層是藉由例如濺鍍法或CVD法所形成，且使用例如Cu、Ni、Al、Ti、Cr、Mo、W、Ta、Au、Ir、Ru、Pd、Pt、AlSi、AlSiCu、AlCu、NiFe、ITO、IZO、AZO、ZnO、PZT、TiN、Cu 3N 4、Cu合金單體或將複數種組合者。 在本揭示之第1種子層3的上方亦可形成無電解電鍍層(無電解鍍銅、無電解鍍鎳等)。 (First Seed Layer) The metal layer constituting the first seed layer 3 functions as a power supply layer for electrolytic plating during the formation of wiring by the semi-additive process. The seed metal layer disposed directly above the substrate 1 and forming the inner wall of the through-hole of the substrate 1 is formed by, for example, a sputtering method or a CVD method, and is formed using, for example, Cu, Ni, Al, Ti, Cr, Mo, W, Ta, Au, Ir, Ru, Pd, Pt, AlSi, AlSiCu, AlCu, NiFe, ITO, IZO, AZO, ZnO, PZT, TiN, Cu 3 N 4 , Cu alloy alone or in combination. An electroless plating layer (electroless copper plating, electroless nickel plating, etc.) may also be formed on the first seed layer 3 of the present disclosure.
(密接層) 在本揭示之實施形態中，在基板1或第1絕緣層6的上方形成種子層之前，在基板1或第1絕緣層6的上面，考慮電氣特性、製造容易性的觀點及成本面，宜將藉由濺鍍法而沉積的鈦形成為密接層2。 在電容器中，下部密接層5具有使下部電極亦即第1導電層與介電質層之密接性提升的功能，上部密接層7具有使介電質層與種子金屬層之密接性提升的功能。下部密接層及上部密接層之材質為例如Ti。另外，亦可使用例如Cu、Ni、Al、Cr、Mo、W、Ta、Au、Ir、Ru、Pd、Pt、AlSi、AlSiCu、AlCu、NiFe、Cu合金單體或將複數種組合者。從密接性、導電性、製造容易性的觀點及成本面來看，Ti是優異的。 (adhesive layer) In the embodiments of the present disclosure, before the seed layer is formed on the substrate 1 or the first insulating layer 6, it is preferable to form the seed layer on the substrate 1 or the first insulating layer 6 in view of electrical characteristics, ease of manufacture, and cost. Titanium deposited by sputtering was formed as the adhesion layer 2 . In the capacitor, the lower adhesion layer 5 has the function of improving the adhesion between the lower electrode, that is, the first conductive layer, and the dielectric layer, and the upper adhesion layer 7 has the function of improving the adhesion between the dielectric layer and the seed metal layer. . The material of the lower adhesive layer and the upper adhesive layer is, for example, Ti. In addition, for example, Cu, Ni, Al, Cr, Mo, W, Ta, Au, Ir, Ru, Pd, Pt, AlSi, AlSiCu, AlCu, NiFe, Cu alloy alone or a combination of plural types can also be used. Ti is excellent in terms of adhesion, conductivity, ease of manufacture, and cost.
下部密接層及上部密接層的厚度宜為例如10nm以上且1μm以下。當小於10nm時，密接強度有不充分之虞。當超過1μm時，在後述之製程中，耗費成膜時間過長，不僅不利於量產性，在去除不要部分的步驟中亦有耗費時間之虞。下部密接層及上部密接層的厚度宜較佳為10nm以上且500nm以下。 下部密接層及上部密接層各自的厚度亦可不同，但為了讓構造上簡潔呈現，宜為相同厚度。又，當下部電極與介電質層充分密接時，沒有下部密接層亦無妨。當介電質層與種子金屬層充分密接時，沒有上部密接層亦無妨。 The thickness of the lower adhesive layer and the upper adhesive layer is preferably, for example, not less than 10 nm and not more than 1 μm. When it is less than 10 nm, the adhesion strength may be insufficient. When the thickness exceeds 1 μm, it takes too long to form a film in the process described later, which is not only detrimental to mass production, but also may take time in the step of removing unnecessary parts. The thickness of the lower adhesive layer and the upper adhesive layer is preferably not less than 10 nm and not more than 500 nm. The respective thicknesses of the lower adhesive layer and the upper adhesive layer may also be different, but they are preferably the same thickness in order to present a simple structure. In addition, if the lower electrode is sufficiently in close contact with the dielectric layer, it does not matter if there is no lower close contact layer. When the dielectric layer and the seed metal layer are sufficiently in close contact, it does not matter if there is no upper close contact layer.
(配線) 形成在基板1之密接層2、第1種子層3及第1導電層4係在基板1上形成有MIM電容器以外的區域上，可作為電路形成用之配線使用。為了作為電路使用，鈦與銅層之合計膜厚，從對於藉由半加成法形成微細配線有利的情形來看，宜為5μm以下。當比5μm厚時，有難以形成間距30μm以下的微細配線之情形。 以第1導電層之形成方法來說，若考慮也作為電路來使用時，因為電解鍍銅簡便且價廉，電傳導性良好，故較佳。然，除了電解鍍銅之外，亦可為電解鍍鎳、電解鍍鉻、電解鍍Pd、電解鍍金、電解鍍銠、電解鍍銥等。 (wiring) The adhesive layer 2, the first seed layer 3, and the first conductive layer 4 formed on the substrate 1 are formed on the substrate 1 other than the area where the MIM capacitor is formed, and can be used as wiring for circuit formation. For use as a circuit, the total film thickness of the titanium and copper layers is preferably 5 μm or less because it is advantageous for forming fine wiring by the semi-additive method. When it is thicker than 5 μm, it may be difficult to form fine wiring with a pitch of 30 μm or less. As for the formation method of the first conductive layer, in consideration of its use as a circuit, electrolytic copper plating is preferable because it is simple and inexpensive, and has good electrical conductivity. Of course, in addition to electrolytic copper plating, electrolytic nickel plating, electrolytic chrome plating, electrolytic Pd plating, electrolytic gold plating, electrolytic rhodium plating, electrolytic iridium plating, etc. can also be used.
(第1絕緣層) 從絕緣性、介電常數的觀點來看，第1絕緣層6亦即介電質層係可從氧化鋁、二氧化矽、氮化矽、氧化鉭、氧化鈦、鈦酸鈣、鈦酸鋇、鈦酸鍶來選擇。 介電質層的厚度宜為10nm以上且5μm以下。當介電質層的厚度為10nm以下時，不能保持絕緣性，不會呈現出作為電容器的功能。當介電質層的厚度為5μm以上時，耗費成膜時間太多，不僅不利於量產性，在去除不要部分的步驟中更耗時。宜較佳為50nm以上且1μm以下。 (1st insulating layer) From the perspective of insulation and dielectric constant, the first insulating layer 6, that is, the dielectric layer system, can be made of aluminum oxide, silicon dioxide, silicon nitride, tantalum oxide, titanium oxide, calcium titanate, barium titanate, etc. , Strontium titanate to choose. The thickness of the dielectric layer is preferably not less than 10 nm and not more than 5 μm. When the thickness of the dielectric layer is 10 nm or less, insulation cannot be maintained, and the function as a capacitor cannot be exhibited. When the thickness of the dielectric layer is more than 5 μm, it takes too much time to form a film, which is not conducive to mass production, and takes more time in the step of removing unnecessary parts. Preferably, it is 50 nm or more and 1 μm or less.
(第2種子層) 第2種子層8係用以藉由半加成法形成作為電容器之第2導電層即上部電極的供電層。第2種子層8係可適用例如Cu、Ni、Al、Ti、Cr、Mo、W、Ta、Au、Ir、Ru、Pd、Pt、AlSi、AlSiCu、AlCu、NiFe、Cu合金單體或組合複數種者。為了後續的蝕刻去除變得簡便，以銅為佳。 種子金屬層的厚度，期望為50nm以上、且5μm以下。種子金屬層的厚度在小於50nm的情況，有可能在接下來的電解鍍敷步驟中發生通電不良。當種子金屬層的厚度超過5μm，會在蝕刻去除上花時間。種子金屬層的厚度，更佳為100nm以上且500nm以下更佳。 (2nd seed layer) The second seed layer 8 is used to form the power supply layer which is the second conductive layer of the capacitor, that is, the upper electrode by the semi-additive method. The second seed layer 8 can be used, for example, Cu, Ni, Al, Ti, Cr, Mo, W, Ta, Au, Ir, Ru, Pd, Pt, AlSi, AlSiCu, AlCu, NiFe, Cu alloy alone or in combination. species. For ease of subsequent etching and removal, copper is preferred. The thickness of the seed metal layer is desirably not less than 50 nm and not more than 5 μm. When the thickness of the seed metal layer is less than 50 nm, there is a possibility that poor conduction may occur in the subsequent electrolytic plating step. When the thickness of the seed metal layer exceeds 5 μm, it takes time for etching removal. The thickness of the seed metal layer is more preferably not less than 100 nm and more preferably not more than 500 nm.
(第2導電層) 第2導電層9即上部電極為電解電鍍層。因為電解鍍銅簡便且價廉，且導電性良好，故較佳。然，除了電解鍍銅之外，亦可為電解鍍鎳、電解鍍鉻、電解鍍Pd、電解鍍金、電解鍍銠、電解鍍銥等。 上部電極的厚度(電解鍍銅的厚度)期望為3μm以上且30μm以下。在小於3μm的情況，依據形成有上部電極之後的蝕刻處理，而有電路會消失之虞。再者，還有造成電路的連接可靠性、導電性降低的危險性。當電解鍍銅的厚度超過30μm，就必須形成厚度達30μm以上的光阻層，無法抑制製造成本。再者，因為光阻影像解析度會降低，因此形成間距30μm以下的微細的配線就變得困難。更佳為5μm以上、且25μm以下更佳。再者，再更佳為10μm以上、且20μm以下。 (2nd conductive layer) The second conductive layer 9, that is, the upper electrode is an electrolytic plating layer. Electrolytic copper plating is preferable because it is simple and inexpensive, and has good electrical conductivity. Of course, in addition to electrolytic copper plating, electrolytic nickel plating, electrolytic chrome plating, electrolytic Pd plating, electrolytic gold plating, electrolytic rhodium plating, electrolytic iridium plating, etc. can also be used. The thickness of the upper electrode (thickness of electrolytic copper plating) is desirably not less than 3 μm and not more than 30 μm. If the thickness is less than 3 μm, the circuit may be lost due to the etching process after the upper electrode is formed. Furthermore, there is a risk of lowering the connection reliability and conductivity of the circuit. When the thickness of the electrolytic copper plating exceeds 30 μm, it is necessary to form a photoresist layer with a thickness of more than 30 μm, which cannot suppress the manufacturing cost. Furthermore, since the resolution of the photoresist image decreases, it becomes difficult to form fine wiring with a pitch of 30 μm or less. More preferably, it is not less than 5 μm and more preferably not more than 25 μm. Furthermore, it is still more preferably 10 μm or more and 20 μm or less.
[習知例之製造方法] 其次，參照圖2至6，針對製造具有如圖1所示之構造之MIM電容器之配線基板時的習知例作說明。 首先，如圖2所示，在表面具有絕緣性的基板1之上方形成密接層2及第1種子層3，且在其上形成阻劑11的圖案。 接著，如圖3所示，將第1種子層3作為供電層，藉由電解電鍍來形成第1導電層4。 接著，如圖4所示，將阻劑11去除，如圖5所示，將第1導電層4作為蝕刻遮罩，將密接層2及第1種子層3之不要部分去除。 惟，一旦採用了上述之製造方法，如圖6之X所示，在第1導電層4之端部周邊的區域中，有產生密接層2及第1種子層3的側邊蝕刻的情況。密接層2及第1種子層3因為膜厚小，所以在x方向上的蝕刻之進行速度快，很難防止側邊蝕刻的情況。 [Manufacturing method of conventional example] Next, with reference to FIGS. 2 to 6, a conventional example of manufacturing a wiring board having a MIM capacitor having the structure shown in FIG. 1 will be described. First, as shown in FIG. 2 , an adhesion layer 2 and a first seed layer 3 are formed on a substrate 1 having an insulating surface, and a pattern of a resist 11 is formed thereon. Next, as shown in FIG. 3 , the first conductive layer 4 is formed by electrolytic plating using the first seed layer 3 as a power supply layer. Next, as shown in FIG. 4 , the resist 11 is removed, and as shown in FIG. 5 , using the first conductive layer 4 as an etching mask, unnecessary portions of the adhesion layer 2 and the first seed layer 3 are removed. However, once the above-mentioned manufacturing method is adopted, side etching of the adhesive layer 2 and the first seed layer 3 may occur in the region around the end of the first conductive layer 4 as shown by X in FIG. 6 . Since the thickness of the adhesive layer 2 and the first seed layer 3 is small, the etching speed in the x direction is fast, and it is difficult to prevent side etching.
在MIM構造之製造步驟中，在製作下部電極即第1導電層4之後，形成作為介電質層之第1絕緣層6，在第1絕緣層6的上方形成了上部密接層7及第2種子層8之後，對第2種子層供電，作成成為上部電極之第2導電層9。 此時，在藉由濺鍍法來形成上部密接層7及第2種子層8的情況，對下部電極層亦即第1導電層4之側壁濺鍍覆膜之均鍍力(THROWING POWER)很大程度是取決於第1導電層4之端部的形狀。 因此，如圖6所示，在密接層2及第1種子層3一旦產生側邊蝕刻，藉由濺鍍之覆膜的均鍍力就變得不充分，使第2種子層8形成不連續。結果在藉由電解電鍍形成第2導電層9時，無法進行供電，而發生無法形成電鍍覆膜的問題。 In the manufacturing steps of the MIM structure, after the first conductive layer 4, which is the lower electrode, is formed, the first insulating layer 6 as a dielectric layer is formed, and the upper adhesive layer 7 and the second insulating layer 6 are formed on the first insulating layer 6. After the seed layer 8, power is supplied to the second seed layer to form the second conductive layer 9 to be the upper electrode. At this time, in the case of forming the upper adhesive layer 7 and the second seed layer 8 by sputtering, the throwing power (THROWING POWER) of the sputtered film on the side wall of the lower electrode layer, that is, the first conductive layer 4 is very low. It largely depends on the shape of the end portion of the first conductive layer 4 . Therefore, as shown in FIG. 6, once side etching occurs in the adhesion layer 2 and the first seed layer 3, the throwing power of the coating film by sputtering becomes insufficient, and the second seed layer 8 is discontinuous. . As a result, when the second conductive layer 9 is formed by electrolytic plating, power supply cannot be performed, and a problem that a plating film cannot be formed occurs.
進而，當將如圖6所示之第1導電層4作為蝕刻遮罩來進行密接層2及第1種子層3之蝕刻時，會損及第1導電層4之上側表面之平滑性，而對MIM電容器的精度或良率等產生不良影響。在這方面，依據本揭示之實施態樣，可以保持下部電極與介電質界面之平滑性，且可以減少因表面龜裂而引起之電容器的短路或因電極表面積偏差而引起的容量偏差。因此，可提高電容器的良率，可穩定地進行製造。Furthermore, when the first conductive layer 4 as shown in FIG. 6 is used as an etching mask to etch the adhesion layer 2 and the first seed layer 3, the smoothness of the upper surface of the first conductive layer 4 will be damaged, and It will adversely affect the accuracy or yield of MIM capacitors. In this regard, according to the implementation aspect of the present disclosure, the smoothness of the interface between the lower electrode and the dielectric can be maintained, and the short circuit of the capacitor caused by surface cracks or the capacitance deviation caused by the deviation of the electrode surface area can be reduced. Therefore, the yield of the capacitor can be improved, and stable manufacturing can be performed.
[第1實施形態] 為了解決如上述之習知的製造方法的課題，針對本發明的第1實施形態，乃採用如下記述之製造方法。 以下，參考圖2至圖4及圖7至圖11說明第1實施形態。 [First Embodiment] In order to solve the problems of the conventional production method as described above, the production method described below is adopted for the first embodiment of the present invention. Hereinafter, the first embodiment will be described with reference to FIGS. 2 to 4 and FIGS. 7 to 11 .
(步驟1) 關於第1實施形態之步驟1至步驟6，與習知例相同，因此參考圖2至圖4進行說明。 首先，儘管在圖2至圖11、圖13至17中未圖示，但基板1是可具有從基板1之上側表面貫穿至下側表面之貫通孔。貫通孔的截面形狀或孔徑，可為例如貫通孔之中央部的孔徑比頂部孔徑和底部孔徑還狹窄的形狀，又，亦可為例如底部孔徑相對於頂部孔徑為小的形狀。再者，亦可為中央部的孔徑比貫通孔的頂部孔徑和底部孔徑還寬的形狀。 (step 1) Steps 1 to 6 of the first embodiment are the same as those of the conventional example, so they will be described with reference to FIGS. 2 to 4 . First, although not shown in FIGS. 2 to 11 and FIGS. 13 to 17 , the substrate 1 may have through holes penetrating from the upper surface to the lower surface of the substrate 1 . The cross-sectional shape or diameter of the through-hole may be, for example, a shape in which the central portion of the through-hole is narrower than the top and bottom diameters, or may be, for example, a shape in which the bottom diameter is smaller than the top diameter. Furthermore, the diameter of the central portion may be wider than the diameters of the top and bottom of the through-holes.
(步驟2) 其次，如圖2所示，在基板1的表面形成密接層2及第1種子層3。若在形成有貫通孔的情況，在貫通孔內亦形成密接層2及第1種子層3。該等密接層2及第1種子層3係於半加成工法之配線形成步驟中，作為電解電鍍的供電層發揮作用。 密接層2及第1種子層3之形成步驟宜為：在基板1藉由濺鍍法形成鈦，作為密接層2，隨後，藉由濺鍍法形成銅層，作為第1種子層3，再於此之後，藉由無電解電鍍，附加形成金屬層。一旦只藉由濺鍍法形成鈦、銅層，就會有使得金屬覆膜無法均勻地形成在貫通孔的內壁之情況。因此，期望藉由無電解電鍍法補強金屬層。無電解電鍍層係可舉出無電解鍍銅、無電解鍍鎳，由於與玻璃或者鈦、銅層之密接性良好來看，以無電解鍍鎳為佳。 若鍍鎳層過厚，有難以形成微細配線的情況。又，因膜應力的增加，亦有使密接性降低的情況。因此，無電解電鍍之厚度係以1μm以下為佳。又，0.5μm以下較佳，0.3μm以下更佳。 又，在無電解鍍鎳覆膜亦可含有源自還原劑之共析物的磷，或無電解鍍鎳液中所包含之硫、鉛或鉍等。經過以上的步驟，可得到在形成有貫通孔之玻璃基板上形成有種子金屬層之基板。 (step 2) Next, as shown in FIG. 2 , the adhesion layer 2 and the first seed layer 3 are formed on the surface of the substrate 1 . When a through hole is formed, the adhesive layer 2 and the first seed layer 3 are also formed in the through hole. The adhesive layer 2 and the first seed layer 3 function as a power supply layer for electrolytic plating in the wiring formation step of the semi-additive process. The steps of forming the adhesion layer 2 and the first seed layer 3 are preferably as follows: form titanium on the substrate 1 by sputtering as the adhesion layer 2, then form a copper layer by sputtering as the first seed layer 3, and then After that, a metal layer is additionally formed by electroless plating. Once the titanium and copper layers are formed only by sputtering, the metal coating may not be uniformly formed on the inner walls of the through-holes. Therefore, it is desirable to reinforce the metal layer by electroless plating. Examples of the electroless plating layer include electroless copper plating and electroless nickel plating, and electroless nickel plating is preferable because of good adhesion to glass, titanium, and copper layers. If the nickel plating layer is too thick, it may be difficult to form fine wiring. In addition, due to an increase in film stress, the adhesiveness may be lowered. Therefore, the thickness of the electroless plating is preferably less than 1 μm. Also, the thickness is preferably not more than 0.5 μm, more preferably not more than 0.3 μm. In addition, the electroless nickel plating film may contain phosphorus derived from the eutectoid of the reducing agent, or sulfur, lead, or bismuth contained in the electroless nickel plating solution. Through the above steps, the substrate with the seed metal layer formed on the glass substrate with the through holes can be obtained.
(步驟3) 接著，如圖2所示，在第1種子層的上方形成藉由阻劑11所形成的圖案。藉由阻劑11所形成之圖案的形成方法係首先在第1種子層上全面形成阻劑11之層。所採用的阻劑可舉出負型乾膜阻劑、負型液狀阻劑、正型液狀阻劑，由於阻劑層之形成簡便且廉價，因此負型光阻為佳。 (step 3) Next, as shown in FIG. 2 , a pattern formed by the resist 11 is formed on the first seed layer. In the method of forming the pattern formed by the resist 11, first, the layer of the resist 11 is formed on the entire surface of the first seed layer. The resist used can include negative dry film resist, negative liquid resist, and positive liquid resist. Since the formation of the resist layer is simple and inexpensive, negative photoresist is preferred.
(步驟4) 接著，藉由公知之光刻法來形成用以於光阻層形成所期望的導體電路層之圖案。亦即，阻劑11之圖案係藉由以供後續之導體電路層形成的部分會露出之方式進行對準、曝光、顯影處理，來實現圖案化。阻劑層的厚度亦視導體電路層的厚度而定，5μm以上較佳，宜為25μm以下。小於5μm時，就無法將成為導體電路層之電解電鍍層的膜厚增加到5μm以上，電路之連接可靠性有可能降低。若大於25μm時，間距30μm以下的微細配線形成變得困難。藉此，得到形成有光阻圖案之基板。 (step 4) Next, a pattern for forming a desired conductor circuit layer on the photoresist layer is formed by a known photolithography method. That is, the pattern of the resist 11 is patterned by performing alignment, exposure, and development so that a portion for subsequent conductor circuit layer formation is exposed. The thickness of the resist layer also depends on the thickness of the conductive circuit layer, preferably more than 5 μm, preferably less than 25 μm. If it is less than 5 μm, the film thickness of the electroplating layer that becomes the conductive circuit layer cannot be increased to more than 5 μm, and the connection reliability of the circuit may be lowered. If it exceeds 25 μm, it becomes difficult to form fine wiring with a pitch of 30 μm or less. In this way, a substrate on which a photoresist pattern is formed is obtained.
(步驟5) 接著，藉由對第1種子層供電，浸泡在鍍敷液，而在未形成有光阻圖案之第1種子層的上面，形成在後面會成為導體電路層之第1導電層亦即電解電鍍層。 (step 5) Then, by supplying power to the first seed layer, soaking in the plating solution, and forming the first conductive layer that will later become the conductor circuit layer on the top of the first seed layer without a photoresist pattern, that is, electrolytic plating layer.
(步驟6) 接著，去除已成為不需要的光阻圖案，如圖4所示，將第1導電層與第1種子層3露出。另，阻劑11之去除方法並不限於任何特定的方法，但例如可以藉由鹼水溶液來剝離去除。 (step 6) Next, the unnecessary photoresist pattern is removed to expose the first conductive layer and the first seed layer 3 as shown in FIG. 4 . In addition, the removal method of the resist 11 is not limited to any specific method, but it can be stripped and removed by an aqueous alkali solution, for example.
(步驟7) 接著，如圖7所示，以涵蓋第1導電層4亦即下部電極上全面的方式，依序堆積形成下部密接層5、第1絕緣層6、上部密接層7及第2種子層8。以上述層之成膜方法來說，可舉出真空蒸鍍法、濺鍍法、離子電鍍法、MBE法、雷射剝離法、CVD法等，但不受限於本實施形態。 位於第1絕緣層6之下層的下部密接層5具有使第1絕緣層6與第1導電層4之密接性提升的功能。惟，在第1絕緣層6與第1導電層4之密接性充分的情況，即使沒有下部密接層5也無妨。 在本實施形態中，在形成第1導電層之後，在不蝕刻第1種子層的情形下形成第1絕緣層及第2種子層等。因此，在形成第2種子層時，可以抑制第2種子層之均鍍性的異常。結果針對第2導電層亦可以穩定地形成。 另，第2種子層是作為供電層發揮作用，其是用以藉由半加成法來形成電容器之上部電極。 (step 7) Next, as shown in FIG. 7 , the lower adhesive layer 5 , the first insulating layer 6 , the upper adhesive layer 7 , and the second seed layer 8 are sequentially deposited to cover the entire surface of the first conductive layer 4 , that is, the lower electrode. Examples of the film-forming method of the above layer include vacuum evaporation method, sputtering method, ion plating method, MBE method, laser lift-off method, CVD method, etc., but are not limited to this embodiment. The lower adhesive layer 5 located under the first insulating layer 6 has a function of improving the adhesiveness between the first insulating layer 6 and the first conductive layer 4 . However, when the adhesiveness between the first insulating layer 6 and the first conductive layer 4 is sufficient, there is no problem without the lower adhesive layer 5 . In this embodiment, after forming the first conductive layer, the first insulating layer, the second seed layer, and the like are formed without etching the first seed layer. Therefore, when forming the second seed layer, it is possible to suppress the abnormality of the throwing property of the second seed layer. As a result, the second conductive layer can also be stably formed. In addition, the second seed layer functions as a power supply layer, and is used to form the upper electrode of the capacitor by the semi-additive method.
(步驟8) 接著，如圖8所示，在第2種子層8之上面，將阻劑11的圖案形成在形成第2導電層9以外的區域。阻劑11的圖案之形成係可藉由與前述之光阻圖案相同的方法進行。在這情況，阻劑11的圖案之開口區域是以成為第1導電層4(下部電極)更內側的方式形成，在積層方向上之平面視角下，除朝MIM電容器之外部連接之連接線的部分之外，也以成為第1導電層4(下部電極)內側的方式形成。 (step 8) Next, as shown in FIG. 8 , on the second seed layer 8 , a pattern of a resist 11 is formed in a region other than where the second conductive layer 9 is formed. The formation of the pattern of the resist 11 can be performed by the same method as the aforementioned photoresist pattern. In this case, the opening area of the pattern of the resist 11 is formed so as to be further inside the first conductive layer 4 (lower electrode), and when viewed from a plane in the lamination direction, the connection line connected to the outside of the MIM capacitor is excluded. Other parts are also formed so as to be inside the first conductive layer 4 (lower electrode).
(步驟9) 接著，對第2種子層供電，藉由電解電鍍法形成第2導電層9(上部電極)。 (step 9) Next, power is supplied to the second seed layer, and the second conductive layer 9 (upper electrode) is formed by electrolytic plating.
(步驟10) 接著，去除阻劑11的圖案。光阻圖案之去除可以藉由公知方法之鹼水溶液來進行去除剝離處理。 (step 10) Next, the pattern of the resist 11 is removed. The removal of the photoresist pattern can be carried out by a known method of alkali aqueous solution for removal and stripping.
(步驟11) 接著，如圖9所示，以圍繞第2導電層9(上部電極)的方式形成阻劑11的圖案。阻劑11的圖案之形成係可以與前述之光阻圖案相同的方法進行。在這情況，光阻圖案之非開口區域係以成為比上部電極更外側，且第1導體層(下部電極)之內側的方式形成，在積層方向上之平面視角下，除朝MIM電容器之外部連接之連接線的部分之外，也以成為第1導電層4(下部電極)內側的方式形成。 藉此，以使第2種子層8、上部密接層7、第1絕緣層6、下部密接層5之端面各自成為第2導電層的外側且第1導電層的內側的方式進行蝕刻，而形成MIM電容器構造。 (step 11) Next, as shown in FIG. 9 , a resist 11 is patterned so as to surround the second conductive layer 9 (upper electrode). The formation of the pattern of the resist 11 can be performed by the same method as the aforementioned photoresist pattern. In this case, the non-aperture region of the photoresist pattern is formed so that it is outside the upper electrode and inside the first conductor layer (lower electrode), except for the outside of the MIM capacitor when viewed from a plane in the stacking direction. The portion other than the connecting wire is also formed so as to be inside the first conductive layer 4 (lower electrode). In this way, the end faces of the second seed layer 8, the upper adhesive layer 7, the first insulating layer 6, and the lower adhesive layer 5 are etched so that they are respectively outside the second conductive layer and inside the first conductive layer. MIM capacitor construction.
(步驟12) 另，第2種子層8及上部密接層7之不要部分的去除係不限於在本步驟實施，例如，亦可在步驟11之前將上部電極作為遮罩，將第2種子層8及上部密接層7的不要部分除去。如此一來，使MIM電容器元件之外表面中之第1絕緣層6的面積變大，可以抑制來自上部電極及下部電極間之側面的電流洩漏等。 (step 12) In addition, the removal of unnecessary parts of the second seed layer 8 and the upper adhesive layer 7 is not limited to this step, for example, the upper electrode can also be used as a mask before step 11, and the second seed layer 8 and the upper adhesive layer The unnecessary part of 7 is removed. In this way, the area of the first insulating layer 6 on the outer surface of the MIM capacitor element is increased, and current leakage from the side surface between the upper electrode and the lower electrode can be suppressed.
(步驟13) 接著，去除阻劑11的圖案。光阻圖案之去除可以藉由公知方法之鹼水溶液來進行去除剝離處理。 (step 13) Next, the pattern of the resist 11 is removed. The removal of the photoresist pattern can be carried out by a known method of alkali aqueous solution for removal and stripping.
(步驟14) 接著，如圖10所示，再次連同第1導電層4也圍繞的方式形成阻劑11的圖案。亦即，阻劑11的圖案係以於至少1個寬度方向(正交於z軸之xy平面上的方向)上成為寬度比前述第1導電層更大之蝕刻遮罩的方式，形成阻劑11的圖案。 亦即，寬度比前述第1導電層更大之蝕刻遮罩的寬度係成為相當於MIM電容器中之第1種子層3的寬度。在這情況，光阻圖案之非開口區域係以成為比下部電極更外側的方式形成，在積層方向上之平面視角下，除朝MIM電容器之外部連接之連接線的部分之外，也以成為第1導電層4(下部電極)外側的方式形成。 (step 14) Next, as shown in FIG. 10 , a pattern of resist 11 is formed so as to surround the first conductive layer 4 again. That is, the pattern of the resist 11 is formed in such a way that it becomes an etching mask having a width larger than that of the first conductive layer in at least one width direction (direction on the xy plane perpendicular to the z axis). 11 patterns. That is, the width of the etching mask larger than that of the first conductive layer is equivalent to the width of the first seed layer 3 in the MIM capacitor. In this case, the non-aperture region of the photoresist pattern is formed so as to be outside the lower electrode, and when viewed from a plane in the stacking direction, except for the part of the connection line connected to the outside of the MIM capacitor, it also becomes The outer side of the first conductive layer 4 (lower electrode) is formed.
更具體來說，至少一個方向上之阻劑11在xy平面(水平方向)上之寬度b與在相同方向上之第1導電層(下部電極)在xy平面上之寬度a之關係，當然滿足以下的數式(1)。 [數式1] a＜b ･･･(1) 進而，較佳為a、b滿足以下的數式(2)。 [數式2] 50nm≦(b-a)/2≦50μm ･･･(2) 另，在數式(2)中，「(b-a)/2」是表示第1導電層(下部電極)4與阻劑11在單側上之寬度之差。將該單側上之寬度之差的上限設為50μm，是因為比該值大時，對圖案之設計上產生限制的緣故。 再者，密接層2與第1種子層3在z軸方向的高度(2層之合計厚度)c較佳為滿足以下的數式(3)。 [數式3] 50nm≦c≦5μm ･･･(3) 另，在數式(3)中將c的下限設為50nm，是因為密接層2及第1種子層3作為供電層而發揮功能之最低值來說必須為50nm的緣故。又，將c的上限設為5μm，是因為在蝕刻種子層時，對可形成之配線寬度產生限制的緣故。 再者，a、b、c較佳為滿足以下的數式(4)。 [數式4] 0.01≦((b-a)/2)/c≦1000 ･･･(4) 只要是滿足數式(4)的形狀，迄至第1導電層(下部電極)的下方亦不會產生側邊蝕刻，在之後的步驟中，可在無斷線不良且充分穩定的狀態下形成第2種子層。 另，阻劑圖案之形成方法係可以與前述光阻圖案相同的方法來進行。 More specifically, the relationship between the width b of the resist 11 on the xy plane (horizontal direction) in at least one direction and the width a of the first conductive layer (lower electrode) on the xy plane in the same direction, of course satisfies The following formula (1). [Formula 1] a<b ･･･(1) Furthermore, it is preferable that a and b satisfy the following formula (2). [Formula 2] 50nm≦(b-a)/2≦50μm ･･･(2) In addition, in the formula (2), "(b-a)/2" represents the difference in the width of the first conductive layer (lower electrode) 4 and the resist 11 on one side. The upper limit of the difference in width on one side is set at 50 μm because, if it is larger than this value, there will be restrictions on the design of the pattern. In addition, it is preferable that the height (total thickness of the two layers) c of the adhesive layer 2 and the first seed layer 3 in the z-axis direction satisfies the following formula (3). [Formula 3] 50nm≦c≦5μm ･･･(3) In addition, the lower limit of c in Equation (3) is set to 50 nm because the minimum value for the adhesion layer 2 and the first seed layer 3 to function as a power supply layer must be 50 nm. Also, the upper limit of c is set to 5 μm because the wiring width that can be formed is limited when the seed layer is etched. Furthermore, a, b, and c preferably satisfy the following formula (4). [Formula 4] 0.01≦((b-a)/2)/c≦1000 ･･･(4) As long as the shape satisfies the formula (4), side etching will not occur up to the bottom of the first conductive layer (lower electrode), and in the subsequent steps, it can be formed in a sufficiently stable state without disconnection defects. 2nd seed layer. In addition, the formation method of the resist pattern can be performed by the same method as the aforementioned photoresist pattern.
(步驟15) 接著，將第1種子層之露出的部分去除。 另，無電解Ni層、銅層、鈦層係可使用依序藉由化學蝕刻去除的方法。蝕刻液的種類係依去除的金屬種的不同適當地選擇，去除方法並不限於本揭示記載之方法。 (step 15) Next, the exposed portion of the first seed layer is removed. In addition, the electroless Ni layer, copper layer, and titanium layer can be sequentially removed by chemical etching. The type of etching solution is appropriately selected according to the metal species to be removed, and the removal method is not limited to the method described in this disclosure.
(步驟16) 接著，當將阻劑11的圖案去除時，如圖11所示，就可以形成形成有MIM電容器之配線基板。光阻圖案之去除是可藉由公知方法之鹼水溶液來進行去除剝離處理。藉由以上的步驟形成電容器。 (step 16) Next, when the pattern of the resist 11 is removed, as shown in FIG. 11 , a wiring board on which MIM capacitors are formed can be formed. The removal of the photoresist pattern can be carried out by a known method of alkali aqueous solution for removal and stripping. A capacitor is formed through the above steps.
(步驟17) 之後，如圖12所示，在配線基板上形成絕緣樹脂層12、通孔(via hole)13。之後，藉由反覆形成積層導體電路層與絕緣樹脂層，而形成多層配線基板。 另，配線基板上之導體電路或積層構造可以使用公知的半加成法或減成法形成。 再者，在形成多層配線基板之後，亦可形成外部連接端子，再者，亦可在外部連接端子形成焊料球。 依據本揭示之配線基板係於單面可具有積層導體電路層、外部連接端子、錫球，作為變形例，也可形成在兩面。再者亦可搭載半導體晶片、晶片零件。 (step 17) After that, as shown in FIG. 12 , an insulating resin layer 12 and via holes 13 are formed on the wiring board. After that, by repeatedly forming a laminated conductor circuit layer and an insulating resin layer, a multilayer wiring board is formed. In addition, the conductive circuit or the laminated structure on the wiring board can be formed using a known semi-additive method or subtractive method. Furthermore, after forming the multilayer wiring board, external connection terminals may be formed, and solder balls may be formed on the external connection terminals. The wiring board according to the present disclosure may have a laminated conductor circuit layer, external connection terminals, and solder balls on one side, or may be formed on both sides as a modified example. Furthermore, semiconductor chips and chip components can also be mounted.
[第2實施形態] 其次，在下文中，參考圖2至圖4及圖13至圖17說明第2實施形態。 在第2實施形態中，步驟1至步驟6和第1實施形態相同，因此針對步驟1至步驟6省略說明。 在第2實施形態中，在圖4所示之第1實施形態之步驟6之後，繼續以下要說明的步驟20。 [Second Embodiment] Next, hereinafter, a second embodiment will be described with reference to FIGS. 2 to 4 and FIGS. 13 to 17 . In the second embodiment, Step 1 to Step 6 are the same as those in the first embodiment, and therefore descriptions of Step 1 to Step 6 are omitted. In the second embodiment, after step 6 in the first embodiment shown in FIG. 4, step 20 to be described below continues.
(步驟20) 在第1實施形態之步驟6之後，如圖13所示，以圍繞第1導電層的方式形成阻劑11的圖案。光阻圖案之形成係可藉由與前述之阻劑圖案相同的方法進行。在這情況，阻劑圖案之非開口區域是以成為比下部電極更外側的方式形成，在積層方向上之平面視角下，除朝MIM電容器之外部連接之連接線的部分之外，也以成為第1導電層4(下部電極)外側的方式形成。 (step 20) After step 6 of the first embodiment, as shown in FIG. 13 , a resist 11 is patterned so as to surround the first conductive layer. The formation of the photoresist pattern can be performed by the same method as the aforementioned resist pattern. In this case, the non-opening region of the resist pattern is formed so as to be outside the lower electrode, and when viewed from the plane in the stacking direction, except for the part of the connecting line connected to the outside of the MIM capacitor, it also becomes The outer side of the first conductive layer 4 (lower electrode) is formed.
再者，此時的阻劑11在xy平面之長度b、在相同方向上之第1導電層(下部電極)在xy平面上之長度a、與密接層2和第1種子層3在z軸方向上之高度(2層之合計厚度)c之理想關係是和第1實施形態中之步驟14中所記述者相同。Furthermore, at this time, the length b of the resist 11 on the xy plane, the length a of the first conductive layer (lower electrode) in the same direction on the xy plane, and the length a of the contact layer 2 and the first seed layer 3 on the z axis The ideal relationship of the height (total thickness of two layers) c in the direction is the same as that described in step 14 in the first embodiment.
(步驟21) 接著，將阻劑11的圖案作為蝕刻遮罩，去除第1種子層3、密接層2。 另，第1種子層3、密接層2之去除可以使用藉由化學蝕刻，依序去除無電解Ni層、銅層、鈦層之方法。蝕刻液的種類係依去除的金屬種的不同而適當選擇，並沒有任何限制。 (step 21) Next, using the pattern of the resist 11 as an etching mask, the first seed layer 3 and the adhesion layer 2 are removed. In addition, the removal of the first seed layer 3 and the adhesion layer 2 can be performed by chemical etching to sequentially remove the electroless Ni layer, copper layer, and titanium layer. The type of etching solution is appropriately selected according to the metal species to be removed, and there is no limitation.
(步驟22) 接著，一將阻劑11的圖案去除，便可以得到圖14所示之剖面。 另，阻劑11之去除係能以公知方法之鹼水溶液進行去除剝離處理。 (step 22) Then, once the pattern of the resist 11 is removed, the cross section shown in FIG. 14 can be obtained. In addition, the removal of the resist 11 can be performed by a known method of alkali aqueous solution for removal and stripping.
(步驟23) 接著，如圖15所示，與第1實施態樣之步驟7同樣地，以涵蓋第1導電層4亦即下部電極上全面的方式，依序堆積形成下部密接層5、第1絕緣層6、上部密接層7及第2種子層8。以上述層之成膜方法來說，可舉出真空蒸鍍法、濺鍍法、離子電鍍法、MBE法、雷射剝離法、CVD法等，但未受限於本實施形態。 位於第1絕緣層6之下層的下部密接層5具有使第1絕緣層6與第1導電層4之密接性提升的功能。惟，在第1絕緣層6與第1導電層4之密接性充分的情況，即使沒有下部密接層5也無妨。 另，第2種子層是作為供電層發揮作用，其用以藉由半加成法來形成電容器之上部電極。 (step 23) Next, as shown in FIG. 15 , similarly to step 7 of the first embodiment, the lower adhesive layer 5 and the first insulating layer 6 are sequentially stacked to cover the entire surface of the first conductive layer 4 , that is, the lower electrode. , The upper adhesion layer 7 and the second seed layer 8 . Examples of the film-forming method of the above-mentioned layer include vacuum evaporation method, sputtering method, ion plating method, MBE method, laser lift-off method, CVD method, etc., but are not limited to this embodiment. The lower adhesive layer 5 located under the first insulating layer 6 has a function of improving the adhesiveness between the first insulating layer 6 and the first conductive layer 4 . However, when the adhesiveness between the first insulating layer 6 and the first conductive layer 4 is sufficient, there is no problem without the lower adhesive layer 5 . In addition, the second seed layer functions as a power supply layer, and is used to form the upper electrode of the capacitor by the semi-additive method.
(步驟24) 接著，如圖16所示，將阻劑11的圖案形成在形成第2導電層9以外的區域。阻劑11的圖案之形成係可藉由與前述之光阻圖案相同的方法進行。在這情況，阻劑11的圖案之開口區域是以成為比第1導電層4(下部電極)更內側的方式形成，在積層方向上之平面視角下，除朝MIM電容器之外部連接之連接線的部分之外，也以成為第1導電層4(下部電極)內側的方式形成。 (step 24) Next, as shown in FIG. 16 , a resist 11 is patterned in a region other than where the second conductive layer 9 is formed. The formation of the pattern of the resist 11 can be performed by the same method as the aforementioned photoresist pattern. In this case, the opening area of the pattern of the resist 11 is formed so as to be inside of the first conductive layer 4 (lower electrode), and when viewed from a plane in the lamination direction, the connection lines connected to the outside of the MIM capacitor are excluded. In addition to the part, it is also formed so as to be inside the first conductive layer 4 (lower electrode).
(步驟25) 接著，對第2種子層供電，藉由電解電鍍法形成第2導電層9(上部電極)。 (step 25) Next, power is supplied to the second seed layer, and the second conductive layer 9 (upper electrode) is formed by electrolytic plating.
(步驟26) 接著，去除阻劑11的圖案。光阻圖案之去除可以藉由公知方法之鹼水溶液來進行去除剝離處理。 (step 26) Next, the pattern of the resist 11 is removed. The removal of the photoresist pattern can be carried out by a known method of alkali aqueous solution for removal and stripping.
(步驟27) 接著，如圖17所示，以圍繞第2導電層9(上部電極)的方式形成阻劑11的圖案。阻劑11的圖案之形成係能以與前述之光阻圖案相同的方法進行。在這情況，光阻圖案之非開口區域係以成為比上部電極更外側，且第1導體層(下部電極)之內側的方式形成，在積層方向上之平面視角下，除朝MIM電容器之外部連接之連接線的部分之外，也以成為第1導電層4(下部電極)內側的方式形成。較佳為以分別成為外側、且內側的方式形成。 (step 27) Next, as shown in FIG. 17 , a resist 11 is patterned so as to surround the second conductive layer 9 (upper electrode). The formation of the pattern of the resist 11 can be performed by the same method as the aforementioned photoresist pattern. In this case, the non-aperture region of the photoresist pattern is formed so that it is outside the upper electrode and inside the first conductor layer (lower electrode), except for the outside of the MIM capacitor when viewed from a plane in the stacking direction. The portion other than the connecting wire is also formed so as to be inside the first conductive layer 4 (lower electrode). Preferably, they are formed so as to be respectively the outer side and the inner side.
(步驟28) 接著，與步驟12同樣，將阻劑11的圖案作為遮罩，將第2種子層8、上部密接層7、第1絕緣層6、及下部密接層5的不要部分去除。對於第2種子層8、上部密接層7、第1絕緣層及下部密接層5的去除，可實施使用化學蝕刻法、乾式蝕刻法等任何公知方法。亦可以在每層採用不同的除去方法，又，亦可在所有層進行相同的方法來除去。 如上述，阻劑11的圖案係形成在第1導電層4(下部電極)的內側，因此即使將阻劑11的圖案作為遮罩去除不要部分，第1絕緣層仍形成僅殘留在第1導電層(下部電極)之內側。 (step 28) Next, similarly to step 12, using the resist 11 pattern as a mask, unnecessary portions of the second seed layer 8, the upper adhesive layer 7, the first insulating layer 6, and the lower adhesive layer 5 are removed. For the removal of the second seed layer 8 , the upper adhesive layer 7 , the first insulating layer, and the lower adhesive layer 5 , any known method such as a chemical etching method or a dry etching method can be used. Different removal methods may be used for each layer, and the removal may be performed by the same method for all layers. As mentioned above, the pattern of resist 11 is formed inside the first conductive layer 4 (lower electrode), so even if the pattern of resist 11 is used as a mask to remove unnecessary parts, the first insulating layer is still formed and only the first conductive layer remains. layer (lower electrode).
另，對於去除第2種子層及上部密接層7的不要部分，就算不在步驟28進行去除，亦可在例如步驟27之後隨即將第2導電層9(上部電極)作為遮罩，進行蝕刻去除。如此一來，MIM電容器元件之外表面中之第1絕緣層的面積變大，且可抑制來自上部電極及下部電極間之側面的電流的洩漏等。In addition, even if the unnecessary portion of the second seed layer and the upper adhesive layer 7 is not removed in step 28, it may be removed by etching immediately after step 27, for example, using the second conductive layer 9 (upper electrode) as a mask. This increases the area of the first insulating layer on the outer surface of the MIM capacitor element, and suppresses leakage of current from the side surface between the upper electrode and the lower electrode.
(步驟29) 接著，將阻劑11的圖案去除。與第1實施形態同樣，如圖11所示，可形成形成有MIM電容器之配線基板。阻劑圖案的去除，能以公知方法的鹼性水溶液來進行去除剝離處理。藉由以上的步驟而形成電容器。 (step 29) Next, the pattern of the resist 11 is removed. As in the first embodiment, as shown in FIG. 11, a wiring board on which MIM capacitors are formed can be formed. Removal of the resist pattern can be performed by a known method of alkaline aqueous solution and stripping treatment. A capacitor is formed through the above steps.
第2實施形態之步驟29之後的步驟和第1實施形態同樣，因此省略說明。The steps after step 29 in the second embodiment are the same as those in the first embodiment, and therefore description thereof will be omitted.
＜效果＞ 在藉由習知例之製造方法製造MIM電容器時，在第1導電層4(下部電極)的下方發生側面蝕刻而不能正常地形成第2導電層9(上部電極)的比例為50%，但只要採用本揭示之第1實施形態及第2實施形態之製造方法，就能以100%的比例來正常地形成第2導電層9(上部電極)。可以看到顯著的改善。 ＜Effect＞ When MIM capacitors are manufactured by conventional manufacturing methods, the rate of side etching occurring below the first conductive layer 4 (lower electrode) and the failure to normally form the second conductive layer 9 (upper electrode) is 50%. As long as the manufacturing methods of the first embodiment and the second embodiment of the present disclosure are used, the second conductive layer 9 (upper electrode) can be normally formed at a ratio of 100%. Significant improvement can be seen.
以上，已針對本發明之實施形態作了說明，然本發明並不限定於上述之實施形態，在不脫離本發明之要旨的範圍內可做各種變更。As mentioned above, although the embodiment of this invention was described, this invention is not limited to the said embodiment, Various changes are possible in the range which does not deviate from the summary of this invention.
1:基板 2:密接層 3:第1種子層 4:第1導電層 5:下部密接層 6:第1絕緣層 7:上部密接層 8:第2種子層 9:第2導電層 11:阻劑 12:絕緣樹脂層 13:通孔 1: Substrate 2: Adhesive layer 3: The first seed layer 4: The first conductive layer 5: Lower bonding layer 6: The first insulating layer 7: Upper adhesive layer 8: The second seed layer 9: The second conductive layer 11: Resist 12: insulating resin layer 13: Through hole
圖1係顯示作為本發明之對象的基本構造之剖面圖。 圖2係說明第1導電層之形成步驟之剖面圖。 圖3係說明第1導電層之形成步驟之剖面圖。 圖4係說明第1導電層之形成步驟之剖面圖。 圖5係說明第1導電層之形成步驟之剖面圖。 圖6係說明習知例中的側面蝕刻之剖面圖。 圖7係說明實施形態之第2導電層之形成步驟之剖面圖。 圖8係說明實施形態之第2導電層之形成步驟之剖面圖。 圖9係說明MIM構造之形成步驟之剖面圖。 圖10係說明第1種子層之蝕刻步驟之剖面圖。 圖11係說明形成有MIM電容器之配線基板之剖面圖。 圖12係將配線基板形成在多層配線基板之剖面圖。 圖13係說明第2實施形態之形成步驟之剖面圖。 圖14係說明第2實施形態之形成步驟之剖面圖。 圖15係說明第2實施形態之形成步驟之剖面圖。 圖16係說明第2實施形態之形成步驟之剖面圖。 圖17係說明第2實施形態之形成步驟之剖面圖。 Fig. 1 is a sectional view showing the basic structure which is the object of the present invention. Fig. 2 is a cross-sectional view illustrating a step of forming a first conductive layer. Fig. 3 is a cross-sectional view illustrating a step of forming a first conductive layer. Fig. 4 is a cross-sectional view illustrating the steps of forming the first conductive layer. Fig. 5 is a cross-sectional view illustrating a step of forming a first conductive layer. Fig. 6 is a cross-sectional view illustrating side etching in a conventional example. Fig. 7 is a cross-sectional view illustrating the steps of forming the second conductive layer in the embodiment. Fig. 8 is a cross-sectional view illustrating the steps of forming the second conductive layer in the embodiment. Fig. 9 is a cross-sectional view illustrating the steps of forming the MIM structure. Fig. 10 is a cross-sectional view illustrating an etching step of the first seed layer. FIG. 11 is a cross-sectional view illustrating a wiring board on which MIM capacitors are formed. Fig. 12 is a cross-sectional view of forming a wiring board on a multilayer wiring board. Fig. 13 is a cross-sectional view illustrating the forming steps of the second embodiment. Fig. 14 is a cross-sectional view illustrating the formation steps of the second embodiment. Fig. 15 is a cross-sectional view illustrating the formation steps of the second embodiment. Fig. 16 is a cross-sectional view illustrating the formation steps of the second embodiment. Fig. 17 is a cross-sectional view illustrating the formation steps of the second embodiment.
1:基板 1: Substrate
2:密接層 2: Adhesive layer
3:第1種子層 3: The first seed layer
4:第1導電層 4: The first conductive layer
5:下部密接層 5: Lower bonding layer
6:第1絕緣層 6: The first insulating layer
7:上部密接層 7: Upper adhesive layer
8:第2種子層 8: The second seed layer
9:第2導電層 9: The second conductive layer
11:阻劑 11: Resist
a:寬度 a: width
b:寬度 b: width
c:高度 c:height
x:軸(方向)(軸方向) x: axis (direction) (axis direction)
z:軸(方向)(軸方向) z: axis (direction) (axis direction)
Claims (7)
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2021-188035 | 2021-11-18 | ||
| JP2021188035 | 2021-11-18 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| TW202331950A true TW202331950A (en) | 2023-08-01 |
Family
ID=86396965
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| TW111143916A TW202331950A (en) | 2021-11-18 | 2022-11-17 | Wiring board and method for manufacturing same |
Country Status (3)
| Country | Link |
|---|---|
| JP (1) | JPWO2023090197A1 (en) |
| TW (1) | TW202331950A (en) |
| WO (1) | WO2023090197A1 (en) |
Family Cites Families (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8730647B2 (en) * | 2008-02-07 | 2014-05-20 | Ibiden Co., Ltd. | Printed wiring board with capacitor |
| WO2018117111A1 (en) * | 2016-12-21 | 2018-06-28 | 大日本印刷株式会社 | Through electrode substrate, semiconductor device and method for producing through electrode substrate |
| JP6725095B2 (en) * | 2018-06-21 | 2020-07-15 | 大日本印刷株式会社 | Wiring board and semiconductor device |
| JP2021100007A (en) * | 2019-12-19 | 2021-07-01 | Tdk株式会社 | Electronic component and manufacturing method thereof |
-
2022
- 2022-11-08 WO PCT/JP2022/041489 patent/WO2023090197A1/en active Application Filing
- 2022-11-08 JP JP2023561537A patent/JPWO2023090197A1/ja active Pending
- 2022-11-17 TW TW111143916A patent/TW202331950A/en unknown
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| Publication number | Publication date |
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| WO2023090197A1 (en) | 2023-05-25 |
| JPWO2023090197A1 (en) | 2023-05-25 |
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