TW202324612A - High voltage cmos device and manufacturing method thereof - Google Patents

High voltage cmos device and manufacturing method thereof Download PDF

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TW202324612A
TW202324612A TW111114904A TW111114904A TW202324612A TW 202324612 A TW202324612 A TW 202324612A TW 111114904 A TW111114904 A TW 111114904A TW 111114904 A TW111114904 A TW 111114904A TW 202324612 A TW202324612 A TW 202324612A
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voltage
type
region
well region
type well
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翁武得
熊志文
楊大勇
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立錡科技股份有限公司
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Publication of TW202324612A publication Critical patent/TW202324612A/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823892—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the wells or tubs, e.g. twin tubs, high energy well implants, buried implanted layers for lateral isolation [BILLI]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823878—Complementary field-effect transistors, e.g. CMOS isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors

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Abstract

The present invention provides a high voltage complementary metal oxide semiconductor (CMOS) device and a manufacturing method thereof. The high voltage CMOS device includes: a semiconductor layer, a plurality of insulation regions, a first high voltage N-type well and a second high voltage N-type well, which are formed by one same ion implantation process step, a first high voltage P-type well and a second high voltage P-type well, which are formed by one same ion implantation process step, a first drift oxided region and a second oxide region, which are formed by one same etch process step by etching a drift oxide layer; a first gate and a second gate, which are formed by one same etch process step by etching a poly silicon layer, an N-type source and an N-type drain, and a P-type source and a P-type drain.

Description

高壓互補式金屬氧化物半導體元件及其製造方法High voltage complementary metal oxide semiconductor element and manufacturing method thereof

本發明有關於一種高壓互補式金屬氧化物半導體元件及其製造方法，特別是指一種整合高壓N型元件與高壓P型元件的高壓互補式金屬氧化物半導體元件及其製造方法。The invention relates to a high-voltage complementary metal oxide semiconductor element and a manufacturing method thereof, in particular to a high-voltage complementary metal oxide semiconductor element integrating a high-voltage N-type element and a high-voltage P-type element and a manufacturing method thereof.

習知高壓元件一般應用於電源管理積體電路(power management integrated circuit, PMIC)、驅動IC或是伺服器IC。但因為導電型為N型或P型的N型高壓元件與P型高壓元件在應用上的適用範圍不同，以致應用範圍受到限制，尤其在伺服器IC應用上。而單純將N型高壓元件與P型高壓元件耦接使用會有面積過大使用效率不佳的問題。Conventional high-voltage components are generally used in power management integrated circuits (power management integrated circuits, PMICs), driver ICs or server ICs. However, because the N-type or P-type N-type high-voltage components have different application ranges from the P-type high-voltage components, the application range is limited, especially in the application of servo ICs. However, simply coupling the N-type high-voltage element to the P-type high-voltage element will have the problem of too large area and poor efficiency.

有鑑於此，本發明提出一種以整合製程步驟，將N型高壓元件與P型高壓元件整合而形成之高壓互補式金屬氧化物半導體(CMOS)元件及其製造方法。In view of this, the present invention proposes a high-voltage complementary metal-oxide-semiconductor (CMOS) device formed by integrating an N-type high-voltage device and a P-type high-voltage device through an integrated process step and a manufacturing method thereof.

於一觀點中，本發明提供了一種高壓互補式金屬氧化物半導體元件包含：一半導體層，形成於一基板上；複數絕緣區，形成於該半導體層上，用以定義一高壓N型元件區與一高壓P型元件區，其中一高壓N型元件形成於該高壓N型元件區，且一高壓P型元件形成於該高壓P型元件區；一第一高壓N型井區與一第二高壓N型井區，以同一離子植入製程步驟分別形成於該高壓N型元件區之該半導體層中與該高壓P型元件區之該半導體層中；一第一高壓P型井區與一第二高壓P型井區，以同一離子植入製程步驟分別形成於該高壓N型元件區之該半導體層中與該高壓P型元件區之該半導體層中，其中該第一高壓N型井區與該第一高壓P型井區於一通道方向上鄰接，且該第二高壓N型井區與該第二高壓P型井區於該通道方向上鄰接；一第一漂移氧化區與一第二漂移氧化區，以同一蝕刻製程步驟蝕刻一漂移氧化層，而分別形成該第一漂移氧化區與該第二漂移氧化區於該高壓N型元件區中與該高壓P型元件區中；一第一閘極與一第二閘極，以同一蝕刻製程步驟蝕刻一多晶矽層，而分別形成該第一閘極與該第二閘極於該高壓N型元件區中與該高壓P型元件區中；一N型源極與一N型汲極，以同一離子植入製程步驟形成於該高壓N型元件區之該半導體層中，且該N型源極與該N型汲極分別位於該第一閘極之外部下方之該第一高壓P型井區中與該第一高壓N型井區中；以及一P型源極與一P型汲極，以同一離子植入製程步驟形成於該高壓P型元件區之該半導體層中，且該P型源極與該P型汲極分別位於該第二閘極之外部下方之該第二高壓N型井區中與該第二高壓P型井區中。In one aspect, the present invention provides a high-voltage complementary metal oxide semiconductor device comprising: a semiconductor layer formed on a substrate; a plurality of insulating regions formed on the semiconductor layer to define a high-voltage N-type device region and a high-voltage P-type element region, wherein a high-voltage N-type element is formed in the high-voltage N-type element region, and a high-voltage P-type element is formed in the high-voltage P-type element region; a first high-voltage N-type well region and a second A high-voltage N-type well region is respectively formed in the semiconductor layer of the high-voltage N-type element region and in the semiconductor layer of the high-voltage P-type element region by the same ion implantation process step; a first high-voltage P-type well region and a first high-voltage P-type well region and a The second high-voltage P-type well region is formed respectively in the semiconductor layer of the high-voltage N-type element region and in the semiconductor layer of the high-voltage P-type element region by the same ion implantation process step, wherein the first high-voltage N-type well region The region is adjacent to the first high-voltage P-type well region in a channel direction, and the second high-voltage N-type well region is adjacent to the second high-voltage P-type well region in the channel direction; a first drift oxidation region and a For the second drift oxide region, a drift oxide layer is etched by the same etching process step, and the first drift oxide region and the second drift oxide region are respectively formed in the high-voltage N-type element region and the high-voltage P-type element region; A first gate and a second gate are etched in the same etching process step to form a polysilicon layer, respectively forming the first gate and the second gate in the high-voltage N-type element region and the high-voltage P-type element In the region; an N-type source and an N-type drain are formed in the semiconductor layer of the high-voltage N-type element region by the same ion implantation process step, and the N-type source and the N-type drain are respectively located In the first high-voltage P-type well region and in the first high-voltage N-type well region under the exterior of the first gate; and a P-type source and a P-type drain are formed by the same ion implantation process step In the semiconductor layer of the high-voltage P-type device region, the P-type source and the P-type drain are respectively located in the second high-voltage N-type well region and the second high-voltage drain below the second gate. In the P-type well area.

於另一觀點中，本發明提供了一種高壓互補式金屬氧化物半導體(CMOS)元件製造方法，其中該高壓CMOS元件包括一高壓N型元件以及一高壓P型元件，該高壓CMOS元件製造方法包含：形成一半導體層於一基板上；形成複數絕緣區於該半導體層上，以定義一高壓N型元件區與一高壓P型元件區，其中該高壓N型元件形成於該高壓N型元件區，且該高壓P型元件形成於該高壓P型元件區；以同一離子植入製程步驟形成一第一高壓N型井區於該高壓N型元件區之該半導體層中，與一第二高壓N型井區於該高壓P型元件區之該半導體層中；以同一離子植入製程步驟形成一第一高壓P型井區於該高壓N型元件區之該半導體層中，與一第二高壓P型井區於該高壓P型元件區之該半導體層中，其中該第一高壓N型井區與該第一高壓P型井區於一通道方向上鄰接，且該第二高壓N型井區與該第二高壓P型井區於該通道方向上鄰接；形成一漂移氧化層於該半導體層上，該漂移氧化層覆蓋該高壓N型元件區與該高壓P型元件區；以同一蝕刻製程步驟蝕刻該漂移氧化層，而形成一第一漂移氧化區於該高壓N型元件區中，與一第二漂移氧化區於該高壓P型元件區中；於該第一漂移氧化區與該第二漂移氧化區形成之後，形成一閘極介電層於該半導體層上，該閘極介電層覆蓋該高壓N型元件區與該高壓P型元件區；形成一多晶矽層於該閘極介電層上，該多晶矽層覆蓋該高壓N型元件區與該高壓P型元件區；以同一蝕刻製程步驟蝕刻該多晶矽層，而形成一第一閘極於該高壓N型元件區中，與一第二閘極於該高壓P型元件區中；以同一離子植入製程步驟形成一N型源極與一N型汲極於該高壓N型元件區之該半導體層中，且該N型源極與該N型汲極分別位於該第一閘極之外部下方之該第一高壓P型井區中與該第一高壓N型井區中；以及以同一離子植入製程步驟形成一P型源極與一P型汲極於該高壓P型元件區之該半導體層中，且該P型源極與該P型汲極分別位於該第二閘極之外部下方之該第二高壓N型井區中與該第二高壓P型井區中。In another viewpoint, the present invention provides a method for manufacturing a high-voltage complementary metal-oxide-semiconductor (CMOS) device, wherein the high-voltage CMOS device includes a high-voltage N-type device and a high-voltage P-type device, and the high-voltage CMOS device manufacturing method includes : Forming a semiconductor layer on a substrate; forming a plurality of insulating regions on the semiconductor layer to define a high-voltage N-type element region and a high-voltage P-type element region, wherein the high-voltage N-type element is formed in the high-voltage N-type element region , and the high-voltage P-type element is formed in the high-voltage P-type element region; a first high-voltage N-type well region is formed in the semiconductor layer of the high-voltage N-type element region by the same ion implantation process step, and a second high-voltage N-type well region is formed with a second high-voltage well region An N-type well region is in the semiconductor layer of the high-voltage P-type element region; a first high-voltage P-type well region is formed in the semiconductor layer of the high-voltage N-type element region by the same ion implantation process step, and a second The high-voltage P-type well region is in the semiconductor layer of the high-voltage P-type element region, wherein the first high-voltage N-type well region is adjacent to the first high-voltage P-type well region in a channel direction, and the second high-voltage N-type well region The well region is adjacent to the second high-voltage P-type well region in the channel direction; a drift oxide layer is formed on the semiconductor layer, and the drift oxide layer covers the high-voltage N-type element region and the high-voltage P-type element region; with the same The etching process step etches the drift oxide layer to form a first drift oxide region in the high-voltage N-type element region, and a second drift oxide region in the high-voltage P-type element region; between the first drift oxide region and the high-voltage P-type element region After the formation of the second drift oxide region, a gate dielectric layer is formed on the semiconductor layer, and the gate dielectric layer covers the high-voltage N-type element region and the high-voltage P-type element region; a polysilicon layer is formed on the gate On the dielectric layer, the polysilicon layer covers the high-voltage N-type device region and the high-voltage P-type device region; the polysilicon layer is etched in the same etching process step to form a first gate in the high-voltage N-type device region, and a second gate in the high-voltage P-type element region; an N-type source and an N-type drain are formed in the semiconductor layer in the high-voltage N-type element region by the same ion implantation process step, and the N The source and the N-type drain are respectively located in the first high-voltage P-type well region and the first high-voltage N-type well region under the exterior of the first gate; and an ion implantation process step is used to form a The P-type source and a P-type drain are in the semiconductor layer of the high-voltage P-type element region, and the P-type source and the P-type drain are respectively located at the second high voltage outside the second gate. In the N-type well area and in the second high-voltage P-type well area.

於一實施例中，該高壓互補式金屬氧化物半導體元件，更包含：一第一淺溝槽隔絕(shallow trench isolation, STI)區與一第二淺溝槽隔絕區，以同一製程步驟分別形成於該高壓N型元件區中與該高壓P型元件區中，其中該第一STI區位於並連接於該第一漂移氧化區正下方，且該第二STI區位於並連接於該第二漂移氧化區正下方。In one embodiment, the high voltage complementary metal oxide semiconductor device further includes: a first shallow trench isolation (shallow trench isolation, STI) region and a second shallow trench isolation region, respectively formed by the same process step In the high-voltage N-type device region and the high-voltage P-type device region, the first STI region is located and connected directly below the first drift oxide region, and the second STI region is located and connected to the second drift directly below the oxidation zone.

於一實施例中，該高壓互補式金屬氧化物半導體元件，更包含：一N型導電區，以形成該N型源極與該N型汲極之同一離子植入製程步驟形成於該第二高壓N型井區中，其中該N型導電區為該第二高壓N型井區之電性接點；以及一P型導電區，以形成該P型源極與該P型汲極之同一離子植入製程步驟形成於該第一高壓P型井區中，其中該P型導電區為該第一高壓P型井區之電性接點。In one embodiment, the high-voltage complementary metal-oxide-semiconductor device further includes: an N-type conduction region, which is formed on the second electrode by the same ion implantation process step for forming the N-type source and the N-type drain. In the high-voltage N-type well region, wherein the N-type conductive region is the electrical contact of the second high-voltage N-type well region; and a P-type conductive region to form the same connection between the P-type source and the P-type drain The ion implantation process step is formed in the first high-voltage P-type well region, wherein the P-type conductive region is an electrical contact of the first high-voltage P-type well region.

於一實施例中，該高壓互補式金屬氧化物半導體元件，更包含：一第一N型埋層與一第二N型埋層，以同一製程步驟分別形成於該高壓N型元件區與該高壓P型元件區中；其中該第一N型埋層形成於並連接於該第一高壓N型井區與該第一高壓P型井區正下方之該半導體層與該基板中；其中該第二N型埋層形成於並連接於該第二高壓N型井區與該第二高壓P型井區正下方之該半導體層與該基板中。In one embodiment, the high-voltage complementary metal-oxide-semiconductor device further includes: a first N-type buried layer and a second N-type buried layer, which are respectively formed in the high-voltage N-type device region and the In the high-voltage P-type element region; wherein the first N-type buried layer is formed in and connected to the first high-voltage N-type well region and the semiconductor layer and the substrate directly below the first high-voltage P-type well region; wherein the The second N-type buried layer is formed and connected in the semiconductor layer and the substrate directly under the second high-voltage N-type well region and the second high-voltage P-type well region.

於一實施例中，該高壓互補式金屬氧化物半導體元件，其更包含：一第一高壓N型隔絕區與一第二高壓N型隔絕區，以形成該第一高壓N型井區與該第二高壓N型井區同一離子植入製程步驟而形成；以及一第一高壓P型隔絕區與一第二高壓P型隔絕區，以形成該第一高壓P型井區與該第二高壓P型井區同一離子植入製程步驟而形成；其中該第一高壓N型隔絕區於該通道方向上，鄰接於該第一高壓P型井區相對於鄰接該第一高壓N型井區之另一側；其中該第二高壓N型隔絕區於該通道方向上，鄰接於該第二高壓P型井區相對於鄰接該第二高壓N型井區之另一側；其中該第一高壓P型隔絕區於該通道方向上，鄰接於該第一高壓N型井區相對於鄰接該第一高壓P型井區之另一側；其中該第二高壓P型隔絕區於該通道方向上，鄰接於該第二高壓N型井區相對於鄰接該第二高壓N型井區之另一側。In one embodiment, the high-voltage complementary metal-oxide-semiconductor device further includes: a first high-voltage N-type isolation region and a second high-voltage N-type isolation region to form the first high-voltage N-type well region and the The second high-voltage N-type well region is formed in the same ion implantation process step; and a first high-voltage P-type isolation region and a second high-voltage P-type isolation region are formed to form the first high-voltage P-type well region and the second high-voltage P-type well region. The P-type well region is formed in the same ion implantation process step; wherein the first high-voltage N-type isolation region is adjacent to the first high-voltage P-type well region relative to the first high-voltage N-type well region in the channel direction. The other side; wherein the second high-voltage N-type isolation region is adjacent to the second high-voltage P-type well region in the direction of the passage, and is adjacent to the other side of the second high-pressure N-type well region; wherein the first high-pressure The P-type isolation region is adjacent to the first high-voltage N-type well region on the other side of the first high-voltage P-type well region in the channel direction; wherein the second high-voltage P-type isolation region is in the channel direction , adjacent to the second high-pressure N-type well region opposite to the other side adjacent to the second high-pressure N-type well region.

於一實施例中，該半導體層係一P型半導體磊晶層，且具有體積電阻率45 Ohm-cm。In one embodiment, the semiconductor layer is a P-type semiconductor epitaxial layer with a volume resistivity of 45 Ohm-cm.

於一實施例中，該漂移氧化區之厚度介於400Å與450 Å之間。In one embodiment, the thickness of the drift oxide region is between 400 Å and 450 Å.

於一實施例中，該閘極介電層之厚度介於80Å與100 Å之間。In one embodiment, the thickness of the gate dielectric layer is between 80 Å and 100 Å.

於一實施例中，該高壓元件區之一高壓元件的閘極驅動電壓為3.3V。In one embodiment, the gate driving voltage of one of the high voltage elements in the high voltage element region is 3.3V.

於一實施例中，該高壓互補式金屬氧化物半導體元件之最小特徵尺寸為0.18微米。In one embodiment, the minimum feature size of the high voltage CMOS device is 0.18 microns.

本發明之優點係為本發明可採用相同製程步驟，同時分別形成高壓互補式金屬氧化物半導體元件之高壓N型元件與高壓P型元件中的不同單元。The advantage of the present invention is that the present invention can use the same process steps to simultaneously form different units in the high-voltage N-type element and the high-voltage P-type element of the high-voltage complementary metal oxide semiconductor element.

本發明之另一優點係為形成隔絕區以於半導體層中電性隔絕高壓N型元件與高壓P型元件。Another advantage of the present invention is to form an isolation region to electrically isolate the high-voltage N-type device and the high-voltage P-type device in the semiconductor layer.

底下藉由具體實施例詳加說明，當更容易瞭解本發明之目的、技術內容、特點及其所達成之功效。In the following detailed description by means of specific embodiments, it will be easier to understand the purpose, technical content, characteristics and effects of the present invention.

有關本發明之前述及其他技術內容、特點與功效，在以下配合參考圖式之較佳實施例的詳細說明中，將可清楚的呈現。本發明中的圖式均屬示意，主要意在表示製程步驟以及各層之間之上下次序關係，至於形狀、厚度與寬度則並未依照比例繪製。The aforementioned and other technical contents, features and effects of the present invention will be clearly presented in the following detailed description of preferred embodiments with reference to the drawings. The drawings in the present invention are all schematic, mainly intended to represent the manufacturing process steps and the relationship between the upper and lower order of each layer, and the shapes, thicknesses and widths are not drawn to scale.

請參考圖1，其根據本發明之一實施例，顯示高壓互補式金屬氧化物半導體元件10之剖視示意圖。如圖1所示，高壓互補式金屬氧化物半導體元件10包含：半導體層11’、複數絕緣區12、以同一離子植入製程步驟形成之第一高壓N型井區14a與第二高壓N型井區14b、以同一離子植入製程步驟形成之第一高壓P型井區15a與第二高壓P型井區15b、以同一蝕刻製程步驟蝕刻一漂移氧化層而形成之第一漂移氧化區16a與第二漂移氧化區16b、以同一蝕刻製程步驟蝕刻一多晶矽層，而形成之第一閘極17a與第二閘極17b、N型源極18a與N型汲極18b、以及P型源極19a與P型汲極19b。Please refer to FIG. 1 , which shows a schematic cross-sectional view of a high-voltage complementary metal-oxide-semiconductor device 10 according to an embodiment of the present invention. As shown in FIG. 1, a high-voltage complementary metal-oxide-semiconductor device 10 includes: a semiconductor layer 11', a plurality of insulating regions 12, a first high-voltage N-type well region 14a and a second high-voltage N-type well region 14a formed in the same ion implantation process step. The well region 14b, the first high-voltage P-type well region 15a and the second high-voltage P-type well region 15b formed by the same ion implantation process step, and the first drift oxide region 16a formed by etching a drift oxide layer by the same etching process step A polysilicon layer is etched in the same etching process step as the second drift oxide region 16b to form the first gate 17a and the second gate 17b, the N-type source 18a and the N-type drain 18b, and the P-type source 19a and the P-type drain 19b.

半導體層11’形成於基板11上，半導體層11’於垂直方向(如圖1中之實線箭號方向所示意，下同)上，具有相對之上表面11a與下表面11b。基板11例如但不限於為一P型或N型的半導體基板。半導體層11’例如以磊晶的步驟，形成於基板11上，或是以基板11的部分，作為半導體層11’。形成半導體層11’的方式，為本領域中具有通常知識者所熟知，在此不予贅述。The semiconductor layer 11' is formed on the substrate 11. The semiconductor layer 11' has an upper surface 11a and a lower surface 11b opposite to each other in a vertical direction (shown by the solid arrow in FIG. 1 , the same below). The substrate 11 is, for example but not limited to, a P-type or N-type semiconductor substrate. The semiconductor layer 11' is formed on the substrate 11 by epitaxy, for example, or a part of the substrate 11 is used as the semiconductor layer 11'. The method of forming the semiconductor layer 11' is well known to those skilled in the art, and will not be repeated here.

請繼續參閱圖1，複數絕緣區12形成於半導體層11’上，複數絕緣區12用以定義高壓N型元件區HV-NMOS與高壓P型元件區HV-PMOS，其中高壓N型元件10a形成於高壓N型元件區HV-NMOS，且高壓P型元件10b形成於該高壓P型元件區HV-PMOS。絕緣區12例如但不限於為如圖1所示之淺溝槽隔絕(shallow trench isolation, STI)結構。Please continue to refer to FIG. 1, a plurality of insulating regions 12 are formed on the semiconductor layer 11', and the plurality of insulating regions 12 are used to define the high-voltage N-type element region HV-NMOS and the high-voltage P-type element region HV-PMOS, wherein the high-voltage N-type element 10a is formed In the high-voltage N-type device region HV-NMOS, and the high-voltage P-type device 10b is formed in the high-voltage P-type device region HV-PMOS. The insulating region 12 is, for example but not limited to, a shallow trench isolation (STI) structure as shown in FIG. 1 .

在本實施例中，高壓N型元件10a包括：第一高壓N型井區14a、第一高壓P型井區15a、第一漂移氧化區16a、第一閘極17a、N型源極18a以及N型汲極18b。高壓P型元件10b包括：第二高壓N型井區14b、第二高壓P型井區15b、第二漂移氧化區16b、第二閘極17b、P型源極19a以及P型汲極19b。In this embodiment, the high-voltage N-type element 10a includes: a first high-voltage N-type well region 14a, a first high-voltage P-type well region 15a, a first drift oxide region 16a, a first gate 17a, an N-type source 18a and N-type drain 18b. The high-voltage P-type device 10b includes: a second high-voltage N-type well region 14b, a second high-voltage P-type well region 15b, a second drift oxide region 16b, a second gate 17b, a P-type source 19a, and a P-type drain 19b.

請繼續參閱圖1，第一高壓N型井區14a與第二高壓N型井區14b，以同一離子植入製程步驟分別形成於高壓N型元件區HV-NMOS之半導體層11’中與高壓P型元件區HV-PMOS之半導體層11’中。第一高壓N型井區14a與第二高壓N型井區14b皆位於上表面11a下並連接於上表面11a。部分第一高壓N型井區14a位於閘極17a正下方並連接於閘極17a，以提供高壓N型元件10a在導通操作中之漂移電流通道；且部分第二高壓N型井區14b位於閘極17b正下方，以提供高壓P型元件10b在導通操作中之反轉電流通道。Please continue to refer to FIG. 1, the first high-voltage N-type well region 14a and the second high-voltage N-type well region 14b are respectively formed in the semiconductor layer 11' of the high-voltage N-type device region HV-NMOS and the high-voltage N-type well region 14b in the same ion implantation process step. In the semiconductor layer 11' of the P-type element region HV-PMOS. Both the first high-voltage N-type well region 14a and the second high-pressure N-type well region 14b are located under the upper surface 11a and connected to the upper surface 11a. Part of the first high-voltage N-type well region 14a is located directly below the gate electrode 17a and connected to the gate electrode 17a to provide a drift current channel for the high-voltage N-type element 10a in the conduction operation; and part of the second high-voltage N-type well region 14b is located at the gate electrode 17a. Directly below the pole 17b to provide the reverse current channel of the high-voltage P-type element 10b in the conduction operation.

請繼續參閱圖1，第一高壓P型井區15a與第二高壓P型井區15b，以同一離子植入製程步驟分別形成於高壓N型元件區HV-NMOS之半導體層11’中與高壓P型元件區HV-PMOS之半導體層11’中，其中第一高壓N型井區14a與第一高壓P型井區15a於通道方向(如圖1中之虛線箭號方向所示意，下同)上鄰接，且第二高壓N型井區14b與第二高壓P型井區15b於通道方向上鄰接。Please continue to refer to FIG. 1. The first high-voltage P-type well region 15a and the second high-voltage P-type well region 15b are respectively formed in the semiconductor layer 11' of the high-voltage N-type element region HV-NMOS by the same ion implantation process step. In the semiconductor layer 11' of the P-type device region HV-PMOS, the first high-voltage N-type well region 14a and the first high-voltage P-type well region 15a are in the channel direction (as shown in the direction of the dashed arrow in Figure 1, the same below. ), and the second high-voltage N-type well region 14b is adjacent to the second high-voltage P-type well region 15b in the channel direction.

第一高壓P型井區15a與第二高壓P型井區15b皆位於上表面11a下並連接於上表面11a。部分第一高壓P型井區15a位於閘極17a正下方並連接於閘極17a，以提供高壓N型元件10a在導通操作中之反轉電流通道；且部分第二高壓P型井區15b位於閘極17b正下方，以提供高壓P型元件10b在導通操作中之漂移電流通道。Both the first high-voltage P-type well region 15a and the second high-pressure P-type well region 15b are located under the upper surface 11a and connected to the upper surface 11a. Part of the first high-voltage P-type well region 15a is located directly below the gate electrode 17a and connected to the gate electrode 17a to provide an inversion current channel for the high-voltage N-type element 10a in the conduction operation; and part of the second high-voltage P-type well region 15b is located at Directly below the gate 17b to provide a drift current channel for the high-voltage P-type element 10b in the conduction operation.

第一漂移氧化區16a與第二漂移氧化16b以同一蝕刻製程步驟蝕刻漂移氧化層，而分別形成第一漂移氧化區16a與第二漂移氧化區16b於高壓N型元件區HV-NMOS中與高壓P型元件區HV-PMOS中。第一漂移氧化區16a與第二漂移氧化16b形成於半導體層11’上，且分別位於高壓N型元件10a的漂移區與高壓P型元件10b的漂移區上。The first drift oxide region 16a and the second drift oxide region 16b are etched with the same etching process step to form the first drift oxide region 16a and the second drift oxide region 16b in the high voltage N-type element region HV-NMOS and the high voltage In the P-type element area HV-PMOS. The first drift oxide region 16a and the second drift oxide region 16b are formed on the semiconductor layer 11', and are respectively located on the drift region of the high-voltage N-type device 10a and the drift region of the high-voltage P-type device 10b.

第一閘極17a與第二閘極17b，以同一蝕刻製程步驟蝕刻一多晶矽層，而分別形成第一閘極17a與第二閘極17b於高壓N型元件區HV-NMOS中與高壓P型元件區HV-PMOS中。The first gate 17a and the second gate 17b etch a polysilicon layer in the same etching process, and respectively form the first gate 17a and the second gate 17b in the high-voltage N-type device region HV-NMOS and the high-voltage P-type In the element area HV-PMOS.

第一閘極17a與第二閘極17b形成於半導體層11’之上表面11a上，第一閘極17a與第二閘極17b分別包含導電層、間隔層以及介電層，其中介電層位於上表面11a上並連接於上表面11a，此為本領域中具有通常知識者所熟知，在此不予贅述。The first gate 17a and the second gate 17b are formed on the upper surface 11a of the semiconductor layer 11', and the first gate 17a and the second gate 17b respectively include a conductive layer, a spacer layer and a dielectric layer, wherein the dielectric layer It is located on and connected to the upper surface 11a, which is well known to those skilled in the art, and will not be repeated here.

N型源極18a與N型汲極18b，以同一離子植入製程步驟形成於高壓N型元件區HV-NMOS之半導體層11’中，且N型源極18a與N型汲極18b分別位於第一閘極17a在通道方向(如圖1中之虛線箭號方向所示意，下同)之外部下方之第一高壓P型井區15a中與第一高壓N型井區14a中。The N-type source 18a and the N-type drain 18b are formed in the semiconductor layer 11' of the high-voltage N-type element region HV-NMOS by the same ion implantation process step, and the N-type source 18a and the N-type drain 18b are respectively located The first gate 17a is in the first high-voltage P-type well region 15a and the first high-voltage N-type well region 14a outside and below the channel direction (shown by the dashed arrow in FIG. 1 , the same below).

於垂直方向上，N型源極18a與N型汲極18b形成於上表面11a下並連接於上表面11a中，且於通道方向上，高壓N型元件10a的漂移區位於N型汲極18b與第一高壓P型井區15a之間，並分隔N型汲極18b與第一高壓P型井區15a，且位於靠近上表面11a之第一高壓N型井區14a中，用以作為高壓N型元件10a在導通操作中之漂移電流通道。In the vertical direction, the N-type source 18a and the N-type drain 18b are formed under the upper surface 11a and connected to the upper surface 11a, and in the channel direction, the drift region of the high-voltage N-type element 10a is located at the N-type drain 18b Between the first high-voltage P-type well region 15a and separates the N-type drain 18b from the first high-voltage P-type well region 15a, and is located in the first high-voltage N-type well region 14a close to the upper surface 11a for high-voltage The drift current channel of the N-type element 10a in the conduction operation.

P型源極19a與P型汲極19b，以同一離子植入製程步驟形成於高壓P型元件區HV-PMOS之半導體層11’中，且P型源極19a與P型汲極19b分別位於第二閘極17b在通道方向(如圖1中之虛線箭號方向所示意，下同)之外部下方之第二高壓N型井區14b中與第二高壓P型井區15b中。The P-type source 19a and the P-type drain 19b are formed in the semiconductor layer 11' of the high-voltage P-type element region HV-PMOS by the same ion implantation process step, and the P-type source 19a and the P-type drain 19b are respectively located The second gate 17b is in the second high-voltage N-type well region 14b and the second high-voltage P-type well region 15b outside and below the channel direction (shown by the dashed arrow in FIG. 1 , the same below).

於垂直方向上，P型源極19a與P型汲極19b形成於上表面11a下並連接於上表面11a中，且於通道方向上，高壓P型元件10b的漂移區位於P型汲極19b與第二高壓N型井區14b之間，並分隔P型汲極19b與第二高壓N型井區14b，且位於靠近上表面11a之第二高壓P型井區15b中，用以作為高壓P型元件10b在導通操作中之漂移電流通道。In the vertical direction, the P-type source 19a and the P-type drain 19b are formed under the upper surface 11a and connected to the upper surface 11a, and in the channel direction, the drift region of the high-voltage P-type element 10b is located at the P-type drain 19b Between the second high-voltage N-type well region 14b and separates the P-type drain 19b from the second high-voltage N-type well region 14b, and is located in the second high-voltage P-type well region 15b near the upper surface 11a for high-voltage The drift current channel of the P-type element 10b in the conduction operation.

在一種實施例中，半導體層11’係P型半導體磊晶層，且具有體積電阻率45 Ohm-cm。In one embodiment, the semiconductor layer 11' is a P-type semiconductor epitaxial layer, and has a volume resistivity of 45 Ohm-cm.

在一種實施例中，第一漂移氧化區16a與第二漂移氧化16b為化學氣相沉積(chemical vapor deposition, CVD)氧化區。In one embodiment, the first drift oxidation region 16 a and the second drift oxidation region 16 b are chemical vapor deposition (chemical vapor deposition, CVD) oxidation regions.

在一種實施例中，第一漂移氧化區16a與第二漂移氧化16b之厚度介於400Å與450 Å之間。In one embodiment, the thickness of the first drift oxide region 16 a and the second drift oxide region 16 b is between 400 Å and 450 Å.

在一種實施例中，第一閘極17a之介電層與第二閘極17b之介電層之厚度介於80Å與100 Å之間。In one embodiment, the thickness of the dielectric layer of the first gate 17 a and the dielectric layer of the second gate 17 b is between 80 Å and 100 Å.

在一種實施例中，高壓N型元件區HV-NMOS之高壓N型元件10a的閘極驅動電壓為3.3V。In one embodiment, the gate driving voltage of the high-voltage N-type device 10a in the high-voltage N-type device region HV-NMOS is 3.3V.

在一種實施例中，高壓互補式金屬氧化物半導體元件10之最小特徵尺寸為0.18微米。In one embodiment, the minimum feature size of the high voltage CMOS device 10 is 0.18 microns.

需說明的是，所謂反轉電流通道係指高壓N型元件10a/高壓P型元件10b在導通操作中，因施加於閘極17a/閘極17b的電壓，而使閘極17a/閘極17b的下方形成反轉層(inversion layer)以使導通電流通過的區域，此為本領域具有通常知識所熟知，在此不予贅述。It should be noted that the so-called reverse current channel refers to the high-voltage N-type element 10a/high-voltage P-type element 10b in the conduction operation, due to the voltage applied to the gate 17a/gate 17b, the gate 17a/gate 17b An inversion layer (inversion layer) is formed below the region to allow the conduction current to pass through, which is well known in the art and will not be repeated here.

需說明的是，所謂漂移電流通道係指壓N型元件10a/高壓P型元件10b在導通操作中使導通電流以漂移的方式通過的區域，此為本領域具有通常知識所熟知，在此不予贅述。It should be noted that the so-called drift current channel refers to the region where the voltage N-type element 10a/high-voltage P-type element 10b allows the conduction current to pass through in a drifting manner during the conduction operation. I will repeat.

需說明的是，上表面11a並非指一完全平坦的平面，而是指半導體層11’的一個表面。在本實施例中，例如絕緣區12與上表面11a接觸的部分上表面11a，就具有下陷的部分。It should be noted that the upper surface 11a does not refer to a completely flat plane, but refers to a surface of the semiconductor layer 11'. In this embodiment, for example, the portion of the upper surface 11a where the insulating region 12 is in contact with the upper surface 11a has a sunken portion.

需說明的是，閘極17a/閘極17b包括具有導電性的導電層、與上表面11a連接的介電層、以及具有電絕緣特性之間隔層，其中，導電層用以作為閘極17a/閘極17b之電性接點，形成於介電層上並連接於介電層。間隔層形成於導電層之兩側以作為閘極17a/閘極17b之兩側之電性絕緣層。此為本領域具有通常知識所熟知，在此不予贅述。It should be noted that the gate 17a/gate 17b includes a conductive layer with conductivity, a dielectric layer connected to the upper surface 11a, and a spacer layer with electrical insulation properties, wherein the conductive layer is used as the gate 17a/ The electrical contact of the gate electrode 17b is formed on the dielectric layer and connected to the dielectric layer. A spacer layer is formed on both sides of the conductive layer to serve as an electrical insulating layer on both sides of the gate 17a/gate 17b. This is well known in the art and will not be repeated here.

需說明的是，前述之「N型」與「P型」係指於高壓互補式金屬氧化物半導體元件中，以不同導電型之雜質摻雜於半導體組成區域(例如但不限於前述之第一高壓N型井區14a與第二高壓N型井區14b、第一高壓P型井區15a與第二高壓P型井區15b、N型源極18a與N型汲極18b以及P型源極19a與P型汲極19b等區域)內，使得半導體組成區域成為N或P型，其中，N型與P型為彼此電性相反的導電型。It should be noted that the aforementioned "N-type" and "P-type" refer to the doping of semiconductor composition regions with impurities of different conductivity types in the high-voltage complementary metal oxide semiconductor device (such as but not limited to the aforementioned first High-voltage N-type well 14a and second high-voltage N-type well 14b, first high-voltage P-type well 15a and second high-voltage P-type well 15b, N-type source 18a, N-type drain 18b, and P-type source 19a and the P-type drain 19b and other regions), make the semiconductor composition region become N or P-type, where N-type and P-type are electrically opposite conductivity types.

此外需說明的是，所謂的高壓互補式金屬氧化物半導體元件，係指於正常操作時，漂移區長度根據正常操作時所承受的操作電壓而調整，因而可操作於較高之特定電壓。此皆為本領域中具有通常知識者所熟知，在此不予贅述。In addition, it should be noted that the so-called high-voltage complementary metal-oxide-semiconductor device means that during normal operation, the length of the drift region is adjusted according to the operating voltage under normal operation, so that it can operate at a higher specific voltage. All of these are well known to those with ordinary knowledge in the art, and will not be repeated here.

圖2根據本發明之另一實施例顯示高壓互補式金屬氧化物半導體元件20之剖視示意圖。本實施例與圖1之實施例的不同在於，本實施例之高壓互補式金屬氧化物半導體元件20更包含：第一淺溝槽隔絕(shallow trench isolation, STI)區22a、第二淺溝槽隔絕區22b、第三淺溝槽隔絕區22c、第四淺溝槽隔絕區22d、N型導電區29c、P型導電區28c、第一N型埋層23a、第二N型埋層23b、第一高壓N型隔絕區24c、第二高壓N型隔絕區24d、第一高壓P型隔絕區25c以及第二高壓P型隔絕區25d。FIG. 2 shows a schematic cross-sectional view of a high-voltage complementary metal-oxide-semiconductor device 20 according to another embodiment of the present invention. The difference between this embodiment and the embodiment of FIG. 1 is that the high-voltage complementary metal-oxide-semiconductor device 20 of this embodiment further includes: a first shallow trench isolation (shallow trench isolation, STI) region 22a, a second shallow trench Isolation region 22b, third shallow trench isolation region 22c, fourth shallow trench isolation region 22d, N-type conductive region 29c, P-type conductive region 28c, first N-type buried layer 23a, second N-type buried layer 23b, The first high-voltage N-type isolation region 24c, the second high-voltage N-type isolation region 24d, the first high-voltage P-type isolation region 25c, and the second high-voltage P-type isolation region 25d.

第一淺溝槽隔絕區22a、第二淺溝槽隔絕區22b、第三淺溝槽隔絕區22c、第四淺溝槽隔絕區22d，例如以與形成絕緣區12同一製程步驟形成。其中，第一淺溝槽隔絕區22a與第三淺溝槽隔絕區22c形成於高壓N型元件區HV-NMOS中，第二淺溝槽隔絕區22b與第四淺溝槽隔絕區22d形成於高壓P型元件區HV-PMOS中。其中第一淺溝槽隔絕區22a位於並連接於第一漂移氧化區16a正下方，且第二淺溝槽隔絕區22b位於並連接於第二漂移氧化區16b正下方。The first STI region 22 a , the second STI region 22 b , the third STI region 22 c , and the fourth STI region 22 d are, for example, formed in the same process step as the insulating region 12 . Wherein, the first STI region 22a and the third STI region 22c are formed in the high voltage N-type element region HV-NMOS, and the second STI region 22b and the fourth STI region 22d are formed in In the high-voltage P-type element area HV-PMOS. The first STI region 22a is located and connected directly under the first drift oxide region 16a, and the second shallow trench isolation region 22b is located and connected directly under the second drift oxide region 16b.

第三淺溝槽隔絕區22c用以於半導體層11’中電性隔絕N型源極18a與P型導電區29c。第四淺溝槽隔絕區22d用以於半導體層11’中電性隔絕P型源極19a與N型導電區28c。The third shallow trench isolation region 22c is used to electrically isolate the N-type source 18a and the P-type conductive region 29c in the semiconductor layer 11'. The fourth shallow trench isolation region 22d is used to electrically isolate the P-type source 19a and the N-type conductive region 28c in the semiconductor layer 11'.

P型導電區29c例如以與P型源極19a與P型汲極19b同一離子植入製程步驟形成於高壓N型元件區HV-NMOS之半導體層11’中，用以作為第一高壓P型井區15a的電性接點。For example, the P-type conductive region 29c is formed in the semiconductor layer 11' of the high-voltage N-type device region HV-NMOS by the same ion implantation process steps as the P-type source 19a and the P-type drain 19b, and is used as the first high-voltage P-type The electrical contact of the well area 15a.

N型導電區28c例如以與N型源極18a與N型汲極18b同一離子植入製程步驟形成於高壓P型元件區HV-PMOS之半導體層11’中，用以作為第二高壓N型井區14b的電性接點。The N-type conductive region 28c is formed in the semiconductor layer 11' of the high-voltage P-type element region HV-PMOS by the same ion implantation process step as the N-type source 18a and the N-type drain 18b, and is used as a second high-voltage N-type The electrical contact of the well region 14b.

第一N型埋層23a與第二N型埋層23b以同一製程步驟分別形成於高壓N型元件區HV-NMOS與高壓P型元件區HV-PMOS中。其中第一N型埋層23a形成於並連接於第一高壓N型井區14a與第一高壓P型井區15a正下方之半導體層11’與基板11中。其中第二N型埋層23b形成於並連接於第二高壓N型井區14b與第二高壓P型井區15b正下方之半導體層11’與基板11中。The first N-type buried layer 23a and the second N-type buried layer 23b are respectively formed in the high-voltage N-type device region HV-NMOS and the high-voltage P-type device region HV-PMOS by the same process step. The first N-type buried layer 23a is formed in and connected to the semiconductor layer 11' and the substrate 11 directly under the first high-voltage N-type well region 14a and the first high-voltage P-type well region 15a. The second N-type buried layer 23b is formed in and connected to the semiconductor layer 11' and the substrate 11 directly under the second high-voltage N-type well region 14b and the second high-voltage P-type well region 15b.

以形成第一高壓N型井區14a與第二高壓N型井區14b同一離子植入製程步驟，形成第一高壓N型隔絕區24c與第二高壓N型隔絕區24d。以形成第一高壓P型井區15a與第二高壓P型井區15b同一離子植入製程步驟，形成第一高壓P型隔絕區25c與第二高壓P型隔絕區25d。The first high voltage N-type isolation region 24c and the second high voltage N-type isolation region 24d are formed in the same ion implantation process step as the formation of the first high voltage N-type well region 14a and the second high voltage N-type well region 14b. The first high-voltage P-type isolation region 25c and the second high-voltage P-type isolation region 25d are formed by the same ion implantation process step as the formation of the first high-voltage P-type well region 15a and the second high-voltage P-type well region 15b.

其中第一高壓N型隔絕區24c於通道方向上，鄰接於第一高壓P型井區15a相對於鄰接第一高壓N型井區14a之另一側。其中第二高壓N型隔絕區24d於通道方向上，鄰接於第二高壓P型井區15b相對於鄰接第二高壓N型井區14b之另一側。其中第一高壓P型隔絕區25c於通道方向上，鄰接於第一高壓N型井區14a相對於鄰接第一高壓P型井區15a之另一側。其中第二高壓P型隔絕區25d於通道方向上，鄰接於第二高壓N型井區14b相對於鄰接第二高壓N型井區15b之另一側。The first high-voltage N-type isolation region 24c is adjacent to the first high-voltage P-type well region 15a on the other side of the first high-voltage N-type well region 14a in the channel direction. The second high-voltage N-type isolation region 24d is adjacent to the second high-voltage P-type well region 15b on the other side of the second high-voltage N-type well region 14b in the channel direction. The first high-voltage P-type isolation region 25c is adjacent to the first high-voltage N-type well region 14a on the other side of the first high-voltage P-type well region 15a in the channel direction. The second high-voltage P-type isolation region 25d is adjacent to the second high-voltage N-type well region 14b on the other side of the second high-voltage N-type well region 15b in the channel direction.

其中，第一N型埋層23a、第一高壓N型隔絕區24c與第一高壓P型隔絕區25c在半導體層11’中覆蓋高壓N型元件20a外部，以於半導體層11’中電性隔絕高壓N型元件20a。其中，第二N型埋層23b、第二高壓N型隔絕區24d與第二高壓P型隔絕區25d半導體層11’中覆蓋高壓P型元件20b外部，以於半導體層11’中電性隔絕高壓P型元件20b。Wherein, the first N-type buried layer 23a, the first high-voltage N-type isolation region 24c, and the first high-voltage P-type isolation region 25c cover the outside of the high-voltage N-type element 20a in the semiconductor layer 11', so as to be electrically conductive in the semiconductor layer 11'. The high voltage N-type element 20a is isolated. Wherein, the second N-type buried layer 23b, the second high-voltage N-type isolation region 24d and the second high-voltage P-type isolation region 25d cover the outside of the high-voltage P-type element 20b in the semiconductor layer 11', so as to be electrically isolated from the semiconductor layer 11'. High voltage P-type element 20b.

形成第一N型埋層23a與第二N型埋層23b的方式，例如但不限於以離子植入製程步驟，將N型導電型雜質，以加速離子的形式，植入基板11中，而在半導體層11’形成過程中或之後，以熱擴散的方式形成第一N型埋層23a與第二N型埋層23b。The method of forming the first N-type buried layer 23a and the second N-type buried layer 23b is, for example but not limited to, implanting N-type conductive impurities into the substrate 11 in the form of accelerated ions by ion implantation process steps, and During or after the formation of the semiconductor layer 11 ′, the first N-type buried layer 23 a and the second N-type buried layer 23 b are formed by thermal diffusion.

請參考圖3A-3L，其係根據本發明之一實施例顯示高壓互補式金屬氧化物半導體元件20的製造方法之示意圖。高壓互補式金屬氧化物半導體元件20包括高壓N型元件20a以及高壓P型元件20b。如圖3A所示，首先提供基板11，並例如但不限於以離子植入製程步驟，將N型導電型雜質，以加速離子的形式，植入基板11中，而在後續半導體層11’形成過程中或之後(如圖3B所示)，以熱擴散的方式形成第一N型埋層23a與第二N型埋層23b。Please refer to FIGS. 3A-3L , which are schematic diagrams showing a manufacturing method of a high voltage CMOS device 20 according to an embodiment of the present invention. The high-voltage CMOS device 20 includes a high-voltage N-type device 20a and a high-voltage P-type device 20b. As shown in FIG. 3A, a substrate 11 is provided first, and, for example but not limited to, an ion implantation process step is used to implant N-type conductive impurities in the form of accelerated ions into the substrate 11, and the subsequent semiconductor layer 11' is formed During or after the process (as shown in FIG. 3B ), the first N-type buried layer 23 a and the second N-type buried layer 23 b are formed by thermal diffusion.

接著，請參閱圖3B，形成半導體層11’於基板11上。半導體層11’例如以磊晶的步驟，形成於基板11上，或是以基板11的部分，作為半導體層11’。如上所述，在形成半導體層11’的過程中或之後，以熱擴散的方式形成第一N型埋層23a與第二N型埋層23b。半導體層11’於垂直方向(如圖3B中之實線箭號方向所示意，下同)上，具有相對之上表面11a與下表面11b。形成半導體層11’的方式，為本領域中具有通常知識者所熟知，在此不予贅述。基板21例如但不限於為P型或N型的半導體基板。Next, referring to FIG. 3B , a semiconductor layer 11' is formed on the substrate 11. Referring to FIG. The semiconductor layer 11' is formed on the substrate 11 by epitaxy, for example, or a part of the substrate 11 is used as the semiconductor layer 11'. As mentioned above, during or after forming the semiconductor layer 11', the first N-type buried layer 23a and the second N-type buried layer 23b are formed by thermal diffusion. The semiconductor layer 11' has an upper surface 11a and a lower surface 11b opposite to each other in a vertical direction (shown by the solid arrow in FIG. 3B , the same below). The method of forming the semiconductor layer 11' is well known to those skilled in the art, and will not be repeated here. The substrate 21 is, for example but not limited to, a P-type or N-type semiconductor substrate.

接著，請參閱圖3C，例如以同一製程步驟形成絕緣區12、第一淺溝槽隔絕區22a、第二淺溝槽隔絕區22b、第三淺溝槽隔絕區22c以及第四淺溝槽隔絕區22d。絕緣區12、第一淺溝槽隔絕區22a、第二淺溝槽隔絕區22b、第三淺溝槽隔絕區22c以及第四淺溝槽隔絕區22d例如但不限於為如圖3C所示之淺溝槽隔絕(shallow trench isolation, STI)結構。Next, please refer to FIG. 3C, for example, the insulating region 12, the first STI region 22a, the second STI region 22b, the third STI region 22c and the fourth STI region are formed in the same process step. District 22d. The insulating region 12, the first STI region 22a, the second STI region 22b, the third STI region 22c and the fourth STI region 22d are, for example but not limited to, as shown in FIG. 3C Shallow trench isolation (STI) structure.

複數絕緣區12用以定義高壓N型元件區HV-NMOS與高壓P型元件區HV-PMOS，其中高壓N型元件20a形成於高壓N型元件區HV-NMOS，且高壓P型元件20b形成於該高壓P型元件區HV-PMOS。第一淺溝槽隔絕區22a與第三淺溝槽隔絕區22c形成於高壓N型元件區HV-NMOS中，第二淺溝槽隔絕區22b與第四淺溝槽隔絕區22d形成於高壓P型元件區HV-PMOS中。其中第一淺溝槽隔絕區22a位於並連接於第一漂移氧化區16a正下方，且第二淺溝槽隔絕區22b位於並連接於第二漂移氧化區16b正下方。第三淺溝槽隔絕區22c用以於半導體層11’中電性隔絕N型源極18a與P型導電區29c。第四淺溝槽隔絕區22d用以於半導體層11’中電性隔絕P型源極19a與N型導電區28c。The plurality of insulating regions 12 are used to define the high-voltage N-type element region HV-NMOS and the high-voltage P-type element region HV-PMOS, wherein the high-voltage N-type element 20a is formed in the high-voltage N-type element region HV-NMOS, and the high-voltage P-type element 20b is formed in the The high voltage P-type element region HV-PMOS. The first STI region 22a and the third STI region 22c are formed in the high voltage N-type element region HV-NMOS, and the second STI region 22b and the fourth STI region 22d are formed in the high voltage P Type element area HV-PMOS. The first STI region 22a is located and connected directly under the first drift oxide region 16a, and the second shallow trench isolation region 22b is located and connected directly under the second drift oxide region 16b. The third shallow trench isolation region 22c is used to electrically isolate the N-type source 18a and the P-type conductive region 29c in the semiconductor layer 11'. The fourth shallow trench isolation region 22d is used to electrically isolate the P-type source 19a and the N-type conductive region 28c in the semiconductor layer 11'.

接著，請參閱圖3D，以同一離子植入製程步驟形成第一高壓N型井區14a、第二高壓N型井區14b、第一高壓N型隔絕區24c與第二高壓N型隔絕區24d。Next, referring to FIG. 3D, the first high-voltage N-type well region 14a, the second high-voltage N-type well region 14b, the first high-voltage N-type isolation region 24c, and the second high-voltage N-type isolation region 24d are formed in the same ion implantation process step. .

第一高壓N型井區14a與第二高壓N型井區14b分別形成於高壓N型元件區HV-NMOS之半導體層11’中與高壓P型元件區HV-PMOS之半導體層11’中。第一高壓N型井區14a與第二高壓N型井區14b皆位於上表面11a下並連接於上表面11a。部分第一高壓N型井區14a位於閘極17a正下方並連接於閘極17a，以提供高壓N型元件10a在導通操作中之漂移電流通道；且部分第二高壓N型井區14b位於閘極17b正下方，以提供高壓P型元件10b在導通操作中之反轉電流通道。The first high-voltage N-type well region 14a and the second high-voltage N-type well region 14b are respectively formed in the semiconductor layer 11' of the high-voltage N-type device region HV-NMOS and the semiconductor layer 11' of the high-voltage P-type device region HV-PMOS. Both the first high-voltage N-type well region 14a and the second high-pressure N-type well region 14b are located under the upper surface 11a and connected to the upper surface 11a. Part of the first high-voltage N-type well region 14a is located directly below the gate electrode 17a and connected to the gate electrode 17a to provide a drift current channel for the high-voltage N-type element 10a in the conduction operation; and part of the second high-voltage N-type well region 14b is located at the gate electrode 17a. Directly below the pole 17b to provide the reverse current channel of the high-voltage P-type element 10b in the conduction operation.

其中第一高壓N型隔絕區24c於通道方向上，鄰接於第一高壓P型井區15a相對於鄰接第一高壓N型井區14a之另一側。其中第二高壓N型隔絕區24d於通道方向上，鄰接於第二高壓P型井區15b相對於鄰接第二高壓N型井區14b之另一側。The first high-voltage N-type isolation region 24c is adjacent to the first high-voltage P-type well region 15a on the other side of the first high-voltage N-type well region 14a in the channel direction. The second high-voltage N-type isolation region 24d is adjacent to the second high-voltage P-type well region 15b on the other side of the second high-voltage N-type well region 14b in the channel direction.

接著，請參閱圖3E，以同一離子植入製程步驟形成第一高壓P型井區15a、第二高壓P型井區15b、第一高壓P型隔絕區25c與第二高壓P型隔絕區25d。Next, referring to FIG. 3E, the first high-voltage P-type well region 15a, the second high-voltage P-type well region 15b, the first high-voltage P-type isolation region 25c, and the second high-voltage P-type isolation region 25d are formed in the same ion implantation process step. .

第一高壓P型井區15a與第二高壓P型井區15b，分別形成於高壓N型元件區HV-NMOS之半導體層11’中與高壓P型元件區HV-PMOS之半導體層11’中，其中第一高壓N型井區14a與第一高壓P型井區15a於通道方向(如圖3E中之虛線箭號方向所示意，下同)上鄰接，且第二高壓N型井區14b與第二高壓P型井區15b於通道方向上鄰接。The first high-voltage P-type well region 15a and the second high-voltage P-type well region 15b are respectively formed in the semiconductor layer 11' of the high-voltage N-type element region HV-NMOS and in the semiconductor layer 11' of the high-voltage P-type element region HV-PMOS , wherein the first high-pressure N-type well region 14a and the first high-pressure P-type well region 15a are adjacent to each other in the channel direction (as shown by the dashed arrow in FIG. 3E , the same below), and the second high-pressure N-type well region 14b Adjacent to the second high-pressure P-type well region 15b in the channel direction.

第一高壓P型井區15a與第二高壓P型井區15b皆位於上表面11a下並連接於上表面11a。部分第一高壓P型井區15a位於閘極17a正下方並連接於閘極17a，以提供高壓N型元件10a在導通操作中之反轉電流通道；且部分第二高壓P型井區15b位於閘極17b正下方，以提供高壓P型元件10b在導通操作中之漂移電流通道。Both the first high-voltage P-type well region 15a and the second high-pressure P-type well region 15b are located under the upper surface 11a and connected to the upper surface 11a. Part of the first high-voltage P-type well region 15a is located directly below the gate electrode 17a and connected to the gate electrode 17a to provide an inversion current channel for the high-voltage N-type element 10a in the conduction operation; and part of the second high-voltage P-type well region 15b is located at Directly below the gate 17b to provide a drift current channel for the high-voltage P-type element 10b in the conduction operation.

其中第一高壓P型隔絕區25c於通道方向上，鄰接於第一高壓N型井區14a相對於鄰接第一高壓P型井區15a之另一側。其中第二高壓P型隔絕區25d於通道方向上，鄰接於第二高壓N型井區14b相對於鄰接第二高壓N型井區15b之另一側。The first high-voltage P-type isolation region 25c is adjacent to the first high-voltage N-type well region 14a on the other side of the first high-voltage P-type well region 15a in the channel direction. The second high-voltage P-type isolation region 25d is adjacent to the second high-voltage N-type well region 14b on the other side of the second high-voltage N-type well region 15b in the channel direction.

其中，第一N型埋層23a、第一高壓N型隔絕區24c與第一高壓P型隔絕區25c在半導體層11’中覆蓋高壓N型元件20a外部，以於半導體層11’中電性隔絕高壓N型元件20a。其中，第二N型埋層23b、第二高壓N型隔絕區24d與第二高壓P型隔絕區25d半導體層11’中覆蓋高壓P型元件20b外部，以於半導體層11’中電性隔絕高壓P型元件20b。Wherein, the first N-type buried layer 23a, the first high-voltage N-type isolation region 24c, and the first high-voltage P-type isolation region 25c cover the outside of the high-voltage N-type element 20a in the semiconductor layer 11', so as to be electrically conductive in the semiconductor layer 11'. The high voltage N-type element 20a is isolated. Wherein, the second N-type buried layer 23b, the second high-voltage N-type isolation region 24d and the second high-voltage P-type isolation region 25d cover the outside of the high-voltage P-type element 20b in the semiconductor layer 11', so as to be electrically isolated from the semiconductor layer 11'. High voltage P-type element 20b.

接著，請參閱圖3F，例如但不限於以沉積(deposition)製程步驟形成漂移氧化層16於半導體層11’上，且漂移氧化層16完全覆蓋高壓N型元件區HV-NMOS與高壓P型元件區HV-PMOS。Next, please refer to FIG. 3F , for example, but not limited to, a drift oxide layer 16 is formed on the semiconductor layer 11' by deposition process steps, and the drift oxide layer 16 completely covers the high-voltage N-type element region HV-NMOS and the high-voltage P-type element Area HV-PMOS.

接著，請參閱圖3G，以同一蝕刻製程步驟蝕刻漂移氧化層16，而形成第一漂移氧化區16a於高壓N型元件區HV-NMOS中，與第二漂移氧化區16b於高壓P型元件區HV-PMOS中。第一漂移氧化區16a與第二漂移氧化16b形成於半導體層11’上，且分別位於高壓N型元件10a的漂移區與高壓P型元件10b的漂移區上。Next, referring to FIG. 3G, the drift oxide layer 16 is etched in the same etching process step to form the first drift oxide region 16a in the high-voltage N-type device region HV-NMOS, and the second drift oxide region 16b in the high-voltage P-type device region. HV-PMOS. The first drift oxide region 16a and the second drift oxide region 16b are formed on the semiconductor layer 11', and are respectively located on the drift region of the high-voltage N-type device 10a and the drift region of the high-voltage P-type device 10b.

接著，請參閱圖3H，於第一漂移氧化區16a與第二漂移氧化區16b形成之後，形成閘極介電層17’於半導體層11’上，閘極介電層17’覆蓋高壓N型元件區HV-NMOS與高壓P型元件區HV-PMOS。Next, please refer to FIG. 3H, after the formation of the first drift oxide region 16a and the second drift oxide region 16b, a gate dielectric layer 17' is formed on the semiconductor layer 11', and the gate dielectric layer 17' covers the high voltage N-type The element area HV-NMOS and the high-voltage P-type element area HV-PMOS.

接著，請參閱圖3I，於閘極介電層17’形成之後，例如但不限於以沉積製程步驟，形成多晶矽層17於閘極介電層17’上。其中，多晶矽層17覆蓋高壓N型元件區HV-NMOS與高壓P型元件區HV-PMOS。Next, please refer to FIG. 3I , after the gate dielectric layer 17' is formed, for example but not limited to deposition process steps, a polysilicon layer 17 is formed on the gate dielectric layer 17'. Wherein, the polysilicon layer 17 covers the high-voltage N-type device region HV-NMOS and the high-voltage P-type device region HV-PMOS.

接著，請參閱圖3J，於多晶矽層17形成之後，以同一蝕刻製程步驟蝕刻多晶矽層17，而形成第一閘極17a於高壓N型元件區HV-NMOS中，與第二閘極17b於高壓P型元件區HV-PMOS中。Next, please refer to FIG. 3J. After the polysilicon layer 17 is formed, the polysilicon layer 17 is etched in the same etching process to form the first gate 17a in the high-voltage N-type device region HV-NMOS, and the second gate 17b in the high-voltage In the P-type element area HV-PMOS.

需說明的是，閘極介電層17’的厚度相對大幅度的低於多晶矽層17，用以在形成第一閘極17a與第二閘極17b後，作為第一閘極17a與第二閘極17b的介電層。此為本領域中具有通常之知識者所熟知，在此不予贅述。It should be noted that the thickness of the gate dielectric layer 17' is relatively much lower than that of the polysilicon layer 17, and is used as the first gate 17a and the second gate 17b after forming the first gate 17a and the second gate 17b. Dielectric layer for gate 17b. This is well known to those with ordinary knowledge in the art, and will not be repeated here.

第一閘極17a與第二閘極17b形成於半導體層11’之上表面11a上，第一閘極17a與第二閘極17b分別包含導電層、間隔層以及介電層，其中介電層位於上表面11a上並連接於上表面11a，此為本領域中具有通常知識者所熟知，在此不予贅述。The first gate 17a and the second gate 17b are formed on the upper surface 11a of the semiconductor layer 11', and the first gate 17a and the second gate 17b respectively include a conductive layer, a spacer layer and a dielectric layer, wherein the dielectric layer It is located on and connected to the upper surface 11a, which is well known to those skilled in the art, and will not be repeated here.

接著，請參閱圖3K， 以同一離子植入製程步驟形成N型源極18a、 N型汲極18b與N型導電區28c。N型源極18a與N型汲極18b形成於高壓N型元件區HV-NMOS之半導體層11’中，且N型源極18a與N型汲極18b分別位於第一閘極17a在通道方向(如圖3K中之虛線箭號方向所示意，下同)之外部下方之第一高壓P型井區15a中與第一高壓N型井區14a中。Next, referring to FIG. 3K, the N-type source 18a, the N-type drain 18b, and the N-type conductive region 28c are formed by the same ion implantation process step. The N-type source 18a and the N-type drain 18b are formed in the semiconductor layer 11' of the high-voltage N-type element region HV-NMOS, and the N-type source 18a and the N-type drain 18b are respectively located in the channel direction of the first gate 17a (As shown in the direction of the dotted arrow in FIG. 3K , the same below), the first high-voltage P-type well region 15 a and the first high-voltage N-type well region 14 a are located below the outside.

於垂直方向上，N型源極18a與N型汲極18b形成於上表面11a下並連接於上表面11a中，且於通道方向上，高壓N型元件10a的漂移區位於N型汲極18b與第一高壓P型井區15a之間，並分隔N型汲極18b與第一高壓P型井區15a，且位於靠近上表面11a之第一高壓N型井區14a中，用以作為高壓N型元件10a在導通操作中之漂移電流通道。In the vertical direction, the N-type source 18a and the N-type drain 18b are formed under the upper surface 11a and connected to the upper surface 11a, and in the channel direction, the drift region of the high-voltage N-type element 10a is located at the N-type drain 18b Between the first high-voltage P-type well region 15a and separates the N-type drain 18b from the first high-voltage P-type well region 15a, and is located in the first high-voltage N-type well region 14a close to the upper surface 11a for high-voltage The drift current channel of the N-type element 10a in the conduction operation.

N型導電區28c形成於高壓P型元件區HV-PMOS之半導體層11’中，用以作為第二高壓N型井區14b的電性接點。The N-type conductive region 28c is formed in the semiconductor layer 11' of the high-voltage P-type device region HV-PMOS, and is used as an electrical contact of the second high-voltage N-type well region 14b.

接著，請參閱圖3L， 以同一離子植入製程步驟形成P型源極19a 、P型汲極19b與P型導電區29c。P型源極19a與P型汲極19b分別位於第二閘極17b在通道方向(如圖3L中之虛線箭號方向所示意，下同)之外部下方之第二高壓N型井區14b中與第二高壓P型井區15b中。Next, referring to FIG. 3L, the P-type source 19a, the P-type drain 19b, and the P-type conductive region 29c are formed by the same ion implantation process step. The P-type source 19a and the P-type drain 19b are respectively located in the second high-voltage N-type well region 14b outside the second gate 17b in the channel direction (shown in the direction of the dashed arrow in FIG. 3L , the same below). and the second high-pressure P-type well region 15b.

於垂直方向上，P型源極19a與P型汲極19b形成於上表面11a下並連接於上表面11a中，且於通道方向上，高壓P型元件10b的漂移區位於P型汲極19b與第二高壓N型井區14b之間，並分隔P型汲極19b與第二高壓N型井區14b，且位於靠近上表面11a之第二高壓P型井區15b中，用以作為高壓P型元件10b在導通操作中之漂移電流通道。In the vertical direction, the P-type source 19a and the P-type drain 19b are formed under the upper surface 11a and connected to the upper surface 11a, and in the channel direction, the drift region of the high-voltage P-type element 10b is located at the P-type drain 19b Between the second high-voltage N-type well region 14b and separates the P-type drain 19b from the second high-voltage N-type well region 14b, and is located in the second high-voltage P-type well region 15b near the upper surface 11a for high-voltage The drift current channel of the P-type element 10b in the conduction operation.

P型導電區29c形成於高壓N型元件區HV-NMOS之半導體層11’中，用以作為第一高壓P型井區15a的電性接點。The P-type conductive region 29c is formed in the semiconductor layer 11' of the high-voltage N-type element region HV-NMOS, and is used as an electrical contact of the first high-voltage P-type well region 15a.

以上已針對較佳實施例來說明本發明，唯以上所述者，僅係為使熟悉本技術者易於了解本發明的內容而已，並非用來限定本發明之權利範圍。在本發明之相同精神下，熟悉本技術者可以思及各種等效變化。例如，在不影響元件主要的特性下，可加入其他製程步驟或結構，如輕摻雜汲極區等；又如，微影技術並不限於光罩技術，亦可包含電子束微影技術。凡此種種，皆可根據本發明的教示類推而得。此外，所說明之各個實施例，並不限於單獨應用，亦可以組合應用，例如但不限於將兩實施例併用。因此，本發明的範圍應涵蓋上述及其他所有等效變化。此外，本發明的任一實施型態不必須達成所有的目的或優點，因此，請求專利範圍任一項也不應以此為限。The present invention has been described above with reference to preferred embodiments, but the above description is only for making those skilled in the art easily understand the content of the present invention, and is not intended to limit the scope of rights of the present invention. Within the same spirit of the present invention, various equivalent changes can be conceived by those skilled in the art. For example, without affecting the main characteristics of the device, other process steps or structures can be added, such as lightly doped drain regions, etc.; as another example, the lithography technology is not limited to the photomask technology, and can also include electron beam lithography technology. All these can be obtained by analogy according to the teaching of the present invention. In addition, each of the described embodiments is not limited to be used alone, and can also be used in combination, for example but not limited to using the two embodiments together. Accordingly, the scope of the invention should encompass the above and all other equivalent variations. In addition, any implementation form of the present invention does not necessarily achieve all purposes or advantages, and therefore, any one of the claims should not be limited thereto.

10, 20:高壓互補式金屬氧化物半導體元件 10a, 20a:高壓N型元件 10b, 20b:高壓P型元件 11:基板 11’:半導體層 11a:上表面 11b:下表面 12:絕緣區 13a:第一N型埋層 13b:第二N型埋層 14a:第一高壓N型井區 14b:第二高壓N型井區 14c:第一高壓N型隔絕區 14d:第二高壓N型隔絕區 15a:第一高壓P型井區 15b:第二高壓P型井區 15c:第一高壓P型隔絕區 15d:第二高壓P型隔絕區 16:漂移氧化層 16a:第一漂移氧化區 16b:第二漂移氧化區 17:多晶矽層 17a:第一閘極 17b:第二閘極 17’:閘極介電層 18a:N型源極 18b:N型汲極 18c:N型導電區 19a:P型源極 19b:P型汲極 19c:P型導電區 22a:第一淺溝槽隔絕 22b:第二淺溝槽隔絕區 22c:第三淺溝槽隔絕區 22d:第四淺溝槽隔絕區 23a:第一N型埋層 23b:第二N型埋層 24c:第一高壓N型隔絕區 24d:第二高壓N型隔絕區 25c:第一高壓P型隔絕區 25d:第二高壓P型隔絕區 28c:P型導電區 29c:N型導電區 HV-NMOS:高壓N型元件區 HV-PMOS:高壓P型元件區 10, 20: High Voltage Complementary Metal Oxide Semiconductor Devices 10a, 20a: High voltage N-type components 10b, 20b: High voltage P-type components 11: Substrate 11': semiconductor layer 11a: upper surface 11b: lower surface 12: Insulation area 13a: the first N-type buried layer 13b: The second N-type buried layer 14a: The first high-pressure N-type well area 14b: The second high pressure N-type well area 14c: The first high-voltage N-type isolation area 14d: The second high voltage N-type isolation area 15a: The first high-pressure P-type well area 15b: The second high pressure P-type well area 15c: The first high-voltage P-type isolation area 15d: The second high-voltage P-type isolation area 16: Drift oxide layer 16a: The first drift oxidation region 16b: The second drift oxidation region 17: Polysilicon layer 17a: The first gate 17b: The second gate 17': gate dielectric layer 18a: N-type source 18b: N-type drain 18c: N-type conductive region 19a: P-type source 19b: P-type drain 19c: P-type conductive region 22a: The first shallow trench isolation 22b: second shallow trench isolation region 22c: The third shallow trench isolation region 22d: The fourth shallow trench isolation region 23a: the first N-type buried layer 23b: The second N-type buried layer 24c: The first high-voltage N-type isolation area 24d: The second high voltage N-type isolation area 25c: The first high-voltage P-type isolation area 25d: The second high-voltage P-type isolation area 28c: P-type conductive region 29c: N-type conductive region HV-NMOS: High voltage N-type component area HV-PMOS: High voltage P-type component area

圖1為據本發明之一實施例，顯示高壓互補式金屬氧化物半導體元件之剖視示意圖。FIG. 1 is a schematic cross-sectional view showing a high-voltage complementary metal-oxide-semiconductor device according to an embodiment of the present invention.

圖2為據本發明之一實施例，顯示高壓互補式金屬氧化物半導體元件之剖視示意圖。FIG. 2 is a schematic cross-sectional view showing a high-voltage complementary metal-oxide-semiconductor device according to an embodiment of the present invention.

圖3A-3L係根據本發明之一實施例，顯示高壓互補式金屬氧化物半導體元件製造方法之剖視示意圖。3A-3L are schematic cross-sectional views showing a method for manufacturing a high-voltage complementary metal-oxide-semiconductor device according to an embodiment of the present invention.

10:高壓互補式金屬氧化物半導體元件 10: High-voltage complementary metal-oxide-semiconductor components

10a:高壓N型元件 10a: High voltage N-type components

10b:高壓P型元件 10b: High voltage P-type element

11:基板 11: Substrate

11’:半導體層 11': semiconductor layer

11a:上表面 11a: upper surface

11b:下表面 11b: lower surface

12:絕緣區 12: Insulation area

14a:第一高壓N型井區 14a: The first high-pressure N-type well area

14b:第二高壓N型井區 14b: The second high pressure N-type well area

15a:第一高壓P型井區 15a: The first high-pressure P-type well area

15b:第二高壓P型井區 15b: The second high pressure P-type well area

16a:第一漂移氧化區 16a: The first drift oxidation region

16b:第二漂移氧化區 16b: The second drift oxidation region

17a:第一閘極 17a: The first gate

17b:第二閘極 17b: The second gate

18a:N型源極 18a: N-type source

18b:N型汲極 18b: N-type drain

19a:P型源極 19a: P-type source

19b:P型汲極 19b: P-type drain

HV-NMOS:高壓N型元件區 HV-NMOS: High voltage N-type component area

HV-PMOS:高壓P型元件區 HV-PMOS: High voltage P-type component area

Claims (20)

一種高壓互補式金屬氧化物半導體(CMOS)元件，包含： 一半導體層，形成於一基板上； 複數絕緣區，形成於該半導體層上，用以定義一高壓N型元件區與一高壓P型元件區，其中一高壓N型元件形成於該高壓N型元件區，且一高壓P型元件形成於該高壓P型元件區； 一第一高壓N型井區與一第二高壓N型井區，以同一離子植入製程步驟分別形成於該高壓N型元件區之該半導體層中與該高壓P型元件區之該半導體層中； 一第一高壓P型井區與一第二高壓P型井區，以同一離子植入製程步驟分別形成於該高壓N型元件區之該半導體層中與該高壓P型元件區之該半導體層中，其中該第一高壓N型井區與該第一高壓P型井區於一通道方向上鄰接，且該第二高壓N型井區與該第二高壓P型井區於該通道方向上鄰接； 一第一漂移氧化區與一第二漂移氧化區，以同一蝕刻製程步驟蝕刻一漂移氧化層，而分別形成該第一漂移氧化區與該第二漂移氧化區於該高壓N型元件區中與該高壓P型元件區中； 一第一閘極與一第二閘極，以同一蝕刻製程步驟蝕刻一多晶矽層，而分別形成該第一閘極與該第二閘極於該高壓N型元件區中與該高壓P型元件區中； 一N型源極與一N型汲極，以同一離子植入製程步驟形成於該高壓N型元件區之該半導體層中，且該N型源極與該N型汲極分別位於該第一閘極之外部下方之該第一高壓P型井區中與該第一高壓N型井區中；以及 一P型源極與一P型汲極，以同一離子植入製程步驟形成於該高壓P型元件區之該半導體層中，且該P型源極與該P型汲極分別位於該第二閘極之外部下方之該第二高壓N型井區中與該第二高壓P型井區中。 A high voltage complementary metal oxide semiconductor (CMOS) device comprising: a semiconductor layer formed on a substrate; A plurality of insulating regions are formed on the semiconductor layer to define a high-voltage N-type element region and a high-voltage P-type element region, wherein a high-voltage N-type element is formed in the high-voltage N-type element region, and a high-voltage P-type element is formed In the high-voltage P-type element area; A first high-voltage N-type well region and a second high-voltage N-type well region are respectively formed in the semiconductor layer of the high-voltage N-type element region and the semiconductor layer of the high-voltage P-type element region by the same ion implantation process step middle; A first high-voltage P-type well region and a second high-voltage P-type well region are respectively formed in the semiconductor layer of the high-voltage N-type element region and the semiconductor layer of the high-voltage P-type element region by the same ion implantation process step , wherein the first high-pressure N-type well region is adjacent to the first high-pressure P-type well region in a passage direction, and the second high-pressure N-type well region and the second high-pressure P-type well region are in the passage direction Adjacent; For a first drift oxide region and a second drift oxide region, a drift oxide layer is etched in the same etching process step, and the first drift oxide region and the second drift oxide region are respectively formed in the high-voltage N-type device region and In the high-voltage P-type element area; A first gate and a second gate are etched in the same etching process step to form a polysilicon layer, respectively forming the first gate and the second gate in the high-voltage N-type element region and the high-voltage P-type element in the district; An N-type source and an N-type drain are formed in the semiconductor layer of the high-voltage N-type element region by the same ion implantation process step, and the N-type source and the N-type drain are respectively located on the first In the first high voltage P-type well region and in the first high voltage N-type well region under the exterior of the gate; and A P-type source and a P-type drain are formed in the semiconductor layer of the high-voltage P-type device region by the same ion implantation process step, and the P-type source and the P-type drain are respectively located on the second In the second high-voltage N-type well region and in the second high-voltage P-type well region under the exterior of the gate. 如請求項1所述之高壓互補式金屬氧化物半導體元件，更包含：一第一淺溝槽隔絕(shallow trench isolation, STI)區與一第二淺溝槽隔絕區，以同一製程步驟分別形成於該高壓N型元件區中與該高壓P型元件區中，其中該第一淺溝槽隔絕區位於並連接於該第一漂移氧化區正下方，且該第二淺溝槽隔絕區位於並連接於該第二漂移氧化區正下方。The high-voltage complementary metal-oxide-semiconductor device as described in claim 1, further comprising: a first shallow trench isolation (shallow trench isolation, STI) region and a second shallow trench isolation region, which are respectively formed in the same process step In the high-voltage N-type device region and in the high-voltage P-type device region, wherein the first shallow trench isolation region is located and connected directly below the first drift oxide region, and the second shallow trench isolation region is located and connected Connected directly below the second drift oxidation region. 如請求項1所述之高壓互補式金屬氧化物半導體元件，更包含： 一N型導電區，以形成該N型源極與該N型汲極之同一離子植入製程步驟形成於該第二高壓N型井區中，其中該N型導電區為該第二高壓N型井區之電性接點；以及 一P型導電區，以形成該P型源極與該P型汲極之同一離子植入製程步驟形成於該第一高壓P型井區中，其中該P型導電區為該第一高壓P型井區之電性接點。 The high-voltage complementary metal-oxide-semiconductor device as described in claim 1 further includes: An N-type conductive region is formed in the second high-voltage N-type well region by the same ion implantation process step of forming the N-type source and the N-type drain, wherein the N-type conductive region is the second high-voltage N The electrical contacts of the type well area; and A P-type conductive region is formed in the first high-voltage P-type well region by the same ion implantation process step of forming the P-type source and the P-type drain, wherein the P-type conductive region is the first high-voltage P The electrical contact of the type well area. 如請求項1所述之高壓互補式金屬氧化物半導體元件，更包含： 一第一N型埋層與一第二N型埋層，以同一製程步驟分別形成於該高壓N型元件區與該高壓P型元件區中； 其中該第一N型埋層形成於並連接於該第一高壓N型井區與該第一高壓P型井區正下方之該半導體層與該基板中； 其中該第二N型埋層形成於並連接於該第二高壓N型井區與該第二高壓P型井區正下方之該半導體層與該基板中。 The high-voltage complementary metal-oxide-semiconductor device as described in claim 1 further includes: A first N-type buried layer and a second N-type buried layer are respectively formed in the high-voltage N-type element region and the high-voltage P-type element region by the same process step; Wherein the first N-type buried layer is formed in and connected to the semiconductor layer and the substrate directly below the first high-voltage N-type well region and the first high-voltage P-type well region; The second N-type buried layer is formed in and connected to the semiconductor layer and the substrate directly below the second high-voltage N-type well region and the second high-voltage P-type well region. 如請求項1所述之高壓互補式金屬氧化物半導體元件，其更包含： 一第一高壓N型隔絕區與一第二高壓N型隔絕區，以形成該第一高壓N型井區與該第二高壓N型井區同一離子植入製程步驟而形成；以及 一第一高壓P型隔絕區與一第二高壓P型隔絕區，以形成該第一高壓P型井區與該第二高壓P型井區同一離子植入製程步驟而形成； 其中該第一高壓N型隔絕區於該通道方向上，鄰接於該第一高壓P型井區相對於鄰接該第一高壓N型井區之另一側； 其中該第二高壓N型隔絕區於該通道方向上，鄰接於該第二高壓P型井區相對於鄰接該第二高壓N型井區之另一側； 其中該第一高壓P型隔絕區於該通道方向上，鄰接於該第一高壓N型井區相對於鄰接該第一高壓P型井區之另一側； 其中該第二高壓P型隔絕區於該通道方向上，鄰接於該第二高壓N型井區相對於鄰接該第二高壓N型井區之另一側。 The high-voltage complementary metal-oxide-semiconductor device as described in claim 1, further comprising: A first high-voltage N-type isolation region and a second high-voltage N-type isolation region are formed in the same ion implantation process step as the first high-voltage N-type well region and the second high-voltage N-type well region; and A first high-voltage P-type isolation region and a second high-voltage P-type isolation region are formed by the same ion implantation process step as forming the first high-voltage P-type well region and the second high-voltage P-type well region; Wherein the first high-voltage N-type isolation region is adjacent to the first high-voltage P-type well region on the other side of the first high-pressure N-type well region in the direction of the channel; Wherein the second high-voltage N-type isolation region is adjacent to the second high-pressure P-type well region on the other side of the second high-voltage N-type well region in the channel direction; Wherein the first high-voltage P-type isolation region is adjacent to the first high-voltage N-type well region on the other side of the first high-voltage P-type well region in the direction of the channel; Wherein the second high-voltage P-type isolation region is adjacent to the second high-voltage N-type well region on the other side of the second high-voltage N-type well region in the channel direction. 如請求項1所述之高壓互補式金屬氧化物半導體元件，其中該半導體層係一P型半導體磊晶層，且具有體積電阻率45 Ohm-cm。The high-voltage complementary metal-oxide-semiconductor device as claimed in claim 1, wherein the semiconductor layer is a P-type semiconductor epitaxial layer, and has a volume resistivity of 45 Ohm-cm. 如請求項1所述之高壓互補式金屬氧化物半導體元件，其中該第一漂移氧化區與該第二漂移氧化區之厚度介於400Å與450 Å之間。The high-voltage complementary metal-oxide-semiconductor device as claimed in claim 1, wherein the thickness of the first drift oxide region and the second drift oxide region is between 400 Å and 450 Å. 如請求項1所述之高壓互補式金屬氧化物半導體元件，其中該第一閘極之介電層與該第二閘極之介電層之厚度介於80Å與100 Å之間。The high-voltage complementary metal-oxide-semiconductor device as claimed in claim 1, wherein the thickness of the dielectric layer of the first gate and the dielectric layer of the second gate is between 80 Å and 100 Å. 如請求項1所述之高壓互補式金屬氧化物半導體元件，其中該高壓N型元件的閘極驅動電壓為3.3V。The high-voltage complementary metal-oxide-semiconductor device as claimed in claim 1, wherein the gate driving voltage of the high-voltage N-type device is 3.3V. 如請求項1所述之高壓互補式金屬氧化物半導體元件，其中該高壓互補式金屬氧化物半導體元件之最小特徵尺寸為0.18微米。The high-voltage complementary metal-oxide-semiconductor device as claimed in claim 1, wherein the minimum feature size of the high-voltage complementary metal-oxide-semiconductor device is 0.18 μm. 一種高壓互補式金屬氧化物半導體(CMOS)元件製造方法，其中該高壓互補式金屬氧化物半導體元件包括一高壓N型元件以及一高壓P型元件，該高壓互補式金屬氧化物半導體元件製造方法包含： 形成一半導體層於一基板上； 形成複數絕緣區於該半導體層上，以定義一高壓N型元件區與一高壓P型元件區，其中該高壓N型元件形成於該高壓N型元件區，且該高壓P型元件形成於該高壓P型元件區； 以同一離子植入製程步驟形成一第一高壓N型井區於該高壓N型元件區之該半導體層中，與一第二高壓N型井區於該高壓P型元件區之該半導體層中； 以同一離子植入製程步驟形成一第一高壓P型井區於該高壓N型元件區之該半導體層中，與一第二高壓P型井區於該高壓P型元件區之該半導體層中，其中該第一高壓N型井區與該第一高壓P型井區於一通道方向上鄰接，且該第二高壓N型井區與該第二高壓P型井區於該通道方向上鄰接； 形成一漂移氧化層於該半導體層上，該漂移氧化層覆蓋該高壓N型元件區與該高壓P型元件區； 以同一蝕刻製程步驟蝕刻該漂移氧化層，而形成一第一漂移氧化區於該高壓N型元件區中，與一第二漂移氧化區於該高壓P型元件區中； 於該第一漂移氧化區與該第二漂移氧化區形成之後，形成一閘極介電層於該半導體層上，該閘極介電層覆蓋該高壓N型元件區與該高壓P型元件區； 形成一多晶矽層於該閘極介電層上，該多晶矽層覆蓋該高壓N型元件區與該高壓P型元件區； 以同一蝕刻製程步驟蝕刻該多晶矽層，而形成一第一閘極於該高壓N型元件區中，與一第二閘極於該高壓P型元件區中； 以同一離子植入製程步驟形成一N型源極與一N型汲極於該高壓N型元件區之該半導體層中，且該N型源極與該N型汲極分別位於該第一閘極之外部下方之該第一高壓P型井區中與該第一高壓N型井區中；以及 以同一離子植入製程步驟形成一P型源極與一P型汲極於該高壓P型元件區之該半導體層中，且該P型源極與該P型汲極分別位於該第二閘極之外部下方之該第二高壓N型井區中與該第二高壓P型井區中。 A method for manufacturing a high-voltage complementary metal oxide semiconductor (CMOS) element, wherein the high-voltage complementary metal oxide semiconductor element includes a high-voltage N-type element and a high-voltage P-type element, and the high-voltage complementary metal-oxide semiconductor element manufacturing method includes : forming a semiconductor layer on a substrate; A plurality of insulating regions are formed on the semiconductor layer to define a high-voltage N-type element region and a high-voltage P-type element region, wherein the high-voltage N-type element is formed in the high-voltage N-type element region, and the high-voltage P-type element is formed in the high-voltage P-type element region. High voltage P-type component area; Forming a first high-voltage N-type well region in the semiconductor layer of the high-voltage N-type device region and a second high-voltage N-type well region in the semiconductor layer of the high-voltage P-type device region by using the same ion implantation process step ; Forming a first high-voltage P-type well region in the semiconductor layer of the high-voltage N-type device region and a second high-voltage P-type well region in the semiconductor layer of the high-voltage P-type device region by using the same ion implantation process step , wherein the first high-pressure N-type well region is adjacent to the first high-pressure P-type well region in a channel direction, and the second high-pressure N-type well region is adjacent to the second high-pressure P-type well region in the channel direction ; forming a drift oxide layer on the semiconductor layer, the drift oxide layer covers the high-voltage N-type element region and the high-voltage P-type element region; Etching the drift oxide layer with the same etching process step to form a first drift oxide region in the high-voltage N-type device region and a second drift oxide region in the high-voltage P-type device region; After the first drift oxide region and the second drift oxide region are formed, a gate dielectric layer is formed on the semiconductor layer, and the gate dielectric layer covers the high-voltage N-type element region and the high-voltage P-type element region ; forming a polysilicon layer on the gate dielectric layer, the polysilicon layer covering the high-voltage N-type element region and the high-voltage P-type element region; Etching the polysilicon layer with the same etching process step to form a first gate in the high-voltage N-type device region and a second gate in the high-voltage P-type device region; An N-type source and an N-type drain are formed in the semiconductor layer of the high-voltage N-type element region by the same ion implantation process step, and the N-type source and the N-type drain are respectively located at the first gate In the first high pressure P-type well region and in the first high pressure N-type well region below the extreme exterior; and A P-type source and a P-type drain are formed in the semiconductor layer of the high-voltage P-type element region by the same ion implantation process step, and the P-type source and the P-type drain are respectively located at the second gate In the second high-voltage N-type well region and in the second high-voltage P-type well region below the pole. 如請求項11所述之高壓互補式金屬氧化物半導體元件製造方法，更包含：以同一製程步驟形成一第一淺溝槽隔絕(shallow trench isolation, STI)區於該高壓N型元件區中，與一第二淺溝槽隔絕區於該高壓P型元件區中，其中該第一淺溝槽隔絕區位於並連接於該第一漂移氧化區正下方，且該第二淺溝槽隔絕區位於並連接於該第二漂移氧化區正下方。The method for manufacturing a high-voltage complementary metal-oxide-semiconductor device as described in Claim 11, further comprising: forming a first shallow trench isolation (shallow trench isolation, STI) region in the high-voltage N-type device region by the same process step, and a second shallow trench isolation region in the high-voltage P-type element region, wherein the first shallow trench isolation region is located and connected directly under the first drift oxidation region, and the second shallow trench isolation region is located And connected directly below the second drift oxidation region. 如請求項11所述之高壓互補式金屬氧化物半導體元件製造方法，更包含： 以形成該N型源極與該N型汲極之同一離子植入製程步驟形成一N型導電區於該第二高壓N型井區中，其中該N型導電區為該第二高壓N型井區之電性接點；以及 以形成該P型源極與該P型汲極之同一離子植入製程步驟形成一P型導電區於該第一高壓P型井區中，其中該P型導電區為該第一高壓P型井區之電性接點。 The method for manufacturing a high-voltage complementary metal-oxide-semiconductor device as described in Claim 11 further includes: Forming an N-type conduction region in the second high-voltage N-type well region by the same ion implantation process step of forming the N-type source and the N-type drain, wherein the N-type conduction region is the second high-voltage N-type electrical contacts in the well area; and A P-type conductive region is formed in the first high-voltage P-type well region by the same ion implantation process step of forming the P-type source and the P-type drain, wherein the P-type conductive region is the first high-voltage P-type The electrical contact of the well area. 如請求項11所述之高壓互補式金屬氧化物半導體元件製造方法，更包含：以同一製程步驟形成一第一N型埋層與一第二N型埋層，其中該第一N型埋層位於該高壓N型元件區中，該第二N型埋層位於該高壓P型元件區中； 其中該第一N型埋層形成於該第一高壓N型井區與該第一高壓P型井區正下方之該半導體層與該基板中； 其中該第二N型埋層形成於該第二高壓N型井區與該第二高壓P型井區正下方之該半導體層與該基板中。 The method for manufacturing a high-voltage complementary metal-oxide-semiconductor device as described in Claim 11 further includes: forming a first N-type buried layer and a second N-type buried layer in the same process step, wherein the first N-type buried layer Located in the high-voltage N-type element region, the second N-type buried layer is located in the high-voltage P-type element region; Wherein the first N-type buried layer is formed in the semiconductor layer and the substrate directly below the first high-voltage N-type well region and the first high-voltage P-type well region; Wherein the second N-type buried layer is formed in the semiconductor layer and the substrate directly below the second high-voltage N-type well region and the second high-voltage P-type well region. 如請求項11所述之高壓互補式金屬氧化物半導體元件製造方法，更包含： 以形成該第一高壓N型井區與該第二高壓N型井區同一離子植入製程步驟，形成一第一高壓N型隔絕區與一第二高壓N型隔絕區；以及 以形成該第一高壓P型井區與該第二高壓P型井區同一離子植入製程步驟，形成一第一高壓P型隔絕區與一第二高壓P型隔絕區； 其中該第一高壓N型隔絕區於該通道方向上，鄰接於該第一高壓P型井區相對於鄰接該第一高壓N型井區之另一側； 其中該第二高壓N型隔絕區於該通道方向上，鄰接於該第二高壓P型井區相對於鄰接該第二高壓N型井區之另一側； 其中該第一高壓P型隔絕區於該通道方向上，鄰接於該第一高壓N型井區相對於鄰接該第一高壓P型井區之另一側； 其中該第二高壓P型隔絕區於該通道方向上，鄰接於該第二高壓N型井區相對於鄰接該第二高壓N型井區之另一側。 The method for manufacturing a high-voltage complementary metal-oxide-semiconductor device as described in Claim 11 further includes: Forming the first high-voltage N-type well region and the second high-voltage N-type well region in the same ion implantation process step to form a first high-voltage N-type isolation region and a second high-voltage N-type isolation region; and Forming the first high-voltage P-type well region and the second high-voltage P-type well region in the same ion implantation process step to form a first high-voltage P-type isolation region and a second high-voltage P-type isolation region; Wherein the first high-voltage N-type isolation region is adjacent to the first high-voltage P-type well region on the other side of the first high-pressure N-type well region in the direction of the channel; Wherein the second high-voltage N-type isolation region is adjacent to the second high-pressure P-type well region on the other side of the second high-voltage N-type well region in the channel direction; Wherein the first high-voltage P-type isolation region is adjacent to the first high-voltage N-type well region on the other side of the first high-voltage P-type well region in the direction of the channel; Wherein the second high-voltage P-type isolation region is adjacent to the second high-voltage N-type well region on the other side of the second high-voltage N-type well region in the channel direction. 如請求項11所述之高壓互補式金屬氧化物半導體元件製造方法，其中該半導體層係一P型半導體磊晶層，且具有體積電阻率45 Ohm-cm。The method for manufacturing a high-voltage complementary metal-oxide-semiconductor device as claimed in claim 11, wherein the semiconductor layer is a P-type semiconductor epitaxial layer, and has a volume resistivity of 45 Ohm-cm. 如請求項11所述之高壓互補式金屬氧化物半導體元件製造方法，其中該第一漂移氧化區與該第二漂移氧化區之厚度介於400Å與450 Å之間。The method for manufacturing a high-voltage complementary metal-oxide-semiconductor device as claimed in claim 11, wherein the thickness of the first drift oxide region and the second drift oxide region is between 400Å and 450Å. 如請求項11所述之高壓互補式金屬氧化物半導體元件製造方法，其中該第一閘極之介電層與該第二閘極之介電層之厚度介於80Å與100 Å之間。The method for manufacturing a high-voltage complementary metal-oxide-semiconductor device as described in Claim 11, wherein the thickness of the dielectric layer of the first gate and the dielectric layer of the second gate is between 80 Å and 100 Å. 如請求項11所述之高壓互補式金屬氧化物半導體元件製造方法，其中該高壓N型元件的閘極驅動電壓為3.3V。The method for manufacturing a high-voltage complementary metal-oxide-semiconductor device as claimed in claim 11, wherein the gate driving voltage of the high-voltage N-type device is 3.3V. 如請求項11所述之高壓互補式金屬氧化物半導體元件製造方法，其中該高壓互補式金屬氧化物半導體元件之最小特徵尺寸為0.18微米。The method for manufacturing a high-voltage complementary metal-oxide-semiconductor device as claimed in claim 11, wherein the minimum feature size of the high-voltage complementary metal-oxide-semiconductor device is 0.18 microns.
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