TWI796237B - Integration manufacturing method of depletion high voltage nmos device and depletion low voltage nmos device - Google Patents

Integration manufacturing method of depletion high voltage nmos device and depletion low voltage nmos device Download PDF

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TWI796237B
TWI796237B TW111121084A TW111121084A TWI796237B TW I796237 B TWI796237 B TW I796237B TW 111121084 A TW111121084 A TW 111121084A TW 111121084 A TW111121084 A TW 111121084A TW I796237 B TWI796237 B TW I796237B
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depletion
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TW202324507A (en
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翁武得
熊志文
楊大勇
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立錡科技股份有限公司
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    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
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    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
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    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823412—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
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    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823437—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
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    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823462—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate insulating layers, e.g. different gate insulating layer thicknesses, particular gate insulator materials or particular gate insulator implants
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    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823481—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure

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Abstract

An integration manufacturing method of a depletion high voltage NMOS device and a depletion low voltage NMOS device. The integration manufacturing method includes: providing a substrate; forming a semiconductor layer on the substrate; forming a plurality of insulation regions on the semiconductor layer; forming an N-type well in the depletion high voltage NMOS device region; forming a high voltage P-type well in the semiconductor layer, wherein the N-type well and the high voltage P-type well are connected to each other in a lateral direction; forming an oxide layer on the semiconductor layer after the N-type well and the high voltage P-type well formed; forming a low voltage P-type well; and forming an N-type high voltage channel region and an N-type low voltage channel region, such that each of the depletion high voltage NMOS device and the depletion low voltage NMOS device turns ON when a gate-source voltage thereof is zero voltage.

Description

空乏型高壓NMOS元件與空乏型低壓NMOS元件整合製造方法Integrated manufacturing method of depletion-type high-voltage NMOS element and depletion-type low-voltage NMOS element

本發明有關於一種空乏型高壓NMOS元件與空乏型低壓NMOS元件整合製造方法，特別是指一種空乏型高壓NMOS元件與空乏型低壓NMOS元件於各自的閘極-源極電壓為零時導通的空乏型高壓NMOS元件與空乏型低壓NMOS元件整合製造方法。 The invention relates to an integrated manufacturing method of a depletion-type high-voltage NMOS element and a depletion-type low-voltage NMOS element, in particular to a depletion-type high-voltage NMOS element and a depletion-type low-voltage NMOS element that are turned on when their respective gate-source voltages are zero. The integrated manufacturing method of the type high-voltage NMOS element and the depletion type low-voltage NMOS element.

典型的空乏型低壓NMOS元件製造方法中，在形成低壓井區之前，形成犧牲氧化層用以作為形成低壓井區之離子植入製程步驟中，離子植入的阻擋層，以避免半導體層本身直接遭受離子轟擊而產生缺陷。 In a typical manufacturing method of a depletion-type low-voltage NMOS device, before forming a low-voltage well region, a sacrificial oxide layer is formed to serve as a barrier layer for ion implantation in the ion implantation process step of forming a low-voltage well region, so as to avoid direct contact of the semiconductor layer itself. Defects are created by ion bombardment.

而犧牲氧化層係以熱氧化(thermal oxide)製程步驟所形成。而熱氧化製程步驟必然伴隨著熱預算(thermal budget)。熱預算的控制對半導體元件的整合製程來說相當重要。因此，隨著半導體元件的尺寸逐漸縮小，熱預算的控制就越加重要。 The sacrificial oxide layer is formed by thermal oxide process steps. The thermal oxidation process step is necessarily accompanied by a thermal budget. Thermal budget control is very important for the integration process of semiconductor devices. Therefore, as the size of semiconductor components shrinks, thermal budget control becomes more and more important.

有鑑於此，本發明提出一種能夠減少熱預算的空乏型高壓NMOS元件與空乏型低壓NMOS元件整合製造方法，以更佳地控制半導體元件中，所摻雜之雜質的輪廓。 In view of this, the present invention proposes an integrated manufacturing method of depletion-type high-voltage NMOS elements and depletion-type low-voltage NMOS elements capable of reducing thermal budget, so as to better control the profile of doped impurities in semiconductor elements.

就其中一觀點言，本發明提供了一種空乏型高壓NMOS元件與空乏型低壓NMOS元件整合製造方法，包含：提供一基板；形成一半導體層於該基板上；形成複數絕緣區於該半導體層上，以定義一空乏型高壓NMOS元件區與一空乏型低壓NMOS元件區；形成一N型井區於該半導體層中之該空乏型高壓NMOS元件區中，其中，部分該N型井區定義一漂移區，用以作為該空乏型高壓NMOS元件在一導通操作中之一漂移電流通道；形成一高壓P型井區於該空乏型高壓NMOS元件區中之該半導體層中，其中該N型井區與該高壓P型井區於一通道方向上連接；於該N型井區與該高壓P型井區形成之後，形成一氧化層於該半導體層上，該氧化層覆蓋該空乏型高壓NMOS元件區與該空乏型低壓NMOS元件區；於該氧化層形成之後，以一離子植入製程步驟，將雜質以加速離子的形式，穿透該氧化層，植入一定義區中，形成一低壓P型井區於該半導體層中之該空乏型低壓NMOS元件區中；以及以同一離子製程步驟形成一N型高壓通道區與一N型低壓通道區，分別位於該空乏型高壓NMOS元件區與該空乏型低壓NMOS元件區，以使該空乏型高壓NMOS元件與該空乏型低壓NMOS元件於各自的閘極-源極電壓為零時導通。 From one point of view, the present invention provides an integrated manufacturing method of a depletion-type high-voltage NMOS element and a depletion-type low-voltage NMOS element, comprising: providing a substrate; forming a semiconductor layer on the substrate; forming a plurality of insulating regions on the semiconductor layer , to define a depletion-type high-voltage NMOS element region and a depletion-type low-voltage NMOS element region; forming an N-type well region in the depletion-type high-voltage NMOS element region in the semiconductor layer, wherein part of the N-type well region defines a The drift region is used as a drift current channel of the depletion-type high-voltage NMOS element in a conduction operation; a high-voltage P-type well region is formed in the semiconductor layer in the depletion-type high-voltage NMOS element region, wherein the N-type well region and the high-voltage P-type well region are connected in a channel direction; after the N-type well region and the high-voltage P-type well region are formed, an oxide layer is formed on the semiconductor layer, and the oxide layer covers the depletion-type high-voltage NMOS The element region and the depletion-type low-voltage NMOS element region; after the formation of the oxide layer, an ion implantation process step is used to penetrate impurities in the form of accelerated ions into the oxide layer and implant them into a defined region to form a low-voltage The P-type well region is in the depletion-type low-voltage NMOS element region in the semiconductor layer; and an N-type high-voltage channel region and an N-type low-voltage channel region are formed in the same ion process step, respectively located in the depletion-type high-voltage NMOS element region and the N-type low-voltage channel region. The depletion-type low-voltage NMOS element region is such that the depletion-type high-voltage NMOS element and the depletion-type low-voltage NMOS element are turned on when their respective gate-source voltages are zero.

在一種較佳的實施型態中，該空乏型高壓NMOS元件與空乏型低壓NMOS元件整合製造方法，更包含：以一離子製程步驟形成一高壓N型埋層於該基板上之該空乏型高壓NMOS元件區中；以與形成該N型井區同一離子製程步驟形成一第一N型隔絕區於該半導體層中，該第一N型隔絕區於一垂直方向上連接該高壓N型埋層，且於一通道方向上，該第一N型隔絕區鄰接於該高壓P型井區相對於鄰接該N型井區之另一側；以與形成該高 壓P型井區同一離子製程步驟形成一第一P型隔絕區於該空乏型高壓NMOS元件區與該空乏型低壓NMOS元件區之間；以及以與形成該低壓P型井區同一離子製程步驟形成一第二P型隔絕區於該空乏型高壓NMOS元件區與該空乏型低壓NMOS元件區之間；其中該第一P型隔絕區與該第二P型隔絕區於該垂直方向上連接；其中，該高壓N型埋層、該第一N型隔絕區、該第一P型隔絕區與該第二P型隔絕區形成一高壓隔絕區，以於該半導體層中，電性隔絕該空乏型高壓NMOS元件區與該空乏型低壓NMOS元件區。 In a preferred implementation mode, the integrated manufacturing method of the depletion-type high-voltage NMOS device and the depletion-type low-voltage NMOS device further includes: forming a high-voltage N-type buried layer on the substrate by an ion process step for the depletion-type high-voltage In the NMOS element region; a first N-type isolation region is formed in the semiconductor layer in the same ion process step as the formation of the N-type well region, and the first N-type isolation region is connected to the high-voltage N-type buried layer in a vertical direction , and in a channel direction, the first N-type isolation region is adjacent to the other side of the high-pressure P-type well region adjacent to the N-type well region; to form the high Forming a first P-type isolation region between the depletion-type high-voltage NMOS device region and the depletion-type low-voltage NMOS device region in the same ion process step as the P-type well region; and forming the low-voltage P-type well region in the same ion process step forming a second P-type isolation region between the depletion-type high-voltage NMOS element region and the depletion-type low-voltage NMOS element region; wherein the first P-type isolation region and the second P-type isolation region are connected in the vertical direction; Wherein, the high-voltage N-type buried layer, the first N-type isolation region, the first P-type isolation region, and the second P-type isolation region form a high-voltage isolation region to electrically isolate the depletion area in the semiconductor layer. type high voltage NMOS element area and the depletion type low voltage NMOS element area.

在一種較佳的實施型態中，該空乏型高壓NMOS元件與空乏型低壓NMOS元件整合製造方法，更包含：於該低壓P型井區形成後，以微影與蝕刻製程步驟，蝕刻該氧化層，以形成一降低表面電場氧化區於該空乏型高壓NMOS元件區中；於該降低表面電場氧化區形成後，形成一閘極氧化層於該半導體層上並連接該半導體層，該閘極氧化層覆蓋該空乏型高壓NMOS元件區與該空乏型低壓NMOS元件區；形成一多晶矽層於該閘極氧化層上並連接該閘極氧化層；以及以微影與蝕刻製程步驟，蝕刻該多晶矽層，以形成一高壓閘極於該空乏型高壓NMOS元件區中與一低壓閘極於該空乏型低壓NMOS元件區。 In a preferred implementation form, the integrated manufacturing method of the depletion-type high-voltage NMOS device and the depletion-type low-voltage NMOS device further includes: after the formation of the low-voltage P-type well region, etching the oxide layer by lithography and etching process steps layer to form a reduced surface electric field oxidation region in the depletion type high-voltage NMOS element region; after the formation of the reduced surface electric field oxidation region, a gate oxide layer is formed on the semiconductor layer and connected to the semiconductor layer, the gate An oxide layer covers the depletion-type high-voltage NMOS device region and the depletion-type low-voltage NMOS device region; forming a polysilicon layer on the gate oxide layer and connecting the gate oxide layer; and etching the polysilicon by lithography and etching process steps layers to form a high-voltage gate in the depletion-type high-voltage NMOS device region and a low-voltage gate in the depletion-type low-voltage NMOS device region.

在一種較佳的實施型態中，該空乏型高壓NMOS元件與空乏型低壓NMOS元件整合製造方法，更包含：以形成該高壓N型埋層之同一離子製程步驟，形成一低壓N型埋層於該基板上之該空乏型低壓NMOS元件區中；以及以與形成該N型井區同一離子製程步驟形成一第二N型隔絕區與一第三N型隔絕區於該半導體層中，該第二N型隔絕區與該第三N型隔絕區於該垂直方向上皆連接該低壓N型埋層，且於該通道方向上，該第二N型隔絕區與該第三N型隔絕區分別鄰接於該低壓P型井區之兩側；其中，該低壓 N型埋層、該第二N型隔絕區與該第三N型隔絕區形成一低壓隔絕區，以於該半導體層中，電性隔絕該空乏型低壓NMOS元件區與該空乏型高壓NMOS元件區。 In a preferred implementation mode, the integrated manufacturing method of the depletion-type high-voltage NMOS device and the depletion-type low-voltage NMOS device further includes: forming a low-voltage N-type buried layer in the same ion process step as forming the high-voltage N-type buried layer In the depletion-type low-voltage NMOS element region on the substrate; and forming a second N-type isolation region and a third N-type isolation region in the semiconductor layer by the same ion process step as forming the N-type well region, the The second N-type isolation region and the third N-type isolation region are connected to the low-voltage N-type buried layer in the vertical direction, and in the channel direction, the second N-type isolation region and the third N-type isolation region respectively adjacent to the two sides of the low-pressure P-type well area; wherein, the low-pressure The N-type buried layer, the second N-type isolation region and the third N-type isolation region form a low-voltage isolation region to electrically isolate the depletion-type low-voltage NMOS element region from the depletion-type high-voltage NMOS element in the semiconductor layer. district.

在一種較佳的實施型態中，該空乏型高壓NMOS元件與空乏型低壓NMOS元件整合製造方法，更包含：形成一高壓源極與一高壓汲極於該半導體層中，且該高壓源極與該高壓汲極分別位於該高壓閘極之外部下方之該高壓P型井區中與遠離該高壓P型井區側之該N型井區中，且於該通道方向上，該漂移區位於該高壓汲極與該高壓P型井區之間的該N型井區中，其中該高壓源極與該高壓汲極具有N型導電型。 In a preferred implementation mode, the integrated manufacturing method of the depletion-type high-voltage NMOS device and the depletion-type low-voltage NMOS device further includes: forming a high-voltage source and a high-voltage drain in the semiconductor layer, and the high-voltage source The high-voltage drain and the high-voltage drain are respectively located in the high-voltage P-type well region under the exterior of the high-voltage gate and in the N-type well region away from the side of the high-voltage P-type well region, and in the direction of the channel, the drift region is located In the N-type well region between the high-voltage drain and the high-voltage P-type well region, the high-voltage source and the high-voltage drain have N-type conductivity.

在一種較佳的實施型態中，該空乏型高壓NMOS元件與空乏型低壓NMOS元件整合製造方法，更包含：以形成該高壓源極與該高壓汲極同一離子植入製程步驟，形成一低壓源極與一低壓汲極於該半導體層中之該空乏型低壓NMOS元件區中，且該低壓源極與該低壓汲極分別位於該低壓閘極不同側之外部下方之該低壓P型井區中。 In a preferred implementation mode, the integrated manufacturing method of the depletion-type high-voltage NMOS element and the depletion-type low-voltage NMOS element further includes: forming the high-voltage source and the high-voltage drain in the same ion implantation process step to form a low-voltage The source and a low-voltage drain are in the depletion-type low-voltage NMOS element region in the semiconductor layer, and the low-voltage source and the low-voltage drain are respectively located in the low-voltage P-type well region outside the different sides of the low-voltage gate middle.

在一種較佳的實施型態中，該空乏型高壓NMOS元件與空乏型低壓NMOS元件整合製造方法，更包含：以同一離子植入製程步驟，形成一高壓P型接觸區於該高壓P型井區中與一低壓P型接觸區於該低壓P型井區中，以分別作為該高壓P型井區與該低壓P型井區之電性接點。 In a preferred implementation mode, the integrated manufacturing method of the depletion-type high-voltage NMOS device and the depletion-type low-voltage NMOS device further includes: forming a high-voltage P-type contact region in the high-voltage P-type well by using the same ion implantation process step and a low-voltage P-type contact region in the low-voltage P-type well region to serve as electrical contacts between the high-voltage P-type well region and the low-voltage P-type well region.

在前述的實施型態中，其中該半導體層係一P型半導體磊晶層，且具有體積電阻率45Ohm-cm。 In the foregoing embodiment, the semiconductor layer is a P-type semiconductor epitaxial layer, and has a volume resistivity of 45 Ohm-cm.

在一種較佳的實施型態中，該降低表面電場氧化區之厚度介於400Å與450Å之間。 In a preferred implementation form, the thickness of the RESURF oxidation region is between 400Å and 450Å.

在一種較佳的實施型態中，該閘極氧化層之厚度介於80Å與100Å之間。 In a preferred embodiment, the thickness of the gate oxide layer is between 80Å and 100Å.

在一種較佳的實施型態中，該空乏型高壓NMOS元件區之一空乏型高壓NMOS元件的閘極驅動電壓為3.3V。 In a preferred implementation form, the gate driving voltage of the depletion high voltage NMOS element in the depletion high voltage NMOS element region is 3.3V.

在一種較佳的實施型態中，其中該低壓閘極之最小長度為0.18微米；且該空乏型低壓NMOS元件之最小特徵尺寸為0.18微米。 In a preferred embodiment, the minimum length of the low-voltage gate is 0.18 microns; and the minimum feature size of the depletion-type low-voltage NMOS device is 0.18 microns.

底下藉由具體實施例詳加說明，當更容易瞭解本發明之目的、技術內容、特點及其所達成之功效。 In the following detailed description by means of specific embodiments, it will be easier to understand the purpose, technical content, characteristics and effects of the present invention.

11,51:基板 11,51: Substrate

11’,51’:半導體層 11', 51': semiconductor layer

11a,51a:上表面 11a, 51a: upper surface

11b,51b:下表面 11b, 51b: lower surface

12,52:絕緣區 12,52: Insulation area

14,53:N型井區 14,53: N-type well area

14a,53’:犧牲氧化層 14a,53': sacrificial oxide layer

15,54:高壓P型井區 15,54: High pressure P-type well area

16,56:低壓P型井區 16,56: Low pressure P-type well area

16a:光阻層 16a: photoresist layer

18,55:氧化層 18,55: oxide layer

18a,58a:降低表面電場氧化區 18a, 58a: Reduced surface electric field oxidation region

20a,58a:高壓閘極 20a, 58a: high voltage gate

20b,58b:低壓閘極 20b, 58b: Low voltage gate

22,59a:高壓源極 22,59a: High voltage source

23,59b:高壓汲極 23,59b: High voltage drain

26,59c:低壓源極 26,59c: Low voltage source

27,59d:低壓汲極 27,59d: Low voltage drain

51c:高壓N型埋層 51c: High voltage N-type buried layer

51d:低壓N型埋層 51d: Low-voltage N-type buried layer

53a:第一N型隔絕區 53a: the first N-type isolation region

53b:第二N型隔絕區 53b: The second N-type isolation region

53c:第三N型隔絕區 53c: The third N-type isolation area

54a,54b,54c:第一P型隔絕區 54a, 54b, 54c: the first P-type isolation region

56a,56b,56c:第二P型隔絕區 56a, 56b, 56c: the second P-type isolation region

57a:N型高壓通道區 57a: N-type high pressure channel area

57b:N型低壓通道區 57b: N-type low pressure channel area

58:多晶矽層 58: Polysilicon layer

60a:高壓P型接觸區 60a: High voltage P-type contact area

60b:低壓P型接觸區 60b: Low voltage P-type contact area

gox:閘極氧化層 gox: gate oxide layer

HV:空乏型高壓NMOS元件區 HV: Depletion type high voltage NMOS element area

HV1:空乏型高壓NMOS元件 HV1: depleted high voltage NMOS element

LV:空乏型低壓NMOS元件區 LV: Depletion-type low-voltage NMOS element area

LV1:空乏型低壓NMOS元件 LV1: Depletion type low voltage NMOS element

圖1A-1H顯示本發明的第一個實施例。 1A-1H show a first embodiment of the present invention.

圖2A-2N顯示本發明的第二個實施例。 2A-2N show a second embodiment of the present invention.

有關本發明之前述及其他技術內容、特點與功效，在以下配合參考圖式之較佳實施例的詳細說明中，將可清楚的呈現。本發明中的圖式均屬示意，主要意在表示製程步驟以及各層之間之上下次序關係，至於形狀、厚度與寬度則並未依照比例繪製。 The aforementioned and other technical contents, features and effects of the present invention will be clearly presented in the following detailed description of preferred embodiments with reference to the drawings. The drawings in the present invention are all schematic, mainly intended to represent the manufacturing process steps and the relationship between the upper and lower order of each layer, and the shapes, thicknesses and widths are not drawn to scale.

請參考圖1A-1H，其顯示本發明的第一個實施例。圖1A-1H顯示根據本發明之空乏型高壓NMOS元件與空乏型低壓NMOS元件整合製造方法之剖視示意圖。 Please refer to FIGS. 1A-1H , which show a first embodiment of the present invention. 1A-1H show schematic cross-sectional views of an integrated manufacturing method of a depletion-type high-voltage NMOS device and a depletion-type low-voltage NMOS device according to the present invention.

如圖1A所示，首先提供基板11。基板11例如但不限於為P型或N型的半導體基板。基板11上可形成空乏型高壓NMOS元件與空乏型低壓NMOS元件。 As shown in FIG. 1A , first, a substrate 11 is provided. The substrate 11 is, for example but not limited to, a P-type or N-type semiconductor substrate. A depletion type high voltage NMOS element and a depletion type low voltage NMOS element can be formed on the substrate 11 .

接著，請參閱圖1B，形成半導體層11’於基板11上，半導體層11’於垂直方向(如圖1B中之實線箭號方向所示意，下同)上，具有相對之上表面11a與下表面11b。此時複數絕緣區12尚未形成，上表面11a也就尚未完全定義出來。複數絕緣區12形成後，上表面11a如圖1B中粗折線所示意。半導體層11’例如以磊晶的步驟，形成於基板11上，或是以基板11的部分，作為半導體層11’。形成半導體層11’的方式，為本領域中具有通常知識者所熟知，在此不予贅述。 Next, referring to FIG. 1B, a semiconductor layer 11' is formed on the substrate 11. The semiconductor layer 11' has an opposite upper surface 11a and Lower surface 11b. At this time, the plurality of insulating regions 12 have not yet been formed, and the upper surface 11a has not yet been fully defined. After the plurality of insulating regions 12 are formed, the upper surface 11a is shown by the thick broken line in FIG. 1B . The semiconductor layer 11' is formed on the substrate 11 by epitaxy, for example, or a part of the substrate 11 is used as the semiconductor layer 11'. The method of forming the semiconductor layer 11' is well known to those skilled in the art, and will not be repeated here.

在一種較佳的實施型態中，半導體層11’係P型半導體磊晶層，且半導體層11’具有體積電阻率45Ohm-cm。 In a preferred embodiment, the semiconductor layer 11' is a P-type semiconductor epitaxial layer, and the semiconductor layer 11' has a volume resistivity of 45 Ohm-cm.

接著，請參閱圖1C，形成複數絕緣區12於半導體層11’上，以定義空乏型高壓NMOS元件區HV與空乏型低壓NMOS元件區LV。絕緣區12例如但不限於如圖所示之淺溝槽絕緣(shallow trench isolation,STI)結構，亦可為區域氧化(local oxidation of silicon,LOCOS)結構。請繼續參閱圖1C，於複數絕緣區12形成後，於半導體層11’之上表面11a上，形成犧牲氧化層14a，以作為形成N型井區14與高壓P型井區15之離子植入製程步驟中，離子植入的阻擋層，以避免半導體層11’本身直接遭受離子轟擊而產生缺陷。 Next, referring to FIG. 1C , a plurality of insulating regions 12 are formed on the semiconductor layer 11' to define a depletion-type high-voltage NMOS device region HV and a depletion-type low-voltage NMOS device region LV. The insulating region 12 is, for example but not limited to, a shallow trench isolation (STI) structure as shown in the figure, and may also be a local oxidation of silicon (LOCOS) structure. Please continue to refer to FIG. 1C, after the formation of the plurality of insulating regions 12, a sacrificial oxide layer 14a is formed on the upper surface 11a of the semiconductor layer 11', as an ion implantation for forming the N-type well region 14 and the high-voltage P-type well region 15 In the process step, the barrier layer is implanted with ions to prevent the semiconductor layer 11 ′ from being directly bombarded by ions and causing defects.

接著，請參閱圖1D，例如但不限於利用至少一個離子植入製程步驟，將具有N型導電型之雜質摻雜至半導體層11’中，以形成N型井區14。N型井區14形成於半導體層11’中之空乏型高壓NMOS元件區HV中，N型井區14具有N型導電型，且於垂直方向上，N型井區14位於上表面11a下 並連接於上表面11a。其中，部分N型井區14定義漂移區，用以作為空乏型高壓NMOS元件區HV中的空乏型高壓NMOS元件在導通操作中之漂移電流通道。 Next, referring to FIG. 1D , for example but not limited to at least one ion implantation process step, doping impurities with N-type conductivity into the semiconductor layer 11 ′ to form N-type well region 14 . The N-type well region 14 is formed in the depletion-type high-voltage NMOS element region HV in the semiconductor layer 11', the N-type well region 14 has an N-type conductivity type, and in the vertical direction, the N-type well region 14 is located under the upper surface 11a And connected to the upper surface 11a. Wherein, part of the N-type well region 14 defines a drift region, which is used as a drift current channel for the depletion-type high-voltage NMOS device in the depletion-type high-voltage NMOS device region HV during the conduction operation.

請繼續參閱圖1D，例如但不限於利用至少一個離子植入製程步驟，將具有P型導電型之雜質摻雜至半導體層11’中，以形成高壓P型井區15。高壓P型井區15形成於半導體層11’中，高壓P型井區15具有P型導電型，且於垂直方向上，高壓P型井區15位於上表面11a下並連接於上表面11a。其中N型井區14與高壓P型井區15於通道方向(如圖1D中之虛線箭號方向所示意，下同)上連接。 Please continue to refer to FIG. 1D , for example, but not limited to, at least one ion implantation process step is used to dope the semiconductor layer 11' with impurities of P-type conductivity to form a high-voltage P-type well region 15 . The high-voltage P-type well region 15 is formed in the semiconductor layer 11', the high-voltage P-type well region 15 has P-type conductivity, and in the vertical direction, the high-voltage P-type well region 15 is located under the upper surface 11a and connected to the upper surface 11a. Wherein the N-type well area 14 and the high-pressure P-type well area 15 are connected in the channel direction (as indicated by the dotted arrow in FIG. 1D , the same below).

接著，請參閱圖1E，於N型井區14與高壓P型井區15形成之後，形成氧化層18於半導體層11’上，氧化層18覆蓋所有空乏型高壓NMOS元件區HV與空乏型低壓NMOS元件區LV。形成氧化層18的方式，例如但不限於以化學氣相沉積(chemical vapor deposition,CVD)製程步驟，形成氧化層18。 Next, please refer to FIG. 1E, after the N-type well region 14 and the high-voltage P-type well region 15 are formed, an oxide layer 18 is formed on the semiconductor layer 11', and the oxide layer 18 covers all the depletion-type high-voltage NMOS element regions HV and the depletion-type low-voltage NMOS element area LV. The oxide layer 18 is formed in a manner such as but not limited to chemical vapor deposition (CVD) process steps to form the oxide layer 18 .

在一種較佳的實施型態中，氧化層18之厚度介於400Å與450Å之間。 In a preferred embodiment, the thickness of the oxide layer 18 is between 400Å and 450Å.

接著，請參閱圖1F，於氧化層18形成之後，例如但不限於利用由微影製程步驟形成光阻層16a為遮罩，將N型導電型雜質摻雜至半導體層11’中之空乏型低壓NMOS元件區LV中，以形成低壓P型井區16。其中，本實施利用例如但不限於離子植入製程步驟，將N型導電型雜質，以加速離子的形式(如圖1F中虛線箭號所示意)，穿透氧化層18，植入半導體層11’中的低壓P型井區16之定義區中，以形成低壓P型井區16。 Next, please refer to FIG. 1F, after the oxide layer 18 is formed, for example but not limited to, use the photoresist layer 16a formed by the photolithography process step as a mask, and dope the N-type conductivity impurity into the depletion type semiconductor layer 11'. In the low-voltage NMOS device region LV, a low-voltage P-type well region 16 is formed. Wherein, this embodiment uses, for example but not limited to, the ion implantation process steps to penetrate the oxide layer 18 into the semiconductor layer 11 in the form of accelerated ions (as indicated by the dotted arrows in FIG. 1F ) with N-type conductive impurities. 'In the defined area of the low-pressure P-type well region 16 to form the low-pressure P-type well region 16.

接著，請參閱圖1G，於低壓P型井區16形成之後，例如但不限於利用由微影製程步驟形成光阻層21為遮罩，將N型導電型雜質摻雜至半導體層11’中之空乏型高壓NMOS元件區HV與空乏型低壓NMOS元件區LV中，以形成N型高壓通道區21a與N型低壓通道區21b。其中，本實施利用同一離子製程步驟將N型導電型雜質，以加速離子的形式(如圖1G中虛線箭號所示意)，穿透氧化層18，植入半導體層11’中的N型高壓通道區21a與N型低壓通道區21b之定義區中，以形成N型高壓通道區21a與N型低壓通道區21b，分別位於空乏型高壓NMOS元件區HV與空乏型低壓NMOS元件區LV，以使空乏型高壓NMOS元件HV1與空乏型低壓NMOS元件LV1於各自的閘極-源極電壓為零時導通。 Next, please refer to FIG. 1G, after the low-voltage P-type well region 16 is formed, for example, but not limited to, using the photoresist layer 21 formed by a lithography process step as a mask, N-type conductive impurities are doped into the semiconductor layer 11' In the depletion-type high-voltage NMOS device region HV and the depletion-type low-voltage NMOS device region LV, an N-type high-voltage channel region 21a and an N-type low-voltage channel region 21b are formed. Among them, this implementation uses the same ion process step to penetrate the N-type conductive impurity in the form of accelerated ions (as shown by the dotted arrow in Figure 1G) to penetrate the oxide layer 18 and implant the N-type high voltage in the semiconductor layer 11'. In the defined area of the channel area 21a and the N-type low-voltage channel area 21b, the N-type high-voltage channel area 21a and the N-type low-voltage channel area 21b are respectively located in the depletion-type high-voltage NMOS element area HV and the depletion-type low-voltage NMOS element area LV, so as to The depletion-type high-voltage NMOS element HV1 and the depletion-type low-voltage NMOS element LV1 are turned on when their respective gate-source voltages are zero.

接著，請參閱圖1H，形成降低表面電場(reduced surface field,RESURF)氧化區18a、高壓閘極20a、高壓源極22與高壓汲極23，以於空乏型高壓NMOS元件區HV中形成空乏型高壓NMOS元件HV1。也就是說，空乏型高壓NMOS元件HV1包含：N型井區14、高壓P型井區15、降低表面電場氧化區18a、高壓閘極20a、高壓源極22與高壓汲極23。 Next, please refer to FIG. 1H , forming a reduced surface field (reduced surface field, RESURF) oxide region 18a, a high voltage gate 20a, a high voltage source 22 and a high voltage drain 23 to form a depletion type high voltage NMOS element region HV. High voltage NMOS element HV1. That is to say, the depletion high-voltage NMOS device HV1 includes: N-type well region 14 , high-voltage P-type well region 15 , RESURF oxidation region 18 a, high-voltage gate 20 a, high-voltage source 22 and high-voltage drain 23 .

其中，一種較佳的實施例中，降低表面電場氧化區18a係由蝕刻氧化層18而形成。降低表面電場氧化區18a形成於空乏型高壓NMOS元件區HV中的上表面11a上並連接上表面11a。降低表面電場氧化區18a用以於空乏型高壓NMOS元件HV1不導通操作時，降低表面電場，以提高崩潰防護電壓。 Wherein, in a preferred embodiment, the RESURF oxide region 18 a is formed by etching the oxide layer 18 . The RESURF oxidation region 18a is formed on the upper surface 11a in the depletion-type high-voltage NMOS device region HV and connected to the upper surface 11a. The RESURF oxidation region 18a is used to reduce the surface electric field when the depletion-type high-voltage NMOS element HV1 is in non-conducting operation, so as to increase the breakdown protection voltage.

請繼續參閱圖1H，形成低壓閘極20b、低壓源極26與低壓汲極27於空乏型低壓NMOS元件區LV中，以於空乏型低壓NMOS元件區LV中 形成空乏型低壓NMOS元件LV1。也就是說，空乏型低壓NMOS元件LV1包含：低壓P型井區16、低壓閘極20b、低壓源極26與低壓汲極27。 Please continue to refer to FIG. 1H, forming a low-voltage gate 20b, a low-voltage source 26 and a low-voltage drain 27 in the depletion-type low-voltage NMOS device region LV, so that in the depletion-type low-voltage NMOS device region LV A depletion type low-voltage NMOS element LV1 is formed. That is to say, the depletion-type low-voltage NMOS device LV1 includes: a low-voltage P-type well region 16 , a low-voltage gate 20 b , a low-voltage source 26 and a low-voltage drain 27 .

其中，部分低壓P型井區16用以作為空乏型低壓NMOS元件區LV之反轉區，以提供空乏型低壓NMOS元件LV1之反轉電流通道。在本實施例中，低壓P型井區16具有P型導電型，低壓源極26與低壓汲極27皆具有N型導電型。 Wherein, part of the low-voltage P-type well region 16 is used as an inversion region of the depletion-type low-voltage NMOS device region LV to provide an inversion current channel of the depletion-type low-voltage NMOS device LV1. In this embodiment, the low-voltage P-type well region 16 has P-type conductivity, and the low-voltage source 26 and the low-voltage drain 27 both have N-type conductivity.

在一種實施例中，低壓閘極20b可以利用與高壓閘極20a同一製程步驟所形成；低壓源極26與低壓汲極27可以利用與高壓源極22與高壓汲極23同一製程步驟所形成。 In one embodiment, the low voltage gate 20b can be formed by the same process steps as the high voltage gate 20a; the low voltage source 26 and the low voltage drain 27 can be formed by the same process steps as the high voltage source 22 and the high voltage drain 23 .

在一種較佳的實施例中，空乏型高壓NMOS元件區HV之空乏型高壓NMOS元件HV1的閘極驅動電壓為3.3V。 In a preferred embodiment, the gate driving voltage of the depletion high voltage NMOS element HV1 in the depletion high voltage NMOS element region HV is 3.3V.

需說明的是，所謂反轉區係指元件在導通操作中因施加於閘極的電壓，而使閘極的下方形成反轉層(inversion layer)以使導通電流通過的區域，此為本領域具有通常知識所熟知，在此不予贅述，本發明其他實施例以此類推。 It should be noted that the so-called inversion region refers to the region where an inversion layer (inversion layer) is formed under the gate due to the voltage applied to the gate during the conduction operation of the element to allow the conduction current to pass. It is well known by common knowledge and will not be described in detail here, and other embodiments of the present invention can be deduced by analogy.

需說明的是，所謂漂移電流通道係指空乏型高壓NMOS元件HV1在導通操作中使導通電流以漂移的方式通過的區域，此為本領域具有通常知識所熟知，在此不予贅述。 It should be noted that the so-called drift current channel refers to the region where the conduction current drifts through the depletion-type high-voltage NMOS element HV1 during the conduction operation, which is well known in the art and will not be repeated here.

需說明的是，上表面11a並非指一完全平坦的平面，而是指半導體層11’的一個表面。在本實施例中，例如絕緣區12與半導體層11’接觸的部分上表面11a，就具有下陷的部分。 It should be noted that the upper surface 11a does not refer to a completely flat plane, but refers to a surface of the semiconductor layer 11'. In this embodiment, for example, the portion of the upper surface 11a of the insulating region 12 in contact with the semiconductor layer 11' has a sunken portion.

需說明的是，在一種較佳的實施例中，閘極包括與上表面連接的介電層、具有導電性的導電層、以及具有電絕緣特性之間隔層。導電層 用以作為閘極之電性接點，形成所有介電層上並連接於介電層。間隔層形成於導電層外之兩側以作為閘極之兩側之電性絕緣層。 It should be noted that, in a preferred embodiment, the gate electrode includes a dielectric layer connected to the upper surface, a conductive layer with conductivity, and an interlayer with electrical insulation properties. conductive layer An electrical contact used as a gate is formed on and connected to all dielectric layers. The spacer layer is formed on two sides outside the conductive layer as the electrical insulation layer on both sides of the gate.

此外，需說明的是，所謂的空乏型高壓NMOS元件，係指於正常操作時，施加於汲極的電壓高於一特定之電壓，例如5V，且高壓P型井區15與高壓汲極23間之通道方向距離(漂移區長度)根據正常操作時所承受的操作電壓而調整，因而可操作於前述較高之特定電壓。此皆為本領域中具有通常知識者所熟知，在此不予贅述。 In addition, it should be noted that the so-called depletion-type high-voltage NMOS device refers to that the voltage applied to the drain is higher than a specific voltage, such as 5V, during normal operation, and the high-voltage P-type well region 15 and the high-voltage drain 23 The distance in the direction of the channel (the length of the drift region) is adjusted according to the operating voltage under normal operation, so it can be operated at the aforementioned higher specific voltage. All of these are well known to those with ordinary knowledge in the art, and will not be repeated here.

相對的，所謂的空乏型低壓NMOS元件，係指於正常操作時，施加於汲極的電壓不高於一特定之電壓，例如5V，此為本領域中具有通常知識者所熟知，在此不予贅述。 In contrast, the so-called depletion-type low-voltage NMOS device means that the voltage applied to the drain is not higher than a specific voltage, such as 5V, during normal operation. I will repeat.

請參考圖2A-2N，其顯示本發明的第二個實施例。圖2A-2N顯示根據本發明之空乏型高壓NMOS元件與空乏型低壓NMOS元件整合製造方法之剖視示意圖。 Please refer to FIGS. 2A-2N , which show a second embodiment of the present invention. 2A-2N show schematic cross-sectional views of an integrated manufacturing method of a depletion-type high-voltage NMOS device and a depletion-type low-voltage NMOS device according to the present invention.

如圖2A所示，首先提供基板51。基板51例如但不限於為P型或N型的半導體基板。基板51上可形成空乏型高壓NMOS元件與空乏型低壓NMOS元件。 As shown in FIG. 2A , first, a substrate 51 is provided. The substrate 51 is, for example but not limited to, a P-type or N-type semiconductor substrate. A depletion type high voltage NMOS element and a depletion type low voltage NMOS element can be formed on the substrate 51 .

請繼續參閱圖2A，以同一離子製程步驟，形成高壓N型埋層51c於基板51上之空乏型高壓NMOS元件區HV中，與低壓N型埋層51d於基板51上之空乏型低壓NMOS元件區LV中。其中高壓N型埋層51c與低壓N型埋層51d具有N型導電型。形成高壓N型埋層51c與低壓N型埋層51d的方法，例如但不限於可以離子植入製程步驟，將N型導電型雜質，以加速離子的形式，植入基板51中，以形成高壓N型埋層51c與低壓N型埋層51d。舉例而言，當半導體層51’為一磊晶層，可於尚未形成磊晶層前，將N型導電型雜質，以 加速離子的形式，植入基板51中，再以磊晶製程步驟形成磊晶層，作為半導體層51’(參閱圖2B)，再經過熱製程，部分第一導電型雜質將會擴散至半導體層51’中，而形成高壓N型埋層51c與低壓N型埋層51d。 Please continue to refer to FIG. 2A. Using the same ion process step, a high-voltage N-type buried layer 51c is formed in the depletion-type high-voltage NMOS element region HV on the substrate 51, and a low-voltage N-type buried layer 51d is formed on the substrate 51. The depletion-type low-voltage NMOS element District LV. The high-voltage N-type buried layer 51c and the low-voltage N-type buried layer 51d have N-type conductivity. The method for forming the high-voltage N-type buried layer 51c and the low-voltage N-type buried layer 51d, for example but not limited to, may be an ion implantation process step, implanting N-type conductive impurities into the substrate 51 in the form of accelerated ions to form a high-voltage N-type buried layer 51c. N-type buried layer 51c and low voltage N-type buried layer 51d. For example, when the semiconductor layer 51' is an epitaxial layer, before the epitaxial layer is formed, the N-type conductivity impurity can be added to In the form of accelerated ions, it is implanted into the substrate 51, and then an epitaxial layer is formed by an epitaxial process step as a semiconductor layer 51' (see FIG. 2B). After a thermal process, part of the impurities of the first conductivity type will diffuse into the semiconductor layer. 51 ′, a high-voltage N-type buried layer 51c and a low-voltage N-type buried layer 51d are formed.

接著，請參閱圖2B，形成半導體層51’於基板51上，半導體層51’於垂直方向(如圖2B中之實線箭號方向所示意，下同)上，具有相對之上表面51a與下表面51b。此時複數絕緣區52尚未形成，上表面51a也就尚未完全定義出來。複數絕緣區52形成後，上表面51a如圖2B中粗折線所示意。半導體層51’例如以磊晶的步驟，形成於基板51上，或是以基板51的部分，作為半導體層51’。形成半導體層51’的方式，為本領域中具有通常知識者所熟知，在此不予贅述。 Next, referring to FIG. 2B, a semiconductor layer 51' is formed on the substrate 51. The semiconductor layer 51' has an opposite upper surface 51a and lower surface 51b. At this time, the plurality of insulating regions 52 have not yet been formed, and the upper surface 51a has not yet been completely defined. After the plurality of insulating regions 52 are formed, the upper surface 51a is shown by the thick broken line in FIG. 2B. The semiconductor layer 51' is formed on the substrate 51, for example, by epitaxy, or a part of the substrate 51 is used as the semiconductor layer 51'. The method of forming the semiconductor layer 51' is well known to those skilled in the art, and will not be repeated here.

在一種較佳的實施型態中，半導體層51’係P型半導體磊晶層，且半導體層51’具有體積電阻率45Ohm-cm。 In a preferred embodiment, the semiconductor layer 51' is a P-type semiconductor epitaxial layer, and the semiconductor layer 51' has a volume resistivity of 45 Ohm-cm.

接著，請參閱圖2C，形成複數絕緣區52於半導體層51’上，以定義空乏型高壓NMOS元件區HV與空乏型低壓NMOS元件區LV。絕緣區52例如但不限於如圖所示之淺溝槽絕緣(shallow trench isolation,STI)結構，亦可為區域氧化(local oxidation of silicon,LOCOS)結構。請繼續參閱圖2C，於複數絕緣區52形成後，於半導體層51’之上表面51a上，形成犧牲氧化層53'，以作為形成N型井區53與高壓P型井區54之離子植入製程步驟中，離子植入的阻擋層，以避免半導體層51’本身直接遭受離子轟擊而產生缺陷。 Next, referring to FIG. 2C , a plurality of insulating regions 52 are formed on the semiconductor layer 51' to define a depletion-type high-voltage NMOS device region HV and a depletion-type low-voltage NMOS device region LV. The insulating region 52 is, for example but not limited to, a shallow trench isolation (STI) structure as shown in the figure, and may also be a local oxidation of silicon (LOCOS) structure. Please continue to refer to FIG. 2C. After the formation of the plurality of insulating regions 52, a sacrificial oxide layer 53' is formed on the upper surface 51a of the semiconductor layer 51' to serve as ion implantation for forming the N-type well region 53 and the high-voltage P-type well region 54. In the process step, the barrier layer is implanted with ions, so as to prevent the semiconductor layer 51 ′ from being directly bombarded by ions and causing defects.

接著，請參閱圖2D，例如但不限於利用至少一個離子植入製程步驟，將具有N型導電型之雜質摻雜至空乏型高壓NMOS元件區HV中之半導體層51’中，以形成N型井區53。其中，N型井區53具有N型導電型，且於垂直方向(如圖2D中之實線箭號方向所示意，下同)上，N型井區53連接 上表面51a與高壓N型埋層51c。其中，部分N型井區53定義漂移區，用以作為空乏型高壓NMOS元件HV1在導通操作中之漂移電流通道。 Next, please refer to FIG. 2D , for example, but not limited to, at least one ion implantation process step is used to dope impurities with N-type conductivity into the semiconductor layer 51' in the depletion-type high-voltage NMOS element region HV to form an N-type Well area 53. Wherein, the N-type well region 53 has N-type conductivity type, and in the vertical direction (shown in the direction of the solid arrow in Figure 2D, the same below), the N-type well region 53 is connected to The upper surface 51a and the high voltage N-type buried layer 51c. Wherein, part of the N-type well region 53 defines a drift region, which is used as a drift current channel of the depletion-type high-voltage NMOS element HV1 in the conduction operation.

請繼續參閱圖2D，在一種實施例中，以與形成該N型井區53同一離子製程步驟，形成第一N型隔絕區53a於半導體層51’中，第一N型隔絕區53a於垂直方向上連接高壓N型埋層51c，且於通道方向上，第一N型隔絕區53a鄰接於高壓P型井區54(參閱圖2E)相對於鄰接N型井區53之另一側。 Please continue to refer to FIG. 2D. In one embodiment, the first N-type isolation region 53a is formed in the semiconductor layer 51' in the same ion process step as the N-type well region 53 is formed, and the first N-type isolation region 53a is vertically Directly connected to the high-voltage N-type buried layer 51c, and in the channel direction, the first N-type isolation region 53a is adjacent to the other side of the high-voltage P-type well region 54 (see FIG. 2E ) opposite to the adjacent N-type well region 53 .

請繼續參閱圖2D，在一種實施例中，以與形成N型井區53同一離子製程步驟，形成第二N型隔絕區53b與第三N型隔絕區53c於半導體層51’中。其中，第二N型隔絕區53b與第三N型隔絕區53c於垂直方向上皆連接低壓N型埋層51d，且於通道方向上，第二N型隔絕區53b與第三N型隔絕區53c分別鄰接於低壓P型井區56之兩側(參閱圖2G)。 Please continue to refer to FIG. 2D. In one embodiment, the second N-type isolation region 53b and the third N-type isolation region 53c are formed in the semiconductor layer 51' in the same ion process step as the formation of the N-type well region 53. Wherein, the second N-type isolation region 53b and the third N-type isolation region 53c are connected to the low-voltage N-type buried layer 51d in the vertical direction, and in the channel direction, the second N-type isolation region 53b and the third N-type isolation region 53c are respectively adjacent to both sides of the low-pressure P-type well region 56 (refer to FIG. 2G ).

接著，請參閱圖2E，例如但不限於利用至少一個離子植入製程步驟，將具有P型導電型之雜質摻雜至半導體層51’中，以形成高壓P型井區54。高壓P型井區54形成於半導體層51’中之空乏型高壓NMOS元件區HV中，高壓P型井區54具有P型導電型，且於垂直方向上，高壓P型井區54位於上表面51a下並連接上表面51a與高壓N型埋層51c。其中，在空乏型高壓NMOS元件區H中，N型井區53與高壓P型井區54於通道方向上連接。 Next, referring to FIG. 2E , for example but not limited to at least one ion implantation process step, doping impurities with P-type conductivity into the semiconductor layer 51 ′ to form a high-voltage P-type well region 54 . The high-voltage P-type well region 54 is formed in the depletion-type high-voltage NMOS element region HV in the semiconductor layer 51'. The high-voltage P-type well region 54 has a P-type conductivity, and in the vertical direction, the high-voltage P-type well region 54 is located on the upper surface 51a and connects the upper surface 51a and the high voltage N-type buried layer 51c. Wherein, in the depletion-type high-voltage NMOS element region H, the N-type well region 53 and the high-voltage P-type well region 54 are connected in the channel direction.

請繼續參閱圖2E，例如但不限於利用與形成高壓P型井區54同一離子製程步驟，形成第一P型隔絕區54a於空乏型高壓NMOS元件區HV中與空乏型低壓NMOS元件區LV之間。在一種實施例中，可進一步利用與形成高壓P型井區54同一離子製程步驟，形成第一P型隔絕區54b與第一P型隔絕區54c，在鏡像排列方式安排空乏型高壓NMOS元件區HV中與空乏型低 壓NMOS元件區LV，第一P型隔絕區54b與第一P型隔絕區54c皆位於空乏型高壓NMOS元件區HV中與空乏型低壓NMOS元件區LV之間。 Please continue to refer to FIG. 2E. For example, but not limited to, the first P-type isolation region 54a is formed between the depletion-type high-voltage NMOS element region HV and the depletion-type low-voltage NMOS element region LV by using the same ion process step as the formation of the high-voltage P-type well region 54. between. In one embodiment, the first P-type isolation region 54b and the first P-type isolation region 54c can be formed by using the same ion process step as that used to form the high-voltage P-type well region 54, and the depletion-type high-voltage NMOS element region can be arranged in a mirror image arrangement. HV medium and depleted type low In the high-voltage NMOS device region LV, the first P-type isolation region 54b and the first P-type isolation region 54c are located between the depletion-type high-voltage NMOS device region HV and the depletion-type low-voltage NMOS device region LV.

接著，請參閱圖2F，於N型井區53與高壓P型井區54形成之後，形成氧化層55於半導體層51’上，氧化層55覆蓋所有空乏型高壓NMOS元件區HV與空乏型低壓NMOS元件區LV。形成氧化層55的方式，例如但不限於以化學氣相沉積(chemical vapor deposition,CVD)製程步驟，形成氧化層55。 Next, please refer to FIG. 2F, after the N-type well region 53 and the high-voltage P-type well region 54 are formed, an oxide layer 55 is formed on the semiconductor layer 51', and the oxide layer 55 covers all the depletion-type high-voltage NMOS element regions HV and the depletion-type low-voltage NMOS element area LV. The way to form the oxide layer 55 is, for example but not limited to, chemical vapor deposition (CVD) process steps to form the oxide layer 55 .

在一種較佳的實施型態中，氧化層55之厚度介於400Å與450Å之間。 In a preferred embodiment, the thickness of the oxide layer 55 is between 400Å and 450Å.

接著，請參閱圖2G，於氧化層55形成之後，例如但不限於利用由微影製程步驟形成光阻層(未示出)為遮罩，將P型導電型雜質摻雜至半導體層51’中之空乏型低壓NMOS元件區LV中，以形成低壓P型井區56。其中，本實施利用例如但不限於離子植入製程步驟，將P型導電型雜質，以加速離子的形式，穿透氧化層55，植入半導體層51’中的低壓P型井區56之定義區中，以形成低壓P型井區56。 Next, please refer to FIG. 2G , after the oxide layer 55 is formed, for example but not limited to using a photoresist layer (not shown) formed by a lithography process step as a mask, doping P-type conductive impurities into the semiconductor layer 51' In the depletion-type low-voltage NMOS device region LV, a low-voltage P-type well region 56 is formed. Among them, this embodiment utilizes, for example but not limited to, the ion implantation process steps, the P-type conductivity impurity, in the form of accelerated ions, penetrates the oxide layer 55, and implants the definition of the low-voltage P-type well region 56 in the semiconductor layer 51'. region to form a low-pressure P-type well region 56.

請繼續參閱圖2G，利用與形成該低壓P型井區56同一離子製程步驟形成第二P型隔絕區56a於空乏型高壓NMOS元件區HV與空乏型低壓NMOS元件區LV之間。在一種實施例中，可進一步利用與形成低壓P型井區56同一離子製程步驟，形成第二P型隔絕區56b與第二P型隔絕區56c，在鏡像排列方式安排空乏型高壓NMOS元件區HV中與空乏型低壓NMOS元件區LV，第二P型隔絕區56b與第二P型隔絕區56c皆位於空乏型高壓NMOS元件區HV中與空乏型低壓NMOS元件區LV之間。 Please continue to refer to FIG. 2G , the second P-type isolation region 56 a is formed between the depletion-type high-voltage NMOS device region HV and the depletion-type low-voltage NMOS device region LV by using the same ion process step as the formation of the low-voltage P-type well region 56 . In one embodiment, the second P-type isolation region 56b and the second P-type isolation region 56c can be formed by further using the same ion process step as the formation of the low-voltage P-type well region 56, and the depletion-type high-voltage NMOS element region is arranged in a mirror image arrangement. The middle HV and the depletion-type low-voltage NMOS device region LV, the second P-type isolation region 56b and the second P-type isolation region 56c are located between the depletion-type high-voltage NMOS device region HV and the depletion-type low-voltage NMOS device region LV.

接著，請參閱圖2H，於氧化層55形成之後，例如但不限於利用由微影製程步驟形成光阻層(未示出)為遮罩，以同一離子製程步驟，將N型導電型雜質摻雜至空乏型高壓NMOS元件區HV與空乏型低壓NMOS元件區LV中之半導體層51’中，以形成N型高壓通道區57a與N型低壓通道區57b，分別位於該空乏型高壓NMOS元件區中高壓閘極58a正下方連接上表面51a與該空乏型低壓NMOS元件區中低壓閘極58b正下方連接上表面51a，以使空乏型高壓NMOS元件HV1與空乏型低壓NMOS元件LV1於各自的閘極-源極電壓為零時導通。其中，本實施利用例如但不限於離子植入製程步驟，將N型導電型雜質，以加速離子的形式，穿透氧化層55，植入半導體層51’中，以形成N型高壓通道區57a與N型低壓通道區57b。 Next, please refer to FIG. 2H , after the oxide layer 55 is formed, for example but not limited to using a photoresist layer (not shown) formed by a lithography process step as a mask, the N-type conductivity impurity is doped with the same ion process step. mixed into the semiconductor layer 51' in the depletion-type high-voltage NMOS element region HV and the depletion-type low-voltage NMOS element region LV to form an N-type high-voltage channel region 57a and an N-type low-voltage channel region 57b, respectively located in the depletion-type high-voltage NMOS element region The upper surface 51a is connected directly under the middle and high voltage gate 58a and the upper surface 51a is connected directly under the middle and low voltage gate 58b of the depletion type low voltage NMOS element region, so that the depletion type high voltage NMOS element HV1 and the depletion type low voltage NMOS element LV1 are connected to the respective gates. conduction when the pole-to-source voltage is zero. Among them, this embodiment uses, for example but not limited to, ion implantation process steps to penetrate the oxide layer 55 in the form of accelerated ions to implant N-type conductive impurities into the semiconductor layer 51' to form the N-type high voltage channel region 57a. and the N-type low-voltage channel region 57b.

在本實施例中，第一P型隔絕區54a與第二P型隔絕區56a於垂直方向上連接。在本實施例中，高壓N型埋層51c、第一N型隔絕區53a、第一P型隔絕區54a與第二P型隔絕區56a形成高壓隔絕區，以於半導體層51’中，電性隔絕空乏型高壓NMOS元件區HV與空乏型低壓NMOS元件區LV。低壓N型埋層51d、第二N型隔絕區53b與第三N型隔絕區53c形成低壓隔絕區，以於該半導體層中，電性隔絕空乏型低壓NMOS元件區LV與空乏型高壓NMOS元件區HV。 In this embodiment, the first P-type isolation region 54a is connected to the second P-type isolation region 56a in a vertical direction. In this embodiment, the high-voltage N-type buried layer 51c, the first N-type isolation region 53a, the first P-type isolation region 54a, and the second P-type isolation region 56a form a high-voltage isolation region, so that in the semiconductor layer 51', the electrical The depletion type high voltage NMOS element area HV is isolated from the depletion type low voltage NMOS element area LV. The low-voltage N-type buried layer 51d, the second N-type isolation region 53b, and the third N-type isolation region 53c form a low-voltage isolation region to electrically isolate the depletion-type low-voltage NMOS element region LV from the depletion-type high-voltage NMOS element in the semiconductor layer. District HV.

接著，請參閱圖2I，於低壓P型井區56、N型高壓通道區57a與N型低壓通道區57b形成後，以微影製程步驟與蝕刻製程步驟，蝕刻氧化層55，以形成降低表面電場氧化區55a於空乏型高壓NMOS元件區HV中。在一種較佳的實施例中，降低表面電場氧化區55a係由蝕刻氧化層55而形成。降低表面電場氧化區55a形成於空乏型高壓NMOS元件區HV中的上表面51a 上並連接上表面51a。降低表面電場氧化區55a用以於空乏型高壓NMOS元件HV1不導通操作時，降低表面電場，以提高崩潰防護電壓。 Next, please refer to FIG. 2I, after the formation of the low-pressure P-type well region 56, the N-type high-voltage channel region 57a and the N-type low-pressure channel region 57b, the oxide layer 55 is etched by the lithography process steps and the etching process steps to form a reduced surface The electric field oxidation region 55a is in the depletion type high voltage NMOS element region HV. In a preferred embodiment, the RESURF oxide region 55 a is formed by etching the oxide layer 55 . The reduced surface electric field oxidation region 55a is formed on the upper surface 51a of the depletion-type high-voltage NMOS element region HV and connected to the upper surface 51a. The RESURF oxidation region 55a is used to reduce the surface electric field when the depleted high-voltage NMOS element HV1 is in non-conduction operation, so as to increase the breakdown protection voltage.

接著，請參閱圖2J，於降低表面電場氧化區55a形成後，形成閘極氧化層gox於半導體層51’上並連接半導體層51’，閘極氧化層gox覆蓋空乏型高壓NMOS元件區HV與空乏型低壓NMOS元件區LV。在一種較佳實施例中，閘極氧化層gox之厚度介於80Å與100Å之間。 Next, please refer to FIG. 2J , after the formation of the reduced surface electric field oxidation region 55a, a gate oxide layer gox is formed on the semiconductor layer 51' and connected to the semiconductor layer 51'. The gate oxide layer gox covers the depletion-type high-voltage NMOS element region HV and Depletion type low-voltage NMOS element region LV. In a preferred embodiment, the thickness of the gate oxide layer gox is between 80Å and 100Å.

接著，請繼續參閱圖2K，形成多晶矽層58於閘極氧化層gox上並連接閘極氧化層gox。多晶矽層58例如但不限於由沉積製程步驟所形成。 Next, please continue referring to FIG. 2K , a polysilicon layer 58 is formed on the gate oxide layer gox and connected to the gate oxide layer gox. The polysilicon layer 58 is formed by, for example but not limited to, deposition process steps.

接著，請參閱圖2L，例如以微影製程步驟與蝕刻製程步驟，蝕刻多晶矽層58，以形成高壓閘極58a於空乏型高壓NMOS元件區HV中與低壓閘極58b於空乏型低壓NMOS元件區LV中。 Next, please refer to FIG. 2L. For example, the polysilicon layer 58 is etched by lithography process steps and etching process steps to form the high voltage gate 58a in the depletion type high voltage NMOS element region HV and the low voltage gate 58b in the depletion type low voltage NMOS element region. LV.

接著，請參閱圖2M，例如以同一離子植入製程步驟形成高壓源極59a與高壓汲極59b於半導體層51’中，且高壓源極59a與高壓汲極59b分別位於高壓閘極58a之外部下方之高壓P型井區54中與遠離高壓P型井區54側之N型井區53中，且於通道方向上，漂移區位於高壓汲極59b與高壓P型井區54之間的N型井區53中，其中高壓源極59a與高壓汲極59b具有N型導電型。 Next, please refer to FIG. 2M , for example, a high-voltage source 59a and a high-voltage drain 59b are formed in the semiconductor layer 51' by the same ion implantation process step, and the high-voltage source 59a and the high-voltage drain 59b are located outside the high-voltage gate 58a respectively. In the lower high-voltage P-type well region 54 and in the N-type well region 53 away from the side of the high-voltage P-type well region 54, and in the channel direction, the drift region is located in the N-type region between the high-voltage drain 59b and the high-voltage P-type well region 54. In the well region 53, the high-voltage source 59a and the high-voltage drain 59b have N-type conductivity.

請繼續參閱圖2M，以形成高壓源極59a與高壓汲極59b同一離子植入製程步驟，形成低壓源極59c與低壓汲極59d於半導體層51’中之空乏型低壓NMOS元件區LV中，且低壓源極59c與第一低壓汲極59d分別位於低壓閘極58b不同側之外部下方之低壓P型井區56中。 Please continue to refer to FIG. 2M to form the high-voltage source 59a and the high-voltage drain 59b in the same ion implantation process step to form the low-voltage source 59c and the low-voltage drain 59d in the depletion-type low-voltage NMOS element region LV in the semiconductor layer 51'. Moreover, the low-voltage source 59c and the first low-voltage drain 59d are respectively located in the low-voltage P-type well region 56 outside and below different sides of the low-voltage gate 58b.

接著，請參閱圖2N，以同一離子植入製程步驟，形成高壓P型接觸區60a於高壓P型井區54中與低壓P型接觸區60b於低壓P型井區56中，以分別作為高壓P型井區54與低壓P型井區56之電性接點。 Next, please refer to FIG. 2N, with the same ion implantation process step, a high-voltage P-type contact region 60a is formed in the high-voltage P-type well region 54 and a low-voltage P-type contact region 60b is formed in the low-voltage P-type well region 56, respectively as high-voltage The electrical contact between the P-type well region 54 and the low-voltage P-type well region 56 .

在一種較佳的實施例中，空乏型高壓NMOS元件區HV之空乏型高壓NMOS元件HV1的閘極驅動電壓為3.3V。 In a preferred embodiment, the gate driving voltage of the depletion high voltage NMOS element HV1 in the depletion high voltage NMOS element region HV is 3.3V.

在一種較佳的實施例中，低壓閘極58b之長度大於或等於0.18微米；且空乏型低壓NMOS元件LV1之最小特徵尺寸(feature size)為0.18微米。 In a preferred embodiment, the length of the low-voltage gate 58b is greater than or equal to 0.18 microns; and the minimum feature size of the depletion-type low-voltage NMOS device LV1 is 0.18 microns.

以上已針對較佳實施例來說明本發明，唯以上所述者，僅係為使熟悉本技術者易於了解本發明的內容而已，並非用來限定本發明之權利範圍。在本發明之相同精神下，熟悉本技術者可以思及各種等效變化。例如，在不影響元件主要的特性下，可加入其他製程步驟或結構，如輕摻雜汲極區(lightly doped drain,LDD)等；又如，微影技術並不限於光罩技術，亦可包含電子束微影技術。凡此種種，皆可根據本發明的教示類推而得。此外，所說明之各個實施例，並不限於單獨應用，亦可以組合應用，例如但不限於將兩實施例併用。因此，本發明的範圍應涵蓋上述及其他所有等效變化。此外，本發明的任一實施型態不必須達成所有的目的或優點，因此，請求專利範圍任一項也不應以此為限。 The present invention has been described above with reference to preferred embodiments, but the above description is only for making those skilled in the art easily understand the content of the present invention, and is not intended to limit the scope of rights of the present invention. Within the same spirit of the present invention, various equivalent changes can be conceived by those skilled in the art. For example, without affecting the main characteristics of the device, other process steps or structures can be added, such as lightly doped drain (LDD), etc.; Contains electron beam lithography. All these can be obtained by analogy according to the teaching of the present invention. In addition, each of the described embodiments is not limited to be used alone, and can also be used in combination, for example but not limited to using the two embodiments together. Accordingly, the scope of the invention should encompass the above and all other equivalent variations. In addition, any implementation form of the present invention does not necessarily achieve all purposes or advantages, and therefore, any one of the claims should not be limited thereto.

11:基板 11: Substrate

11’:半導體層 11': semiconductor layer

11a:上表面 11a: upper surface

11b:下表面 11b: lower surface

12:絕緣區 12: Insulation area

14:N型井區 14: N-type well area

15:高壓P型井區 15: High pressure P-type well area

16:低壓P型井區 16: Low pressure P-type well area

18a:降低表面電場氧化區 18a: Reduce the surface electric field oxidation area

20a:高壓閘極 20a: High voltage gate

20b:低壓閘極 20b: Low voltage gate

21a:N型高壓通道區 21a: N-type high pressure channel area

21b:N型低壓通道區 21b: N-type low pressure channel area

22:高壓源極 22: High voltage source

23:高壓汲極 23: High voltage drain

26:低壓源極 26: Low voltage source

27:低壓汲極 27: Low voltage drain

HV:空乏型高壓NMOS元件區 HV: Depletion type high voltage NMOS element area

HV1:空乏型高壓NMOS元件 HV1: depleted high voltage NMOS element

LV:空乏型低壓NMOS元件區 LV: Depletion-type low-voltage NMOS element area

LV1:空乏型低壓NMOS元件 LV1: Depletion type low voltage NMOS element

Claims (11)

一種空乏型高壓NMOS元件與空乏型低壓NMOS元件整合製造方法，包含：提供一基板；形成一半導體層於該基板上；形成複數絕緣區於該半導體層上，以定義一空乏型高壓NMOS元件區與一空乏型低壓NMOS元件區；形成一N型井區於該半導體層中之該空乏型高壓NMOS元件區中，其中，部分該N型井區定義一漂移區，用以作為該空乏型高壓NMOS元件在一導通操作中之一漂移電流通道；形成一高壓P型井區於該空乏型高壓NMOS元件區中之該半導體層中，其中該N型井區與該高壓P型井區於一通道方向上連接；於該N型井區與該高壓P型井區形成之後，形成一氧化層於該半導體層上，該氧化層覆蓋該空乏型高壓NMOS元件區與該空乏型低壓NMOS元件區；於該氧化層形成之後，以一離子植入製程步驟，將雜質以加速離子的形式，穿透該氧化層，植入一定義區中，形成一低壓P型井區於該半導體層中之該空乏型低壓NMOS元件區中；以同一離子製程步驟，將N型導電型雜質，以加速離子的形式，穿透該氧化層，以形成一N型高壓通道區與一N型低壓通道區，分別位於該空乏型高壓NMOS元件區與該空乏型低壓NMOS元件區，以使該空乏型高壓NMOS元件與該空乏型低壓NMOS元件於各自的閘極-源極電壓為零時導通；於該低壓P型井區形成後，以微影與蝕刻製程步驟，蝕刻該氧化層，以部分該氧化層形成一降低表面電場氧化區於該空乏型高壓NMOS元件區中； 於該降低表面電場氧化區形成後，形成一閘極氧化層於該半導體層上並連接該半導體層，該閘極氧化層覆蓋該空乏型高壓NMOS元件區與該空乏型低壓NMOS元件區；形成一多晶矽層於該閘極氧化層上並連接該閘極氧化層；以微影與蝕刻製程步驟，蝕刻該多晶矽層，以形成一高壓閘極於該空乏型高壓NMOS元件區中與一低壓閘極於該空乏型低壓NMOS元件區。 An integrated manufacturing method of a depletion-type high-voltage NMOS element and a depletion-type low-voltage NMOS element, comprising: providing a substrate; forming a semiconductor layer on the substrate; forming a plurality of insulating regions on the semiconductor layer to define a depletion-type high-voltage NMOS element region and a depletion-type low-voltage NMOS element region; forming an N-type well region in the depletion-type high-voltage NMOS element region in the semiconductor layer, wherein part of the N-type well region defines a drift region for the depletion-type high-voltage A drift current channel of the NMOS element in a turn-on operation; forming a high-voltage P-type well region in the semiconductor layer in the depletion-type high-voltage NMOS element region, wherein the N-type well region and the high-voltage P-type well region are in one Connecting in the channel direction; after the N-type well region and the high-voltage P-type well region are formed, an oxide layer is formed on the semiconductor layer, and the oxide layer covers the depletion-type high-voltage NMOS element region and the depletion-type low-voltage NMOS element region ; After the oxide layer is formed, an ion implantation process is used to penetrate the oxide layer in the form of accelerated ions and implant impurities into a defined region to form a low-voltage P-type well region in the semiconductor layer. In the depletion-type low-voltage NMOS element region; in the same ion process step, the N-type conductive impurity, in the form of accelerated ions, penetrates the oxide layer to form an N-type high-voltage channel region and an N-type low-voltage channel region, respectively located in the depletion-type high-voltage NMOS element region and the depletion-type low-voltage NMOS element region, so that the depletion-type high-voltage NMOS element and the depletion-type low-voltage NMOS element are turned on when their respective gate-source voltages are zero; After the P-type well region is formed, the oxide layer is etched by photolithography and etching process steps, and a part of the oxide layer is used to form a reduced surface electric field oxidation region in the depletion-type high-voltage NMOS element region; After the formation of the reduced surface electric field oxidation region, a gate oxide layer is formed on the semiconductor layer and connected to the semiconductor layer, the gate oxide layer covers the depletion type high voltage NMOS element region and the depletion type low voltage NMOS element region; forming A polysilicon layer is on the gate oxide layer and connected to the gate oxide layer; the polysilicon layer is etched by lithography and etching process steps to form a high-voltage gate in the depletion-type high-voltage NMOS device region and a low-voltage gate Extremely in the depletion type low-voltage NMOS element area. 如請求項1所述之空乏型高壓NMOS元件與空乏型低壓NMOS元件整合製造方法，更包含：以一離子製程步驟形成一高壓N型埋層於該基板上之該空乏型高壓NMOS元件區中；以與形成該N型井區同一離子製程步驟形成一第一N型隔絕區於該半導體層中，該第一N型隔絕區於一垂直方向上連接該高壓N型埋層，且於一通道方向上，該第一N型隔絕區鄰接於該高壓P型井區相對於鄰接該N型井區之另一側；以與形成該高壓P型井區同一離子製程步驟形成一第一P型隔絕區於該空乏型高壓NMOS元件區與該空乏型低壓NMOS元件區之間；以及以與形成該低壓P型井區同一離子製程步驟形成一第二P型隔絕區於該空乏型高壓NMOS元件區與該空乏型低壓NMOS元件區之間；其中該第一P型隔絕區與該第二P型隔絕區於該垂直方向上連接；其中，該高壓N型埋層、該第一N型隔絕區、該第一P型隔絕區與該第二P型隔絕區形成一高壓隔絕區，以於該半導體層中，電性隔絕該空乏型高壓NMOS元件區與該空乏型低壓NMOS元件區。 The integrated manufacturing method of the depletion-type high-voltage NMOS device and the depletion-type low-voltage NMOS device as described in Claim 1, further comprising: forming a high-voltage N-type buried layer in the depletion-type high-voltage NMOS device region on the substrate by an ion process step ; forming a first N-type isolation region in the semiconductor layer in the same ion process step as forming the N-type well region, the first N-type isolation region is connected to the high-voltage N-type buried layer in a vertical direction, and in a In the channel direction, the first N-type isolation region is adjacent to the other side of the high-voltage P-type well region relative to the adjacent N-type well region; a first P type isolation region between the depletion-type high-voltage NMOS element region and the depletion-type low-voltage NMOS element region; between the element region and the depletion-type low-voltage NMOS element region; wherein the first P-type isolation region and the second P-type isolation region are connected in the vertical direction; wherein, the high-voltage N-type buried layer, the first N-type The isolation region, the first P-type isolation region and the second P-type isolation region form a high-voltage isolation region to electrically isolate the depletion-type high-voltage NMOS device region and the depletion-type low-voltage NMOS device region in the semiconductor layer. 如請求項2所述之空乏型高壓NMOS元件與空乏型低壓NMOS元件整合製造方法，更包含：以形成該高壓N型埋層之同一離子製程步驟，形成一低壓N型埋層於該基板上之該空乏型低壓NMOS元件區中；以及以與形成該N型井區同一離子製程步驟形成一第二N型隔絕區與一第三N型隔絕區於該半導體層中，該第二N型隔絕區與該第三N型隔絕區於該垂直方向上皆連接該低壓N型埋層，且於該通道方向上，該第二N型隔絕區與該第三N型隔絕區分別鄰接於該低壓P型井區之兩側；其中，該低壓N型埋層、該第二N型隔絕區與該第三N型隔絕區形成一低壓隔絕區，以於該半導體層中，電性隔絕該空乏型低壓NMOS元件區與該空乏型高壓NMOS元件區。 The integrated manufacturing method of the depletion-type high-voltage NMOS device and the depletion-type low-voltage NMOS device as described in Claim 2 further includes: forming a low-voltage N-type buried layer on the substrate by the same ion process step as forming the high-voltage N-type buried layer In the depletion type low-voltage NMOS element region; and forming a second N-type isolation region and a third N-type isolation region in the semiconductor layer by the same ion process step as forming the N-type well region, the second N-type The isolation region and the third N-type isolation region are connected to the low-voltage N-type buried layer in the vertical direction, and in the channel direction, the second N-type isolation region and the third N-type isolation region are respectively adjacent to the Both sides of the low-voltage P-type well region; wherein, the low-voltage N-type buried layer, the second N-type isolation region, and the third N-type isolation region form a low-voltage isolation region to electrically isolate the semiconductor layer. The depletion type low voltage NMOS element area and the depletion type high voltage NMOS element area. 如請求項3所述之空乏型高壓NMOS元件與空乏型低壓NMOS元件整合製造方法，更包含：形成一高壓源極與一高壓汲極於該半導體層中，且該高壓源極與該高壓汲極分別位於該高壓閘極之外部下方之該高壓P型井區中與遠離該高壓P型井區側之該N型井區中，且於該通道方向上，該漂移區位於該高壓汲極與該高壓P型井區之間的該N型井區中，其中該高壓源極與該高壓汲極具有N型導電型。 The integrated manufacturing method of the depletion-type high-voltage NMOS device and the depletion-type low-voltage NMOS device as described in Claim 3 further includes: forming a high-voltage source and a high-voltage drain in the semiconductor layer, and the high-voltage source and the high-voltage drain The poles are respectively located in the high-voltage P-type well region outside the high-voltage gate and in the N-type well region away from the high-voltage P-type well region, and in the direction of the channel, the drift region is located at the high-voltage drain In the N-type well region between the high-voltage P-type well region, the high-voltage source and the high-voltage drain have N-type conductivity. 如請求項4所述之空乏型高壓NMOS元件與空乏型低壓NMOS元件整合製造方法，更包含：以形成該高壓源極與該高壓汲極同一離子植入製程步驟，形成一低壓源極與一低壓汲極於該半導體層中之該空乏型低壓NMOS元件區中，且該低壓源極與該低壓汲極分別位於該低壓閘極不同側之外部下方之該低壓P型井區中。 The integrated manufacturing method of a depletion-type high-voltage NMOS device and a depletion-type low-voltage NMOS device as described in Claim 4 further includes: forming a low-voltage source and a high-voltage drain in the same ion implantation process step as forming the high-voltage source and the high-voltage drain The low-voltage drain is in the depletion-type low-voltage NMOS element region in the semiconductor layer, and the low-voltage source and the low-voltage drain are respectively located in the low-voltage P-type well region outside the different sides of the low-voltage gate. 如請求項5項所述之空乏型高壓NMOS元件與空乏型低壓NMOS元件整合製造方法，更包含：以同一離子植入製程步驟，形成一高壓P型接觸區於該高壓P型井區中與一低壓P型接觸區於該低壓P型井區中，以分別作為該高壓P型井區與該低壓P型井區之電性接點。 The integrated manufacturing method of the depletion-type high-voltage NMOS element and the depletion-type low-voltage NMOS element as described in item 5 of the claim further includes: forming a high-voltage P-type contact region in the high-voltage P-type well region and the same ion implantation process step A low-voltage P-type contact region is in the low-voltage P-type well region, serving as electrical contacts between the high-voltage P-type well region and the low-voltage P-type well region. 如請求項1項所述之空乏型高壓NMOS元件與空乏型低壓NMOS元件整合製造方法，其中該半導體層係一P型半導體磊晶層，且具有體積電阻率45Ohm-cm。 The integrated manufacturing method of the depletion-type high-voltage NMOS element and the depletion-type low-voltage NMOS element as described in Claim 1, wherein the semiconductor layer is a P-type semiconductor epitaxial layer with a volume resistivity of 45 Ohm-cm. 如請求項1項所述之空乏型高壓NMOS元件與空乏型低壓NMOS元件整合製造方法，其中該降低表面電場氧化區之厚度介於400Å與450Å之間。 The integrated manufacturing method of the depletion-type high-voltage NMOS device and the depletion-type low-voltage NMOS device as described in Claim 1, wherein the thickness of the reduced surface electric field oxidation region is between 400Å and 450Å. 如請求項1項所述之空乏型高壓NMOS元件與空乏型低壓NMOS元件整合製造方法，其中該閘極氧化層之厚度介於80Å與100Å之間。 The integrated manufacturing method of the depletion-type high-voltage NMOS device and the depletion-type low-voltage NMOS device as described in claim 1, wherein the thickness of the gate oxide layer is between 80 Å and 100 Å. 如請求項1項所述之空乏型高壓NMOS元件與空乏型低壓NMOS元件整合製造方法，其中該空乏型高壓NMOS元件區之該空乏型高壓NMOS元件的閘極驅動電壓為3.3V。 The integrated manufacturing method of the depletion-type high-voltage NMOS element and the depletion-type low-voltage NMOS element as described in claim 1, wherein the gate driving voltage of the depletion-type high-voltage NMOS element in the depletion-type high-voltage NMOS element region is 3.3V. 如請求項5項所述之空乏型高壓NMOS元件與空乏型低壓NMOS元件整合製造方法，其中該低壓閘極之最小長度為0.18微米；且該空乏型低壓NMOS元件之最小特徵尺寸為0.18微米。 The integrated manufacturing method of the depletion-type high-voltage NMOS device and the depletion-type low-voltage NMOS device as described in claim 5, wherein the minimum length of the low-voltage gate is 0.18 microns; and the minimum feature size of the depletion-type low-voltage NMOS device is 0.18 microns.
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* Cited by examiner, † Cited by third party
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US20060141714A1 (en) * 2004-12-29 2006-06-29 Dongbuanam Semiconductor Inc. Method for manufacturing a semiconductor device
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