TW202320276A

TW202320276A - Semiconductor substrate structure and manufacturing method thereof

Info

Publication number: TW202320276A
Application number: TW111138748A
Authority: TW
Inventors: 胡迪群
Original assignee: 胡迪群
Priority date: 2021-11-04
Filing date: 2022-10-13
Publication date: 2023-05-16
Also published as: TW202349517A; TW202320251A; TWI820992B

Abstract

A semiconductor substrate structure includes a first group of circuit structure and a second group of circuit structure. The first group of circuit structure includes a plurality of first wiring layers and a plurality of first conductive connectors, and each of the first conductive connectors includes a conductive cap. The second group of circuit structure includes a plurality of second wiring layers and a plurality of second conductive connectors. The first group of circuit structure and the second group of circuit structure are electrically connected through the bonding of the first conductive connectors and the second conductive connectors to form a multilayer redistribution structure. A manufacturing method of the semiconductor substrate structure is also provided.

Description

半導體基板結構及其製造方法Semiconductor substrate structure and manufacturing method thereof

本發明是有關於一種半導體基板結構及其製造方法。The invention relates to a semiconductor substrate structure and a manufacturing method thereof.

在積體電路應用中，重佈線路層(RDL)是由導電材料與介電材料所形成的多層結構，且重佈線路層常會於臨時載板上製作，然而，前述多層結構使用的材料與臨時載板使用的材料會有熱膨脹係數(coefficient of thermal expansion, CTE)失配(mismatch)的情形，因此在臨時載板上連續形成前述多層結構(連續形成至少四層)的過程中容易導致翹曲問題，且層數越多時翹曲問題會更加明顯，如此一來，會對半導體基板結構的良率與電氣性能產生不良影響。In integrated circuit applications, a redistribution layer (RDL) is a multi-layer structure formed of conductive materials and dielectric materials, and the RDL is often fabricated on a temporary carrier. However, the materials used in the aforementioned multi-layer structure are different from the The material used for the temporary carrier will have a mismatch in the coefficient of thermal expansion (CTE), so warping is likely to occur during the continuous formation of the aforementioned multi-layer structure (continuously forming at least four layers) on the temporary carrier. The warping problem will be more obvious when the number of layers increases, which will have a negative impact on the yield rate and electrical performance of the semiconductor substrate structure.

本發明提供一種半導體基板結構及其製造方法，其可以在具有多層重佈線結構的同時維持較佳的良率與電氣性能。The invention provides a semiconductor substrate structure and a manufacturing method thereof, which can maintain better yield rate and electrical performance while having a multi-layer rewiring structure.

本發明的一種半導體基板結構，包括第一組線路結構以及第二組線路結構。第一組線路結構包括多層第一線路層與多個第一導電連接件，且每一第一導電連接件包括導電蓋。第二組線路結構包括多層第二線路層與多個第二導電連接件。第一組線路結構與第二組線路結構藉由多個第一導電連接件與多個第二導電連接件的接合形成電性連接且構成多層重佈線結構。A semiconductor substrate structure of the present invention includes a first group of circuit structures and a second group of circuit structures. The first group of wiring structures includes multiple first wiring layers and a plurality of first conductive connectors, and each first conductive connector includes a conductive cover. The second set of wiring structures includes multiple second wiring layers and a plurality of second conductive connectors. The first group of circuit structures and the second group of circuit structures are electrically connected through the bonding of the plurality of first conductive connectors and the plurality of second conductive connectors to form a multilayer redistribution structure.

本發明的一種半導體基板結構的製造方法至少包括以下步驟。形成第一組線路結構於第一臨時載板上，其中第一組線路結構包括多層第一線路層與多個第一導電連接件，且每一第一導電連接件包括導電蓋。形成第二組線路結構於第二臨時載板上，其中第二組線路結構包括多層第二線路層與多個第二導電連接件。第一組線路結構的多個第一導電連接件接合於第二組線路結構的多個第二導電連接件以形成電性連接且構成多層重佈線結構。A method for manufacturing a semiconductor substrate structure of the present invention at least includes the following steps. A first group of circuit structures is formed on the first temporary carrier, wherein the first group of circuit structures includes multiple first circuit layers and a plurality of first conductive connectors, and each first conductive connector includes a conductive cover. A second group of circuit structures is formed on the second temporary carrier, wherein the second group of circuit structures includes multiple layers of second circuit layers and a plurality of second conductive connectors. The plurality of first conductive connectors of the first group of circuit structures are bonded to the plurality of second conductive connectors of the second group of circuit structures to form an electrical connection and form a multilayer redistribution structure.

基於上述，本發明先將多組線路結構分別單獨製作於臨時載板上，再將前述多組線路結構直接接合組裝成多層重佈線結構，如此一來，相較於一次性連續製作的多層重佈線結構而言，可以有效地降低翹曲程度，使半導體基板結構可以在具有多層重佈線結構的同時維持較佳的良率與電氣性能。Based on the above, the present invention separately manufactures multiple sets of circuit structures on the temporary carrier board, and then directly joins and assembles the aforementioned multiple sets of circuit structures into a multi-layer rewiring structure. As far as the wiring structure is concerned, the degree of warpage can be effectively reduced, so that the semiconductor substrate structure can maintain better yield and electrical performance while having a multi-layer rewiring structure.

為讓本發明的上述特徵和優點能更明顯易懂，下文特舉實施例，並配合所附圖式作詳細說明如下。In order to make the above-mentioned features and advantages of the present invention more comprehensible, the following specific embodiments are described in detail together with the accompanying drawings.

以下將參考圖式來全面地描述本發明的例示性實施例，但本發明還可按照多種不同形式來實施，且不應解釋為限於本文所述的實施例。在圖式中，為了清楚起見，各區域、部位及層的大小與厚度可不按實際比例繪製。為了方便理解，下述說明中相同的元件將以相同之符號標示來說明。Exemplary embodiments of the present invention will be fully described below with reference to the drawings, but the invention may also be embodied in many different forms and should not be construed as limited to the embodiments described herein. In the drawings, for the sake of clarity, the sizes and thicknesses of regions, parts and layers may not be drawn in actual scale. In order to facilitate understanding, the same components in the following description will be described with the same symbols.

參照本實施例之圖式以更全面地闡述本發明。然而，本發明亦可以各種不同的形式體現，而不應限於本文中所述之實施例。圖式中的層或區域的厚度、尺寸或大小會為了清楚起見而放大。相同或相似之參考號碼表示相同或相似之元件，以下段落將不再一一贅述。The present invention will be described more fully with reference to the drawings of this embodiment. However, the present invention can also be embodied in various forms and should not be limited to the embodiments described herein. The thickness, size or magnitude of layers or regions in the drawings may be exaggerated for clarity. The same or similar reference numbers indicate the same or similar elements, and the following paragraphs will not repeat them one by one.

本文所使用之方向用語(例如，上、下、右、左、前、後、頂部、底部)僅作為參看所繪圖式使用且不意欲暗示絕對定向。Directional terms (eg, up, down, right, left, front, back, top, bottom) as used herein are used pictorially by reference only and are not intended to imply absolute orientation.

應當理解，儘管術語”第一”、”第二”、”第三”等在本文中可以用於描述各種元件、部件、區域、層及/或部分，但是這些元件、部件、區域、及/或部分不應受這些術語的限制。這些術語僅用於將一個元件、部件、區域、層或部分與另一個元件、部件、區域、層或部分區分開。It should be understood that although the terms "first", "second", "third" and the like may be used herein to describe various elements, components, regions, layers and/or sections, these elements, components, regions, and/or or parts thereof shall not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section.

除非另有定義，本文使用的所有術語(包括技術和科學術語)具有與本發明所屬領域的普通技術人員通常理解的相同的含義。Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs.

圖1A至圖1C是示出根據本發明的一些實施例的半導體基板結構的製造方法的部分示意性剖視圖。圖1D是示出圖1C的其他替代性實施例的導電連接件的接合示意圖。圖1E、圖1F是示出根據本發明的另一些實施例的半導體基板結構的部分示意性剖視圖。請參考圖1A，於第一臨時載板10上形成第一組線路結構110，其中第一臨時載體10可以由玻璃、塑料、矽、金屬或其他合適的材料製成，只要該材料能夠承受後續製程並同時承載在其上形成的結構即可。1A to 1C are partially schematic cross-sectional views illustrating a method of manufacturing a semiconductor substrate structure according to some embodiments of the present invention. FIG. 1D is a schematic diagram showing the bonding of the conductive connectors of the other alternative embodiment of FIG. 1C . 1E and 1F are partial schematic cross-sectional views illustrating structures of semiconductor substrates according to other embodiments of the present invention. Please refer to FIG. 1A, a first group of circuit structures 110 are formed on a first temporary carrier 10, wherein the first temporary carrier 10 can be made of glass, plastic, silicon, metal or other suitable materials, as long as the material can withstand subsequent process and carry the structure formed thereon at the same time.

在一些實施例中，可選地可以在第一臨時載體10與第一組線路結構110之間塗敷第一離型層12(例如光熱轉換膜或其他合適的離型層)，以增強在後續過程中第一臨時載體10與第一組線路結構110之間的可剝離性且可以改善第一組線路結構110的平面度，但本發明不限於此。In some embodiments, a first release layer 12 (such as a light-to-heat conversion film or other suitable release layer) can optionally be applied between the first temporary carrier 10 and the first group of circuit structures 110 to enhance the The detachability between the first temporary carrier 10 and the first set of wiring structures 110 in the subsequent process can improve the planarity of the first set of wiring structures 110 , but the invention is not limited thereto.

在本實施例中，可以在第一臨時載體10上形成包括多層第一線路層111(圖1A示意地繪示出三層)與多個第一導電連接件112的第一組線路結構110，其中每一第一線路層111可以包括第一導電圖案111a、第一介電層111b及/或第一導電通孔111c，而每一第一導電連接件112可以包括導電柱112a與導電蓋112b。在此，第一導電圖案111a與第一導電通孔111c可以是嵌設於第一介電層111b內，且導電蓋112b可以是位於導電柱112a上，但本發明不限於此，在未繪示的實施例中，導電柱112a可以被省略，亦即導電蓋112b可以直接形成於第一線路層111上，以直接作為第一導電連接件112。In this embodiment, a first group of circuit structures 110 including multiple first circuit layers 111 (three layers are schematically shown in FIG. 1A ) and a plurality of first conductive connectors 112 may be formed on the first temporary carrier 10, Each first circuit layer 111 may include a first conductive pattern 111a, a first dielectric layer 111b and/or a first conductive via 111c, and each first conductive connector 112 may include a conductive column 112a and a conductive cover 112b . Here, the first conductive pattern 111a and the first conductive via 111c may be embedded in the first dielectric layer 111b, and the conductive cover 112b may be located on the conductive pillar 112a, but the present invention is not limited thereto, and not shown In the illustrated embodiment, the conductive pillar 112a can be omitted, that is, the conductive cover 112b can be directly formed on the first circuit layer 111 to directly serve as the first conductive connecting member 112 .

在一些實施例中，可使用沉積製程、微影製程和蝕刻製程或其他合適的製程在第一臨時載體10上形成第一導電圖案111a。接下來，可使用例如塗覆製程、微影蝕刻製程或其他合適的製程在第一臨時載體10上形成包括多個開口的第一介電層111b，其中開口暴露出第一導電圖案111a的至少一部分以用於電性連接。然後，可在第一介電層111b的開口內形成導電材料，以使用合適的沉積製程形成第一導電通孔111c。然後，多次執行上述步驟，以形成多層第一線路層111。應當注意的是，圖1A中所示的第一組線路結構110僅為示例性的，可以根據電路設計要求形成更多層或更少層的第一組線路結構110，只要第一組線路結構110包括至少二層的第一線路層111與多個導電連接件112皆屬於本發明的保護範圍。In some embodiments, the first conductive pattern 111a may be formed on the first temporary carrier 10 using a deposition process, a lithography process, an etching process, or other suitable processes. Next, a first dielectric layer 111b including a plurality of openings may be formed on the first temporary carrier 10 using, for example, a coating process, a lithographic etching process, or other suitable processes, wherein the openings expose at least a portion of the first conductive pattern 111a. A part is used for electrical connection. A conductive material may then be formed within the opening of the first dielectric layer 111b to form the first conductive via 111c using a suitable deposition process. Then, the above steps are performed multiple times to form multiple first circuit layers 111 . It should be noted that the first group of wiring structures 110 shown in FIG. 1A is only exemplary, and more layers or fewer layers of the first group of wiring structures 110 can be formed according to circuit design requirements, as long as the first group of wiring structures 110 includes at least two layers of the first circuit layer 111 and the plurality of conductive connectors 112 , both of which belong to the protection scope of the present invention.

在一些實施例中，第一導電圖案111a、第一導電通孔111c的材料可以包括銅、金、鎳、鋁、鉑、錫、其組合、其合金或其他合適的導電材料，而第一介電層111b的材料可以包括聚酰亞胺(polyimide, PI)、苯並環丁烯(benzocyclobutene, BCB)、聚苯並噁唑(polybenzoxazole, PBO)、無機介電材料(例如氧化矽，氮化矽等)或其他合適的電性絕緣材料，但本發明不限於此。In some embodiments, the material of the first conductive pattern 111a and the first conductive via hole 111c may include copper, gold, nickel, aluminum, platinum, tin, a combination thereof, an alloy thereof, or other suitable conductive materials, and the first via The material of the electrical layer 111b may include polyimide (polyimide, PI), benzocyclobutene (benzocyclobutene, BCB), polybenzoxazole (polybenzoxazole, PBO), inorganic dielectric materials (such as silicon oxide, nitride Silicon, etc.) or other suitable electrical insulating materials, but the present invention is not limited thereto.

在一些實施例中，導電柱112a的材料可以包括銅，且導電蓋112b的材料可以包括焊料(solder)，但本發明不限於此，導電柱112a與導電蓋112b可以是其他適宜的導電材料。In some embodiments, the material of the conductive post 112a may include copper, and the material of the conductive cover 112b may include solder, but the invention is not limited thereto, and the conductive post 112a and the conductive cover 112b may be other suitable conductive materials.

在本實施例中，第一組線路結構110包括靠近第一臨時載體10的底表面110b，其中在底表面110b處的第一導電圖案111a和第一介電層111b可基本上為齊平的。此外，第一導電通孔111c朝向所述多個導電連接件112的方向上逐漸變粗(如寬度或直徑逐漸變粗)，換句話說，第一導電通孔111c朝向第一臨時載體10的方向上逐漸變細(如寬度或直徑逐漸變細)，但本發明不限於此。In this embodiment, the first group of wiring structures 110 includes a bottom surface 110b close to the first temporary carrier 10, wherein the first conductive pattern 111a and the first dielectric layer 111b at the bottom surface 110b can be substantially flush. . In addition, the first conductive via 111c gradually becomes thicker toward the direction of the plurality of conductive connectors 112 (for example, the width or diameter gradually becomes thicker), in other words, the first conductive via 111c faces toward the direction of the first temporary carrier 10 Tapering in direction (such as tapering in width or diameter), but the invention is not limited thereto.

在一些實施例中，第一組線路結構110的底表面110b的第一導電圖案111a的分布密度須足以用於後續安裝半導體晶片(chip)，但本發明不限於此。In some embodiments, the distribution density of the first conductive patterns 111a on the bottom surface 110b of the first group of wiring structures 110 must be sufficient for subsequent mounting of semiconductor chips (chips), but the invention is not limited thereto.

在一些實施例中，可選地可以對導電柱112a上的導電蓋112b的頂表面進行平坦化製程(例如研磨製程、飛刀加工(fly cutting)、化學機械研磨(CMP)製程或其組合)，以確保第一導電連接件112的頂部平面度，但本發明不限於此。In some embodiments, the top surface of the conductive cap 112b on the conductive post 112a may optionally be planarized (such as grinding, fly cutting, chemical mechanical polishing (CMP) or a combination thereof) , so as to ensure the flatness of the top of the first conductive connecting member 112, but the present invention is not limited thereto.

請參考圖1B，於第二臨時載板20上形成第二組線路結構120，其中第二組線路結構120包括多層第二線路層121(圖1B示意地繪示出三層)與第二導電連接件122，且每一第二線路層121可以包括第二導電圖案121a、第二介電層121b及/或第二導電通孔121c。在此，第二導電圖案121a與第二導電通孔121c可以是嵌設於第二介電層121b內，但本發明不限於此。Please refer to FIG. 1B, a second set of wiring structures 120 are formed on the second temporary carrier 20, wherein the second set of wiring structures 120 includes a multi-layer second wiring layer 121 (three layers are schematically shown in FIG. 1B) and a second conductive layer. The connector 122, and each second circuit layer 121 may include a second conductive pattern 121a, a second dielectric layer 121b and/or a second conductive via 121c. Here, the second conductive pattern 121a and the second conductive via 121c may be embedded in the second dielectric layer 121b, but the invention is not limited thereto.

在本實施例中，第二組線路結構120包括靠近第二臨時載板20的底表面120b，其中在底表面120b處的第二導電圖案121a和第二介電層121b可基本上為齊平的。此外，第二導電通孔121c朝向所述多個第二導電連接件122的方向上逐漸變粗(如寬度或直徑逐漸變粗)，換句話說，第二導電通孔121c朝向第二臨時載體20的方向上逐漸變細(如寬度或直徑逐漸變細)，但本發明不限於此。In this embodiment, the second group of circuit structures 120 includes a bottom surface 120b close to the second temporary carrier 20, wherein the second conductive pattern 121a and the second dielectric layer 121b at the bottom surface 120b can be substantially flush. of. In addition, the second conductive vias 121c gradually become thicker toward the direction of the plurality of second conductive connectors 122 (for example, the width or diameter gradually becomes thicker), in other words, the second conductive vias 121c face toward the second temporary carrier 20 in the direction of tapering (such as width or diameter tapering), but the present invention is not limited thereto.

在一些實施例中，第二導電連接件122可以是接墊形式(pad form)、導電柱形式(pillar form)或其他適宜的形式，本發明不加以限制。此外，在未繪示的實施例中，第二導電連接件122可以是由第一晶種層、第二晶種層(材料例如是鈦/銅(Ti/Cu))與電鍍層 (材料例如是銅)依序堆疊所形成，但本發明不限於此，在另一些實施例中，第二導電連接件122可以包括其他合適的導電材料如銀、金、鎳或其合金，舉例而言，可以是Cu、Cu/Ni/Au、Cu/Ti、Cu/Ag或其類似者，舉例而言，可以在導電墊(材料例如是銅)上形成黏著層(材料例如是鈦)，再藉由電鍍、濺鍍或其他合適的沉積方式於黏著層上形成金屬層(材料例如是銀)，其中黏著層的厚度可以小於金屬層的厚度，但本發明不限於此，第二導電連接件122的形式皆可以視實際設計上的需求進行選擇。In some embodiments, the second conductive connection member 122 may be in the form of pads, pillars or other suitable forms, which are not limited by the present invention. In addition, in an unillustrated embodiment, the second conductive connector 122 may be composed of a first seed layer, a second seed layer (material such as titanium/copper (Ti/Cu)) and an electroplating layer (material such as is formed by stacking copper) sequentially, but the present invention is not limited thereto. In some other embodiments, the second conductive connector 122 may include other suitable conductive materials such as silver, gold, nickel or alloys thereof. For example, It may be Cu, Cu/Ni/Au, Cu/Ti, Cu/Ag or the like. For example, an adhesive layer (material such as titanium) may be formed on a conductive pad (material such as copper), and then by Electroplating, sputtering or other suitable deposition methods form a metal layer (material such as silver) on the adhesive layer, wherein the thickness of the adhesive layer can be less than the thickness of the metal layer, but the present invention is not limited thereto, the second conductive connector 122 The form can be selected according to the actual design requirements.

在一些實施例中，第二組線路結構120的底表面120b的第二導電圖案121a可以是用於後續安裝基板(substrate)或外部端子(terminal)，但本發明不限於此。In some embodiments, the second conductive patterns 121a on the bottom surface 120b of the second group of line structures 120 may be used for subsequent mounting substrates or external terminals, but the invention is not limited thereto.

應說明的是，形成第二組線路結構120的其他具體細節(如材料、形成方法及第二離型層22的設置)皆類似於形成第一組線路結構110，於此不再贅述。It should be noted that other specific details of forming the second set of wiring structures 120 (such as materials, forming methods, and setting of the second release layer 22 ) are similar to those of forming the first set of wiring structures 110 , and will not be repeated here.

請參考圖1C，將圖1B所繪示的結構上下翻面(flipped upside down)，直接接合第一組線路結構110與第二組線路結構120，以使第一導電連接件112接合至第二導電連接件122構成多層重佈線結構RDL。此外，可選地，可以於第一組線路結構110與第二組線路結構120之間設置底膠101，且底膠101可以填入第一導電連接件112與第二導電連接件122之間的間隙，因此底膠101可以圍繞第一導電連接件112與第二導電連接件122，以進一步提升接合可靠度，但本發明不限於此。經由上述製作已經大致完成本實施例的半導體基板結構100。Please refer to FIG. 1C , the structure shown in FIG. 1B is flipped upside down, and the first group of circuit structures 110 and the second group of circuit structures 120 are directly bonded, so that the first conductive connector 112 is bonded to the second circuit structure. The conductive connectors 122 constitute a multilayer redistribution structure RDL. In addition, optionally, a primer 101 may be provided between the first group of circuit structures 110 and the second group of circuit structures 120, and the primer 101 may be filled between the first conductive connector 112 and the second conductive connector 122 Therefore, the primer 101 can surround the first conductive connector 112 and the second conductive connector 122 to further improve bonding reliability, but the invention is not limited thereto. The semiconductor substrate structure 100 of this embodiment has been roughly completed through the above fabrication.

在本實施例中，半導體基板結構100包括第一組線路結構110以及第二組線路結構120。第一組線路結構110包括多層第一線路層111與多個第一導電連接件112。第二組線路結構120包括多層第二線路層121與多個第二導電連接件122。第一組線路結構110與第二組線路結構120藉由多個第一導電連接件112與多個第二導電連接件122的接合形成電性連接且構成多層重佈線結構RDL。據此，本實施例先將多組線路結構(第一組線路結構110與第二組線路結構120)分別單獨製作於臨時載板(第一臨時載體10與第二臨時載體20)上，再將多組線路結構直接接合組裝成多層重佈線結構(多層重佈線結構RDL)，如此一來，相較於一次性連續製作多層重佈線結構而言，可以有效地降低翹曲程度，使半導體基板結構100可以在具有多層重佈線結構RDL的同時維持較佳的良率與電氣性能。In this embodiment, the semiconductor substrate structure 100 includes a first group of circuit structures 110 and a second group of circuit structures 120 . The first group of wiring structures 110 includes multiple first wiring layers 111 and a plurality of first conductive connectors 112 . The second circuit structure 120 includes multiple second circuit layers 121 and a plurality of second conductive connectors 122 . The first group of circuit structures 110 and the second group of circuit structures 120 are electrically connected by joining the plurality of first conductive connectors 112 and the plurality of second conductive connectors 122 to form a multilayer redistribution structure RDL. Accordingly, in this embodiment, multiple groups of circuit structures (the first group of circuit structures 110 and the second group of circuit structures 120) are separately fabricated on the temporary carrier boards (the first temporary carrier 10 and the second temporary carrier 20), and then Multiple groups of circuit structures are directly bonded and assembled into a multilayer redistribution structure (multilayer redistribution structure RDL). In this way, compared with one-time continuous production of multilayer redistribution structures, the degree of warpage can be effectively reduced, making the semiconductor substrate The structure 100 can maintain good yield and electrical performance while having a multilayer redistribution structure RDL.

進一步而言，由於製程上的限制，困難度與製作的層數會呈正相關，因此當要製作越多層時，在製造過程中使整個重佈線結構受到損壞的機率就越高，進而無法有效控管良率與成本的問題，而本實施例將多層重佈線結構RDL拆分成多組較少層數的線路結構分別單獨製作，因此可以避免連續堆疊多層無法有效控管良率與成本的問題，但本發明不限於此。Furthermore, due to the limitations of the manufacturing process, the degree of difficulty is positively correlated with the number of layers to be fabricated. Therefore, when more layers are to be fabricated, the probability of damage to the entire rewiring structure during the manufacturing process is higher, and thus cannot be effectively controlled. However, in this embodiment, the multi-layer redistribution structure RDL is divided into multiple groups of circuit structures with fewer layers and made separately, so that the problem of continuous stacking of multiple layers that cannot effectively control the yield and cost can be avoided , but the present invention is not limited thereto.

在一些實施例中，由於第一組線路結構110以及第二組線路結構120之間具有由包括焊料的導電蓋112b所形成的接合介面，因此多層重佈線結構RDL的連接可以視為包括焊料(solder-containing)連接，但本發明不限於此。In some embodiments, since there is a bonding interface between the first group of wiring structures 110 and the second group of wiring structures 120 formed by the conductive cover 112b including solder, the connection of the multilayer redistribution structure RDL can be regarded as including solder ( solder-containing) connection, but the present invention is not limited thereto.

在一些實施例中，第一組線路結構110與第二組線路結構120可以是相互對齊接合的，因此第一導電連接件112與第二導電連接件122可以是以一對一的方式對應接合，但本發明不限於此。In some embodiments, the first set of wiring structures 110 and the second set of wiring structures 120 may be aligned and bonded to each other, so the first conductive connectors 112 and the second conductive connectors 122 may be correspondingly bonded in a one-to-one manner. , but the present invention is not limited thereto.

在一些實施例中，第一導電連接件112的導電柱112a的高度可以大於第二導電連接件122的高度，但本發明不限於此，在其他替代性的實施例中，如圖1D所示，第一導電連接件112的導電柱112a的高度可以實質上等於第二導電連接件122的高度，也就是說，第一導電連接件112的導電柱112a的高度與第二導電連接件122的高度可以視實際設計上的需求進行調整，本發明不加以限制。In some embodiments, the height of the conductive column 112a of the first conductive connector 112 may be greater than the height of the second conductive connector 122, but the present invention is not limited thereto. In other alternative embodiments, as shown in FIG. 1D , the height of the conductive pillar 112a of the first conductive connector 112 can be substantially equal to the height of the second conductive connector 122, that is, the height of the conductive pillar 112a of the first conductive connector 112 is the same as the height of the second conductive connector 122 The height can be adjusted according to actual design requirements, which is not limited by the present invention.

在一些實施例中，可以對第一導電連接件112的導電蓋112b進行回焊製程(reflow process)，以使第二導電連接件122電性耦合至導電柱112a，但本發明不限於此。In some embodiments, a reflow process may be performed on the conductive cover 112b of the first conductive connection part 112 to electrically couple the second conductive connection part 122 to the conductive post 112a, but the invention is not limited thereto.

在一些實施例中，當線路的線距/間距(L/S)(例如是線寬)越細的時候，製程的要求會更加嚴苛，因此欲形成多層重佈線結構會遭遇到更多困難，而本實施例使用接合組裝多組線路結構的方式製作精細線距/間距結構相較於連續形成的結構在良率與電氣性能上可以具有更大的優勢，舉例而言，第一組線路結構110與第二組線路結構120可以皆具有至少小於7微米的精細線距/間距，因此第一組線路結構110與第二組線路結構120接合組裝後可以為精細線距/間距的多層重佈線結構RDL，但本發明不限於此。In some embodiments, when the line pitch/spacing (L/S) (such as line width) is thinner, the requirements for the manufacturing process will be more stringent, so it will be more difficult to form a multi-layer wiring structure. , and this embodiment uses the method of bonding and assembling multiple groups of circuit structures to make fine line spacing/spacing structures, which can have greater advantages in yield and electrical performance than continuously formed structures. For example, the first group of circuit The structure 110 and the second group of circuit structures 120 can both have a fine pitch/spacing of at least less than 7 microns, so the first group of circuit structures 110 and the second group of circuit structures 120 can be multi-layered with fine pitch/spacing after bonding and assembling. wiring structure RDL, but the present invention is not limited thereto.

在一些實施例中，如圖1C所示，每一第一線路層111包括相鄰的二個第一線路，相鄰的二個第一線路的中心點之間具有第一間距111s，每一第二線路層121包括相鄰的二個第二線路，相鄰的二個第二線路的中心點之間具有第二間距121s，每一第一線路層111的第一間距111s皆小於每一第二線路層121的第二間距121s，且各層間距從第一組線路結構110朝向第二組線路結構120逐漸變大。在此，第一間距111s與第二間距121s為各層之最小間距，但本發明不限於此，在其他實施例中，第一間距111s與第二間距121s可以為各層之平均間距。In some embodiments, as shown in FIG. 1C, each first circuit layer 111 includes two adjacent first circuits, and there is a first distance 111s between the center points of the two adjacent first circuits, and each The second circuit layer 121 includes two adjacent second circuits, and there is a second distance 121s between the center points of the two adjacent second circuits, and the first distance 111s of each first circuit layer 111 is smaller than each The second spacing 121s of the second circuit layer 121 , and the spacing of each layer gradually increases from the first group of circuit structures 110 to the second group of circuit structures 120 . Here, the first distance 111s and the second distance 121s are the minimum distances of each layer, but the present invention is not limited thereto. In other embodiments, the first distance 111s and the second distance 121s may be the average distance of each layer.

圖5A是示出線路結構的間距的部分示意性剖視圖。圖5B是對應圖5A的部分示意性俯視圖。進一步而言，如圖5A與圖5B所示，線路層中可以具有細間距F與粗間距C，且間距可以例如是相鄰的二個線路的中心點之間的距離，如相鄰的二個線路L1的中心點之間的距離為細間距F，相鄰的二個線路L2的中心點之間的距離為粗間距C，或者是相鄰的二個接墊之間的距離，如相鄰的二個接墊P1的中心點之間的距離為細間距F，相鄰的二個接墊P2的中心點之間的距離為粗間距C，因此前述第一間距111s與第二間距121s可以依照實際設計上的需求使用該些設計，本發明不加以限制。FIG. 5A is a partially schematic cross-sectional view showing pitches of wiring structures. Fig. 5B is a partially schematic top view corresponding to Fig. 5A. Further, as shown in FIG. 5A and FIG. 5B , there may be a fine pitch F and a coarse pitch C in the circuit layer, and the pitch may be, for example, the distance between the center points of two adjacent lines, such as two adjacent lines The distance between the center points of a line L1 is a fine pitch F, the distance between the center points of two adjacent lines L2 is a coarse pitch C, or the distance between two adjacent pads, such as phase The distance between the center points of two adjacent pads P1 is a fine pitch F, and the distance between the center points of two adjacent pads P2 is a coarse pitch C, so the aforementioned first pitch 111s and second pitch 121s These designs can be used according to actual design requirements, and the present invention is not limited thereto.

在一些實施例中，第一導電通孔111c朝向第一導電連接件112的方向上逐漸變粗(如寬度或直徑逐漸變粗)，且第二導電通孔121c朝向第二導電連接件122的方向上逐漸變粗(如寬度或直徑逐漸變粗)，換句話說，第一導電通孔111c朝向第一臨時載體10的方向上逐漸變細(如寬度或直徑逐漸變細)，且第二導電通孔121c朝向第二臨時載體20的方向上逐漸變細(如寬度或直徑逐漸變細)，也就是說，在接合製程之後，第一導電通孔111c逐漸變細的方向與第二導電通孔121c逐漸變細的方向相反。In some embodiments, the first conductive via 111c gradually becomes thicker toward the direction of the first conductive connection 112 (for example, the width or diameter gradually becomes thicker), and the second conductive via 121c faces toward the direction of the second conductive connection 122 The direction gradually becomes thicker (such as the width or diameter gradually becomes thicker), in other words, the first conductive via 111c gradually becomes thinner toward the direction of the first temporary carrier 10 (such as the width or diameter gradually becomes thinner), and the second The conductive via 121c is gradually tapered toward the second temporary carrier 20 (eg, the width or diameter is tapered). The tapering direction of the through hole 121c is opposite.

應說明的是，依照實際應用上的需求，可以可選地移除第一臨時載體10及/或第二臨時載體20，以暴露出第一導電圖案111a及/或第二導電圖案121a並與其他元件進行電性連接。在此，可以藉由在線路結構的底表面和臨時載體之間施加外部能量以剝離離型層。It should be noted that, according to actual application requirements, the first temporary carrier 10 and/or the second temporary carrier 20 can be optionally removed to expose the first conductive pattern 111a and/or the second conductive pattern 121a and be connected with other components are electrically connected. Here, the release layer can be peeled off by applying external energy between the bottom surface of the wiring structure and the temporary carrier.

在一些實施例中，線路結構的組數也可以不限制於二組，舉例而言，如圖1E所示的半導體結構100A的多層重佈線結構RDL1可以更包括第三組線路結構130，其中第三組線路結構130包括多層第三線路層131與第三導電連接件132。進一步而言，第二組線路結構120設置在第一組線路結構110與第三組線路結構130之間且彼此相互電性連接，第二組線路結構120具有相對於第一組線路結構110的另一導電連接件123，且另一導電連接件接合至第三導電連接件132，但本發明不限於此。此外，亦可以於第二組線路結構120與第三組線路結構130之間設置另一底膠102，且底膠102可以填入第四導電連接件123與第三導電連接件132之間的間隙，因此底膠102可以圍繞第四導電連接件123與第三導電連接件132，以進一步提升接合可靠度，但本發明不限於此。In some embodiments, the number of groups of wiring structures may not be limited to two groups. For example, the multilayer redistribution structure RDL1 of the semiconductor structure 100A shown in FIG. 1E may further include a third group of wiring structures 130, wherein the first The three-set circuit structure 130 includes a multi-layer third circuit layer 131 and a third conductive connection member 132 . Further, the second group of wiring structures 120 is disposed between the first group of wiring structures 110 and the third group of wiring structures 130 and are electrically connected to each other, the second group of wiring structures 120 has a relative to the first group of wiring structures 110 Another conductive connection part 123 , and the other conductive connection part is joined to the third conductive connection part 132 , but the invention is not limited thereto. In addition, another primer 102 can also be provided between the second group of circuit structures 120 and the third group of circuit structures 130, and the primer 102 can be filled into the space between the fourth conductive connector 123 and the third conductive connector 132. Therefore, the primer 102 can surround the fourth conductive connection part 123 and the third conductive connection part 132 to further improve bonding reliability, but the invention is not limited thereto.

在一些實施例中，半導體結構100A例如是藉由下述步驟完成。半導體結構100A可以是接續圖1C，移除第二臨時載體20，於第二組線路結構110上形成第四導電連接件123，且於形成有第三離型層32的第三臨時載體30上形成第三組線路結構130，接著，再接合第四導電連接件123與第三導電連接件132，以形成多層重佈線結構RDL1，但本發明不限於此。In some embodiments, the semiconductor structure 100A is completed by the following steps, for example. The semiconductor structure 100A can be continued from FIG. 1C , the second temporary carrier 20 is removed, the fourth conductive connection member 123 is formed on the second set of circuit structures 110 , and on the third temporary carrier 30 formed with the third release layer 32 The third group of circuit structures 130 is formed, and then the fourth conductive connectors 123 and the third conductive connectors 132 are bonded to form a multilayer redistribution structure RDL1, but the invention is not limited thereto.

在一些實施例中，第一組線路結構110的第一線路層111的數量(六層結構)與第二組線路結構120的第二線路層121的數量(六層結構)相同，如圖1C所示，但也可以具有不同實施態樣，舉例而言，如圖1E所示的半導體基板結構100A，第一組線路結構110的第一線路層111的數量(六層結構)不同於第三組線路結構130的數量(四層結構)，而前述數量差可以為一層或兩層。In some embodiments, the number of first circuit layers 111 (six-layer structure) of the first group of circuit structures 110 is the same as the number of second circuit layers 121 (six-layer structure) of the second group of circuit structures 120, as shown in FIG. 1C As shown, but it can also have different implementation aspects. For example, in the semiconductor substrate structure 100A shown in FIG. The number of group line structures 130 (four-layer structure), and the aforementioned difference in number can be one or two layers.

在一些實施例中，每一第三線路層包括相鄰的二個第三線路，相鄰的二個第三線路的中心點之間具有第三間距131s，每一第二線路層121的第二間距121s皆小於每一第三線路層131的第三間距131s，且各層間距從第一組線路結構110朝向第三組線路結構130逐漸變大。In some embodiments, each third circuit layer includes two adjacent third circuits, and there is a third distance 131s between the center points of the two adjacent third circuits, and the third circuit layer 121 of each second circuit layer 121 The two intervals 121s are both smaller than the third interval 131s of each third circuit layer 131 , and the intervals between the layers gradually become larger from the first group of circuit structures 110 to the third group of circuit structures 130 .

在一些實施例中，第一組線路結構110的第一線路層111的厚度(六層結構)與第二組線路結構120的第二線路層121的厚度(六層結構)相同，但也可以具有不同實施態樣，舉例而言，如圖1F所示的半導體基板結構100B，第一組線路結構110的第一線路層111的厚度與第二組線路結構120的第二線路層121的厚度不同於第三組線路結構130的厚度，以形成多層重佈線結構RDL2，但本發明不限於此。In some embodiments, the thickness of the first circuit layer 111 of the first group of circuit structures 110 (six-layer structure) is the same as the thickness of the second circuit layer 121 of the second group of circuit structures 120 (six-layer structure), but it can also be There are different implementation aspects. For example, in the semiconductor substrate structure 100B shown in FIG. The thickness of the third group of wiring structures 130 is different to form the multilayer redistribution structure RDL2, but the invention is not limited thereto.

在此必須說明的是，以下實施例沿用上述實施例的元件標號與部分內容，其中採用相同或近似的標號來表示相同或近似的元件，並且省略了相同技術內容的說明，關於省略部分的說明可參考前述實施例，下述實施例不再重複贅述。It must be noted here that the following embodiments continue to use the component numbers and part of the content of the above-mentioned embodiments, wherein the same or similar numbers are used to indicate the same or similar components, and the description of the same technical content is omitted, and the description of the omitted part Reference can be made to the aforementioned embodiments, and the following embodiments will not be repeated.

圖2是示出根據本發明的又一些實施例的半導體結構的部分示意性剖視圖。請參考圖2，本實施例的半導體基板結構200與圖1C的半導體結構100差異在於：第二組線路結構220具有至少大於7微米的粗線距/間距，也就是說，在本實施例中，多層重佈線結構RDL3可以是粗線距/間距線路結構與精細線距/間距線路結構的組合，而具有更多應用彈性。此外，本實施例中可以省略底膠101，但亦可以進一步配置底膠101。FIG. 2 is a partially schematic cross-sectional view illustrating a semiconductor structure according to still other embodiments of the present invention. Please refer to FIG. 2, the difference between the semiconductor substrate structure 200 of this embodiment and the semiconductor structure 100 of FIG. , the multi-layer redistribution structure RDL3 can be a combination of thick line/space line structure and fine line space/space line structure, and has more application flexibility. In addition, the primer 101 can be omitted in this embodiment, but the primer 101 can also be further configured.

進一步而言，第二組線路結構220包括多層第二線路層221(圖2示意地繪示出三層)與第二導電連接件222，且每一第二線路層221可以包括第二導電圖案221a、第二介電層221b及/或第二導電通孔221c。在此，第二導電圖案221a與第二導電通孔221c可以是嵌設於第二介電層221b內，於此不再贅述。Further, the second circuit structure 220 includes multiple layers of second circuit layers 221 (three layers are schematically shown in FIG. 2 ) and second conductive connectors 222, and each second circuit layer 221 may include a second conductive pattern 221a, the second dielectric layer 221b and/or the second conductive via 221c. Here, the second conductive pattern 221a and the second conductive via hole 221c may be embedded in the second dielectric layer 221b, and details will not be repeated here.

在本實施例中，靠近第二導電連接件222的第二線路層221的第二導電圖案221a密度可以比遠離第二導電連接件222的第二線路層221的第二導電圖案221a的密度還密，也就是說，在第二組線路結構220中的導電圖案密度從第二臨時載板20往第二導電連接件222方向會呈現疏到密的線路分布，但本發明不限於此。In this embodiment, the density of the second conductive pattern 221a of the second circuit layer 221 close to the second conductive connector 222 may be higher than the density of the second conductive pattern 221a of the second circuit layer 221 away from the second conductive connector 222. Dense, that is to say, the conductive pattern density in the second set of circuit structures 220 will show a distribution of sparse to dense circuits from the second temporary carrier 20 to the second conductive connector 222, but the present invention is not limited thereto.

在本實施例中，第二導電圖案221a及/或第二導電通孔221c的材料與形成方法類似於第二導電圖案121a及/或第二導電通孔121，但第二介電層221b的材料不同於第二介電層121b，舉例而言，第二介電層221b的材料可以是ABF(Ajinomoto Build-up Film)、PP(Polypropylene)或其類似者，且第二介電層221b可以藉由適宜的沉積製程所形成。In this embodiment, the material and forming method of the second conductive pattern 221a and/or the second conductive via 221c are similar to the second conductive pattern 121a and/or the second conductive via 121, but the second dielectric layer 221b The material is different from the second dielectric layer 121b. For example, the material of the second dielectric layer 221b can be ABF (Ajinomoto Build-up Film), PP (Polypropylene) or the like, and the second dielectric layer 221b can be Formed by a suitable deposition process.

在一些實施例中，第二組線路結構220的總厚度T2會大於圖1C的第二組線路結構120的總厚度T1，因此多層重佈線結構RDL3可以是為厚膜RDL，但本發明不限於此。In some embodiments, the total thickness T2 of the second group of wiring structures 220 is greater than the total thickness T1 of the second group of wiring structures 120 in FIG. this.

圖3A至圖3E是示出根據本發明的再一些實施例的半導體結構的製造方法的部分示意性剖視圖。請參考圖3A，接續圖1C，移除第二臨時載體20與第二離型層22，以暴露出第二組線路結構120的底表面120b的第二導電圖案121a與第二介電層121b(可以視為多層重佈線結構RDL的端子端)。在此，可以選擇如圖1D所示的第一導電連接件112的導電柱112a的高度實質上等於第二導電連接件122的高度。3A to 3E are partially schematic cross-sectional views illustrating methods of fabricating semiconductor structures according to further embodiments of the present invention. Please refer to FIG. 3A , following FIG. 1C , the second temporary carrier 20 and the second release layer 22 are removed to expose the second conductive pattern 121a and the second dielectric layer 121b on the bottom surface 120b of the second set of wiring structures 120 (It can be regarded as the terminal end of the multilayer redistribution structure RDL). Here, as shown in FIG. 1D , the height of the conductive column 112 a of the first conductive connecting member 112 may be selected to be substantially equal to the height of the second conductive connecting member 122 .

接著，可以於第二組線路結構120的底表面120b的第二導電圖案121a上形成多個第五導電連接件340，其中第五導電連接件340包括導電柱341以及形成於其上的導電蓋342。在此，導電柱341可以由銅所製成，而導電蓋342可以由焊料所製成，但本發明不限於此，導電柱341與導電蓋342也可以是使用其他合適的材料所製成。Next, a plurality of fifth conductive connectors 340 may be formed on the second conductive patterns 121a on the bottom surface 120b of the second group of circuit structures 120, wherein the fifth conductive connectors 340 include conductive pillars 341 and conductive covers formed thereon. 342. Here, the conductive pillar 341 can be made of copper, and the conductive cover 342 can be made of solder, but the invention is not limited thereto, and the conductive pillar 341 and the conductive cover 342 can also be made of other suitable materials.

請參考圖3B，藉由第五導電連接件340將多層重佈線結構RDL接合至基板350。在一些實施例中，可以對第五導電連接件340的導電蓋342進行回焊製程(reflow process)，以使多層重佈線結構RDL電性耦合至基板350，但本發明不限於此。在此，基板350可以是陶瓷基板、層壓有機基板、封裝基板、積體基板或其類似者。Referring to FIG. 3B , the multilayer redistribution structure RDL is bonded to the substrate 350 through the fifth conductive connector 340 . In some embodiments, a reflow process may be performed on the conductive cover 342 of the fifth conductive connector 340 to electrically couple the multilayer redistribution structure RDL to the substrate 350 , but the invention is not limited thereto. Here, the substrate 350 may be a ceramic substrate, a laminated organic substrate, an encapsulation substrate, a build-up substrate, or the like.

在一些實施例中，基板350包括核心層(core layer)351、增層結構352與多個穿孔351a，其中增層結構352分別形成在增層結構352的二側，且多個穿孔351a貫穿核心層351以電性連接兩側的增層結構352，其中增層結構352包括嵌設於介電層中的導電圖案352a，但本發明不限於此，在未繪示的實施例中，基板350也可以不具有核心層351。In some embodiments, the substrate 350 includes a core layer 351, a build-up structure 352 and a plurality of through holes 351a, wherein the build-up structure 352 is respectively formed on two sides of the build-up structure 352, and the plurality of through holes 351a pass through the core The layer 351 is used to electrically connect the build-up structure 352 on both sides, wherein the build-up structure 352 includes a conductive pattern 352a embedded in a dielectric layer, but the present invention is not limited thereto. In an unillustrated embodiment, the substrate 350 The core layer 351 may not be provided.

請參考圖3C，移除第一臨時載體10與第一離型層12，以暴露出第一組線路結構110的底表面110b的第一導電圖案111a與第一介電層111b(可以視為多層重佈線結構RDL的晶片端)。此外，在圖3C中多層重佈線結構RDL與基板350之間的間隙可以選擇性地填入底膠103。3C, the first temporary carrier 10 and the first release layer 12 are removed to expose the first conductive pattern 111a and the first dielectric layer 111b (which can be regarded as Wafer side of RDL). In addition, the gap between the multilayer redistribution structure RDL and the substrate 350 in FIG. 3C can be selectively filled with the primer 103 .

請參考圖3D，於第一組線路結構110的底表面110b的第一導電圖案111a上形成多個晶片連接件360，其中晶片連接件360包括導電柱361以及形成於其上的導電蓋362。在此，導電柱361可以由銅所製成，而導電蓋362可以由焊料所製成，但本發明不限於此，導電柱361與導電蓋362也可以是使用其他合適的材料所製成。此外，可以於基板350上形成多個外部端子370，其中多層重佈線結構RDL藉由基板350與外部端子260電性連接。在此，多個晶片連接件360的分布密度可以大於多個第五導電連接件340的分布密度。Referring to FIG. 3D , a plurality of chip connectors 360 are formed on the first conductive patterns 111 a of the bottom surface 110 b of the first group of circuit structures 110 , wherein the chip connectors 360 include conductive pillars 361 and conductive caps 362 formed thereon. Here, the conductive pillar 361 can be made of copper, and the conductive cover 362 can be made of solder, but the invention is not limited thereto, and the conductive pillar 361 and the conductive cover 362 can also be made of other suitable materials. In addition, a plurality of external terminals 370 can be formed on the substrate 350 , wherein the redistribution structure RDL is electrically connected to the external terminals 260 through the substrate 350 . Here, the distribution density of the plurality of chip connectors 360 may be greater than the distribution density of the plurality of fifth conductive connectors 340 .

請參考圖3E，半導體晶片40可使用例如覆晶接合以連接到第一組線路結構110的底表面110b。舉例來說，半導體晶片40的導電凸塊42可以接合到晶片連接件360的導電蓋362上，換句話說，半導體晶片40的導電凸塊42可以與晶片連接件360的導電蓋362直接接觸，以形成異質整合模組(heterogeneous integration module)或系統。Referring to FIG. 3E , the semiconductor chip 40 can be connected to the bottom surface 110 b of the first set of circuit structures 110 by using, for example, flip-chip bonding. For example, the conductive bumps 42 of the semiconductor chip 40 can be bonded to the conductive cap 362 of the chip connector 360 , in other words, the conductive bumps 42 of the semiconductor chip 40 can be in direct contact with the conductive cap 362 of the chip connector 360 , To form a heterogeneous integration module or system.

在一些實施例中，半導體晶片40例如是邏輯晶片(logic chip)、記憶體晶片(memory chip)、三維積體電路(3DIC)晶片(如高頻寬記憶體晶片(high bandwidth memory chip))及/或其類似者，其中3DIC晶片包括相互堆疊的多個層，且形成有矽穿孔(TSVs)以提供各層之間的垂直電性連接，但本發明不限於此。In some embodiments, the semiconductor chip 40 is, for example, a logic chip, a memory chip, a three-dimensional integrated circuit (3DIC) chip (such as a high bandwidth memory chip) and/or Similarly, the 3DIC wafer includes multiple layers stacked on top of each other, and through-silicon vias (TSVs) are formed to provide vertical electrical connections between layers, but the invention is not limited thereto.

在一些實施例中，導電凸塊42的高度42h可以大於對應的晶片連接件360的高度360h，但本發明不限於此，導電凸塊42的高度42h與晶片連接件360的高度360h可以依照實際設計上的需求而定。In some embodiments, the height 42h of the conductive bump 42 may be greater than the height 360h of the corresponding chip connector 360, but the present invention is not limited thereto. Depends on design requirements.

在一些實施例中，底膠104可形成在第一組線路結構110的底表面110b上，以填充底表面110b和半導體晶片40之間的間隙，從而增強覆晶接合的可靠性。在一些實施例中，可以在第一組線路結構110上設置多於一個執行相同或不同功能的半導體晶片40。在這種情況下，多個半導體晶片40可以與第一組線路結構110電性連接且藉由第一組線路結構110彼此電性連接。設置在第一組線路結構110上的半導體晶片40的數量不構成本公開的限制。經由上述製作已經大致完成本實施例的半導體結構300。In some embodiments, the underfill 104 may be formed on the bottom surface 110b of the first set of wiring structures 110 to fill the gap between the bottom surface 110b and the semiconductor wafer 40 to enhance the reliability of the flip-chip bonding. In some embodiments, more than one semiconductor die 40 performing the same or different functions may be disposed on the first set of wiring structures 110 . In this case, the plurality of semiconductor chips 40 may be electrically connected to the first group of circuit structures 110 and electrically connected to each other through the first group of circuit structures 110 . The number of semiconductor wafers 40 disposed on the first set of wiring structures 110 is not a limitation of the present disclosure. The semiconductor structure 300 of this embodiment has been roughly completed through the above fabrication.

在一些實施例中，外部端子370可以是焊球，並可使用植球製程形成以放置在第二組線路結構120的第二導電圖案121a上，且可選擇性地執行焊接製程和回焊(reflow)製程，以增強外部端子370與第二導電圖案121a之間的黏附，但本發明不限於此。In some embodiments, the external terminals 370 may be solder balls, and may be formed using a ball planting process to be placed on the second conductive pattern 121a of the second group of wiring structures 120, and a soldering process and reflow ( reflow) process to enhance the adhesion between the external terminal 370 and the second conductive pattern 121a, but the present invention is not limited thereto.

在未繪示的實施例中，可以進一步將半導體結構200設置在電路載體(例如印刷電路板(PCB)、系統板、母板等)、封裝體及/或其他元件上，以形成電子裝置。舉例來說，外部端子370設置在電路載體上，且半導體晶片40藉由多層重佈線結構RDL電性連接到電路載體上或電路載體中的其他元件，但本發明不限於此。In an unillustrated embodiment, the semiconductor structure 200 may be further disposed on a circuit carrier (such as a printed circuit board (PCB), a system board, a motherboard, etc.), a package and/or other components to form an electronic device. For example, the external terminals 370 are disposed on the circuit carrier, and the semiconductor chip 40 is electrically connected to the circuit carrier or other elements in the circuit carrier through the multilayer redistribution structure RDL, but the invention is not limited thereto.

在一些實施例中，半導體結構300為晶圓級半導體封裝結構(wafer level semiconductor packaging structure)，但本發明不限於此。In some embodiments, the semiconductor structure 300 is a wafer level semiconductor packaging structure, but the invention is not limited thereto.

圖4是示出根據本發明的又再一些實施例的半導體結構的部分示意性剖視圖。請參考圖4，本實施例的半導體結構400與圖3E的半導體結構300差異在於：本實施例的半導體結構400更包括模組框架480與散熱元件490，其中模組框架480設置於第一組線路結構110的底表面110b上且圍繞半導體晶片40，而散熱元件490設置於半導體晶片40上且與模組框架480共同形成框住半導體晶片40的空間，但本發明不限於此。在此，模組框架480與散熱元件490可以依照實際設計上的需求進行選擇與組裝，本發明不加以限制。4 is a partially schematic cross-sectional view illustrating a semiconductor structure according to still further embodiments of the present invention. Please refer to FIG. 4, the difference between the semiconductor structure 400 of this embodiment and the semiconductor structure 300 of FIG. The bottom surface 110b of the circuit structure 110 surrounds the semiconductor chip 40, and the heat dissipation element 490 is disposed on the semiconductor chip 40 and together with the module frame 480 forms a space to frame the semiconductor chip 40, but the present invention is not limited thereto. Here, the module frame 480 and the heat dissipation element 490 can be selected and assembled according to actual design requirements, which is not limited by the present invention.

綜上所述，本發明先將多組線路結構分別單獨製作於臨時載板上，再將前述多組線路結構直接接合組裝成多層重佈線結構，如此一來，相較於一次性連續製作的多層重佈線結構而言，可以有效地降低翹曲程度，使半導體結構可以在具有多層重佈線結構的同時維持較佳的良率與電氣性能。To sum up, in the present invention, multiple groups of circuit structures are separately manufactured on the temporary carrier board, and then the aforementioned multiple groups of circuit structures are directly bonded and assembled into a multi-layer rewiring structure. For the multi-layer redistribution structure, the degree of warpage can be effectively reduced, so that the semiconductor structure can maintain better yield and electrical performance while having the multi-layer redistribution structure.

雖然本發明已以實施例揭露如上，然其並非用以限定本發明，任何所屬技術領域中具有通常知識者，在不脫離本發明的精神和範圍內，當可作些許的更動與潤飾，故本發明的保護範圍當視後附的申請專利範圍所界定者為準。Although the present invention has been disclosed above with the embodiments, it is not intended to limit the present invention. Anyone with ordinary knowledge in the technical field may make some changes and modifications without departing from the spirit and scope of the present invention. The scope of protection of the present invention should be defined by the scope of the appended patent application.

10、20、30:臨時載板 12、22、32:離型層 40:半導體晶片 42:導電凸塊 42h、360h:導電凸塊 100、100A、100B、200、300、400:半導體結構 101、102、103、104:底膠 110、120、120A、130、220:線路結構 110b、120b:底表面 111、121、131、221:線路層 111s、121s、131s、F、C:間距 111a、121a、221a、352a:導電圖案 111b、121b、221b:介電層 111c、121c、221c:導電通孔 112、122、123、132、222、340:導電連接件 112a、341、361:導電柱 112b、342、362:導電蓋 350:基板 351:核心層 351a:穿孔 352:增層結構 360:晶片連接件 370:外部端子 480:模組框架 490:散熱元件 L1、L2:線路 P1、P2:接墊 RDL、RDL1、RDL2、RDL3:多層重佈線結構 T1、T2:厚度 10, 20, 30: Temporary carrier board 12, 22, 32: release layer 40: Semiconductor wafer 42: Conductive bump 42h, 360h: conductive bump 100, 100A, 100B, 200, 300, 400: semiconductor structure 101, 102, 103, 104: primer 110, 120, 120A, 130, 220: line structure 110b, 120b: bottom surface 111, 121, 131, 221: line layer 111s, 121s, 131s, F, C: Spacing 111a, 121a, 221a, 352a: conductive pattern 111b, 121b, 221b: dielectric layer 111c, 121c, 221c: conductive vias 112, 122, 123, 132, 222, 340: Conductive connectors 112a, 341, 361: conductive column 112b, 342, 362: conductive cover 350: Substrate 351: core layer 351a: perforation 352: Build-up structure 360: chip connector 370: External terminal 480:Module frame 490: cooling element L1, L2: line P1, P2: Pads RDL, RDL1, RDL2, RDL3: multilayer redistribution structure T1, T2: Thickness

圖1A至圖1C是示出根據本發明的一些實施例的半導體基板結構的製造方法的部分示意性剖視圖。圖1D是示出圖1C的其他替代性實施例的導電連接件的接合示意圖。圖1E、圖1F是示出根據本發明的另一些實施例的半導體基板結構的部分示意性剖視圖。圖2是示出根據本發明的又一些實施例的半導體基板結構的部分示意性剖視圖。圖3A至圖3E是示出根據本發明的再一些實施例的半導體結構的製造方法的部分示意性剖視圖。圖4是示出根據本發明的又再一些實施例的半導體結構的部分示意性剖視圖。圖5A是示出線路結構的間距的部分示意性剖視圖。圖5B是對應圖5A的部分示意性俯視圖。 1A to 1C are partially schematic cross-sectional views illustrating a method of manufacturing a semiconductor substrate structure according to some embodiments of the present invention. FIG. 1D is a schematic diagram showing the bonding of the conductive connectors of the other alternative embodiment of FIG. 1C . 1E and 1F are partial schematic cross-sectional views illustrating structures of semiconductor substrates according to other embodiments of the present invention. FIG. 2 is a partially schematic cross-sectional view illustrating a structure of a semiconductor substrate according to still other embodiments of the present invention. 3A to 3E are partially schematic cross-sectional views illustrating methods of fabricating semiconductor structures according to further embodiments of the present invention. 4 is a partially schematic cross-sectional view illustrating a semiconductor structure according to still further embodiments of the present invention. FIG. 5A is a partially schematic cross-sectional view showing pitches of wiring structures. Fig. 5B is a partially schematic top view corresponding to Fig. 5A.

10、20:臨時載板 10, 20: Temporary carrier board

12、22:離型層 12, 22: release layer

100:半導體結構 100: Semiconductor Structures

101:底膠 101: primer

110、120:線路結構 110, 120: line structure

111s、121s:間距 111s, 121s: Spacing

111c、121c:導電通孔 111c, 121c: conductive vias

112、122:導電連接件 112, 122: Conductive connectors

112a:導電柱 112a: conductive column

112b:導電蓋 112b: conductive cover

RDL:多層重佈線結構 RDL: Redistribution Layer Structure

T1:厚度 T1: Thickness

Claims

一種半導體基板結構，包括：第一組線路結構，包括多層第一線路層與多個第一導電連接件，且每一所述第一導電連接件包括導電蓋；以及第二組線路結構，包括多層第二線路層與多個第二導電連接件，其中所述第一組線路結構與所述第二組線路結構藉由所述多個第一導電連接件與所述多個第二導電連接件的接合形成電性連接且構成多層重佈線結構。 A semiconductor substrate structure, comprising: A first set of wiring structures, including a multi-layer first wiring layer and a plurality of first conductive connectors, and each of the first conductive connectors includes a conductive cover; and The second group of circuit structures includes multiple layers of second circuit layers and a plurality of second conductive connectors, wherein the first group of circuit structures and the second group of circuit structures are connected by the plurality of first conductive connectors and the plurality of second conductive connectors. The bonding of the plurality of second conductive connectors forms an electrical connection and constitutes a multilayer redistribution structure.

如請求項1所述的半導體基板結構，其中每一所述第一線路層包括相鄰的二個第一線路，所述相鄰的二個第一線路的中心點之間具有第一間距，每一所述第二線路層包括相鄰的二個第二線路，所述相鄰的二個第二線路的中心點之間具有第二間距，每一所述第一線路層的所述第一間距皆大於每一所述第二線路層的所述第二間距，且各層間距從所述第一組線路結構朝向所述第二組線路結構逐漸變大。The semiconductor substrate structure according to claim 1, wherein each of the first wiring layers includes two adjacent first wirings, and there is a first distance between the center points of the two adjacent first wirings, Each of the second circuit layers includes two adjacent second circuits, and there is a second distance between the center points of the two adjacent second circuits, and the first circuit layer of each of the first circuit layers A pitch is greater than the second pitch of each of the second circuit layers, and the pitch of each layer becomes gradually larger from the first group of circuit structures toward the second group of circuit structures.

如請求項2所述的半導體基板結構，其中所述第一間距與所述第二間距為各層之最小間距。The semiconductor substrate structure according to claim 2, wherein the first distance and the second distance are minimum distances between layers.

如請求項1所述的半導體基板結構，其中所述第一組線路結構的所述第一線路層的數量與所述第二組線路結構的所述第二線路層的數量相同。The semiconductor substrate structure according to claim 1, wherein the number of the first wiring layers of the first group of wiring structures is the same as the number of the second wiring layers of the second group of wiring structures.

如請求項1所述的半導體基板結構，其中所述第一組線路結構的所述第一線路層的數量與所述第二組線路結構的所述第二線路層的數量不同。The semiconductor substrate structure according to claim 1, wherein the number of the first wiring layers of the first group of wiring structures is different from the number of the second wiring layers of the second group of wiring structures.

如請求項5所述的半導體基板結構，其中所述第一組線路結構的所述第一線路層的數量與所述第二組線路結構的所述第二線路層的數量的數量差為一層或兩層。The semiconductor substrate structure according to claim 5, wherein the difference between the number of the first wiring layers of the first group of wiring structures and the number of the second wiring layers of the second group of wiring structures is one layer or two layers.

如請求項1所述的半導體基板結構，其中所述多層重佈線結構更包括：第三組線路結構，包括多層第三線路層與多個第三導電連接件，其中所述第二組線路結構設置在所述第一組線路結構與所述第三組線路結構之間且彼此相互電性連接，所述第二組線路結構具有相對於所述第一組線路結構的另一導電連接件，且所述另一導電連接件接合至所述第三導電連接件。 The semiconductor substrate structure as claimed in item 1, wherein the multilayer redistribution structure further includes: A third group of wiring structures, including multiple layers of third wiring layers and a plurality of third conductive connectors, wherein the second group of wiring structures is arranged between the first group of wiring structures and the third group of wiring structures and mutually are electrically connected to each other, the second group of circuit structures has another conductive connector relative to the first group of circuit structures, and the other conductive connector is bonded to the third conductive connector.

如請求項7所述的半導體基板結構，其中每一所述第一線路層包括相鄰的二個第一線路，所述相鄰的二個第一線路的中心點之間具有第一間距，每一所述第二線路層包括相鄰的二個第二線路，所述相鄰的二個第二線路的中心點之間具有第二間距，每一所述第三線路層包括相鄰的二個第三線路，所述相鄰的二個第三線路的中心點之間具有第三間距，每一所述第一線路層的所述第一間距皆大於每一所述第二線路層的所述第二間距，每一所述第二線路層的所述第二間距皆小於每一所述第三線路層的所述第三間距，且各層間距從所述第一組線路結構朝向所述第三組線路結構逐漸變大。The semiconductor substrate structure according to claim 7, wherein each of the first circuit layers includes two adjacent first circuits, and there is a first distance between the center points of the two adjacent first circuits, Each of the second circuit layers includes two adjacent second circuits, and there is a second distance between the center points of the two adjacent second circuits, and each of the third circuit layers includes adjacent Two third lines, there is a third distance between the center points of the two adjacent third lines, and the first distance of each of the first line layers is greater than that of each of the second line layers The second spacing of each of the second wiring layers is smaller than the third spacing of each of the third wiring layers, and each layer spacing is from the first group of wiring structures toward The third group of line structures gradually becomes larger.

如請求項1所述的半導體基板結構，更包括底膠，設置於所述第一組線路結構與所述第二組線路結構之間並填入所述多個第一導電連接件與所述多個第二導電連接件之間的間隙。The semiconductor substrate structure according to claim 1, further comprising a primer disposed between the first group of circuit structures and the second group of circuit structures and filled with the plurality of first conductive connectors and the Gaps between the plurality of second conductive connectors.

一種半導體基板結構的製造方法，包括：形成第一組線路結構於第一臨時載板上，其中所述第一組線路結構包括多層第一線路層與多個第一導電連接件，且每一所述第一導電連接件包括導電蓋；形成第二組線路結構於第二臨時載板上，其中所述第二組線路結構包括多層第二線路層與多個第二導電連接件；以及所述第一組線路結構的所述多個第一導電連接件接合於所述第二組線路結構的所述多個第二導電連接件以形成電性連接且構成多層重佈線結構。 A method for manufacturing a semiconductor substrate structure, comprising: forming a first group of circuit structures on the first temporary carrier, wherein the first group of circuit structures includes multiple first circuit layers and a plurality of first conductive connectors, and each of the first conductive connectors includes a conductive cover ; forming a second set of wiring structures on the second temporary carrier, wherein the second set of wiring structures includes multiple second wiring layers and a plurality of second conductive connectors; and The plurality of first conductive connectors of the first group of circuit structures are bonded to the plurality of second conductive connectors of the second group of circuit structures to form an electrical connection and form a multilayer redistribution structure.