TW202312421A

TW202312421A - Three-dimensional integration of processing chiplet and static random-access memory (sram) chiplets

Info

Publication number: TW202312421A
Application number: TW111119759A
Authority: TW
Inventors: 潤滋常
Original assignee: 新加坡商馬維爾亞洲私人有限公司
Priority date: 2021-05-28
Filing date: 2022-05-26
Publication date: 2023-03-16

Abstract

An electronic device, includes: (i) a processing chiplet configured to process data and having a first side and a second side, (ii) one or more first static random-access memory (SRAM) chiplets disposed on the first side of the processing chiplet and configured to store a first portion of the data, (iii) one or more second SRAM chiplets disposed on the second side of the processing chiplet and configured to store a second portion of the data, (iv) one or more first electrical terminals disposed on the first side of the processing chiplet and configured to electrically connect between the first side of the processing chiplet and the first SRAM chiplets, and (v) one or more second electrical terminals disposed on the second side of the processing chiplet and configured to electrically connect between the second side of the processing chiplet and the second SRAM chiplets.

Description

處理小晶片和靜態隨機存取記憶體(SRAM)小晶片之三維整合3D integration of processing chiplets and static random access memory (SRAM) chiplets

本發明大體上係關於電子裝置且特定言之，係關於用於藉由將處理小晶片及靜態隨機存取記憶體(SRAM)小晶片堆疊在一起而改良電子裝置之效能之方法及系統。The present invention relates generally to electronic devices and in particular to methods and systems for improving the performance of electronic devices by stacking together processing dies and static random access memory (SRAM) dies.

此項技術中已知用於在一電子裝置中整合處理及靜態隨機存取記憶體(SRAM)能力之各種技術。Various techniques are known in the art for integrating processing and static random access memory (SRAM) capabilities in an electronic device.

上文之描述被呈現為此領域中之相關技術之一般概述，且不應被解釋為承認其含有之任何資訊構成對抗本專利申請案之先前技術。The above description is presented as a general overview of related art in this field and should not be construed as an admission that any of the information it contains constitutes prior art against the present patent application.

本文中描述之一實施例提供一種電子裝置，其包含：(i)一處理小晶片，其經組態以處理資料且具有一第一側及一第二側，(ii)一或多個第一靜態隨機存取記憶體(SRAM)小晶片，其或其等安置於該處理小晶片之該第一側上且經組態以儲存該資料之一第一部分，(iii)一或多個第二SRAM小晶片，其或其等安置於該處理小晶片之該第二側上且經組態以儲存該資料之一第二部分，(iv)一或多個第一電端子，其或其等安置於該處理小晶片之該第一側上且經組態以在該處理小晶片之該第一側與該一或多個第一SRAM小晶片之間電連接，及(v)一或多個第二電端子，其或其等安置於該處理小晶片之該第二側上且經組態以在該處理小晶片之該第二側與該一或多個第二SRAM小晶片之間電連接。One embodiment described herein provides an electronic device comprising: (i) a processing chiplet configured to process data and having a first side and a second side, (ii) one or more third a static random access memory (SRAM) die, which or others are disposed on the first side of the processing die and configured to store a first portion of the data, (iii) one or more third Two SRAM chiplets, which or are disposed on the second side of the handle chiplet and are configured to store a second portion of the data, (iv) one or more first electrical terminals, which or etc. disposed on the first side of the handle die and configured for electrical connection between the first side of the handle die and the one or more first SRAM dies, and (v) one or A plurality of second electrical terminals, which or are disposed on the second side of the handle die and configured to be between the second side of the handle die and the one or more second SRAM die Electrical connection between.

在一些實施例中，該電子裝置包含一或多個矽穿孔(TSV)，該一或多個矽穿孔(TSV)穿過該處理小晶片之至少部分形成且經組態以在該處理小晶片與該等第一及第二電端子之至少一者之間傳導電信號。在其他實施例中，該一或多個第一SRAM小晶片包含至少第一及第二給定SRAM小晶片，且該第一給定SRAM小晶片包含：(i)一第一給定側，其面向該處理小晶片之該第一側且連接至該一或多個第一電端子，及(ii)一第二給定側，其面向堆疊於該第一給定SRAM小晶片上之該第二給定SRAM小晶片。在又其他實施例中，該第一給定SRAM小晶片之該第一給定側安置於經組態以在該處理小晶片與該第一給定SRAM小晶片之間交換該資料之該第一部分之至少部分之該一或多個第一電端子上。In some embodiments, the electronic device includes one or more through-silicon vias (TSVs) formed through at least a portion of the handle die and configured to pass through at least a portion of the handle die. conducting electrical signals with at least one of the first and second electrical terminals. In other embodiments, the one or more first SRAM dielets include at least first and second given SRAM dielets, and the first given SRAM dielet includes: (i) a first given side, which faces the first side of the handle die and connects to the one or more first electrical terminals, and (ii) a second given side which faces the first given SRAM die stacked on the first given SRAM die A second given SRAM dielet. In still other embodiments, the first given side of the first given SRAM dielet is disposed on the second side configured to exchange the data between the process dielet and the first given SRAM dielet. A portion of at least a portion of the one or more first electrical terminals.

在一些實施例中，該電子裝置包含安置於該第一給定SRAM小晶片之該第二側上且經組態以在該第一給定SRAM小晶片之該第二側與該第二給定SRAM小晶片之間電連接之一或多個第三電端子。在其他實施例中，該電子裝置包含一或多個給定TSV，該一或多個給定TSV穿過該第一給定SRAM小晶片之至少部分形成且經組態以在該處理小晶片與該等第一及第二給定SRAM小晶片之至少一者之間傳導電信號。在又其他實施例中，該等TSV之至少一者及該等給定TSV之至少一者彼此不同。In some embodiments, the electronic device includes a device disposed on the second side of the first given SRAM die and configured to connect the second side of the first given SRAM die with the second given SRAM die. One or more third electrical terminals are used to electrically connect the SRAM chiplets. In other embodiments, the electronic device includes one or more given TSVs formed across at least a portion of the first given SRAM dielet and configured to operate on the handle dielet. Electrical signals are conducted to and from at least one of the first and second given SRAM dielets. In yet other embodiments, at least one of the TSVs and at least one of the given TSVs are different from each other.

在一些實施例中，該等TSV之該至少一者：(i)具有穿過該處理小晶片之至少部分之一第一長度，(ii)具有沿著該處理小晶片之該第一側之一第一寬度，且(iii)含有具有在該處理小晶片內之一第一體積之一第一金屬層，且該等給定TSV之該至少一者：(a)具有穿過該第一給定SRAM小晶片之至少部分之一第二長度，(b)具有沿著該第一給定SRAM小晶片之該第三側之一第二寬度，且(c)含有具有在該第一給定SRAM小晶片內之一第二體積之一第二金屬層，且該等第一及第二以下項之至少一者彼此不同：(1)長度、(2)寬度、(3)金屬層及(4)體積。在其他實施例中，該處理小晶片形成於一第一基板上且包含第一金屬互連件，且至少該等第一及第二給定SRAM小晶片形成於一第二基板上且包含第二金屬互連件。在又其他實施例中，該第一側包含該第一基板之一第一表面且該第二側包含該等第一金屬互連件，且該第三側包含：(i)該第二基板之一第二表面，或(ii)該等第二金屬互連件。In some embodiments, the at least one of the TSVs: (i) has a first length across at least a portion of the handle die, (ii) has a length along the first side of the handle die. a first width, and (iii) contains a first metal layer having a first volume within the handle dielet, and the at least one of the given TSVs: (a) has A second length of at least part of a given SRAM dielet, (b) having a second width along the third side of the first given SRAM dielet, and (c) having A second metal layer defining a second volume within the SRAM chiplet, and the first and second at least one of: (1) length, (2) width, (3) metal layer, and (4) Volume. In other embodiments, the handle dielet is formed on a first substrate and includes first metal interconnects, and at least the first and second given SRAM dielets are formed on a second substrate and include first metal interconnects. Two metal interconnects. In yet other embodiments, the first side includes a first surface of the first substrate and the second side includes the first metal interconnects, and the third side includes: (i) the second substrate a second surface, or (ii) the second metal interconnects.

在一些實施例中，該等第一及第二SRAM小晶片包含第一及第二數目個SRAM小晶片，且該等第一及第二數目彼此不同。在其他實施例中，該等第一及第二SRAM小晶片包含第一及第二數目個SRAM小晶片，且該等第一及第二數目彼此相等。In some embodiments, the first and second SRAM dielets include first and second numbers of SRAM dielets, and the first and second numbers are different from each other. In other embodiments, the first and second SRAM dielets include first and second numbers of SRAM dielets, and the first and second numbers are equal to each other.

在一些實施例中，該電子裝置包含以下項之至少一者：(i)一第一電路板(CB)基板，其面向該等第一SRAM小晶片之一第一外部SRAM小晶片，(ii)一第二CB基板，其面向該等第二SRAM小晶片之一第二外部SRAM小晶片，及(iii)一或多個第三CB基板，其或其等分別面向該電子裝置之一或多個邊緣，該等邊緣之至少一者正交於該等第一、第二及第三側之至少一者。在其他實施例中，該電子裝置包含第三電端子，該等第三電端子安置於該等第一、第二及第三CB基板之至少一者上且經組態以在以下項之間傳導信號：(i)該等第一、第二及第三CB基板之至少一者，及(ii)以下項之至少一者：(a)處理小晶片，(b)該等第一SRAM小晶片之一或多者，及(c)該等第二SRAM小晶片之一或多者。In some embodiments, the electronic device includes at least one of: (i) a first circuit board (CB) substrate facing a first outer SRAM dielet of the first SRAM dielets, (ii ) a second CB substrate facing a second outer SRAM dielet of the second SRAM dielets, and (iii) one or more third CB substrates facing one or more of the electronic devices respectively A plurality of edges, at least one of the edges is orthogonal to at least one of the first, second and third sides. In other embodiments, the electronic device includes third electrical terminals disposed on at least one of the first, second and third CB substrates and configured to be between Conducting signals: (i) at least one of the first, second and third CB substrates, and (ii) at least one of: (a) processing chiplets, (b) the first SRAM chiplets one or more of the dies, and (c) one or more of the second SRAM dielets.

根據本發明之一實施例，額外提供一種用於生產一電子裝置之方法，該方法包含在具有一第一側及一第二側之一處理小晶片之該第一側上安置一或多個第一靜態隨機存取記憶體(SRAM)小晶片。一或多個第二SRAM小晶片安置於該處理小晶片之該第二側上。一或多個第一電端子安置於該處理小晶片之該第一側上用於在該處理小晶片之該第一側與該一或多個第一SRAM小晶片之間電連接。一或多個第二電端子安置於該處理小晶片之該第二側上用於在該處理小晶片之該第二側與該一或多個第二SRAM小晶片之間電連接。According to an embodiment of the present invention, there is additionally provided a method for producing an electronic device, the method comprising arranging one or more A first static random access memory (SRAM) chiplet. One or more second SRAM dielets are disposed on the second side of the handle dielet. One or more first electrical terminals are disposed on the first side of the handle die for electrical connection between the first side of the handle die and the one or more first SRAM die. One or more second electrical terminals are disposed on the second side of the handle die for electrical connection between the second side of the handle die and the one or more second SRAM die.

在一些實施例中，安置該一或多個第一SRAM小晶片包含安置至少第一及第二給定SRAM小晶片，該第一給定SRAM小晶片包含：(i)一第一給定側，其經安置用於面向該處理小晶片之該第一側且連接至該一或多個第一電端子，及(ii)一第二給定側，其經安置用於面向堆疊於該第一給定SRAM小晶片上之該第二給定SRAM小晶片。在其他實施例中，該方法包含測試以下項之至少一者：(i)處理小晶片，(ii)該等第一SRAM小晶片之一或多者，(iii)該等第二SRAM小晶片之一或多者，(iv)包含電連接至該等第一及第二SRAM小晶片之至少一者之該處理小晶片之一堆疊，及(v)電連接至該堆疊之一或多個電路板(CB)基板。In some embodiments, disposing the one or more first SRAM dielets comprises disposing at least first and second given SRAM dielets, the first given SRAM dielet comprising: (i) a first given side , which is arranged to face the first side of the handle die and is connected to the one or more first electrical terminals, and (ii) a second given side, which is arranged to face the stack on the first The second given SRAM die on a given SRAM die. In other embodiments, the method includes testing at least one of: (i) a process dielet, (ii) one or more of the first SRAM dielets, (iii) the second SRAM dielets One or more of, (iv) a stack comprising the handle dielet electrically connected to at least one of the first and second SRAM dielets, and (v) electrically connected to one or more of the stack Circuit board (CB) substrate.

自結合圖式一起進行之本發明之實施例之以下詳細描述，將更完全理解本發明，其中：The invention will be more fully understood from the following detailed description of embodiments of the invention taken in conjunction with the accompanying drawings, in which:

相關申請案之交叉參考Cross References to Related Applications

本申請案主張2021年5月28日申請之美國臨時專利申請案63/194,812之權利，該案之揭示內容以引用的方式併入本文中。This application claims the benefit of U.S. Provisional Patent Application 63/194,812, filed May 28, 2021, the disclosure of which is incorporated herein by reference.

電子裝置(諸如中央處理單元(CPU)、特定應用積體電路(ASIC)及系統單晶片(SoC)裝置)通常整合(i)用於處理資料之邏輯功能，及(ii)用於對藉由邏輯功能處理之資料執行高速儲存操作之靜態隨機存取記憶體(SRAM)功能。Electronic devices, such as central processing units (CPUs), application-specific integrated circuits (ASICs), and system-on-chip (SoC) devices, typically incorporate (i) logic functions for processing data, and (ii) Static random access memory (SRAM) function of high-speed storage operation of data processed by logic function.

製造技術之改良(諸如經減小尺寸及鰭式場效電晶體(finFET)之引入)降低邏輯功能中之電晶體成本。然而，SRAM功能之縮放速率實質上較緩慢且因此，限制整合式電子裝置之電子效能及/或成本降低。換言之，包括一CPU及SRAM之一SoC可具有不足處理及/或記憶體資源，或可需要用於併入所需處理及/或記憶體資源之SoC之經增加大小及成本。Improvements in fabrication technology, such as through size reduction and the introduction of fin field effect transistors (finFETs), have reduced the cost of transistors in logic functions. However, the scaling rate of SRAM functions is substantially slower and thus, limits the electronic performance and/or cost reduction of integrated electronic devices. In other words, an SoC including a CPU and SRAM may have insufficient processing and/or memory resources, or may require increased size and cost of the SoC to incorporate the required processing and/or memory resources.

一個可能暫時解決方案係使用其他記憶體功能(諸如動態隨機存取記憶體(DRAM))替換至少一些SRAM功能。然而，此組態可限制整合式電子裝置之效能，此係因為邏輯與DRAM之間之通信資料速率比邏輯與一對應SRAM之間之通信資料速率緩慢約十倍(10X)。另一可能暫時解決方案係使用一多晶片模組(MCM)組態並排整合不同邏輯及SRAM晶片。然而，經MCM組態裝置之佔據面積通常實質上大於SoC之佔據面積，且用於在兩個或更多個晶片之間路由信號之通道之數目不足以用於獲得MCM之所需效能。One possible temporary solution is to replace at least some of the SRAM functions with other memory functions, such as Dynamic Random Access Memory (DRAM). However, this configuration can limit the performance of integrated electronics because the communication data rate between the logic and the DRAM is approximately ten times (10X) slower than the communication data rate between the logic and a corresponding SRAM. Another possible temporary solution is to use a multi-chip module (MCM) configuration to integrate different logic and SRAM chips side by side. However, the footprint of an MCM configured device is typically substantially larger than that of an SoC, and the number of channels used to route signals between two or more chips is insufficient for obtaining the required performance of an MCM.

本文中描述之本發明之實施例提供用於藉由在一邏輯小晶片(本文中亦稱為一處理小晶片，其經組態以處理資料)之至少兩側上堆疊多個SRAM小晶片而改良此等電子裝置之成本及/或電子效能之技術。在本發明之背景內容中且在發明申請專利範圍中，術語「小晶片」指代含有功能性之一明確定義子集之一積體電路(IC)。在一實施例中，各小晶片經組態以與一單一封裝中之一中介層上之其他小晶片垂直整合。Embodiments of the invention described herein provide for implementing multiple SRAM dielets by stacking multiple SRAM dielets on at least two sides of a logic dielet (also referred to herein as a processing dielet configured to process data). Technologies to improve the cost and/or electronic performance of these electronic devices. In the context of the present invention and in the claims of the invention, the term "chiplet" refers to an integrated circuit (IC) containing a well-defined subset of functionality. In one embodiment, each dielet is configured to be vertically integrated with other dielets on an interposer in a single package.

在一些實施例中，一電子裝置包括在一或多個邏輯小晶片及多個SRAM小晶片之一總成中實施之一組整合式小晶片。在本實例中，一種電子裝置包括：(i)一處理小晶片，其經組態以處理資料且具有一第一側及一第二側，(ii)一或多個第一SRAM小晶片，其或其等安置於處理小晶片之第一側上且經組態以儲存資料之一第一部分，及(iii)一或多個第二SRAM小晶片，其或其等安置於處理小晶片之第二側上且經組態以儲存在處理小晶片中處理之資料之一第二部分。In some embodiments, an electronic device includes a set of integrated dielets implemented in an assembly of one or more logic dielets and a plurality of SRAM dielets. In this example, an electronic device includes: (i) a processing dielet configured to process data and having a first side and a second side, (ii) one or more first SRAM dielets, which are disposed on the first side of the handle die and are configured to store a first portion of the data, and (iii) one or more second SRAM dies which are disposed on the handle die On the second side and configured to store a second portion of the data processed in the processing chiplet.

在一些實施例中，各小晶片包括：(i)一基板，其具有一主動側(具有本文中描述之主動元件)及一被動側(其不具有主動元件)，(ii)主動元件，諸如電晶體，其等形成於基板之主動側中，及(iii)金屬連接，其等形成於該等電晶體上方且經組態以在該等電晶體之間且在該小晶片與安置於鄰近堆疊小晶片之間之電端子(諸如凸塊或微凸塊)之間互連。小晶片之第一側包括基板之被動側之表面，且在本文中亦稱為小晶片之一背側或背面，且小晶片之第二側(在本文中亦稱為小晶片之一前側或一正面)包括經組態以依一所要方式在小晶片之元件之間(例如，在一或多個電晶體中之摻雜區域之間)互連之金屬連接。在此等實施例中，各對小晶片可以各種組態(諸如面對面、背對背或面對背)配置。In some embodiments, each dielet includes: (i) a substrate having an active side (with active elements as described herein) and a passive side (with no active elements), (ii) active elements such as Transistors formed in the active side of the substrate, and (iii) metal connections formed over the transistors and configured to be between the transistors and between the dielet and disposed adjacent Interconnection between electrical terminals, such as bumps or micro-bumps, between stacked dielets. The first side of the dielet comprises the surface of the passive side of the substrate, and is also referred to herein as a backside or rear side of the dielet, and the second side of the dielet (also referred to herein as a front side or A front side) includes metal connections configured to interconnect in a desired manner between elements of the chiplet (eg, between doped regions in one or more transistors). In these embodiments, pairs of dielets can be arranged in various configurations, such as face-to-face, back-to-back, or face-to-back.

小晶片之基板通常包括具有低導電率之一單晶體半導體基板。在一些實施例中，一或多個矽穿孔(TSV)至少穿過小晶片之至少一者且通常各者之基板形成。TSV經組態以在以背對背或面對背組態堆疊之一對小晶片之金屬連接之間傳導電信號。The substrate of the chiplet usually comprises a single crystal semiconductor substrate with low electrical conductivity. In some embodiments, one or more through-silicon vias (TSVs) are formed at least through the substrate of at least one of, and typically each of, the dielets. TSVs are configured to conduct electrical signals between the metal connections of a pair of dielets stacked in a back-to-back or face-to-back configuration.

在一些實施例中，一指定電子裝置包括一指定處理小晶片，且第一及第二指定SRAM小晶片分別面向指定處理小晶片之第一及第二側。在此等實施例中，指定電子裝置包括：(i)一第一組凸塊，其等安置於指定處理小晶片之第一側與第一指定SRAM小晶片之間，及(ii)一第二組凸塊，其等安置於指定處理小晶片之第二側與第二指定SRAM小晶片之間。應注意，在此組態中，指定處理小晶片經堆疊如下：(i)與第一指定SRAM小晶片背對面或背對背，且(ii)與第二指定SRAM小晶片面對面或面對背(取決於第一及第二指定SRAM小晶片之側配置)。In some embodiments, a given electronic device includes a given process dielet, and first and second given SRAM dielets face first and second sides of the given dealt dielet, respectively. In these embodiments, the designated electronic device includes: (i) a first set of bumps disposed between the first side of the designated handle die and the first designated SRAM die, and (ii) a first designated SRAM die. Two sets of bumps are disposed between the second side of the designated handle die and the second designated SRAM die. It should be noted that in this configuration, the designated process die is stacked as follows: (i) back-to-face or back-to-back with the first designated SRAM die, and (ii) face-to-face or face-to-back with the second designated SRAM die (depending on on the sides of the first and second designated SRAM chiplets).

在一些實施例中，在面對面配置中：(i)一個或全部凸塊形成於指定處理小晶片與第二指定SRAM小晶片之金屬連接(之墊)之間，(ii)一或多個墊可形成於一TSV與金屬連接之間，且(iii)一或多個凸塊可形成於各自兩個堆疊小晶片(例如，指定處理小晶片及第二指定SRAM小晶片)之兩個TSV之間。在面對背組態中，一或多個凸塊形成於TSV之間，且一或多個凸塊可形成於一TSV與金屬連接之間。在背對背組態中，全部凸塊形成於各自兩個堆疊小晶片之兩個TSV之間，如上文描述。下文在圖1、圖2及圖3中詳細描述與小晶片、TSV及凸塊之各種配置相關之實施例。In some embodiments, in a face-to-face configuration: (i) one or all of the bumps are formed between (the pads of) the metal connections of a given handle die and a second given SRAM die, (ii) one or more pads Can be formed between a TSV and the metal connection, and (iii) one or more bumps can be formed between the two TSVs of each of the two stacked dies (e.g., a designated handle die and a second designated SRAM die). between. In the face-to-back configuration, one or more bumps are formed between TSVs, and one or more bumps may be formed between a TSV and a metal connection. In the back-to-back configuration, all bumps are formed between two TSVs of each of the two stacked dielets, as described above. Embodiments related to various configurations of chiplets, TSVs and bumps are described in detail below in FIGS. 1 , 2 and 3 .

在一些實施例中，在處理小晶片之兩側上堆疊任何適合數目個SRAM小晶片為電子裝置提供相對於處理小晶片之處理能力之充分SRAM資源。堆疊SRAM小晶片之數目可在處理小晶片之兩側中相等，或可在處理小晶片之不同側中堆疊不同數目個SRAM小晶片。再者，電子裝置可包括安置於SRAM小晶片之堆疊之間之一或多個額外處理小晶片。In some embodiments, stacking any suitable number of SRAM dielets on both sides of the process dielet provides the electronic device with sufficient SRAM resources relative to the processing capabilities of the process dielet. The number of stacked SRAM dielets can be equal in both sides of the process dielet, or different numbers of SRAM dielets can be stacked in different sides of the process dielet. Furthermore, the electronic device may include one or more additional process dielets disposed between the stack of SRAM dielets.

在一些實施例中，電子裝置包括(例如)經由球電連接至一或多個小晶片之一或多個電路板(CB)基板。在一第一例示性組態中，一第一CB基板之表面面向經堆疊SRAM小晶片之一外部SRAM小晶片之一表面，且使用球電連接至外部SRAM小晶片。在一第二例示性組態中，一第二CB基板之表面正交於處理及SRAM小晶片之正及背側安置，且(例如，經由球)電連接至一些或全部處理及SRAM小晶片之金屬連接。在一第三例示性組態中，電子裝置可包括(例如，經由球)分別電連接至處理及SRAM小晶片之堆疊之六個小面之至多六個CB基板。取決於處理及記憶體能力之規範及在電子裝置中堆疊在一起之處理及SRAM小晶片之各自經實施數目，此等例示性組態改良電子裝置之頻寬及客製化。下文在圖1至圖3中詳細繪示且描述此等實施例。In some embodiments, the electronic device includes one or more circuit board (CB) substrates electrically connected to one or more chiplets, eg, via balls. In a first exemplary configuration, the surface of a first CB substrate faces a surface of an outer SRAM die of the stacked SRAM dies and is electrically connected to the outer SRAM die using balls. In a second exemplary configuration, the surface of a second CB substrate is positioned orthogonal to the front and backsides of the process and SRAM dielets and is electrically connected (e.g., via balls) to some or all of the process and SRAM dielets The metal connection. In a third exemplary configuration, the electronic device may include up to six CB substrates electrically connected (eg, via balls) to the six facets of the stack of process and SRAM dielets, respectively. These exemplary configurations improve bandwidth and customization of electronic devices, depending on the specification of processing and memory capabilities and the respective implemented numbers of processing and SRAM dielets stacked together in the electronic device. These embodiments are illustrated and described in detail in FIGS. 1-3 below.

在一些實施例中，至少一個處理小晶片具有CPU核心之一冗餘，使得旨在在變得不起作用之一第一CPU核心中處理之給定資料可經傳送以供在一第二CPU核心中處理。在具有一或多個處理小晶片之一小晶片堆疊中，CPU核心之此冗餘可改良(i)生產中之良率，及(ii)此小晶片堆疊之操作期間之可靠性。例如，在美國專利申請案17/071,910 (Chang等人在2020年10月15日申請)中描述CPU核心之冗餘之一個實施方案，該案之揭示內容以引用的方式併入本文中。類似地，SRAM小晶片通常具有記憶體區塊之冗餘，使得回應於識別一第一記憶體區塊不起作用，旨在儲存於第一記憶體區塊中之資料可儲存於一第二不同記憶體區塊中。In some embodiments, at least one processing chiplet has redundancy of CPU cores such that given data intended for processing in a first CPU core that becomes inactive can be routed for processing on a second CPU core processed in the core. In a dielet stack with one or more process dielets, this redundancy of CPU cores can improve (i) yield in production, and (ii) reliability during operation of the dielet stack. For example, one implementation of CPU core redundancy is described in US Patent Application 17/071,910 (Chang et al., filed Oct. 15, 2020), the disclosure of which is incorporated herein by reference. Similarly, SRAM chiplets typically have redundancy of memory blocks such that data intended to be stored in a first memory block can be stored in a second memory block in response to identifying a first memory block as ineffective. in different memory blocks.

在一些實施例中，CPU核心及記憶體區塊中之冗餘與各小晶片、CB基板及兩個或更多個經堆疊小晶片之測試一起改良良率且降低與此等電子裝置之製造相關聯之成本。下文在圖4中進一步詳細描述製造及測試程序。In some embodiments, redundancy in the CPU cores and memory blocks along with testing of individual dielets, CB substrates, and two or more stacked dielets improves yield and reduces costs associated with the manufacture of these electronic devices. associated costs. The fabrication and testing procedure is described in further detail below in FIG. 4 .

上文之描述被呈現為在本文中詳細描述之本發明之實施例之一般概述。The above description is presented as a general overview of the embodiments of the invention described in detail herein.

圖1係根據本文中描述之一實施例之一電子裝置11之一示意性橫截面視圖。FIG. 1 is a schematic cross-sectional view of an electronic device 11 according to an embodiment described herein.

在一些實施例中，電子裝置11包括一處理小晶片(PC) 22及多個靜態隨機存取記憶體(SRAM)小晶片(SC) 33a、33b、33c及33d。PC 22包括一基板14，該基板14具有一主動側(在本文中亦稱為前段製程(FEOL) 16)及一被動側。在本實例中，基板14包括一半導體晶圓，諸如由單晶矽製成之一晶圓。In some embodiments, electronic device 11 includes a processing chiplet (PC) 22 and a plurality of static random access memory (SRAM) chiplets (SC) 33a, 33b, 33c, and 33d. The PC 22 includes a substrate 14 having an active side (also referred to herein as front end of line (FEOL) 16 ) and a passive side. In the present example, substrate 14 comprises a semiconductor wafer, such as one made of single crystal silicon.

在一些實施例中，主動元件(諸如電晶體)形成於基板14之主動側中。例如，在主動側中使用離子植入形成電晶體之井及源極/汲極(S/D)，且在基板之表面上(例如，使用擴散及沈積程序)形成閘極(諸如鰭式場效電晶體(finFET)閘極)，使得FEOL 16包括FEOL 16之電晶體(及視情況其他主動元件(例如，二極體))及/或被動元件(例如，電阻器及電容器)之井、S/D及閘極。In some embodiments, active elements, such as transistors, are formed in the active side of substrate 14 . For example, ion implantation is used in the active side to form the wells and source/drains (S/D) of the transistors, and gates (such as FinFETs) are formed on the surface of the substrate (e.g., using diffusion and deposition processes). transistor (finFET gate) such that FEOL 16 includes wells, S /D and gate.

在一些實施例中，電子裝置11包括形成於FEOL 16之電晶體上方且經組態以在FEOL 16之電晶體之間互連以便實行PC 22中之處理功能之金屬連接，在本文中亦稱為後段製程(BEOL) 18。術語FEOL及BEOL與其中電晶體形成於生產線之前段且互連件形成於生產線之後段之小晶片之製造程序相關。應注意，即使FEOL 16之部分形成於基板14內，術語「基板14」仍指代基板之被動側，且術語FEOL 16指代基板之主動側及形成於其中之電晶體。In some embodiments, electronic device 11 includes metal connections, also referred to herein as For back-end-of-line (BEOL)18. The terms FEOL and BEOL relate to a small die manufacturing process where transistors are formed earlier in the production line and interconnects are formed later in the production line. It should be noted that even though portions of FEOL 16 are formed within substrate 14, the term "substrate 14" still refers to the passive side of the substrate, and the term FEOL 16 refers to the active side of the substrate and the transistors formed therein.

在一些實施例中，各SC 33包括(i)一基板14，其通常類似於PC 22之基板14且具有其之被動側，(ii) FEOL 15，其包括基板之具有電晶體之主動側及形成於其中之其他主動及被動元件，及(iii) BEOL 17，其具有用於在FEOL 15之電晶體之間連接之金屬連接。應注意，FEOL 15及16兩者具有以不同組態配置之電晶體。例如，FEOL 15之電晶體以重複記憶體胞元(例如，通常配置於正反器電路中之約四或六個電晶體)配置，而FEOL 16之電晶體以通常不形成一重複圖案之若干類型之邏輯庫配置。In some embodiments, each SC 33 includes (i) a substrate 14, which is generally similar to that of PC 22 and has a passive side thereof, (ii) FEOL 15, which includes an active side of the substrate with transistors and Other active and passive elements formed therein, and (iii) BEOL 17 with metal connections for connection between transistors of FEOL 15 . It should be noted that both FEOLs 15 and 16 have transistors configured in different configurations. For example, the transistors of FEOL 15 are arranged in repeating memory cells (e.g., about four or six transistors typically arranged in a flip-flop circuit), while the transistors of FEOL 16 are arranged in a number of cells that typically do not form a repeating pattern. Type logic library configuration.

在一些實施例中，在當前最先進技術程序節點中，FEOL 16可包括約100億與800億個之間的電晶體 (取決於小晶片大小)且因此，BEOL 18通常包括約八與二十個之間的金屬層以便在FEOL電晶體之間連接。然而，SRAM小晶片通常包括數百萬個胞元且因此，BEOL 17需要遠更小數目個金屬層，例如，約二與六個金屬層之間。歸因於處理與SRAM小晶片之FEOL及BEOL之不同組態，PC 22及SC 33之FEOL及BEOL得到不同數字，而基板之被動側類似，且因此，得到相同數字14。In some embodiments, in current state-of-the-art technology process nodes, FEOL 16 may include between about 10 and 80 billion transistors (depending on dielet size) and thus, BEOL 18 typically includes about eight and twenty The metal layer between each is used to connect between FEOL transistors. However, SRAM dielets typically include millions of cells and thus, BEOL 17 requires a much smaller number of metal layers, eg, between about two and six metal layers. The FEOL and BEOL of PC 22 and SC 33 get different numbers due to processing and different configuration of FEOL and BEOL of SRAM dielets, while the passive side of the substrate is similar, and therefore, gets the same number 14.

在一些實施例中，電子裝置11包括沿著一Y軸穿過PC 22及SC 33之厚度之至少部分形成之一或多個(通常數百或數千個)矽穿孔(TSV) 44。TSV 44經組態以在小晶片之間且更具體言之，在PC 22與SC 33之間傳導電信號。在圖1之實例中，TSV 44穿過全部小晶片之整個厚度形成，但其中TSV 44未形成於基板14中之SC 33b除外。在其他實施例中，TSV 44可僅穿過基板14以及FEOL 15及16形成，使得BEOL之金屬層用於與TSV 44一起傳導電信號。In some embodiments, electronic device 11 includes one or more (typically hundreds or thousands) through-silicon vias (TSVs) 44 formed along a Y-axis through at least part of the thickness of PC 22 and SC 33 . TSV 44 is configured to conduct electrical signals between the dielets, and more specifically, between PC 22 and SC 33 . In the example of FIG. 1 , TSVs 44 are formed through the entire thickness of all dielets except for SC 33b where TSVs 44 are not formed in substrate 14 . In other embodiments, TSV 44 may be formed only through substrate 14 and FEOLs 15 and 16 such that the metal layer of the BEOL is used to conduct electrical signals with TSV 44 .

在本發明之背景內容中且在發明申請專利範圍中，小晶片之基板14之被動側之表面在本文中亦稱為小晶片之背面，且BEOL 17及18之外表面在本文中亦稱為小晶片之正面。在此等實施例中，電子裝置11之各對小晶片可以各種組態(諸如面對面、背對背或面對背)配置。在圖1之實例中，SC 33a及33b經翻轉，使得PC 22及SC 33a以一面對面組態配置(即，FEOL 17及18面向彼此)，且全部其他對小晶片以一面對背組態配置(即，BEOL 17及基板14之對面向彼此)。In the context of the present invention and in the scope of the patent claim, the surface of the passive side of the chiplet's substrate 14 is also referred to herein as the backside of the chiplet, and the outer surfaces of BEOLs 17 and 18 are also referred to herein as The front of the small chip. In these embodiments, each pair of chiplets of electronic device 11 may be arranged in various configurations, such as face-to-face, back-to-back, or face-to-back. In the example of FIG. 1, SCs 33a and 33b are flipped over so that PC 22 and SC 33a are configured in a face-to-face configuration (ie, FEOLs 17 and 18 face each other), and all other pair of dielets are in a face-to-back configuration configuration (ie, opposite sides of BEOL 17 and substrate 14 face each other).

現參考插圖7、8、9、10及13，其等展示電氣裝置11之小晶片之間之介面。Reference is now made to Figures 7, 8, 9, 10 and 13, which show the interfaces between the chiplets of the electrical device 11.

在一些實施例中，電子裝置11包括經組態以在各自對小晶片之間電連接之多個電端子。在本實例中，此等電端子包括由銅製成且具有在約10 µm與30 µm之間之一寬度(例如，沿著X軸)及約5 µm與20 µm之間之一高度(沿著Y軸)之凸塊或微凸塊，在本文中被稱為凸塊19。應注意，TSV 44經組態以(例如)在處理小晶片22與隨後詳細描述之凸塊19之至少一者之間傳導電信號。In some embodiments, electronic device 11 includes a plurality of electrical terminals configured to electrically connect between respective pairs of dielets. In this example, the electrical terminals comprise copper and have a width (e.g., along the X-axis) of between about 10 µm and 30 µm and a height (along Y-axis) bumps or micro-bumps are referred to herein as bumps 19 . It should be noted that the TSVs 44 are configured to conduct electrical signals, for example, between the process dielet 22 and at least one of the bumps 19 described in detail later.

在插圖7及10之實例中，凸塊19a經組態以分別在以下項之間電連接：(i) PC 22之TSV 44a，與(ii)定位於PC 22之兩側上之SC 33a及33c之TSV 44b。在插圖9之實例中，凸塊19a經組態以分別地在PC 22及SC 33a之BEOL 18與17之間電連接。然而，在插圖8中展示之區段中，面對背組態不具有一TSV，使得無電信號被傳導，且因此，此區段不需要一凸塊。應注意，當兩個小晶片之BEOL面向彼此時，凸塊用於在BEOL之金屬連接器及視情況導電墊(未展示)之間傳導電信號，即使在各自區段中不具有TSV。In the example of Figs. 7 and 10, bump 19a is configured to electrically connect between (i) TSV 44a of PC 22, and (ii) SC 33a and TSV 44b of 33c. In the example of Fig. 9, bump 19a is configured to electrically connect between BEOLs 18 and 17 of PC 22 and SC 33a, respectively. However, in the segment shown in Fig. 8, the face-to-back configuration does not have a TSV, so that no electrical signal is conducted, and therefore, this segment does not require a bump. It should be noted that when the BEOLs of the two dielets face each other, the bumps are used to conduct electrical signals between the metal connectors of the BEOLs and optionally conductive pads (not shown), even though there are no TSVs in the respective segments.

返回參考插圖8，在其他實施例中，凸塊19可經形成用於機械支撐基板14與BEOL 17之間之介面。此等凸塊可被稱為虛設凸塊，其等不傳導電信號。返回參考插圖13，一凸塊19b形成於以下項之間：(i)穿過SC 33b之BEOL 17形成之TSV 44d，與(ii)穿過SC 33a形成之TSV 44c。Referring back to FIG. 8 , in other embodiments, bumps 19 may be formed for the interface between the mechanical support substrate 14 and the BEOL 17 . Such bumps may be referred to as dummy bumps, which do not conduct electrical signals. Referring back to Fig. 13, a bump 19b is formed between (i) TSV 44d formed through BEOL 17 of SC 33b, and (ii) TSV 44c formed through SC 33a.

在一些實施例中，TSV 44a、44b、44c及44d全部類似。在其他實施例中，需要各TSV 44傳導具有不同性質(諸如電壓及電流)之信號且因此，TSV 44a、44b、44c及44d之兩者或更多者可彼此不同。各TSV 44具有沿著Y軸之一預定義長度、沿著X軸之寬度(例如，直徑)及其他結構性質(諸如側壁角)。再者，各TSV 44填充有具有一適合紋理、體積及子層之一適合類型之金屬(例如，銅合金)。例如，BEOL 17薄於(沿著Y軸) BEOL 18 (由於具有更少金屬層，如上文描述)且因此，TSV 44b短於TSV 44a。類似地，TSV 44d短於(沿著Y軸) TSV 44c，且可包括：(i)一不同銅合金，及/或(ii)一不同寬度，用於在PC 22與SC 33b之間傳導具有更高各自電流及/或電壓之信號。In some embodiments, TSVs 44a, 44b, 44c, and 44d are all similar. In other embodiments, each TSV 44 is required to conduct signals having different properties, such as voltage and current, and thus, two or more of TSVs 44a, 44b, 44c, and 44d may be different from each other. Each TSV 44 has a predefined length along the Y-axis, a width (eg, diameter) along the X-axis, and other structural properties (such as sidewall angles). Again, each TSV 44 is filled with a suitable type of metal (eg, copper alloy) with a suitable texture, volume, and sublayer. For example, BEOL 17 is thinner (along the Y axis) than BEOL 18 (due to having fewer metal layers, as described above) and thus, TSV 44b is shorter than TSV 44a. Similarly, TSV 44d is shorter (along the Y axis) than TSV 44c, and may include: (i) a different copper alloy, and/or (ii) a different width for conducting between PC 22 and SC 33b with Signals of higher respective current and/or voltage.

類似地，在一些實施例中，凸塊19a及19b全部類似。在其他實施例中，至少兩個凸塊19a及19b (例如)在分別沿著Y及X軸之長度及/或寬度上及/或在其一或多個層之類型上彼此不同。如針對TSV描述，基於透過其傳導之電信號之性質判定各凸塊19之特徵及結構。Similarly, in some embodiments, bumps 19a and 19b are all similar. In other embodiments, at least two bumps 19a and 19b differ from each other, eg, in length and/or width along the Y and X axes, respectively, and/or in the type of one or more layers thereof. As described for TSVs, the characteristics and structure of each bump 19 are determined based on the nature of the electrical signal conducted therethrough.

在一些實施例中，TSV及凸塊之一些特徵之差異(例如，不同材料)需要不同各自程序操作，該等程序操作增加電子裝置11之製造成本。諸如在不同凸塊及/或TSV之寬度(沿著X軸)上之其他差異可被併入使用各自微影遮罩之一適合設計之相同程序操作中。In some embodiments, differences in some features of the TSVs and bumps (eg, different materials) require different respective process operations, which increase the manufacturing cost of the electronic device 11 . Other differences, such as in the width of different bumps and/or TSVs (along the x-axis), can be incorporated into the same process operation using an appropriate design of the respective lithography masks.

在一些實施例中，電子裝置11包括一適合基板，諸如一中介層或任何其他適合類型之一封裝基板。在本實例中，基板包括經組態以在電子裝置11與一電子系統之外部電子裝置(未展示)之間傳導信號之一印刷電路板(CB)基板，在本文中稱為一CB 12。電子裝置11包括經組態以在TSV 44與CB 12之間傳導電信號之多個球55。在本實例中，CB 12面向一外部小晶片(例如，SC 33d)，且球55安置於CB 12與SC 33d之間。In some embodiments, electronic device 11 includes a suitable substrate, such as an interposer or any other suitable type of packaging substrate. In this example, the substrate comprises a printed circuit board (CB) substrate, referred to herein as a CB 12 , configured to conduct signals between the electronic device 11 and external electronic devices (not shown) of an electronic system. Electronic device 11 includes a plurality of balls 55 configured to conduct electrical signals between TSV 44 and CB 12 . In this example, CB 12 faces an outer chiplet (eg, SC 33d), and ball 55 is disposed between CB 12 and SC 33d.

在一些實施例中，球55係由任何適合(通常焊接)材料製成，具有約50 µm與100 µm之間之一典型直徑且係使用任何適合球柵陣列(BGA)焊接程序或任何其他適合程序形成。在其他實施例中，代替球55，電子裝置11可包括一岸面柵格陣列陣列(LGA)、一接腳柵格陣列(PGA)或形成於CB 12與電子裝置11之一或多個外部小晶片之間之任何其他適合類型之電端子。In some embodiments, balls 55 are made of any suitable (typically solder) material, have a typical diameter of between about 50 µm and 100 µm and are made using any suitable ball grid array (BGA) soldering procedure or any other suitable program formed. In other embodiments, instead of the balls 55, the electronic device 11 may include a land grid array array (LGA), a pin grid array (PGA), or be formed outside one or more of the CB 12 and the electronic device 11. Any other suitable type of electrical terminal between chiplets.

應注意，取決於特定電子裝置之處理及記憶體能力，使用處理小晶片22及多個SRAM小晶片33之一垂直三維(3D)整合改良電子裝置11之頻寬及客製化。在本實例中，電子裝置11包括一個處理小晶片及四個SRAM小晶片33，但在其他實施例中，另一電子裝置可包括以下項之至少一者：(i)多個處理小晶片，及(ii)安置於處理小晶片之兩側上及/或不同側上之不同數目個SRAM小晶片。例如，電子裝置可包括堆疊在PC 22之一第一側上之三個SRAM小晶片33及堆疊在電子裝置之第二側上之兩個SRAM小晶片33。再者，兩個或更多個SRAM小晶片可彼此不同，且可更改SRAM小晶片之定向(正面及背面)以便獲得各自電子裝置之所需電氣性質。It should be noted that vertical three-dimensional (3D) integration using the processing dielet 22 and multiple SRAM dielets 33 improves bandwidth and customization of the electronic device 11, depending on the processing and memory capabilities of the particular electronic device. In this example, the electronic device 11 includes one processing dielet and four SRAM dielets 33, but in other embodiments, another electronic device may include at least one of: (i) multiple processing dielets, and (ii) different numbers of SRAM dielets disposed on both sides and/or on different sides of the handle dielet. For example, the electronic device may include three SRAM dielets 33 stacked on a first side of the PC 22 and two SRAM dielets 33 stacked on a second side of the electronic device. Also, two or more SRAM dielets can be different from each other, and the orientation (front and back) of the SRAM dielets can be altered in order to obtain the desired electrical properties of the respective electronic devices.

電子裝置11之組態係藉由實例提供以便繪示藉由本發明之實施例解決之某些問題且演示此等實施例在增強此一電子裝置之效能上之應用。然而，本發明之實施例絕不限於此特定種類之例示性電子裝置，且本文中描述之原理可類似地應用於(例如)下文在圖2及圖3中展示之其他種類之電子裝置。The configuration of electronic device 11 is provided by way of example in order to illustrate some of the problems solved by embodiments of the present invention and to demonstrate the application of these embodiments in enhancing the performance of such an electronic device. However, embodiments of the present invention are in no way limited to this particular class of exemplary electronic devices, and the principles described herein may be similarly applied to other classes of electronic devices, such as shown in FIGS. 2 and 3 below.

圖2係根據本文中描述之另一實施例之一電子裝置21之一示意性橫截面視圖。FIG. 2 is a schematic cross-sectional view of an electronic device 21 according to another embodiment described herein.

在一些實施例中，電子裝置21包括分別面向SC 33b及33d之CB 12a及12b。複數個CB 12減小傳導至少一些電信號所需之距離，且因此，可改良在電子裝置21內處理資料及/或在電子裝置21與上文在圖1中提及之電子系統之外部裝置之間傳輸資料之頻寬及資料速率。再者，電子裝置21包括用於在(i) TSV 44與(ii) CB 12a及12b之間傳導電信號之球55a及55b。In some embodiments, electronic device 21 includes CBs 12a and 12b facing SCs 33b and 33d, respectively. The plurality of CBs 12 reduces the distance required to conduct at least some electrical signals, and thus, may improve the processing of data within the electronic device 21 and/or external devices between the electronic device 21 and the electronic system mentioned above in FIG. 1 The bandwidth and data rate of the data transmitted between them. Furthermore, electronic device 21 includes balls 55a and 55b for conducting electrical signals between (i) TSV 44 and (ii) CBs 12a and 12b.

在一些實施例中，相較於上文之圖1之電子裝置11中之PC 22之定向，電子裝置21之PC 22經翻轉(倒置)。再者，SC 33a、33b及33d之定向亦經翻轉。在此組態中，PC 22及SC 33c以一面對面組態配置，SC 33a及33b以一面對背組態配置，PC 22及SC 33a以一背對背組態配置，且SC 33c及33d亦以一背對背組態配置。應注意，在電子裝置21之組態中，外部SRAM小晶片(例如，SC 33b及33d)之BEOL 17分別面向CB 12a及12d，此可更改(例如，改良)在經堆疊小晶片與CB之間傳導之信號之至少一些之資料速率。In some embodiments, PC 22 of electronic device 21 is flipped (upside down) compared to the orientation of PC 22 in electronic device 11 of FIG. 1 above. Furthermore, the orientations of SCs 33a, 33b and 33d are also reversed. In this configuration, PC 22 and SC 33c are arranged in a face-to-face configuration, SC 33a and 33b are arranged in a side-to-back configuration, PC 22 and SC 33a are arranged in a back-to-back configuration, and SCs 33c and 33d are also arranged in a A back-to-back configuration configuration. It should be noted that in the configuration of the electronic device 21, the BEOLs 17 of the external SRAM dielets (e.g., SC 33b and 33d) face the CBs 12a and 12d, respectively, which can be altered (e.g., improved) between the stacked dielets and the CBs. The data rate of at least some of the signals conducted between them.

如上文在圖1中描述，電子裝置21可包括堆疊在PC 22之各側處之任何適合數目個SRAM小晶片33。As described above in FIG. 1 , electronic device 21 may include any suitable number of SRAM dielets 33 stacked at each side of PC 22 .

圖3係根據本文中描述之另一實施例之一電子裝置31之一示意性橫截面視圖。FIG. 3 is a schematic cross-sectional view of an electronic device 31 according to another embodiment described herein.

在一些實施例中，電子裝置31之小晶片(即，PC 22及SC 33a至33d)之定向類似於電子裝置21之小晶片之定向，但在其他實施例中，可更改小晶片之數目及/或至少一個小晶片之定向，如上文在圖1及圖2中描述。In some embodiments, the orientation of the dielets of electronic device 31 (i.e., PC 22 and SCs 33a-33d) is similar to the orientation of the dielets of electronic device 21, but in other embodiments the number and number of dielets can be varied. and/or orientation of at least one dielet as described above in FIGS. 1 and 2 .

在一些實施例中，電子裝置31包括六個CB 12a、12b、12c、12d、12e及12f (CB 12e及12f以一假想平面圖描繪)及分別用於在CB與經堆疊小晶片之間電連接之六組球55a、55b、55c、55d、55e及55f (球55f以一假想平面圖描繪)。In some embodiments, electronic device 31 includes six CBs 12a, 12b, 12c, 12d, 12e, and 12f (CBs 12e and 12f are depicted in a phantom plan view) and each for electrical connection between the CBs and the stacked dielets. Six groups of balls 55a, 55b, 55c, 55d, 55e and 55f (ball 55f is depicted in a virtual plan view).

在一些實施例中，各CB 12面向經堆疊小晶片之一各自小面。CB 12a及12b分別面向SC 33b及33d，如上文在圖2中描述，且CB 12a及12b之表面通常平行於SC 33b及33d之BEOL之外表面，且通常亦平行於電子裝置31之其他小晶片之外表面。In some embodiments, each CB 12 faces a respective facet of one of the stacked dielets. CBs 12a and 12b face SCs 33b and 33d, respectively, as described above in FIG. the outer surface of the wafer.

在一些實施例中，CB 12c及12d之外表面通常正交於PC 22及SC 33a至33d之前側及背側，且分別經由球55c及55d電連接至電子裝置31之處理及SRAM小晶片之一些或全部之BEOL。例如，(i) CB 12c經由球55c電連接至PC 22以及SC 33b及33d之BEOL，且(ii) CB 12d經由球55d電連接至PC 22之BEOL及全部SRAM小晶片(例如，SC 33a至33d)之BEOL。In some embodiments, the outer surfaces of CBs 12c and 12d are generally orthogonal to the front and back sides of PC 22 and SCs 33a-33d, and are electrically connected to the process of electronics 31 and the SRAM chiplets via balls 55c and 55d, respectively. Some or all of BEOL. For example, (i) CB 12c is electrically connected to PC 22 and the BEOL of SCs 33b and 33d via ball 55c, and (ii) CB 12d is electrically connected to the BEOL of PC 22 and all SRAM dielets (e.g., SC 33a to 33d) via ball 55d. 33d) BEOL.

在一些實施例中，CB 12e及12f之外表面通常正交於PC 22及SC 33a至33d之前側及背側，且分別經由球55e及55f電連接至電子裝置31之全部BEOL。應注意，CB 12e及12f以虛線框展示，此係因為其等沿著XYZ座標系統之Z軸定位，使得其等之兩者定位於圖3之橫截面視圖之XY平面之外。例如，相較於經堆疊小晶片，CB 12e更接近且CB 12f更遠離圖3之橫截面視圖之觀看者。In some embodiments, the outer surfaces of CBs 12e and 12f are generally orthogonal to the front and back sides of PC 22 and SCs 33a-33d, and are electrically connected to all BEOLs of electronic device 31 via balls 55e and 55f, respectively. It should be noted that CBs 12e and 12f are shown in dashed boxes because they are positioned along the Z-axis of the XYZ coordinate system such that they are both positioned outside the XY plane of the cross-sectional view of FIG. 3 . For example, CB 12e is closer and CB 12f is further away from the viewer of the cross-sectional view of FIG. 3 than the stacked dielets.

在一些實施例中，球55c至55f安置於電子裝置31之各自經堆疊小晶片之BEOL上且通常直接連接至該等BEOL。在本發明之背景內容中，術語「直接」指代一小晶片與一各自球之間不使用一TSV之一連接。應注意，在所謂的直接連接中，電子裝置31可包括一或多個層(例如，導電墊)，該一或多個層安置於：(i) CB 12與各自球55之間，及(ii)球55與各自小晶片之BEOL之間。In some embodiments, balls 55c-55f are disposed on the BEOLs of the respective stacked dielets of electronic device 31 and are typically directly connected to the BEOLs. In the context of the present invention, the term "direct" refers to a connection between a chiplet and a respective ball without using a TSV. It should be noted that in a so-called direct connection, the electronic device 31 may include one or more layers (eg, conductive pads) disposed between: (i) the CB 12 and the respective ball 55, and ( ii) Between the ball 55 and the BEOL of the respective dielet.

在一些實施例中，相較於電子裝置11及21之一者或兩者之組態，電子裝置31之組態可改良頻寬及資料速率。多個(例如，六個) CB 12之整合縮短用於傳導信號之距離，且因此，亦可改良此等電子裝置之信號完整性及/或功率完整性。再者，可取決於處理及記憶體能力之規範及在電子裝置31中堆疊在一起之處理及SRAM小晶片之數目更改CB 12及球55之組態，亦如上文在圖1及圖2中詳細描述。In some embodiments, the configuration of electronic device 31 may improve bandwidth and data rate compared to the configuration of one or both of electronic devices 11 and 21 . Integration of multiple (eg, six) CBs 12 shortens the distance used to conduct signals, and thus, may also improve the signal integrity and/or power integrity of these electronic devices. Again, the configuration of the CB 12 and balls 55 can be changed depending on the specifications of the processing and memory capabilities and the number of processing and SRAM dielets stacked together in the electronic device 31, also as above in FIGS. 1 and 2 A detailed description.

電子裝置31之組態係藉由實例提供以便繪示藉由本發明之實施例解決之某些問題且演示此等實施例在增強此一電子裝置之效能上之應用。The configuration of the electronic device 31 is provided by way of example in order to illustrate some of the problems solved by the embodiments of the present invention and to demonstrate the application of these embodiments in enhancing the performance of such an electronic device.

然而，本發明之實施例絕不限於此特定種類之例示性電子裝置，且本文中描述之原理可類似地應用於(例如)上文在圖1及圖2中展示之其他種類之電子裝置或在其他適合類型之電子裝置中使用任何其他適合組態。However, embodiments of the present invention are in no way limited to this particular class of exemplary electronic devices, and the principles described herein may be similarly applied to other classes of electronic devices such as those shown above in FIGS. 1 and 2 or Any other suitable configuration is used in other suitable types of electronic devices.

圖4係示意性地繪示根據本文中描述之一實施例之用於生產電子裝置31之一方法之一流程圖。方法在一SRAM小晶片形成操作100以生產SC 33 (例如，SC 33a至33d)及形成TSV 44及凸塊19開始。應注意，操作100係在晶圓規模(即，晶圓級)實行，使得多個(例如，數十或數百個) SRAM晶粒(包含TSV 44)形成於上文在圖1中描述之晶圓(例如，基板14)上，且隨後，在基板14之表面及SRAM晶粒之BEOL 17上形成凸塊19。在本發明之背景內容中且在發明申請專利範圍中，術語「SRAM晶粒」指代在形成TSV 44及凸塊19之後且在切割晶圓並形成SC 33之前之一SRAM小晶片。FIG. 4 schematically shows a flowchart of a method for producing an electronic device 31 according to an embodiment described herein. The method begins at a SRAM dielet formation operation 100 by producing SCs 33 (eg, SCs 33 a - 33 d ) and forming TSVs 44 and bumps 19 . It should be noted that operation 100 is performed at the wafer scale (ie, wafer level), such that multiple (eg, tens or hundreds) of SRAM die (including TSVs 44) are formed as described above in FIG. Bumps 19 are formed on the wafer (eg, substrate 14 ), and subsequently, on the surface of substrate 14 and the BEOL 17 of the SRAM die. In the context of the present invention and in the patent claims, the term "SRAM die" refers to a small chip of SRAM after the TSVs 44 and bumps 19 are formed and before the wafer is diced and the SCs 33 are formed.

在一SRAM測試及分類操作102，對晶圓之全部SRAM晶粒實行測試及分類程序以便挑入完全起作用(本文中亦稱為「良好」)的SRAM晶粒，且挑出不起作用或部分起作用(本文中亦稱為「不良」)的SRAM晶粒。在一些實施例中，SRAM晶粒通常具有記憶體區塊之冗餘，使得回應於識別一第一記憶體區塊不起作用，旨在儲存於第一記憶體區塊中之資料可儲存於一第二不同記憶體區塊中。另外或替代地，各種技術(諸如錯誤校正碼(ECC))適用於SRAM晶粒。使用記憶體區塊之冗餘及EEC以便改良SRAM晶粒之良率(即，每一晶圓之良好SRAM晶粒之數目)。In a SRAM test and sort operation 102, the test and sort procedure is performed on all of the SRAM dies of the wafer in order to pick out fully functioning (also referred to herein as "good") SRAM die, and pick out non-functioning or Partially functional (also referred to herein as "bad") SRAM die. In some embodiments, the SRAM die typically has redundancy of memory blocks such that in response to identifying a first memory block as ineffective, data intended to be stored in the first memory block can be stored in In a second different memory block. Additionally or alternatively, various techniques such as error correction code (ECC) are applied to the SRAM die. Redundancy of memory blocks and EEC are used in order to improve the yield of SRAM dies (ie, the number of good SRAM dies per wafer).

在一些實施例中，在測試及分類之後，切割晶圓，且處理良好SRAM晶粒以生產經保持用於生產電子裝置31之SRAM小晶片33。In some embodiments, after testing and sorting, the wafer is diced and the SRAM die processed to produce SRAM dielets 33 that are held for production of electronic devices 31 .

在一邏輯小晶片形成操作104，在晶圓級生產旨在用於製造處理小晶片22之邏輯晶粒，包含形成TSV 44及凸塊19，如在上文之操作100中針對SRAM晶粒描述。In a logic die formation operation 104, the logic die intended for fabrication of the handle die 22 is produced at the wafer level, including the formation of TSVs 44 and bumps 19, as described above for the SRAM die in operation 100 .

在一邏輯測試及分類操作106，對晶圓之全部邏輯晶粒實行測試及分類程序以便挑入完全起作用(本文中亦稱為「良好」)的邏輯晶粒，且挑出並丟棄不起作用或部分起作用(本文中亦稱為「不良」)的邏輯晶粒。In a logic test and sort operation 106, the test and sort procedure is performed on all logic dies of the wafer in order to pick fully functional (also referred to herein as "good") logic die, and pick and discard unusable logic die. Functional or partially functional (also referred to herein as "bad") logic die.

在一些實施例中，至少一個及通常全部邏輯晶粒具有CPU核心之一冗餘，使得旨在在不起作用之一第一CPU核心中處理之給定資料可經傳送供在同一邏輯晶粒之一第二CPU核心中處理。CPU核心冗餘特徵可用於改良晶圓上之邏輯晶粒之良率，如上文在操作102中針對SRAM晶粒描述。In some embodiments, at least one and typically all logical dies have redundancy of one of the CPU cores so that a given data intended for processing in a first CPU core that is inactive can be routed to be processed on the same logical die One of the second CPU cores is processed. The CPU core redundancy feature can be used to improve the yield of logic die on the wafer, as described above for SRAM die in operation 102 .

在一些實施例中，在測試及分類之後，切割晶圓，且處理良好邏輯晶粒以生產經保持用於生產電子裝置31之處理小晶片22。In some embodiments, after testing and sorting, the wafer is diced and the good logic die is processed to produce processed dielets 22 that are held for production of electronic devices 31 .

在一3D整合操作108，將經測試良好PC 22及經測試良好SC 33a至33d堆疊在一起，如在上文在圖3中展示且詳細描述之電子裝置31 (排除CB 12)之橫截面視圖中展示。In a 3D integration operation 108, the tested good PC 22 and the tested good SCs 33a-33d are stacked together, as in the cross-sectional view of the electronic device 31 (excluding the CB 12) shown and described in detail above in FIG. displayed in .

在一堆疊測試操作110，對在操作108中形成之經堆疊小晶片實行測試及分類程序。在一些實施例中，將記憶體及CPU核心中之冗餘以及ECC技術用於改良所測試之經堆疊小晶片之良率。操作110以獲得PC 22及SC 33a至33d之經測試良好堆疊之一或多個單元結束，如上文在圖3中展示。In a stack testing operation 110 , testing and sorting procedures are performed on the stacked dielets formed in operation 108 . In some embodiments, redundancy and ECC techniques in memory and CPU cores are used to improve the yield of stacked dielets tested. Operation 110 ends with obtaining one or more units of a tested good stack of PC 22 and SCs 33a - 33d , as shown above in FIG. 3 .

在一基板整合操作112，在PC 22及SC 33a至33d之經測試良好堆疊上及/或在CB 12a至12f上產生球55，且將PC 22及SC 33a至33d之經測試良好堆疊與CB 12a至12f整合以便生產其結構及功能性在上文的圖3中描述之電子裝置31。In a substrate integration operation 112, balls 55 are generated on the tested good stack of PC 22 and SC 33a-33d and/or on the CB 12a-12f, and the tested good stack of PC 22 and SC 33a-33d is combined with the CB 12a to 12f are integrated to produce an electronic device 31 whose structure and functionality is described above in FIG. 3 .

在結束該方法之一最終測試操作114，電子裝置31被測試且在成功地通過測試之後，電子裝置31準備好用於任何適合電子系統中。At the conclusion of one of the final testing operations 114 of the method, the electronic device 31 is tested and after successfully passing the test, the electronic device 31 is ready for use in any suitable electronic system.

在其他實施例中，測試及分類操作(例如，操作102、106、110及114)之至少一者可被部分實行(例如，對旨在被測試之全部或一些晶粒及/或小晶片及/或電子裝置執行測試之一些)或可被跳過以便降低電子裝置31之生產成本。In other embodiments, at least one of the testing and classification operations (e.g., operations 102, 106, 110, and 114) may be performed partially (e.g., on all or some of the die and/or dielets and/or chiplets intended to be tested and and/or some of the tests performed by the electronic device) may be skipped in order to reduce the production cost of the electronic device 31 .

應注意，上文描述之實施例係藉由實例引用，且本發明不限於已在上文中特定展示且描述之內容。實情係，本發明之範疇包含上文中描述之各種特徵之組合及子組合兩者，以及熟習此項技術者在閱讀前述描述之後將想到且在先前技術中未揭示之本發明的變動及修改。以引用的方式併入本專利申請案中之文件應被視為申請案之一整合部分，惟在任何術語在此等經併入文件中以與在本說明書中明確或隱含地作出之定義衝突之一方式定義之範圍內，應僅考量本說明書中之定義除外。It should be noted that the embodiments described above are cited by way of example and that the invention is not limited to what has been particularly shown and described above. Rather, the scope of the invention encompasses both combinations and subcombinations of the various features described above, as well as variations and modifications of the invention that would occur to those skilled in the art after reading the foregoing description and that were not disclosed in the prior art. Documents incorporated by reference into this application for patent shall be considered an integral part of the application, provided that no term is defined in such incorporated document as expressly or impliedly in this specification. Within the scope of the definition of a conflicting method, only the definition in this manual shall be considered except.

7:插圖 8:插圖 9:插圖 10:插圖 11:電子裝置 12:印刷電路板(CB) 12a:印刷電路板(CB) 12b:印刷電路板(CB) 12c:印刷電路板(CB) 12d:印刷電路板(CB) 12e:印刷電路板(CB) 12f:印刷電路板(CB) 13:插圖 14:基板 15:前段製程(FEOL) 16:前段製程(FEOL) 17:後段製程(BEOL) 18:後段製程(BEOL) 19a:凸塊 19b:凸塊 21:電子裝置 22:處理小晶片(PC) 31:電子裝置 33a:靜態隨機存取記憶體(SRAM)小晶片(SC) 33b:靜態隨機存取記憶體(SRAM)小晶片(SC) 33c:靜態隨機存取記憶體(SRAM)小晶片(SC) 33d:靜態隨機存取記憶體(SRAM)小晶片(SC) 44:矽穿孔(TSV) 44a:矽穿孔(TSV) 44b:矽穿孔(TSV) 44c:矽穿孔(TSV) 44d:矽穿孔(TSV) 55:球 55a:球 55b:球 55c:球 55d:球 55e:球 55f:球 100:SRAM小晶片形成操作 102:SRAM測試及分類操作 104:邏輯小晶片形成操作 106:邏輯測試及分類操作 108:3D整合操作 110:堆疊測試操作 112:基板整合操作 114:最終測試操作 7: Illustration 8: Illustration 9: Illustration 10: Illustration 11: Electronic device 12: Printed circuit board (CB) 12a: Printed Circuit Board (CB) 12b: Printed Circuit Board (CB) 12c: Printed Circuit Board (CB) 12d: Printed circuit board (CB) 12e: Printed Circuit Board (CB) 12f: Printed circuit board (CB) 13: Illustration 14: Substrate 15: Front end of line (FEOL) 16: Front end of line (FEOL) 17: Back end of line (BEOL) 18: Back end of line (BEOL) 19a: Bump 19b: Bump 21: Electronic device 22: Handling Chiplets (PC) 31: Electronic device 33a: Static Random Access Memory (SRAM) Chiplet (SC) 33b: Static Random Access Memory (SRAM) Chiplet (SC) 33c: Static Random Access Memory (SRAM) Chiplet (SC) 33d: Static Random Access Memory (SRAM) Chiplet (SC) 44: Through Silicon Via (TSV) 44a: Through Silicon Via (TSV) 44b: Through Silicon Via (TSV) 44c: Through Silicon Via (TSV) 44d: Through Silicon Via (TSV) 55: ball 55a: ball 55b: ball 55c: ball 55d: ball 55e: ball 55f: ball 100: SRAM small die formation operation 102: SRAM test and classification operation 104:Logic dielet formation operation 106: Logic test and classification operation 108: 3D integrated operation 110:Stack test operation 112: Substrate integration operation 114: Final test operation

圖1、圖2及圖3係根據本文中描述之實施例之各自電子裝置之示意性橫截面視圖；及1 , 2 and 3 are schematic cross-sectional views of respective electronic devices according to embodiments described herein; and

圖4係示意性地繪示根據本文中描述之一實施例之用於生產圖3之電子裝置之一方法之一流程圖。FIG. 4 schematically illustrates a flowchart of a method for producing the electronic device of FIG. 3 according to an embodiment described herein.

7:插圖 7: Illustration

8:插圖 8: Illustration

9:插圖 9: Illustration

10:插圖 10: Illustration

11:電子裝置 11: Electronic device

12:印刷電路板(CB) 12: Printed circuit board (CB)

13:插圖 13: Illustration

14:基板 14: Substrate

15:前段製程(FEOL) 15: Front end of line (FEOL)

16:前段製程(FEOL) 16: Front end of line (FEOL)

17:後段製程(BEOL) 17: Back end of line (BEOL)

18:後段製程(BEOL) 18: Back end of line (BEOL)

19a:凸塊 19a: Bump

19b:凸塊 19b: Bump

22:處理小晶片(PC) 22: Handling Chiplets (PC)

33a:靜態隨機存取記憶體(SRAM)小晶片(SC) 33a: Static Random Access Memory (SRAM) Chiplet (SC)

33b:靜態隨機存取記憶體(SRAM)小晶片(SC) 33b: Static Random Access Memory (SRAM) Chiplet (SC)

33c:靜態隨機存取記憶體(SRAM)小晶片(SC) 33c: Static Random Access Memory (SRAM) Chiplet (SC)

33d:靜態隨機存取記憶體(SRAM)小晶片(SC) 33d: Static Random Access Memory (SRAM) Chiplet (SC)

44:矽穿孔(TSV) 44: Through Silicon Via (TSV)

44a:矽穿孔(TSV) 44a: Through Silicon Via (TSV)

44b:矽穿孔(TSV) 44b: Through Silicon Via (TSV)

44c:矽穿孔(TSV) 44c: Through Silicon Via (TSV)

44d:矽穿孔(TSV) 44d: Through Silicon Via (TSV)

55:球 55: ball

Claims

一種電子裝置，其包括：一處理小晶片，其經組態以處理資料且具有一第一側及一第二側；一或多個第一靜態隨機存取記憶體(SRAM)小晶片，其或其等安置於該處理小晶片之該第一側上且經組態以儲存該資料之一第一部分；一或多個第二SRAM小晶片，其或其等安置於該處理小晶片之該第二側上且經組態以儲存該資料之一第二部分；一或多個第一電端子，其或其等安置於該處理小晶片之該第一側上且經組態以在該處理小晶片之該第一側與該一或多個第一SRAM小晶片之間電連接；及一或多個第二電端子，其或其等安置於該處理小晶片之該第二側上且經組態以在該處理小晶片之該第二側與該一或多個第二SRAM小晶片之間電連接。 An electronic device comprising: a processing chiplet configured to process data and having a first side and a second side; one or more first static random access memory (SRAM) dielets disposed on the first side of the handle dielet and configured to store a first portion of the data; one or more second SRAM dielets disposed on the second side of the handle dielet and configured to store a second portion of the data; One or more first electrical terminals disposed on the first side of the handle die and configured to communicate with the one or more first SRAM dies on the first side of the handle die electrical connections between chips; and One or more second electrical terminals disposed on the second side of the handle die and configured to communicate with the one or more second SRAM dies on the second side of the handle die Electrical connections between chips.

如請求項1之電子裝置，其進一步包括一或多個矽穿孔(TSV)，該一或多個矽穿孔(TSV)穿過該處理小晶片之至少部分形成且經組態以在該處理小晶片與該等第一及第二電端子之至少一者之間傳導電信號。The electronic device of claim 1, further comprising one or more through-silicon vias (TSVs) formed through at least a portion of the handle die and configured to pass through at least a portion of the handle die Electrical signals are conducted between the chip and at least one of the first and second electrical terminals.

如請求項2之電子裝置，其中該一或多個第一SRAM小晶片包括至少第一及第二給定SRAM小晶片，且其中該第一給定SRAM小晶片包括：(i)一第一給定側，其面向該處理小晶片之該第一側且連接至該一或多個第一電端子，及(ii)一第二給定側，其面向堆疊於該第一給定SRAM小晶片上之該第二給定SRAM小晶片。The electronic device of claim 2, wherein the one or more first SRAM dielets include at least first and second given SRAM dielets, and wherein the first given SRAM dielet includes: (i) a first a given side facing the first side of the handle die and connected to the one or more first electrical terminals, and (ii) a second given side facing towards the first given SRAM chip stacked on the first given SRAM die The second given SRAM dielet on the die.

如請求項3之電子裝置，其中該第一給定SRAM小晶片之該第一給定側安置於經組態以在該處理小晶片與該第一給定SRAM小晶片之間交換該資料之該第一部分之至少部分之該一或多個第一電端子上。The electronic device of claim 3, wherein the first given side of the first given SRAM dielet is disposed on a side configured to exchange the data between the processing dielet and the first given SRAM dielet On the one or more first electrical terminals of at least a portion of the first portion.

如請求項3之電子裝置，其進一步包括安置於該第一給定SRAM小晶片之該第二側上且經組態以在該第一給定SRAM小晶片之該第二側與該第二給定SRAM小晶片之間電連接之一或多個第三電端子。The electronic device of claim 3, further comprising disposed on the second side of the first given SRAM chiplet and configured to connect the second side of the first given SRAM chiplet to the second side of the first given SRAM chiplet. One or more third electrical terminals are electrically connected between given SRAM dielets.

如請求項3之電子裝置，其進一步包括一或多個給定TSV，該一或多個給定TSV穿過該第一給定SRAM小晶片之至少部分形成且經組態以在該處理小晶片與該等第一及第二給定SRAM小晶片之至少一者之間傳導電信號。The electronic device of claim 3, further comprising one or more given TSVs formed across at least a portion of the first given SRAM dielet and configured to process Electrical signals are conducted between the die and at least one of the first and second given SRAM dielets.

如請求項6之電子裝置，其中該等TSV之至少一者及該等給定TSV之至少一者彼此不同。The electronic device according to claim 6, wherein at least one of the TSVs and at least one of the given TSVs are different from each other.

如請求項7之電子裝置，其中該等TSV之該至少一者：(i)具有穿過該處理小晶片之至少部分之一第一長度，(ii)具有沿著該處理小晶片之該第一側之一第一寬度，且(iii)含有具有在該處理小晶片內之一第一體積之一第一金屬層，且該等給定TSV之該至少一者：(a)具有穿過該第一給定SRAM小晶片之至少部分之一第二長度，(b)具有沿著該第一給定SRAM小晶片之該第三側之一第二寬度，且(c)含有具有在該第一給定SRAM小晶片內之一第二體積之一第二金屬層，且其中該等第一及第二以下項之至少一者彼此不同：(1)長度、(2)寬度、(3)金屬層及(4)體積。The electronic device of claim 7, wherein the at least one of the TSVs: (i) has a first length across at least a portion of the handle die, (ii) has a first length along the handle die a first width on one side, and (iii) contains a first metal layer having a first volume within the handle dielet, and the at least one of the given TSVs: (a) has a through A second length of at least a portion of the first given SRAM dielet, (b) has a second width along the third side of the first given SRAM dielet, and (c) has A second metal layer of a second volume within a first given SRAM dielet, and wherein the first and second at least one of: (1) length, (2) width, (3) differ from each other ) metal layer and (4) volume.

如請求項3之電子裝置，其中該處理小晶片形成於一第一基板上且包括第一金屬互連件，且至少該等第一及第二給定SRAM小晶片形成於一第二基板上且包括第二金屬互連件。The electronic device of claim 3, wherein the handle dielet is formed on a first substrate and includes first metal interconnects, and at least the first and second given SRAM dielets are formed on a second substrate and includes a second metal interconnection.

如請求項9之電子裝置，其中該第一側包括該第一基板之一第一表面且該第二側包括該等第一金屬互連件，且其中該第三側包括：(i)該第二基板之一第二表面，或(ii)該等第二金屬互連件。The electronic device of claim 9, wherein the first side includes a first surface of the first substrate and the second side includes the first metal interconnects, and wherein the third side includes: (i) the A second surface of the second substrate, or (ii) the second metal interconnections.

如請求項1之電子裝置，其中該等第一及第二SRAM小晶片包括第一及第二數目個SRAM小晶片，其中該等第一及第二數目彼此不同。The electronic device of claim 1, wherein the first and second SRAM dielets comprise first and second numbers of SRAM dielets, wherein the first and second numbers are different from each other.

如請求項1之電子裝置，其中該等第一及第二SRAM小晶片包括第一及第二數目個SRAM小晶片，其中該等第一及第二數目彼此相等。The electronic device of claim 1, wherein the first and second SRAM dielets comprise first and second numbers of SRAM dielets, wherein the first and second numbers are equal to each other.

如請求項1之電子裝置，其進一步包括以下項之至少一者：(i)一第一電路板(CB)基板，其面向該等第一SRAM小晶片之一第一外部SRAM小晶片，(ii)一第二CB基板，其面向該等第二SRAM小晶片之一第二外部SRAM小晶片，及(iii)一或多個第三CB基板，其或其等分別面向該電子裝置之一或多個邊緣，其中該等邊緣之至少一者正交於該等第一、第二及第三側之至少一者。As the electronic device of claim 1, it further includes at least one of the following items: (i) a first circuit board (CB) substrate facing a first external SRAM chiplet of the first SRAM chiplets, ( ii) a second CB substrate facing a second outer SRAM dielet of the second SRAM dielets, and (iii) one or more third CB substrates facing one or more of the electronic devices respectively or a plurality of edges, wherein at least one of the edges is orthogonal to at least one of the first, second and third sides.

如請求項13之電子裝置，其進一步包括第三電端子，該等第三電端子安置於該等第一、第二及第三CB基板之至少一者上且經組態以在以下項之間傳導信號：(i)該等第一、第二及第三CB基板之至少一者，及(ii)以下項之至少一者：(a)處理小晶片，(b)該等第一SRAM小晶片之一或多者，及(c)該等第二SRAM小晶片之一或多者。As the electronic device of claim 13, it further comprises a third electrical terminal disposed on at least one of the first, second and third CB substrates and configured to be in the following items conducting signals between: (i) at least one of the first, second and third CB substrates, and (ii) at least one of: (a) processing chiplets, (b) the first SRAMs one or more of the dielets, and (c) one or more of the second SRAM dielets.

一種用於生產一電子裝置之方法，該方法包括：在具有一第一側及一第二側之一處理小晶片之該第一側上安置一或多個第一靜態隨機存取記憶體(SRAM)小晶片；在該處理小晶片之該第二側上安置一或多個第二SRAM小晶片；在該處理小晶片之該第一側上安置用於在該處理小晶片之該第一側與該一或多個第一SRAM小晶片之間電連接之一或多個第一電端子；及在該處理小晶片之該第二側上安置用於在該處理小晶片之該第二側與該一或多個第二SRAM小晶片之間電連接之一或多個第二電端子。 A method for producing an electronic device, the method comprising: disposing one or more first static random access memory (SRAM) dielets on the first side of a handle dielet having a first side and a second side; disposing one or more second SRAM dielets on the second side of the handle dielet; disposing one or more first electrical terminals on the first side of the handle dielet for electrical connection between the first side of the handle dielet and the one or more first SRAM dielets; and One or more second electrical terminals are disposed on the second side of the handle dielet for electrical connection between the second side of the handle dielet and the one or more second SRAM dielets.

如請求項15之方法，其進一步包括穿過該處理小晶片之至少部分形成用於在該處理小晶片與該等第一及第二電端子之至少一者之間傳導電信號之一或多個矽穿孔(TSV)。The method of claim 15, further comprising forming one or more through at least a portion of the handle dielet for conducting electrical signals between the handle dielet and at least one of the first and second electrical terminals. through silicon vias (TSVs).

如請求項16之方法，其中安置該一或多個第一SRAM小晶片包括安置至少第一及第二給定SRAM小晶片，其中該第一給定SRAM小晶片包括：(i)一第一給定側，其經安置用於面向該處理小晶片之該第一側且連接至該一或多個第一電端子，及(ii)一第二給定側，其經安置用於面向堆疊於該第一給定SRAM小晶片上之該第二給定SRAM小晶片。The method of claim 16, wherein disposing the one or more first SRAM dielets comprises disposing at least first and second given SRAM dielets, wherein the first given SRAM dielet comprises: (i) a first a given side arranged to face the first side of the handle dielet and connected to the one or more first electrical terminals, and (ii) a second given side arranged to face the stack The second given SRAM die on the first given SRAM die.

如請求項16之方法，其進一步包括安置以下項之至少一者：(i)一第一電路板(CB)基板，其面向該等第一SRAM小晶片之一第一外部SRAM小晶片，(ii)一第二CB基板，其面向該等第二SRAM小晶片之一第二外部SRAM小晶片，及(iii)一或多個第三CB基板，其或其等分別面向該電子裝置之一或多個邊緣，其中該等邊緣之至少一者正交於該等第一、第二及第三側之至少一者。The method of claim 16, further comprising disposing at least one of: (i) a first circuit board (CB) substrate facing a first outer SRAM dielet of the first SRAM dielets, ( ii) a second CB substrate facing a second outer SRAM dielet of the second SRAM dielets, and (iii) one or more third CB substrates facing one or more of the electronic devices respectively or a plurality of edges, wherein at least one of the edges is orthogonal to at least one of the first, second and third sides.

如請求項18之方法，其進一步包括在該等第一、第二及第三CB基板之至少一者上安置用於在以下項之間傳導信號之第三電端子：(i)該等第一、第二及第三CB基板之至少一者，及(ii)以下項之至少一者：(a)處理小晶片，(b)該等第一SRAM小晶片之一或多者，及(c)該等第二SRAM小晶片之一或多者。The method of claim 18, further comprising disposing on at least one of the first, second and third CB substrates a third electrical terminal for conducting signals between: (i) the first 1. At least one of the second and third CB substrates, and (ii) at least one of the following: (a) handle chiplets, (b) one or more of the first SRAM chiplets, and ( c) One or more of the second SRAM dielets.

如請求項15之方法，其進一步包括測試以下項之至少一者：(i)處理小晶片，(ii)該等第一SRAM小晶片之一或多者，(iii)該等第二SRAM小晶片之一或多者，(iv)包括電連接至該等第一及第二SRAM小晶片之至少一者之該處理小晶片之一堆疊，及(v)電連接至該堆疊之一或多個電路板(CB)基板。The method of claim 15, further comprising testing at least one of: (i) the process dielet, (ii) one or more of the first SRAM dielets, (iii) the second SRAM dielets One or more of the chips, (iv) comprising a stack of the handle chiplets electrically connected to at least one of the first and second SRAM chiplets, and (v) electrically connected to one or more of the stack a circuit board (CB) substrate.