CN114497033A - Three-dimensional chip - Google Patents

Three-dimensional chip Download PDF

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Publication number
CN114497033A
CN114497033A CN202210101030.6A CN202210101030A CN114497033A CN 114497033 A CN114497033 A CN 114497033A CN 202210101030 A CN202210101030 A CN 202210101030A CN 114497033 A CN114497033 A CN 114497033A
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functional
chip
units
unit
path
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顾东华
吴日新
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Shanghai Enflame Technology Co ltd
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Shanghai Enflame Technology Co ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
    • H01L27/0688—Integrated circuits having a three-dimensional layout
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B10/00—Static random access memory [SRAM] devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B61/00—Magnetic memory devices, e.g. magnetoresistive RAM [MRAM] devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N59/00—Integrated devices, or assemblies of multiple devices, comprising at least one galvanomagnetic or Hall-effect element covered by groups H10N50/00 - H10N52/00

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

The embodiment of the invention discloses a three-dimensional chip, which comprises: at least two functional chips stacked in sequence; each functional chip comprises N functional units and N connecting units which are in one-to-one correspondence with the N functional units, wherein the connecting units are used for accessing the corresponding functional units; the at least two functional chips comprise at least one multipath functional chip; in the multi-path functional chip, the N link units include at least two multi-path link units, and the multi-path link units are configured to be in communication connection with at least one other multi-path link unit; in two adjacent functional chips, the connecting unit in one functional chip is correspondingly and electrically connected with the connecting unit in the other functional chip; wherein N is more than or equal to 2. The embodiment of the invention can improve the integration level of the chips, and the multi-interconnection channel design among the chips can also improve the yield of the chips.

Description

Three-dimensional chip
Technical Field
The embodiment of the invention relates to a chip technology, in particular to a three-dimensional chip.
Background
Chips, such as processor chips, are a way to miniaturize circuits in electronics, typically by fabricating circuits on semiconductor wafers, and are widely used in modern electronics.
However, the performance of the single-core processor at present reaches the bottleneck stage, and it becomes very difficult to further improve the processing capability of the single-core processor, so that the new processor mostly adopts a multi-core design. The Cache (Cache) and the processing unit of the traditional multi-core processor are on the same wafer, the Cache (Cache) mainly comprises an SRAM (static random access memory), the SRAM is limited along with the reduction of the process, the SRAM occupies a large proportion of the area of a chip, the reduction of the whole area of the chip is influenced, the further increase of the number of the processor cores is limited, and the performance improvement of the chip is influenced.
Disclosure of Invention
The invention provides a three-dimensional chip, which is used for improving the integration level of the chip, further improving the performance of the chip and simultaneously improving the overall yield through the connection of multiple channels among the chips.
The embodiment of the invention provides a three-dimensional chip, which comprises:
at least two functional chips stacked in sequence; each functional chip comprises N functional units and N connecting units which are in one-to-one correspondence with the N functional units, wherein the connecting units are used for accessing the corresponding functional units;
the at least two functional chips comprise at least one multipath functional chip; in the multi-path functional chip, the N link units include at least two multi-path link units, and the multi-path link units are configured to be in communication connection with at least one other multi-path link unit;
in two adjacent functional chips, the connecting unit in one functional chip is correspondingly and electrically connected with the connecting unit in the other functional chip; wherein N is more than or equal to 2.
Optionally, the multi-path function chip includes a system bus, and each of the connection units is communicatively connected to the system bus.
Optionally, in the multi-path functional chip, the N link units are all multi-path link units, and each multi-path link unit is in communication connection with at least one other multi-path link unit.
Optionally, in the multi-path functional chip, the N functional units are arranged in an array in the first direction and the second direction, and gaps between the N functional units form a grid structure, the multi-path connection unit is located at a node position of the grid structure adjacent to the corresponding functional unit, and the N multi-path connection units are arranged in an array; any one of the multipath connecting units is in communication connection with the multipath connecting unit adjacent to the multipath connecting unit along the first direction and the multipath connecting unit adjacent to the multipath connecting unit along the second direction.
Alternatively, N functional units may be combined according to requirements, and small units may be combined to form larger-scale units to support larger-scale computing requirements.
Alternatively, at least one of the link units other than the multipath link unit is integrated inside the corresponding functional unit.
Optionally, the at least two functional chips include a computing chip and a memory chip; the functional unit in the computing chip is a computing unit, and the functional unit in the storage chip is a storage unit.
Optionally, the computing unit is any one of a central processing unit CPU, a processor distributed processing unit DPU, or an AI acceleration core;
the memory unit is any one of a Static Random Access Memory (SRAM), a Dynamic Random Access Memory (DRAM) and a nonvolatile Magnetic Random Access Memory (MRAM).
Optionally, the memory chip may be divided into a plurality of units according to the calculation scale, and the size of the unit may be configured according to the calculation requirement.
Optionally, the connection unit includes a bonding bump, and a corresponding connection unit in an adjacent functional chip is bonded through the bonding bump.
Optionally, the connection unit includes a bonding bump and a through silicon via TSV, where the bonding bump and the through silicon via TSV are located at two opposite sides of the connection unit;
optionally, the connection unit inter-chip connection also includes bumps (Bump) or micro bumps (uBump) to connect multiple chips;
in the adjacent functional chips, the bonding convex point of one of the two corresponding connecting units is connected with the silicon through hole of the other connecting unit.
Optionally, the three-dimensional chip further includes a substrate, and the substrate and the outermost functional chip are packaged by flip-chip bonding.
According to the technical scheme of the embodiment of the invention, the adopted three-dimensional chips comprise at least two functional chips which are sequentially stacked; each functional chip comprises N functional units and N connecting units which are in one-to-one correspondence with the N functional units, wherein the connecting units are used for accessing the corresponding functional units; the at least two functional chips comprise at least one multipath functional chip; in the multipath function chip, the N connection units comprise at least two multipath connection units, and the multipath connection units are configured to be in communication connection with at least one other multipath connection unit; in two adjacent functional chips, the connecting unit in one functional chip is correspondingly and electrically connected with the connecting unit in the other functional chip; wherein N is more than or equal to 2. In this embodiment, a calculation function (logic) and a storage function (cache) are respectively placed in different functional chips, and then the two functional chips are connected in a three-dimensional packaging manner, so that the integration level of the chips is further improved, and the chips have higher processing performance. In addition, by arranging at least two multipath connecting units, a plurality of access paths can be provided for the functional units corresponding to the multipath connecting units, the condition that the functional units cannot be accessed due to the fact that the access paths are failed once only one access path exists is avoided, the probability of damage of the multipath functional chip is reduced, and the overall yield of the chip is improved.
Drawings
Fig. 1 is a schematic structural diagram of a three-dimensional chip according to an embodiment of the present invention;
fig. 2 is a schematic structural diagram of a functional chip according to an embodiment of the present invention;
FIG. 3 is a schematic structural diagram of another functional chip according to an embodiment of the present invention;
FIG. 4 is a schematic structural diagram of another three-dimensional chip according to an embodiment of the present invention;
FIG. 5 is a schematic structural diagram of another three-dimensional chip according to an embodiment of the present invention;
fig. 6 is a schematic structural diagram of another three-dimensional chip according to an embodiment of the present invention.
Detailed Description
The present invention will be described in further detail with reference to the accompanying drawings and examples. It is to be understood that the specific embodiments described herein are merely illustrative of the invention and are not limiting of the invention. It should be further noted that, for the convenience of description, only some of the structures related to the present invention are shown in the drawings, not all of the structures.
Fig. 1 is a schematic structural diagram of a three-dimensional chip according to an embodiment of the present invention, and fig. 2 is a schematic structural diagram of a functional chip according to an embodiment of the present invention, where with reference to fig. 1 and fig. 2, the three-dimensional chip includes: at least two functional chips 1, wherein the at least two functional chips 1 are stacked in sequence, each functional chip 1 comprises N functional units 102 and N connecting units 101 corresponding to the N functional units 102 one by one, and the connecting units 101 are used for accessing the corresponding functional units 102; at least two functional chips 1 comprise at least one multipath functional chip; in the multi-path functional chip, the N connection units 101 include at least two multi-path connection units 1011, and the multi-path connection units 1011 are configured to be in communication connection with at least one other multi-path connection unit 1011; in two adjacent functional chips 1, the connecting unit 101 in one functional chip 1 is correspondingly and electrically connected with the connecting unit 101 in the other functional chip 1; wherein N is more than or equal to 2.
Specifically, the functional chip 1 is a chip that implements a specific function, such as implementing a storage function or implementing a calculation function; the functional units 102 in the same functional chip 1 have the same function, for example, all are computing units or all are storage units; the functions of the functional units 102 in different functional chips 1 may be the same or different; exemplarily, as shown in fig. 1, fig. 1 exemplarily shows that the three-dimensional chip includes two functional chips, namely a first functional chip 10 and a second functional chip 11, which are stacked in sequence, where the first functional chip 10 may be, for example, a computing chip, and then the functional units 102 in the first functional chip 10 are all computing units, and the computing units are used for completing the computation of data; the second functional chip 11 may be, for example, a memory chip, and the functional units 102 in the second functional chip 11 are all memory units, and the memory units are used for completing storage of data; the number of the computing units in the first functional chip 10 is the same as the number of the storage units in the second functional chip 11, and each computing unit corresponds to one storage unit, that is, the connection unit corresponding to each computing unit in the first functional chip 10 is connected with the connection unit corresponding to each storage unit in the second functional chip 11, so that the computing unit in the first functional chip 10 can read data in the storage unit in the second functional chip 11; in this embodiment, a calculation function (logic) and a storage function (cache) are respectively placed in different functional chips, and then the two functional chips are connected in a three-dimensional packaging manner, so that the integration level of the chips is further improved, and the chips have higher processing performance.
In addition, in the present embodiment, at least one multi-path function chip is included in the at least two function chips, in other words, all the function chips in the three-dimensional chip may be multi-path function chips, or some of the multi-path function chips, the function chips other than the multi-path function chips are defined as single-path function chips, for example, and the first function chip 10 and the second function chip 11 shown in fig. 1 are both multi-path function chips; the multi-path functional chip is different from the single-path functional chip in that the multi-path functional chip includes at least two functional units having multiple access paths, as shown in fig. 1 and 2, the connection unit 101 in the first functional chip 10 is divided into a single-path connection unit 1012 and a multi-path connection unit 1011, and the connection unit 111 in the second functional chip 11 includes a single-path connection unit 1112 and a multi-path connection unit 1111; taking the first functional chip 10 as an example, the single path connection unit 1012 can only access the corresponding functional unit, and the multi-path connection unit 1011 can directly access the corresponding functional unit, and can also access the functional unit corresponding to the other multi-path connection unit through the other multi-path connection unit 1011 having a communication connection with the multi-path connection unit, that is, by providing at least two multi-path connection units, a plurality of access paths can be provided for the functional unit corresponding to the multi-path connection unit, thereby avoiding the situation that the functional unit cannot be accessed once the access path fails when only one access path exists, and reducing the probability of damage to the multi-path functional chip. The connection unit 101 can provide communication connection in a vertical direction (stacking direction of the functional chips) and communication connection in a horizontal direction (inside the functional units, between the connection unit and the connection unit, or between the connection unit and the functional units), and the connection unit 101 can be implemented by various logic circuits; in addition, the connection unit 101 may be integrated inside the corresponding function unit 102 (e.g., the upper half function unit 102 and the corresponding connection unit in fig. 2), or may be located outside the corresponding function unit 102 (e.g., the lower half function unit 102 and the corresponding connection unit in fig. 2).
According to the technical scheme of the embodiment, the adopted three-dimensional chips comprise at least two functional chips which are sequentially stacked; each functional chip comprises N functional units and N connecting units which are in one-to-one correspondence with the N functional units, wherein the connecting units are used for accessing the corresponding functional units; the at least two functional chips comprise at least one multipath functional chip; in the multipath function chip, the N connection units comprise at least two multipath connection units, and the multipath connection units are configured to be in communication connection with at least one other multipath connection unit; in two adjacent functional chips, the connecting unit in one functional chip is correspondingly and electrically connected with the connecting unit in the other functional chip; wherein N is more than or equal to 2. In this embodiment, a calculation function (logic) and a storage function (cache) are respectively placed in different functional chips, and then the two functional chips are connected in a three-dimensional packaging manner, so that the integration level of the chips is further improved, and the chips have higher processing performance. In addition, by arranging at least two multipath connection units, a plurality of access paths can be provided for the functional units corresponding to the multipath connection units, the condition that the functional units cannot be accessed due to the fact that the access paths are failed once only one access path exists is avoided, and the probability of damage of the multipath functional chips is reduced. In addition, the yield of the multi-path functional chip can be improved through the design of multiple interconnection channels.
Optionally, with continued reference to fig. 2, the multi-path function chip includes a system bus 20, and each connection unit 101 is communicatively connected to the system bus 20.
Specifically, the system bus 20 may include, for example, an address bus, a data bus, and a control bus for transmitting address information, data information, and control information, respectively; the system bus 20 can access any one of the connection units, thereby controlling the functional unit corresponding to the connection unit; in addition, the connection units can communicate with each other through a system bus; the multi-path connection units can also directly communicate with each other without a communication bus, that is, the system bus can directly access the multi-path connection unit with a certain address and further access the corresponding functional unit, and can also access the multi-path connection unit with the certain address and further access the functional unit corresponding to the certain address through the multi-path connection units with other addresses.
Optionally, fig. 3 is a schematic structural diagram of another functional chip according to an embodiment of the present invention, and referring to fig. 3, in the multi-path functional chip, each of the N link units is a multi-path link unit 1011, and each of the multi-path link units 1011 is in communication connection with at least one other multi-path link unit.
Specifically, in this embodiment, the multipath functional chip does not need to additionally provide a system bus, but is connected to each other through the multipath connection units 1011, so as to access each connection unit; each multipath connecting unit 1011 is in direct communication with at least one other multipath connecting unit, thereby enabling each functional unit to be accessed via multiple access paths, and further reducing the probability of functional chip damage.
Optionally, with reference to fig. 3, in the multi-path functional chip, the N functional units are arranged in an array in the first direction X and the second direction Y, gaps between the N functional units 102 form a grid structure, the multi-path connecting unit 1011 is located at a node position of the grid structure adjacent to the corresponding functional unit 102, and the N multi-path connecting units 1011 are arranged in an array; any one of the multipath connecting units 1011 is communicatively connected to the multipath connecting unit 1011 adjacent to the multipath connecting unit 1011 in the first direction and the multipath connecting unit 1011 adjacent to the multipath connecting unit 1011 in the second direction Y.
Specifically, in the present embodiment, each multipath connecting unit 1011 is communicatively connected to other multipath connecting units 1011 adjacent to the multipath connecting unit 1011, in other words, each multipath connecting unit 1011 can be accessed by at least two other multipath connecting units 1011; by configuring the N multipath connecting units 1011 to be in a grid structure, the number of paths accessed by each multipath connecting unit 1011 will be greatly increased, for example, two adjacent multipath connecting units 1011 can communicate through other multipath connecting units in addition to direct communication, and as long as any access path between two multipath connecting units 1011 is normal, the two multipath connecting units 1011 can communicate. In addition, in the present embodiment, all the multipath connecting units 1011 are configured outside the corresponding functional units 102, and all the multipath connecting units 1011 can be configured to have the same structure, so that the difficulty in manufacturing the multipath connecting units 1011 in the multipath functional chip can be greatly reduced; although the function of the functional units in the multi-path functional chip is the same, the functional units 102 may be of different types, for example, when all the functional units are memory units, the types of the memory units are also different, in this embodiment, because the corresponding multi-path connecting units 1011 are all disposed outside the functional units 102, and the structures of the multi-path connecting units 1011 are also the same, the types of the interfaces that can be disposed on the different functional units 102 are also the same, and thus the difficulty in manufacturing the functional units 102 in the multi-path functional chip can be reduced.
It should be noted that, in this embodiment, N functional units in the computing chip may be combined according to actual needs, for example, at least two functional units may be equivalent to a larger-scale "equivalent functional unit", so as to support larger-scale computing requirements.
Alternatively, at least one of the connection units other than the multipath connection unit is integrated inside the functional unit.
Specifically, the multi-path link unit needs to access other multi-path link units besides the corresponding functional units, so that the multi-path link unit can be configured outside the corresponding functional units, thereby facilitating communication connection with other multi-path link units; the connecting units except the multipath connecting unit can be integrated in the corresponding functional units only by accessing the corresponding functional units, so that the integration level of the three-dimensional chip can be further improved.
Exemplarily, in the computing chip, the computing unit is any one of a central processing unit CPU, a processor distributed processing unit DPU, or an AI acceleration core; in the same computing chip, different computing units may be of the same type, such as Central Processing Units (CPUs), or of different types, such as a portion of a CPU and the other portion of a DPU.
In the memory chip, the memory cell is any one of a Static Random Access Memory (SRAM), a Dynamic Random Access Memory (DRAM) and a nonvolatile Magnetic Random Access Memory (MRAM); in the same memory chip, different memory cells may be of the same type, such as static random access memory SRAM, or of different types, such as static random access memory SRAM for a portion, and dynamic random access memory DRAM for the other portion.
It should be noted that, in this embodiment, N functional units in the memory chip may be combined according to actual needs (such as a calculation scale), for example, at least two functional units may be equivalent to a larger-scale "equivalent functional unit", so as to support a larger-scale calculation requirement. Optionally, fig. 4 is a schematic structural diagram of another three-dimensional chip according to an embodiment of the present invention, and referring to fig. 4, the connection unit includes a bonding bump 1013, and the corresponding connection unit 101 in the adjacent functional chip 1 is bonded through the bonding bump 1013.
Specifically, the bonding bump 1013 may be composed of, for example, a metal material, which may be, for example, a single layer of metal, such as metallic copper; the bonding bump 1013 may also be a combination of at least two of titanium, copper, nickel, gold, tin, and silver. In other embodiments, the corresponding connection units in the adjacent functional chips 1 can also be connected by direct bonding.
The inter-chip connection of the connection unit may be a Bump (Bump) or a micro-Bump (uBump), so that a plurality of chips can be connected.
Optionally, fig. 5 is a schematic structural diagram of another three-dimensional chip according to an embodiment of the present invention, in this embodiment, the connection unit includes a bonding bump 1013 and a through-silicon via TSV 1014, and the bonding bump 1013 and the through-silicon via 1014 are located on two opposite sides of the connection unit; in the adjacent functional chip 1, the bonding bump 1013 of one of the corresponding two connection units is connected to the through-silicon via 1014 of the other.
Specifically, the bonding bump 1013 may be disposed on the surface of the functional chip 1, when a plurality of functional chips need to be stacked, one side (set as a first side) of the functional chip 1 where the bonding bump 1013 is disposed needs to be connected with one functional chip, and the opposite side (set as a second side) needs to be connected with another functional chip, and the connection unit may be electrically connected with the functional chip disposed on the second side of the functional chip through the design of the through-silicon via 1014; that is, by providing the through-silicon via 1014 and the bonding bump 1013 in the connection unit, any plurality of functional chips can be stacked.
Optionally, fig. 6 is a schematic structural diagram of another three-dimensional chip according to an embodiment of the present invention, and referring to fig. 6, the three-dimensional chip further includes a substrate 2, and the substrate 2 and an outermost functional chip 1 are packaged by flip-chip bonding.
Specifically, after the functional chips 1 are stacked, the solder bumps 21 may be formed by using a flip-chip bonding method (C4 method for short), so as to package the functional chips. It should be noted that solder balls 22 may also be formed on the substrate 2, and the solder balls 22 may be used as pins of a three-dimensional chip, so that the three-dimensional chip can be connected with other electronic circuits.
In summary, the length and the width of the three-dimensional chip provided by the embodiment of the invention are not increased compared with those of the traditional chip, so that the calculation capacity of the final three-dimensional chip is improved and the integration level is increased compared with that of the traditional chip.
It is to be noted that the foregoing is only illustrative of the preferred embodiments of the present invention and the technical principles employed. It will be understood by those skilled in the art that the present invention is not limited to the particular embodiments described herein, but is capable of various obvious changes, rearrangements and substitutions as will now become apparent to those skilled in the art without departing from the scope of the invention. Therefore, although the present invention has been described in greater detail by the above embodiments, the present invention is not limited to the above embodiments, and may include other equivalent embodiments without departing from the spirit of the present invention, and the scope of the present invention is determined by the scope of the appended claims.

Claims (10)

1. A three-dimensional chip, comprising:
at least two functional chips stacked in sequence; each functional chip comprises N functional units and N connecting units which are in one-to-one correspondence with the N functional units, wherein the connecting units are used for accessing the corresponding functional units;
the at least two functional chips comprise at least one multipath functional chip; in the multi-path functional chip, the N link units include at least two multi-path link units, and the multi-path link units are configured to be in communication connection with at least one other multi-path link unit;
in two adjacent functional chips, the connecting unit in one functional chip is correspondingly and electrically connected with the connecting unit in the other functional chip; wherein N is more than or equal to 2.
2. The three-dimensional chip according to claim 1,
the multi-path function chip comprises a system bus, and each connecting unit is in communication connection with the system bus.
3. The three-dimensional chip according to claim 1, wherein in the multi-path functional chip, the N link elements are all multi-path link elements, and each of the multi-path link elements is communicatively connected to at least one other multi-path link element.
4. The three-dimensional chip according to claim 3,
in the multi-path functional chip, the N functional units are arranged in an array in a first direction and a second direction, gaps among the N functional units form a grid structure, the multi-path connecting unit is located at a node position of the grid structure adjacent to the corresponding functional unit, and the N multi-path connecting units are arranged in an array; any one of the multipath connecting units is in communication connection with the multipath connecting unit adjacent to the multipath connecting unit along the first direction and the multipath connecting unit adjacent to the multipath connecting unit along the second direction.
5. The three-dimensional chip according to claim 1, wherein at least one of the connection units other than the multipath connection unit is integrated inside the corresponding functional unit.
6. The three-dimensional chip according to claim 1, wherein the at least two functional chips comprise a computing chip and a memory chip; the functional unit in the computing chip is a computing unit, and the functional unit in the storage chip is a storage unit.
7. The three-dimensional chip of claim 6, wherein the computing unit is any one of a Central Processing Unit (CPU), a processor Distributed Processing Unit (DPU), or an AI acceleration core;
the memory cell is any one of a Static Random Access Memory (SRAM), a Dynamic Random Access Memory (DRAM) and a nonvolatile Magnetic Random Access Memory (MRAM).
8. The three-dimensional chip according to claim 1, wherein the connection units comprise bonding bumps, and corresponding connection units in adjacent functional chips are bonded by the bonding bumps.
9. The three-dimensional chip of claim 1, wherein the connection unit comprises a bonding bump and a Through Silicon Via (TSV), the bonding bump and the TSV being located on opposite sides of the connection unit;
in the adjacent functional chips, the bonding convex point of one of the two corresponding connecting units is connected with the silicon through hole of the other connecting unit.
10. The three-dimensional chip according to claim 1, further comprising a substrate, wherein the substrate and the outermost one of the functional chips are packaged by flip-chip bonding.
CN202210101030.6A 2022-01-27 2022-01-27 Three-dimensional chip Pending CN114497033A (en)

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