TW202245083A - 基於雷射的重新分佈和多層堆疊之封裝 - Google Patents
基於雷射的重新分佈和多層堆疊之封裝 Download PDFInfo
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Abstract
本發明提供一種半導體裝置,其具有第一封裝層。第一屏蔽層形成於該第一封裝層上方。該第一屏蔽層經圖案化以形成重新分佈層。電組件安置於該重新分佈層上方。囊封體沈積於該電組件上方。第二屏蔽層形成於該囊封體上方。該第二屏蔽層經圖案化。該第一屏蔽層及該第二屏蔽層之該圖案化可藉由雷射進行。該第二屏蔽層可經圖案化以形成天線。
Description
本發明一般關於一種半導體製造,且更特定言之,關於一種用於使用基於雷射的重新分佈和多層堆疊之封裝來形成電磁干擾(electromagnetic interference;EMI)屏蔽封裝之半導體裝置及方法。
半導體裝置通常可見於現代電子產品中。半導體裝置執行廣泛範圍之功能,諸如信號處理、高速計算、傳輸及接收電磁信號、控制電子裝置、將日光變換成電以及產生電視顯示器之視覺影像。半導體裝置可見於娛樂、通信、電力轉換、網路、電腦及消費產品領域。半導體裝置亦可見於軍事應用、航空、汽車、工業控制器及辦公設備。
半導體裝置常常易受電磁干擾(EMI)、射頻干擾(RFI)、諧波失真或可干擾其操作之其他裝置間干擾(諸如電容式、電感式或電導式耦接,亦稱為串擾)影響。高速類比電路,例如射頻(radio frequency;RF)濾波器,或數位電路亦產生干擾。
導電層通常形成於半導體封裝上方以屏蔽封裝內之電子部件免受EMI及其他干擾。屏蔽層在信號可擊中半導體晶粒並離散封裝內之組件之前吸收EMI,此可另外引起裝置之故障。屏蔽層亦形成於具有預期產生EMI以保護附近裝置之組件的封裝上方。
半導體封裝屏蔽之先前技術方法的一個問題為在封裝上方形成屏蔽層之方法可使得難以形成多層封裝。然而,由於電子裝置變得較小且執行更多功能,裝置必須在有限區域中容納更高密度之組件。在封裝中堆疊多層為用於增大組件密度之一選項,但在涉及EMI屏蔽時變得困難。因此,需要具有EMI屏蔽及多層堆疊層之組件的半導體裝置及製造半導體裝置之方法。
本發明的一態樣為一種製造半導體裝置之方法,其包含:提供第一封裝層;在該第一封裝層上方形成第一屏蔽層;使該第一屏蔽層圖案化以形成重新分佈層;將電組件安置於該重新分佈層上方;將囊封體沈積於該電組件上方;在該囊封體上方形成第二屏蔽層;以及使該第二屏蔽層圖案化。
本發明的所述態樣之方法進一步包括使用雷射使該第一屏蔽層及該第二屏蔽層圖案化。
本發明的所述態樣之方法進一步包括使該第二屏蔽層圖案化以包括天線。
本發明的所述態樣之方法進一步包括形成穿過該囊封體之導電通孔,其中該電組件藉由該導電通孔耦接至該第二屏蔽層。
本發明的所述態樣之方法進一步包括:在該囊封體中形成經圖案化空腔;及使該第二屏蔽層圖案化以匹配該經圖案化空腔。
本發明的所述態樣之方法進一步包括:使該第二屏蔽層圖案化以包括接觸墊;及將板對板連接器安置於該接觸墊上方。
本發明的另一態樣為一種製造半導體裝置之方法,其包含:提供第一封裝層;在該第一封裝層上方形成第一重新分佈層;將第一囊封體沈積於該第一重新分佈層上方;在該第一囊封體上方形成第一屏蔽層;以及使該第一屏蔽層圖案化。
本發明的所述另一態樣之方法進一步包括藉由噴墨或電流體動力噴射列印形成該第一重新分佈層。
本發明的所述另一態樣之方法進一步包括:將第二囊封體沈積於該第一重新分佈層上方;在該第二囊封體上方形成第二重新分佈層;以及將該第一囊封體沈積於該第二囊封體上方。
本發明的所述另一態樣之方法進一步包括使該第一屏蔽層圖案化以形成天線。
本發明的又一態樣為一種半導體裝置,其包含:第一封裝層;重新分佈層,其形成於該第一封裝層上方;第二封裝層,其形成於該重新分佈層上方;以及天線,其形成於該第二封裝層上方。
在本發明的所述又一態樣之半導體裝置中,該重新分佈層形成為嵌入於該第一封裝層中。
在本發明的所述又一態樣之半導體裝置中,該天線形成為嵌入於該第二封裝層中。
本發明的所述又一態樣之半導體裝置進一步包括穿過該第一封裝層形成以將該第一封裝層耦接至該重新分佈層之導電通孔。
本發明的所述又一態樣之半導體裝置進一步包括:第一屏蔽層,其圍繞該第一封裝層而形成;及第二屏蔽層,其圍繞該第一屏蔽層及該第一封裝層而形成。
於以下描述中參考圖式於一或多個具體實例中描述本發明,在圖式中,相似編號表示相同或類似元件。儘管本發明係依據用於達成本發明目標之最佳模式來描述,所屬領域中具通常知識者將瞭解,其意欲涵蓋如可包括如由所附申請專利範圍及如由以下揭示內容及附圖支援之其等效物所界定的本發明之精神及範圍內的替代方案、修改及等效物。如本文中所使用之術語「半導體晶粒」係指詞之單數形式及複數形式兩者,並且因此,可指單個半導體裝置及多個半導體裝置兩者。術語「晶粒」與「半導體晶粒」可互換地使用。
通常使用兩種複雜製程來製造半導體裝置:前端製造及後端製造。前端製造包括在半導體晶圓之表面上形成複數個晶粒。晶圓上之每一晶粒含有主動及被動電組件,該等電組件電連接以形成功能性電路。諸如電晶體及二極體之主動電組件具有控制電流之流動的能力。諸如電容器、電感器及電阻器之被動電組件在執行電路功能所需的電壓與電流之間建立了關係。
後端製造係指將成品晶圓切割或單粒化成個別半導體晶粒且封裝半導體晶粒以用於結構支撐、電互連及環境隔離。為了使半導體晶粒單粒化,沿著稱為鋸切道或劃線之晶圓之非功能性區刻劃及打破晶圓。使用雷射切割工具或鋸片使晶圓單粒化。在單粒化之後,將個別半導體晶粒安裝至封裝基板,該封裝基板包括接腳或接觸墊以用於與其他系統組件互連。接著將形成於半導體晶粒上方之接觸墊連接至封裝內之接觸墊。可與導電層、凸塊、柱形凸塊、導電膏、接合線或其他適合的互連結構進行電連接。囊封體或其他模製化合物沈積於封裝上方以提供實體支撐及電隔離。成品封裝接著***至電系統中,並且使得半導體裝置之功能性可用於其他系統組件。
圖1a展示具有基底基板材料102之半導體晶圓100,該基底基板材料諸如矽、鍺、磷化鋁、砷化鋁、砷化鎵、氮化鎵、磷化銦、碳化矽或其他塊狀半導體材料。複數個半導體晶粒或組件104形成於由如上文所描述之非主動晶粒間晶圓區域或鋸切道106分隔開之晶圓100上。鋸切道106提供切割區域以將半導體晶圓100單粒化成個別半導體晶粒104。在一個具體實例中,半導體晶圓100具有100公釐至450公釐(mm)之寬度或直徑。
圖1b展示半導體晶圓100之一部分的橫截面視圖。每一半導體晶粒104具有後部或非主動表面108及主動表面110,該後部或非主動表面及該主動表面含有實施為主動裝置、被動裝置、導電層及介電層之類比或數位電路,該等主動裝置、被動裝置、導電層及介電層形成於晶粒內或上方且根據晶粒之電氣設計及功能而電互連。舉例而言,電路可包括形成於主動表面110內之一或多個電晶體、二極體及其他電路元件以實施類比電路或數位電路,諸如數位信號處理器(digital signal processor;DSP)、ASIC、MEMS、記憶體或其他信號處理電路。半導體晶粒104亦可含有諸如電感器、電容器及電阻器等積體被動裝置(integrated passive device;IPD)以用於RF信號處理。半導體晶圓100之後表面108可藉由機械研磨或蝕刻製程進行視情況選用之背磨操作以移除基底材料102之一部分且減小半導體晶圓100及半導體晶粒104之厚度。
導電層112使用PVD、CVD、電解電鍍、無電極電鍍製程或其他適合之金屬沈積製程形成於主動表面110上方。導電層112包括鋁(Al)、銅(Cu)、錫(Sn)、鎳(Ni)、金(Au)、銀(Ag)或其他適合之導電材料之一或多個層。導電層112作為電連接至主動表面110上之電路的接觸墊操作。
導電層112可形成為與半導體晶粒104之邊緣相距第一距離並列安置之接觸墊,如圖1b中所展示。替代地,導電層112可形成為接觸墊,該等接觸墊在多個列中偏移以使得第一列接觸墊安置成距晶粒之邊緣第一距離,且第二列接觸墊與安置成距晶粒之邊緣第二距離的第一列交替。導電層112表示形成於具有用於後續電互連至較大系統之接觸墊的半導體晶粒104上方之最後導電層。然而,可存在形成於主動表面110上之實際半導體裝置與接觸墊112之間的一或多個中間導電層及絕緣層以用於信號路由。
使用蒸發、電解電鍍、無電極電鍍、落球或網版列印製程將導電凸塊材料沈積於導電層112上方。凸塊材料可為Al、Sn、Ni、Au、Ag、鉛(Pb)、鉍(Bi)、Cu、焊料及其組合,其具有視情況選用之焊劑溶液。舉例而言,凸塊材料可為共晶Sn/Pb、高鉛焊料或不含鉛焊料。凸塊材料使用合適附接或接合製程接合至導電層112。在一個具體實例中,凸塊材料藉由將材料加熱超過其熔點而回焊以形成導電球或凸塊114。導電凸塊114視情況形成於具有潤濕層、障壁層及黏著層之凸塊下金屬化物(under-bump metallization;UBM)上方。導電凸塊114亦可壓縮接合或熱壓接合至導電層112。導電凸塊114表示可形成於導電層112上方以用於電連接至基板之一種類型的互連結構。互連結構亦可使用接合線、導電膏、柱形凸塊、微型凸塊或其他電互連件。
在圖1c中,半導體晶圓100使用鋸片或雷射切割工具118藉由鋸切道106單粒化成個別半導體晶粒104。可檢查及電測試個別半導體晶粒104以用於已知良好晶粒(known-good die;KGD)後單粒化之識別。
圖2a說明形成有半導體晶粒104之例示性半導體封裝200的橫截面視圖。圖2a展示中間形成步驟中之半導體封裝200,在該步驟中,封裝之第一層210已完成。基板212包括與一或多個導電層216交錯之一或多個絕緣層214。在一個具體實例中,絕緣層214為芯絕緣板,其中導電層216在例如覆銅壓合基板之頂表面及底表面上方圖案化。導電層216亦包括藉由絕緣層214電耦接以用於垂直互連之導電通孔。
基板212可包括在彼此上方交錯之任何數目個導電層216及絕緣層214。焊料遮罩或鈍化層可形成於基板212之任一側面或兩個側面上方。開口形成於鈍化層中以暴露用於後續互連之導電層216的接觸墊。在其他具體實例中,任何合適類型之基板或引線框係用於基板212。通常,第一層210在基板212上形成為大到足以一次性形成若干至數百或數千個封裝的面板或條帶。一旦完成,第一層210可自條帶單粒化,或者,封裝200在完成所有所要層之後單粒化為個別封裝。
第一層210之功能所需的任何組件安裝在基板212上或安置在該基板上方,且使用焊料、焊錫膏、接合線或另一合適的機構電連接至導電層216。圖2a說明安裝在基板212上之半導體晶粒104以及離散電組件224。離散電組件224可為諸如電容器、電阻器或電感器之被動組件,諸如二極體或電晶體之主動組件,或任何其他所要電組件。多個半導體晶粒可安置於基板212上。半導體晶粒104可作為較小子封裝之部分而非裸晶粒來提供。任何所要電組件可安裝在基板212上,諸如被動裝置、半導體晶粒、晶圓級晶片尺寸封裝(WLCSP)或封裝內系統(SiP)模組。除作為形成半導體封裝200之部分提供的屏蔽之外,所安裝組件亦可具有形成於個別組件上方之EMI屏蔽層。
藉由使用例如取置製程或取置機將半導體晶粒安置在基板上且接著對凸塊114進行回焊以將凸塊物理地且電連接至導電層216之暴露的接觸墊而將半導體晶粒104安裝至基板212。離散組件224藉由類似焊料凸塊或焊錫膏226來連接。在將離散組件取置至基板上之前,焊錫膏226可經列印至基板212或離散組件224上。對焊錫膏226進行回焊將離散組件224物理地且電耦接至導電層216之接觸墊。
在將半導體晶粒104、離散組件224及任何其他所要電組件安裝至基板212上之後,該等組件藉由囊封體或模製化合物228囊封。使用膏體列印、壓縮模製、轉移模製、液體囊封體模製、真空層壓、旋塗或另一合適的施用器將囊封體228沈積於基板212、半導體晶粒104及離散組件224上方。囊封體228可為聚合物複合材料,諸如環氧樹脂、環氧丙烯酸酯或具有或不具有填充劑之聚合物。囊封體228不導電、提供結構支撐且在環境上保護半導體裝置免受外部元件及污染物影響。
開口穿過囊封體228形成以暴露導電層216之接觸墊。使用任何合適的金屬沈積技術用導電材料填充開口以形成導電通孔230。導電通孔230之開口可藉由機械鑽孔、化學蝕刻、雷射鑽孔或任何其他合適的製程形成。導電材料可為Al、Cu、Sn、Ni、Au、Ag或其他合適導電材料。導電通孔230提供第一層210與隨後形成的半導體封裝200之層之間的垂直互連。在其他具體實例中,在沈積囊封體228之前,導電通孔230在基板212上形成為導電柱、焊料凸塊、覆銅焊料凸塊(CCSB)、PCB單元、模組化互連單元或任何其他合適的互連結構。當在沈積囊封體228之前形成導電通孔230時,囊封體在必要時經歷背磨製程以暴露導電通孔。
基板212及囊封體228與封閉組件之組合為連接在一起之多個裝置之面板,圖2a僅展示其單一者。在運用囊封體228囊封後,視情況使用鋸片、雷射切割工具、水切割工具或其他合適器具將面板單粒化成個別裝置,這針對每一個別單元暴露囊封體及基板212之側表面。該等單元保持在適當位置以供進一步處理或可移動至另一載體以允許單元之間的額外間距。在其他具體實例中,在完成全部或一部分所要層之前不發生單粒化。在底層保持為單元條帶或面板形式而非個別單元時,形成後續層將使後續層對於一些製造製程而言更容易。在一個具體實例中,封裝200保存為未單粒化面板直至最終層完全形成之後但在形成最終屏蔽層之前,使得最終屏蔽層為所有層之側表面提供屏蔽。
導電材料濺鍍於第一層210上方以形成屏蔽層246。使用任何合適的金屬沈積技術,例如化學氣相沈積、物理氣相沈積、其他濺鍍方法、噴塗或鍍覆來形成屏蔽層246。濺鍍材料可為銅、鋼、鋁、金、其組合或任何其他合適材料。屏蔽層246完全覆蓋囊封體228、基板212以及導電通孔230之暴露表面。
詳言之,囊封體228之所有四個側表面及頂表面均由屏蔽層246覆蓋,以圍繞經囊封組件。基板212之所有側表面由屏蔽層246覆蓋。典型地不在基板212之底表面上形成屏蔽層246,此係因為濺鍍製程自上方沈積金屬微粒。歸因於囊封體228的存在,屏蔽層246並未形成於基板212之頂表面上。在其他具體實例中,基板212之頂表面部分自囊封體228暴露以允許屏蔽層246接觸頂表面。導電層216可在基板212之側面處暴露以經由基板將屏蔽層246連接至地面。
凸塊248係在製造製程中之任何階段形成於基板212之底表面上。凸塊248類似於半導體晶粒104上之凸塊114且與其以類似方式形成。雖然針對第一層210展示一個特定封裝類型,但第一層可以任何合適的封裝類型形成,諸如嵌入式晶圓級球狀柵格陣列(eWLB)或雙側SiP模組,其中基板212之兩側具有經囊封組件。
圖2b以完全由屏蔽層246覆蓋之透視圖展示第一層210。在屏蔽層246下的導電通孔230之位置係由虛線指示。僅示出四個導電通孔230,但典型地將按需要形成更多導電通孔以在層之間傳輸電力、接地、資料、位址、時脈及任何其他所要信號。
在圖2c中,藉由使用雷射252將屏蔽層246圖案化成複數個接觸墊256a、導電跡線256b及任何其他所要導電結構來開始形成第二層250。雷射252可為經二極體泵浦之固態(DPSS)雷射、準分子雷射、CO
2雷射、或釹(Nd)、鉺(Eb)或摻雜鐿(Yb)之釔鋁石榴石(YAG)雷射。雷射252可發射紫外、可見光或紅外光譜中之光。脈衝雷射圖案化可運用約微秒(μs)、奈秒(ns)或飛秒(fs)之脈衝來執行。在其他具體實例中使用任何其他合適類型之雷射及圖案化製程。可視需要使用任何合適的蝕刻方式。
雷射252選擇性地移除屏蔽層246。移除屏蔽層246之區域使囊封體228暴露。屏蔽層246未由雷射252移除之區域保持為接觸墊256a、導電跡線256b及任何其他所要導電結構。接觸墊256a按需要分佈以用於連接至下方通孔230,以用於半導體組件之後續安裝,且用於在額外層將形成之情況下後續互連至上覆層。舉例而言,接觸墊256a之陣列保持用於倒裝晶片或表面安裝積體電路之應用。保留一對接觸墊以用於安裝離散被動裝置。接觸墊256a保留在導電通孔230上以將第二層250連接至第一層210之下方組件。導電跡線256b視需要將接觸墊256a連接至彼此以實施封裝200之所要電功能。在一些具體實例中,保留屏蔽層246之部分以作為EMI屏蔽操作。雖然僅囊封體228之頂表面上之部分屏蔽層246經說明為經圖案化,但雷射252亦可用以在必要時使屏蔽層之側壁圖案化。
圖2d展示安裝至接觸墊256a上之半導體晶粒262、eWLB封裝264、WLCSP 266及離散電容器268。諸如藉由取置機器使用任何合適的製程將安裝組件安置在第一層210上方。在安裝組件262至268的接觸墊與接觸墊256a之間回焊的焊料凸塊或膏提供機械耦接及電耦接兩者。模具底部填充料可沈積於組件與第一層210之間。在使屏蔽層圖案化之後,任何所要電組件可作為第二層250之部分安裝至屏蔽層246上。組件可為任何離散被動或主動裝置、裸晶粒、WLCSP或單側或雙側模製SiP模組。除形成為封裝200之部分的屏蔽件之外,組件中之任一者視情況亦具有形成於個別組件上方或內之其自有屏蔽層。
在圖2e中,囊封體270沈積於安裝組件262至268上方以提供用於第二層250之封裝主體。囊封體270類似於囊封體228,亦即,以類似製程沈積且由類似材料形成。可使用模具來形成囊封體270以保持囊封體含於經單粒化第一層210單元之覆蓋面積上方。在另一具體實例中,囊封體270沈積於個別第一層210單元之間,且隨後被移除。囊封體270之預成型薄片可層壓於複數個第一層210單元上方以允許囊封體覆蓋多個單元而不會在屏蔽層246上方之單元之間向下流動。囊封體270之預成型薄片可預先部分固化以允許囊封體包封(envelop)安裝為第二層250之部分的裝置而無需完全為液體。在第一層210保持作為非單粒化面板或條帶之具體實例中,液態囊封體可經沈積而無與囊封體270在第一層之單元之間流動相關的問題。
導電通孔272以類似於上述導電通孔230之方式穿過囊封體270形成。導電通孔272可取決於封裝200之所要功能而直接形成於導電通孔230上方或其他位置處。導電通孔272係視情況選用的且可不在不存在超出第二層250之額外垂直路由之需要的具體實例中形成。替代使用導電通孔230及272,可藉由使屏蔽層之側壁圖案化來提供垂直路由。
圖2f展示形成於封裝200之第二層250上方的屏蔽層276。屏蔽層276以與屏蔽層246類似的方式形成且具有與其類似的材料。屏蔽層276接觸並完全覆蓋囊封體270之頂表面及全部側表面。屏蔽層276實體接觸導電通孔272之暴露頂表面,該導電通孔將屏蔽層276電連接至接觸墊256a、導電跡線256b以及安裝於其上作為第二層250的部分之組件。屏蔽層276亦形成於第一層210之側面上方,其中屏蔽層246仍保持暴露。因此,第一層210現包括屏蔽層246及屏蔽層276兩者完全包圍第一層之雙屏蔽層。
在圖2g中,屏蔽層276再次使用雷射252或另一合適製程經圖案化成任何所要導電結構。圖2g展示在囊封體270上方在屏蔽層276之外形成之貼片天線280之陣列。可形成任何類型之微條帶線或貼片天線。可使用任何合適的貼片形狀,諸如矩形、圓形、三角形、U形或E形。在一個具體實例中,封裝200為5G收發器,且屏蔽層276形成為適用於5G傳輸之天線。天線280藉由導電通孔272、導電跡線256b、導電通孔230及導電層216電耦接至第一層210及第二層250之下方組件。
圖2g展示完成的封裝200之透視圖,而圖2h展示橫截面視圖。封裝200包括兩個組件層,第一層210及第二層250。形成於第一層210上之屏蔽層246經圖案化以作為用於第二層250的重新分佈層操作。形成於第二層250上之屏蔽層276經圖案化以作為天線操作或用於任何其他所要目的。將經圖案化屏蔽層利用為重新分佈層或天線會減小封裝大小、允許較高密度封裝、改良裝置效能,且允許廣泛多種零件功能整合至單一封裝中。
在一些具體實例中,屏蔽層276如同屏蔽層246一般經圖案化成複數個接觸墊,使得板對板(board-to-board,B2B)連接器或其他組件可安裝至封裝200上。使用雷射252使屏蔽層246及276圖案化提供了電路設計靈活性,包括形成重新分佈層及天線圖案。屏蔽層246及276之任何部分可具有至地面之連接以具有EMI屏蔽效應。
每一封裝層可具有其各別屏蔽層圖案,該屏蔽層圖案形成於其各別囊封體之頂表面上方或雕刻至其中。圖3a至圖3c展示形成經壓印之屏蔽層,而圖4a至圖4d展示形成經雕刻之屏蔽層。圖3a展示囊封之後的第一層210。屏蔽層246應用於圖3b中之囊封體228的平坦表面上。在圖3c中,用雷射252使屏蔽層246圖案化。屏蔽層246之其餘部分246a至246d在囊封體228之頂表面上方的高度具有等於屏蔽層之厚度。圖3c中之部分246a至246d之厚度出於說明而放大。雖然僅示出四個正方形,但可出於任何所要目的形成任何合適圖案。
替代地,屏蔽層246圖案可嵌入或雕刻至囊封體228之頂表面中而非壓印在其上。圖4a同樣展示在囊封之後但在形成屏蔽層之前的第一層210。在圖4b中,將用於屏蔽層246之所要圖案首先蝕刻至囊封體228中。蝕刻可為任何合適的蝕刻製程,諸如化學蝕刻、雷射蝕刻或機械蝕刻。蝕刻在囊封體228之頂表面中形成對應於接觸墊、導電跡線及為屏蔽層246之最終圖案化形式所需之其他結構的空腔290。
在圖4c中,屏蔽層246形成於囊封體228及空腔290上方。在一個具體實例中,屏蔽層246形成為符合空腔290之形狀的保形塗層。在另一具體實例中,屏蔽層246完全填充空腔290。在圖4d中,自空腔290外部之囊封體228之其餘頂表面移除屏蔽層246。在一個具體實例中,藉由雷射252使用雷射圖案化來移除屏蔽層246。兩步製程可由第一陰影線且隨後剝離屏蔽層246使用。在其他具體實例中,可藉由機械地研磨第一層210之頂部來移除屏蔽層246之所要部分。屏蔽層246保持保形地塗佈於空腔290內之側表面及底表面上方。在一些具體實例中,屏蔽層246保持完全填充空腔290。本文所揭示之用於任何封裝層之屏蔽層中之任一者可藉由壓印或雕刻而進行其圖案化。
圖5a及圖5b展示其中重新分佈層藉由列印而非雷射蝕刻形成之製程。圖5a展示沈積有囊封體228但無屏蔽層246之第一層210。替代在整個封裝上方形成屏蔽層246且隨後使屏蔽層圖案化成所要電結構,重新分佈層僅列印於囊封體228之頂表面上。圖5b展示將導電材料沈積於囊封體228上方以列印所要電路圖案302之噴墨或電流體動力(EHD)噴嘴300。與雷射蝕刻相比,電路列印允許更精細線寬,同時仍能夠形成相同導電結構中之任一者。在一個具體實例中,使用雷射252完成導電通孔230之孔形成,且隨後藉由噴墨噴嘴300填充孔。任何封裝層可如圖5b中所示般形成,包括頂層。
圖6展示將額外層無限地堆疊至任何合適數目個層。雖然上述具體實例僅展示兩個層210及250,但額外層可繼續無限形成。屏蔽層276經圖案化以容納第三層之任何所要電組件,繼之以經囊封、屏蔽且接著使屏蔽層圖案化。圖案化、組件安裝、模製或部分模製及接著金屬沈積或EMI屏蔽之製程可無限地重複直至形成所要頂層310為止。頂層310可具有用於形成於其上之B2B連接器的天線或端子。
圖7a及圖7b說明將上述封裝,例如具有第一層210及第二層250之封裝200併入至電子裝置400中。圖7a示出安裝至印刷電路板(printed circuit board;PCB)或其他基板402上作為電子裝置400之部分之封裝200的部分橫截面。凸塊248形成於基板212之底部上的導電層216上。可在製造製程之任一階段,例如在對囊封體228進行模製之前、在單粒化之前或在形成屏蔽層276及使其圖案化之後形成導電凸塊248。凸塊248經回焊至PCB 402之導電層404上,以將封裝200物理地附接及電連接至PCB。在其他具體實例中,使用熱壓縮或其他適合的附接及連接方法。在一些具體實例中,在封裝200與PCB 402之間使用黏著劑或底部填充層。半導體晶粒104藉由基板212及凸塊248電耦接至導電層404。
圖7b示出電子裝置400,其具有安裝於PCB 402之表面上的複數個半導體封裝,包括封裝200。視應用而定,電子裝置400可具有一種類型之半導體封裝或多種類型之半導體封裝。電子裝置400可為使用半導體封裝以執行一或多個電功能之獨立系統。替代地,電子裝置400可為較大系統之子組件。舉例而言,電子裝置400可為平板電腦、行動電話、數位攝影機、通信系統或其他電子裝置之部分。電子裝置400亦可為圖形卡、網路介面卡或***至電腦中之另一信號處理卡。半導體封裝可包括微處理器、記憶體、ASIC、邏輯電路、類比電路、RF電路、離散主動或被動裝置及其他半導體晶粒或電組件。
在圖7b中,PCB 402提供通用基板以用於安裝於PCB上之半導體封裝的結構支撐及電互連。使用蒸發、電解電鍍、無電極電鍍、網版列印或其他合適金屬沈積製程於PCB 402之表面上方或層內形成導電信號跡線404。信號跡線404提供半導體封裝、安裝組件及其他外部系統或組件之間的電通信。跡線404亦視需要將電力及接地連接提供至半導體封裝。
在一些具體實例中,半導體裝置具有兩個封裝層級。第一層級封裝為用於將半導體晶粒機械且電附接至中間基板之技術。第二層級封裝涉及將中間基板機械且電附接至PCB 402。在其他具體實例中,半導體裝置可僅具有第一層級封裝,其中晶粒直接機械且電安裝至PCB 402。
出於說明之目的,包括接合線封裝406及倒裝晶片408之若干類型之第一層級封裝展示於PCB 402上。另外,若干類型的第二層級封裝,包括球狀柵格陣列(ball grid array;BGA)410、凸塊晶片載體(bump chip carrier;BCC)412、平台柵格陣列(land grid array;LGA)416、多晶片模組(multi-chip module;MCM)418、四邊扁平無引線封裝(quad flat non-leaded;QFN)420、四邊扁平封裝422及eWLB 424經展示為連同封裝200一起安裝在PCB 402上。導電跡線404將安置在PCB 402上之各種封裝及組件電耦接至封裝200,從而使封裝200內之組件可用於PCB上之其他組件。
視系統要求而定,經組態具有第一及第二層級封裝式樣以及其他電子組件之任何組合的半導體封裝之任何組合可連接至PCB 402。在一些具體實例中,電子裝置400包括單個附接之半導體封裝,而其他具體實例需要多個互連之封裝。藉由在單個基板上方組合一或多個半導體封裝,製造商可將預製組件併入至電子裝置及系統中。因為半導體封裝包括複雜功能,因此可使用較不昂貴組件及流線化製造製程來製造電子裝置。所得裝置不大可能失效且製造較不昂貴,從而使消費者所需成本較低。
儘管已詳細說明本發明之一或多個具體實例,但熟習此項技術者將瞭解,可在不脫離如以下申請專利範圍表中所闡述之本發明的範圍的情況下對彼等具體實例作出修改及調適。
100:半導體晶圓
102:基底基板材料/基底材料
104:半導體晶粒或組件
106:非主動晶粒間晶圓區域或鋸切道
108:後部或非主動表面/後表面
110:主動表面
112:導電層
114:導電球或凸塊
118:鋸片或雷射切割工具
200:半導體封裝/封裝
210:第一層
212:基板
214:絕緣層
216:導電層
224:離散電組件/離散組件
226:焊料凸塊或焊錫膏
228:囊封體或模製化合物
230:導電通孔/下方通孔
246:屏蔽層
246a-246d:其餘部分
248:凸塊/導電凸塊
250:第二層
252:雷射
256a:接觸墊
256b:導電跡線
262:半導體晶粒
264:嵌入式晶圓級球狀柵格陣列封裝
266:晶圓級晶片尺寸封裝
268:離散電容器
270:囊封體
272:導電通孔
276:屏蔽層
280:貼片天線
290:空腔
300:噴墨或電流體動力噴嘴
302:電路圖案
310:頂層
400:電子裝置
402:基板/印刷電路板
404:導電信號跡線/信號跡線/導電跡線/導電層
406:接合線封裝
408:倒裝晶片
410:球狀柵格陣列
412:凸塊晶片載體
416:平台柵格陣列
418:多晶片模組
420:四方無引線封裝
422:四邊扁平封裝
424:嵌入式晶圓級球狀柵格陣列
[圖1a至圖1c]說明具有由鋸切道分隔開之複數個半導體晶粒的半導體晶圓;
[圖2a至圖2h]說明形成具有基於雷射之重新分佈及EMI屏蔽之雙層封裝;
[圖3a至圖3c]說明形成壓印於囊封體上方之EMI屏蔽層區域;
[圖4a至圖4d]說明形成雕刻至囊封體中之EMI屏蔽層區域;
[圖5a及圖5b]說明使用列印製程來形成經圖案化層;
[圖6]說明任何數目個層之連續形成;及
[圖7a及圖7b]說明將多層封裝整合至電子裝置中。
210:第一層
228:囊封體或模製化合物
230:導電通孔/下方通孔
246:屏蔽層
248:凸塊/導電凸塊
250:第二層
252:雷射
256a:接觸墊
256b:導電跡線
Claims (15)
- 一種製造半導體裝置之方法,其包含: 提供第一封裝層; 在該第一封裝層上方形成第一屏蔽層; 使該第一屏蔽層圖案化以形成重新分佈層; 將電組件安置於該重新分佈層上方; 將囊封體沈積於該電組件上方; 在該囊封體上方形成第二屏蔽層;以及 使該第二屏蔽層圖案化。
- 如請求項1之方法,其進一步包括使用雷射使該第一屏蔽層及該第二屏蔽層圖案化。
- 如請求項1之方法,其進一步包括使該第二屏蔽層圖案化以包括天線。
- 如請求項1之方法,其進一步包括形成穿過該囊封體之導電通孔,其中該電組件藉由該導電通孔耦接至該第二屏蔽層。
- 如請求項1之方法,其進一步包括: 在該囊封體中形成經圖案化空腔;及 使該第二屏蔽層圖案化以匹配該經圖案化空腔。
- 如請求項1之方法,其進一步包括: 使該第二屏蔽層圖案化以包括接觸墊;及 將板對板連接器安置於該接觸墊上方。
- 一種製造半導體裝置之方法,其包含: 提供第一封裝層; 在該第一封裝層上方形成第一重新分佈層; 將第一囊封體沈積於該第一重新分佈層上方; 在該第一囊封體上方形成第一屏蔽層;以及 使該第一屏蔽層圖案化。
- 如請求項7之方法,其進一步包括藉由噴墨或電流體動力噴射列印形成該第一重新分佈層。
- 如請求項7之方法,其進一步包括: 將第二囊封體沈積於該第一重新分佈層上方; 在該第二囊封體上方形成第二重新分佈層;以及 將該第一囊封體沈積於該第二囊封體上方。
- 如請求項7之方法,其進一步包括使該第一屏蔽層圖案化以形成天線。
- 一種半導體裝置,其包含: 第一封裝層; 重新分佈層,其形成於該第一封裝層上方; 第二封裝層,其形成於該重新分佈層上方;以及 天線,其形成於該第二封裝層上方。
- 如請求項11之半導體裝置,其中該重新分佈層形成為嵌入於該第一封裝層中。
- 如請求項11之半導體裝置,其中該天線形成為嵌入於該第二封裝層中。
- 如請求項11之半導體裝置,其進一步包括穿過該第一封裝層形成以將該第一封裝層耦接至該重新分佈層之導電通孔。
- 如請求項11之半導體裝置,其進一步包括: 第一屏蔽層,其圍繞該第一封裝層而形成;及 第二屏蔽層,其圍繞該第一屏蔽層及該第一封裝層而形成。
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