TW202235648A - Physical vapor deposition chamber, method for depositing film, and method for forming semiconductor structure - Google Patents

Abstract

A physical vapor deposition chamber includes a chamber, a wafer support, a cover ring, and a shield. The wafer support is disposed on a bottom of the chamber. The cover ring surrounds the wafer support and is electrically insulated from the wafer support. The shield surrounds a chamber wall of the physical vapor deposition chamber. The shield includes a first vertical portion, a second vertical portion, and a horizontal portion. The first vertical portion is substantially parallel to the chamber wall of the physical vapor deposition chamber, and the cover ring is disposed between the first vertical portion and the wafer support. The first vertical portion is separated from an outer side wall of the cover ring by about 2.3 mm to about 2.7 mm. The second vertical portion is disposed below the cover ring, and a top end of the second vertical portion is substantially in direct with contact with the cover ring. The horizontal portion is disposed below the cover ring and connects a first bottom end of the first vertical portion and a second end of the second vertical portion.

Description

物理氣相沉積裝置、沉積薄膜的方法和形成半導體結構的方法Physical vapor deposition apparatus, method of depositing thin film and method of forming semiconductor structure

本揭露是有關於一種物理氣相沉積裝置、沉積薄膜的方法以及形成半導體結構的方法。The present disclosure relates to a physical vapor deposition device, a method for depositing a thin film, and a method for forming a semiconductor structure.

物理氣相沉積(physical vapor deposition，PVD)係用於在基板上沉積材料薄膜之熟知製程且通常用於製造半導體器件。物理氣相沉積製程係在高真空下在接納基板(例如，晶圓)且含有待沉積於基板上之一固體源或材料板之腔室中實行。因此，固體源或材料板被稱為物理氣相沉積靶材。在物理氣相沉積製程中，物理氣相沉積靶材從固體物理性地轉化為氣體。靶材的氣體自物理氣相沉積靶材輸送至基板，其在此處作為一薄膜沉積於基板上。Physical vapor deposition (PVD) is a well-known process for depositing thin films of materials on substrates and is commonly used in the manufacture of semiconductor devices. The physical vapor deposition process is performed under high vacuum in a chamber that receives a substrate (eg, a wafer) and contains a solid source or sheet of material to be deposited on the substrate. Therefore, the solid source or slab of material is called a physical vapor deposition target. During the PVD process, the PVD target material is physically converted from a solid to a gas. The target gas is transported from the physical vapor deposition target to the substrate where it is deposited as a thin film on the substrate.

實現物理氣相沉積的許多方法，包含蒸鍍、電子束蒸鍍、電漿噴塗沉積及濺鍍。目前，濺鍍為實現物理氣相沉積之最常用方法。在濺鍍期間，在腔室中產生電漿且將其引導至物理氣相沉積靶材。由於與電漿之高能粒子(離子)碰撞，電漿物理性地使原子或分子自物理氣相沉積靶材之反應表面位移或侵蝕(濺鍍)至靶材的氣體中。靶材之經濺鍍原子或分子的氣體透過一減壓區輸送至基板且沉積於基板上，而形成含有靶材之薄膜。There are many methods of achieving physical vapor deposition, including evaporation, electron beam evaporation, plasma spray deposition, and sputtering. Currently, sputtering is the most common method for realizing physical vapor deposition. During sputtering, a plasma is generated in a chamber and directed to a physical vapor deposition target. As a result of collisions with energetic particles (ions) of the plasma, the plasma physically displaces or erodes (sputters) atoms or molecules from the reaction surface of the physical vapor deposition target into the gas of the target. The gas of the sputtered atoms or molecules of the target is delivered to the substrate through a decompression zone and deposited on the substrate to form a thin film containing the target.

本揭露之一態樣是提供一種物理氣相沉積裝置包含腔室、基座、蓋環以及屏障。基座設置於腔室內的底部。蓋環環繞基座並與基座電性絕緣。屏障環繞物理氣相沉積裝置的腔室壁。屏障包含第一垂直部分、第二垂直部分以及水平部分。第一垂直部分與物理氣相沉積裝置的腔室壁實質上平行，蓋環位於第一垂直部分與基座之間，其中第一垂直部分與蓋環的外側壁側壁間隔第一距離，第一距離介於2.3毫米至2.7毫米之間。第二垂直部分位於蓋環下方，其中第二垂直部分的頂端接觸蓋環。水平部分位於該蓋環下方並連接第一垂直部分的第一底端和第二垂直部分的第二底端。One aspect of the present disclosure is to provide a physical vapor deposition apparatus including a chamber, a susceptor, a cover ring, and a barrier. The base is arranged at the bottom of the chamber. The cover ring surrounds the base and is electrically insulated from the base. A barrier surrounds a chamber wall of the physical vapor deposition apparatus. The barrier includes a first vertical section, a second vertical section and a horizontal section. The first vertical portion is substantially parallel to the chamber wall of the physical vapor deposition device, and the cover ring is located between the first vertical portion and the base, wherein the first vertical portion is spaced from the outer side wall of the cover ring by a first distance, the first The distance is between 2.3mm and 2.7mm. The second vertical portion is located below the cover ring, wherein the top end of the second vertical portion contacts the cover ring. The horizontal portion is located below the cover ring and connects the first bottom end of the first vertical portion and the second bottom end of the second vertical portion.

本揭露之另一態樣是提供一種沉積薄膜的方法，包含以下操作。在物理氣相沉積裝置中接納一晶圓。藉由氣體通道引入製程氣體，且製程氣體由基座下方流經蓋環的凹口並通過屏障與蓋環之外側壁之間的一通道，而向上流入腔室。輸送能量至腔室中以使製程氣體形成電漿，其中所述能量是由射頻源和直流源提供。使電漿轟擊物理氣相沉積裝置內的靶材。沉積一薄膜至晶圓的表面上。Another aspect of the present disclosure provides a method for depositing a thin film, which includes the following operations. A wafer is received in a physical vapor deposition apparatus. The process gas is introduced through the gas channel, and the process gas flows from the bottom of the susceptor through the notch of the cover ring and through a channel between the barrier and the outer side wall of the cover ring, and flows upward into the chamber. Energy is delivered into the chamber to form a plasma of the process gas, wherein the energy is provided by an RF source and a DC source. A plasma is bombarded against a target in a physical vapor deposition apparatus. A thin film is deposited onto the surface of the wafer.

本揭露之又一態樣是提供一種形成半導體結構的方法，包含以下操作。沉積介電層於下層結構上。形成開口貫穿介電層。形成功函數層於開口中。在物理氣相沉積裝置中沉積第一鈷薄膜層於開口中，且第一鈷薄膜層位於功函數層上，其中沉積第一鈷薄膜層包含使一製程氣體流經屏障與蓋環間的空隙的一流量介於約400sccm至約450sccm之間。形成第二鈷薄膜層覆蓋第一鈷薄膜層及開口之側壁。形成第三鈷薄膜覆蓋第二鈷薄膜層。Another aspect of the present disclosure provides a method of forming a semiconductor structure, including the following operations. A dielectric layer is deposited on the underlying structure. An opening is formed through the dielectric layer. A work function layer is formed in the opening. Depositing a first cobalt thin film layer in the opening in a physical vapor deposition apparatus, and the first cobalt thin film layer is located on the work function layer, wherein depositing the first cobalt thin film layer includes flowing a process gas through a gap between the barrier and the cover ring A flow rate is between about 400 sccm and about 450 sccm. A second cobalt thin film layer is formed to cover the first cobalt thin film layer and the sidewall of the opening. A third cobalt thin film is formed to cover the second cobalt thin film layer.

為了使本揭示內容的敘述更加詳盡與完備，下文針對了本揭露的實施態樣與具體實施例提出了說明性的描述；但這並非實施或運用本揭露具體實施例的唯一形式。以下所揭露的各實施例，在有益的情形下可相互組合或取代，也可在一實施例中附加其他的實施例，而無須進一步的記載或說明。In order to make the description of the present disclosure more detailed and complete, the following provides illustrative descriptions of the implementations and specific embodiments of the present disclosure; but this is not the only way to implement or use the specific embodiments of the present disclosure. The various embodiments disclosed below can be combined or replaced with each other when beneficial, and other embodiments can also be added to one embodiment, without further description or illustration.

以下的揭露內容提供許多不同的實施例或範例以實施本揭露多個實施例的不同特徵。以下的內容敘述各個構件及其排列方式的特定範例，以簡化說明。當然，這些特定的範例並非用以限定。例如，在下文描述中，第一構件形成於第二構件上方或上可包含其中第一構件及第二構件經形成而直接接觸之實施例，且亦可包含其中額外構件可形成於第一構件與第二構件之間使得第一構件及第二構件可未直接接觸之實施例。另外，本揭露可在各項實例中重複元件符號及/或字母。此重複用於簡化及清楚之目的且本身並不指示所論述之各項實施例及/或組態之間之一關係。The following disclosure provides many different embodiments or examples to implement different features of various embodiments of the present disclosure. Specific examples of each component and its arrangement are described below to simplify the description. Of course, these specific examples are not intended to be limiting. For example, in the description below, a first feature is formed over or on a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed on the first feature An embodiment in which the first member and the second member are not in direct contact with the second member. In addition, the present disclosure may repeat element symbols and/or letters in various examples. This repetition is used for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and/or configurations discussed.

此外，為便於描述，本文中可使用空間相對術語(諸如「在…下面」、「在…下方」、「下」、「在…上方」、「上」、「在…上」及類似者)來描述一個元件或構件與另一(些)元件或構件之關係，如圖中繪示。除圖中描繪之定向以外，空間相對術語亦意欲涵蓋器件在使用或操作中之不同定向。裝置可以其他方式定向(旋轉100度或成其他定向)且因此可同樣解釋本文中所使用之空間相對描述詞。In addition, spatially relative terms (such as "under", "under", "under", "above", "on", "on" and the like) may be used herein for ease of description. To describe the relationship between one element or component and another element or component(s), as shown in the figure. Spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 100 degrees or at other orientations) and thus the spatially relative descriptors used herein should be interpreted similarly.

如本文中所使用，諸如「第一」、「第二」及「第三」之術語描述各種元件、組件、區、膜層及/或區段，但此等元件、組件、區、膜層及/或區段應不受此等術語限制。此等術語可僅用於區分一個元件、組件、區、膜層或區段與另一元件、組件、區、膜層或區段。除非上下文清楚指示，否則諸如「第一」、「第二」及「第三」之術語在本文中使用時並不暗示一序列或順序。As used herein, terms such as "first", "second" and "third" describe various elements, components, regions, layers and/or sections, but these elements, components, regions, layers and/or sections shall not be limited by these terms. These terms may be only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Terms such as "first," "second," and "third" when used herein do not imply a sequence or order unless clearly indicated by the context.

物理氣相沉積用於在基板(即，晶圓)上形成一薄膜之一適當且廣泛使用的製程。通常，執行物理氣相沉積操作之裝置包含腔室及製程套件。腔室可包含腔室壁及基座，且製程套件可放置於腔室內，用以避免腔室組件(諸如腔室壁及基座)上之非期望材料沉積。Physical vapor deposition is an appropriate and widely used process for forming a thin film on a substrate (ie, wafer). Typically, an apparatus for performing physical vapor deposition operations includes a chamber and a process kit. The chamber may include chamber walls and a pedestal, and a process kit may be placed within the chamber to avoid deposition of undesired materials on chamber components such as the chamber walls and pedestal.

通常，製程套件包含沉積環(deposition ring)、蓋環(cover ring)以及屏障(shield)，但不限於此。沉積環安置於基座上。蓋環設置以環繞沉積環和基座，且可至少部分覆蓋沉積環。晶圓可以被安置在基座上，且晶圓的邊緣可與沉積環至少一部分重疊。屏障在蓋環與腔室壁之間形成一封閉空間。於晶圓上形成一膜層(例如但不限於)之物理氣相沉積製程期間，可能發生電弧(electric arcing)的問題。電弧可能是由於電場過強，氣體發生電擊穿而持續形成電漿體，其中導致電場過強的原因為電荷累積超越臨界值。在此，須說明的是，臨界值會因靶材阻抗或製程套件間的距離而有所差異。舉例來說，相較於常見的金屬材料(例如，鈦(Ti)或鋁(Al))，鈷材料具有較大的電阻，在PVD製程期間，其電荷的累積也相對較大，進而容易發生電弧現象。一般而言，電弧通常發生於蓋環與屏障交界處。物理氣相沉積期間所產生的電弧可能引起晶圓上之含有靶材薄膜的局部發生較厚沉積或不期望的汙染物殘留。舉例來說，在晶圓邊緣上方會形成不期望的局部較厚的膜層。Typically, a process kit includes a deposition ring, a cover ring, and a shield, but is not limited thereto. The deposition ring is placed on the base. A cover ring is disposed to surround the deposition ring and the base, and may at least partially cover the deposition ring. A wafer may be positioned on the susceptor, and an edge of the wafer may overlap at least a portion of the deposition ring. The barrier forms a closed space between the cover ring and the chamber wall. The problem of electric arcing may occur during a physical vapor deposition process for forming a layer, such as but not limited to, on a wafer. The arc may be due to the electric field is too strong, the gas undergoes electrical breakdown and continues to form plasma, and the cause of the electric field is too strong because the charge accumulation exceeds the critical value. Here, it should be noted that the critical value may vary due to target impedance or distance between process kits. For example, compared with common metal materials (such as titanium (Ti) or aluminum (Al)), cobalt material has a higher electrical resistance, and its charge accumulation is relatively larger during the PVD process, which is prone to Arc phenomenon. Generally speaking, the arc usually occurs at the junction of the cover ring and the barrier. The arcing generated during physical vapor deposition may cause thicker deposits or undesired residues of contaminants on localized regions of the wafer containing the target film. For example, an undesirably thicker film layer may form locally over the edge of the wafer.

在一些對照實施例中，可額外執行清潔操作以在物理氣相沉積操作之前移除充當潛在電弧源之殘留物。這種方法可減輕電弧問題，但降低總生產量且增加製程成本。在其他對照實施例中，延長物理氣相沉積操作期間之排氣時間或提高物理氣相沉積操作期間的排氣溫度以減輕電弧問題，但降低物理氣相沉積操作生產量且增加能量消耗。在其他對照實施例中，降低放電功率以減少電荷累積，但此方法會降低物理氣相沉積的生產量。總而言之，儘管裝置設計者已試圖藉由進行上述修改來防止物理氣相沉積操作期間的電弧問題，然而，這些方法皆無法在不增加製程時間、能量消耗及成本或不降低總生產量的情況下有效地減少電弧。In some comparative embodiments, a cleaning operation may additionally be performed to remove residues that serve as potential sources of arcing prior to the physical vapor deposition operation. This approach alleviates the arcing problem, but reduces overall throughput and increases process cost. In other comparative examples, extending the exhaust time or increasing the exhaust temperature during the PVD operation alleviated the arcing problem, but decreased the PVD operation throughput and increased energy consumption. In other comparative examples, the discharge power was reduced to reduce charge accumulation, but this method would reduce the throughput of PVD. In summary, although device designers have attempted to prevent arcing problems during PVD operations by making the above modifications, none of these methods have been effective without increasing process time, energy consumption, and cost, or reducing overall throughput. Effectively reduce arcing.

因此，本揭露提供一種用於在不降低物理氣相沉積生產量、不增加製程成本或不增加能量消耗之情況下減輕電弧問題的物理氣相沉積裝置。在一些實施例中，藉由調整物理氣相沉積裝置中蓋環與屏障之間的距離，能夠變更電子密度分佈，進而調降電場強度以避免電弧產生。Accordingly, the present disclosure provides a physical vapor deposition apparatus for mitigating arcing problems without reducing physical vapor deposition throughput, increasing process cost, or increasing energy consumption. In some embodiments, by adjusting the distance between the cover ring and the barrier in the physical vapor deposition device, the electron density distribution can be changed, and then the electric field intensity can be lowered to avoid arc generation.

第1圖繪示根據本揭露某些實施例之物理氣相沉積裝置100的示意圖。應理解，儘管一裝置被繪示為具有特定於一物理氣相沉積製程之組件，但是所揭示裝置之態樣可應用於利用電漿之任何類型的處理操作。例如，所揭示之態樣可應用於一電漿輔助化學氣相沉積(PECVD)操作或電漿蝕刻操作。FIG. 1 shows a schematic diagram of a physical vapor deposition apparatus 100 according to some embodiments of the present disclosure. It should be understood that although an apparatus is shown with components specific to a physical vapor deposition process, aspects of the disclosed apparatus are applicable to any type of processing operation utilizing a plasma. For example, the disclosed aspects can be applied to a plasma assisted chemical vapor deposition (PECVD) operation or a plasma etching operation.

如第1圖所示，物理氣相沉積裝置100包含腔室壁102。在一些實施例中，腔室壁102可為真空密閉的不鏽鋼腔室主體，且形成一腔室104(或稱處理區)於腔室壁102內。物理氣相沉積裝置100還包含基座110、蓋環120以及屏障130。具體的說，基座110(亦可稱為晶圓載物台或基板支撐件)設置於腔室104內的底部。基座110用以支撐及容納一待處理加工物件，例如晶圓。在一些實施例中，基座110可包含一加熱器(圖未示)和/或一靜電吸盤(electrostatic chuck，ESC)(圖未示)。As shown in FIG. 1 , a physical vapor deposition apparatus 100 includes a chamber wall 102 . In some embodiments, the chamber wall 102 can be a vacuum-tight stainless steel chamber body, and a chamber 104 (or called a processing area) is formed in the chamber wall 102 . The physical vapor deposition apparatus 100 further includes a base 110 , a cover ring 120 and a barrier 130 . Specifically, the base 110 (also referred to as a wafer stage or a substrate support) is disposed at the bottom of the chamber 104 . The base 110 is used to support and accommodate an object to be processed, such as a wafer. In some embodiments, the susceptor 110 may include a heater (not shown) and/or an electrostatic chuck (ESC) (not shown).

如第1圖所示，蓋環120環繞基座110，並與基座110電性絕緣。在一些實施例中，蓋環120包含鋁、不鏽鋼或銅。在一些實施例中，當在加熱器與基座110之間施加一正氣壓使得熱可有效率地自加熱器傳導至晶圓時，蓋環120將晶圓保持在基座110上之適當位置。在一些實施例中，蓋環120包含一凹口122，其由蓋環120的下表面朝蓋環120的上表面凹陷。因此，蓋環120之另一功能為容許一製程氣流(例如氬氣)自基座110下方流通至腔室104中。在一實施例中，凹口122的底角124不為直角。在一些實施例中，凹口122的底角124可以是倒角(chamfering)。一般來說，倒角是使具有較銳利稜角或邊緣之物件的稜角變得和緩的工藝，常見的作法為將一個直角稜加工成一個約45度角的面。在其他替代實施例中，凹口122的底角124可藉由加工而形成具有其他角度(例如，約30度至約60度)的面。當凹口122的底角124經加工而形成倒角時，凹口122的底面會縮小。詳細的說，凹口122之鄰近開口部分具有第一寬度W1，遠離開口部分具有第二寬度W2，且第一寬度W1大於第二寬度W2。As shown in FIG. 1 , the cover ring 120 surrounds the base 110 and is electrically insulated from the base 110 . In some embodiments, cover ring 120 comprises aluminum, stainless steel, or copper. In some embodiments, the cover ring 120 holds the wafer in place on the susceptor 110 when a positive air pressure is applied between the heater and the susceptor 110 such that heat can be efficiently conducted from the heater to the wafer. . In some embodiments, the cover ring 120 includes a notch 122 that is recessed from the lower surface of the cover ring 120 toward the upper surface of the cover ring 120 . Therefore, another function of the cover ring 120 is to allow a process gas flow (eg, argon gas) to pass from under the susceptor 110 into the chamber 104 . In one embodiment, the bottom corner 124 of the notch 122 is not a right angle. In some embodiments, the bottom corners 124 of the recess 122 may be chamfered. Generally speaking, chamfering is a process of softening the corners of objects with sharp corners or edges. A common practice is to process a right-angled corner into a surface with an angle of about 45 degrees. In other alternative embodiments, the bottom corner 124 of the notch 122 can be machined to form a surface with other angles (eg, about 30 degrees to about 60 degrees). When the bottom corner 124 of the notch 122 is processed to form a chamfer, the bottom surface of the notch 122 will shrink. In detail, the portion adjacent to the opening of the notch 122 has a first width W1, and the portion away from the opening has a second width W2, and the first width W1 is greater than the second width W2.

在一些實施例中，物理氣相沉積裝置100還包含沉積環150位於基座110與蓋環之間120。在一些實施例中，如第1圖所示，沉積環150位於基座110上並環繞基座110的外圍。沉積環150可至少部分地被蓋環120覆蓋。在一些實施例中，沉積環150包含絕緣材料，例如氧化鋁(Al _XO _Y)或氮化鋁(Al _XN _Y)，但不限於此。沉積環150用以將基座110與蓋環120電性絕緣。 In some embodiments, the physical vapor deposition apparatus 100 further includes a deposition ring 150 located between the base 110 and the cover ring 120 . In some embodiments, as shown in FIG. 1 , the deposition ring 150 is located on the susceptor 110 and surrounds the periphery of the susceptor 110 . The deposition ring 150 may be at least partially covered by the cover ring 120 . In some embodiments, the deposition ring 150 includes an insulating material, such as aluminum oxide ( _AlXOY ) or aluminum _nitride ( _{AlXNY )} , but is not limited thereto. The deposition ring 150 is used to electrically insulate the base 110 from the cover ring 120 .

如第1圖所示，屏障130環繞物理氣相沉積裝置100的腔室壁102。具體的說，屏障130設置於蓋環120與腔室壁102之間以形成腔室104。屏障130有助於防止或最小化自靶材濺鍍出之顆粒沉積於腔室壁102的內表面上。在一些實施例中，屏障130包含鋁、不鏽鋼或銅。As shown in FIG. 1 , the barrier 130 surrounds the chamber wall 102 of the physical vapor deposition apparatus 100 . Specifically, barrier 130 is disposed between cover ring 120 and chamber wall 102 to form chamber 104 . The barrier 130 helps prevent or minimize deposition of particles sputtered from the target on the inner surface of the chamber wall 102 . In some embodiments, barrier 130 comprises aluminum, stainless steel, or copper.

如第1圖所示，屏障130可包含第一垂直部分132、第二垂直部分134、水平部分136以及附接部分138。更詳細的說，蓋環120位於第一垂直部分132與基座110之間。在一些實施例中，附接部分138安裝至腔室壁102的頂部。第一垂直部分132自附接部分138向下延伸，且與腔室壁102實質上平行。水平部分136連接第一垂直部分132的底端，並向內延伸。在一些實施例中，水平部分136與第一垂直部分132之間的夾角實質上呈現直角。第二垂直部分134連接水平部分136的一端並向上延伸。水平部分136的兩端各自連接第一垂直部分132的底端和第二垂直部分134的底端，且位於蓋環120下方。在一些實施例中，第二垂直部分134實質上與第一垂直部分132平行。在一些實施例中，第二垂直部分134小於第一垂直部分132。在一實施例中，屏障130的第一垂直部分132、第二垂直部分134、水平部分136以及附接部分138可以為一體成形。在另一實施例中，屏障130的第一垂直部分132、第二垂直部分134、水平部分136以及附接部分138可以經焊接後組裝而成。As shown in FIG. 1 , the barrier 130 may include a first vertical portion 132 , a second vertical portion 134 , a horizontal portion 136 , and an attachment portion 138 . In more detail, the cover ring 120 is located between the first vertical portion 132 and the base 110 . In some embodiments, the attachment portion 138 is mounted to the top of the chamber wall 102 . The first vertical portion 132 extends downward from the attachment portion 138 and is substantially parallel to the chamber wall 102 . The horizontal portion 136 is connected to the bottom end of the first vertical portion 132 and extends inward. In some embodiments, the angle between the horizontal portion 136 and the first vertical portion 132 is substantially a right angle. The second vertical portion 134 connects one end of the horizontal portion 136 and extends upward. Both ends of the horizontal portion 136 are respectively connected to the bottom end of the first vertical portion 132 and the bottom end of the second vertical portion 134 , and are located below the cover ring 120 . In some embodiments, the second vertical portion 134 is substantially parallel to the first vertical portion 132 . In some embodiments, the second vertical portion 134 is smaller than the first vertical portion 132 . In one embodiment, the first vertical portion 132, the second vertical portion 134, the horizontal portion 136, and the attachment portion 138 of the barrier 130 may be integrally formed. In another embodiment, the first vertical portion 132 , the second vertical portion 134 , the horizontal portion 136 and the attachment portion 138 of the barrier 130 may be assembled after welding.

第2A圖繪示根據本揭露某些實施例之屏障130與蓋環120的立體示意圖。第2B圖繪示第2A圖沿剖線A-A’的剖面示意圖。第2C圖繪示第2B圖區域R的局部放大圖。可同時參閱第1圖、第2A圖、第2B圖及第2C圖。應注意，第一垂直部分132與蓋環120的外側壁間隔第一距離D1，且第一距離D1介於約2.3毫米至約2.7毫米之間。在一些實施例中，第一距離D1可以為介於約2.4毫米至約2.6毫米之間、介於約2.4毫米至約2.5毫米之間或介於約2.5毫米至約2.6毫米之間。FIG. 2A shows a schematic perspective view of the barrier 130 and the cover ring 120 according to some embodiments of the present disclosure. Fig. 2B shows a schematic cross-sectional view of Fig. 2A along the section line A-A'. FIG. 2C shows a partially enlarged view of the region R in FIG. 2B. You can refer to Figure 1, Figure 2A, Figure 2B and Figure 2C at the same time. It should be noted that the first vertical portion 132 is separated from the outer sidewall of the cover ring 120 by a first distance D1, and the first distance D1 is between about 2.3 mm and about 2.7 mm. In some embodiments, the first distance D1 may be between about 2.4 mm to about 2.6 mm, between about 2.4 mm to about 2.5 mm, or between about 2.5 mm to about 2.6 mm.

第2D圖、第2E圖及第2F圖繪示根據本揭露各種實施例之第一距離與電荷的分佈關係圖。第2D圖是繪示第一距離D1介於約2.3毫米至約2.7毫米之間時，電荷的分佈。由第2D圖可看出，當第一距離D1介於約2.3毫米至約2.7毫米之間時，電荷呈現均勻性地分佈。第2E圖是繪示第一距離D1小於約2.3毫米時，電荷的分佈。由第2E圖可看出，當第一距離D1小於約2.3毫米時，電荷大部分會集中並累積在第一垂直部分132與蓋環120的外側壁之間，從而致使電弧發生。第2F圖是繪示第一距離D1大於約2.7毫米時，電荷的分佈。由第2F圖可看出，當第一距離D1大於約2.7毫米時，在第一垂直部分132與蓋環120的外側壁之間電荷呈現較為疏鬆分佈，使得電漿不易生成或需增大施加功率才能產生所需的電漿量。據此，第一距離D1過大或過小皆會影響電荷分佈的均勻性或電場強度，而導致電漿量不足或致使電弧產生。FIG. 2D , FIG. 2E , and FIG. 2F illustrate the relationship between the first distance and the distribution of charges according to various embodiments of the present disclosure. FIG. 2D shows the charge distribution when the first distance D1 is between about 2.3 mm and about 2.7 mm. It can be seen from FIG. 2D that when the first distance D1 is between about 2.3 mm and about 2.7 mm, the charges are distributed uniformly. FIG. 2E shows the charge distribution when the first distance D1 is less than about 2.3 mm. It can be seen from FIG. 2E that when the first distance D1 is less than about 2.3 mm, most of the charges are concentrated and accumulated between the first vertical portion 132 and the outer sidewall of the cover ring 120 , thereby causing arcing. FIG. 2F shows the charge distribution when the first distance D1 is greater than about 2.7 millimeters. It can be seen from FIG. 2F that when the first distance D1 is greater than about 2.7 millimeters, the charge distribution between the first vertical portion 132 and the outer wall of the cover ring 120 is relatively loose, so that the plasma is not easy to generate or needs to be increased. power to produce the required amount of plasma. Accordingly, if the first distance D1 is too large or too small, the uniformity of charge distribution or the electric field strength will be affected, resulting in insufficient plasma volume or arc generation.

繼續參閱第1圖、第2A圖、第2B圖及第2C圖。第二垂直部分134位於蓋環120下方。在一些實施例中，第二垂直部分134的頂端延伸進入蓋環120的凹口122並實質上接觸凹口122的底面。應注意，雖然第二垂直部分134的頂端大致接觸凹口122的底面，但不會阻擋製程氣流(例如氬氣)的流進腔室104內。在物理氣相沉積的製程期間，高能粒子(離子)在腔室內相互高速地碰撞，可能撞擊腔室內的製程套件(例如，屏障130)，使得製程套件間的距離生微小的位移。藉由將蓋環120的凹口122的底角124加工成倒角，進一步限制在物理氣相沉積的製程期間，屏障130的第二垂直部分134的位移程度，進而能夠將第一距離D1控制在約2.3毫米至約2.7毫米之間。在一實施例中，凹口122的底面具有一第二寬度W2，第二垂直部分具有第三寬度W3，且第二寬度W2實質上大於或等於第三寬度W3。更詳細的說，第二寬度W2大於第三寬度W3約0.1毫米至約0.4毫米，例如約0.2毫米至約0.3毫米。Continue to refer to Figure 1, Figure 2A, Figure 2B and Figure 2C. The second vertical portion 134 is located below the cover ring 120 . In some embodiments, the top end of the second vertical portion 134 extends into the notch 122 of the cover ring 120 and substantially contacts the bottom surface of the notch 122 . It should be noted that although the top of the second vertical portion 134 substantially touches the bottom surface of the notch 122 , it does not block the flow of process gas (such as argon) into the chamber 104 . During the PVD process, high-energy particles (ions) collide with each other at high speed in the chamber, and may hit process kits (eg, the barrier 130 ) in the chamber, causing a slight shift in the distance between the process kits. By processing the bottom corner 124 of the notch 122 of the cover ring 120 into a chamfer, the degree of displacement of the second vertical portion 134 of the barrier 130 can be further limited during the process of physical vapor deposition, so that the first distance D1 can be controlled. Between about 2.3 mm and about 2.7 mm. In one embodiment, the bottom surface of the notch 122 has a second width W2, the second vertical portion has a third width W3, and the second width W2 is substantially greater than or equal to the third width W3. In more detail, the second width W2 is greater than the third width W3 by about 0.1 mm to about 0.4 mm, such as about 0.2 mm to about 0.3 mm.

第2G圖繪示根據本揭露另一實施例之第2B圖中區域R的局部放大圖。在一些實施例中，第二垂直部分134的頂端延伸進入蓋環120的凹口122且並未接觸凹口122的底面。FIG. 2G shows a partially enlarged view of the region R in FIG. 2B according to another embodiment of the present disclosure. In some embodiments, the top end of the second vertical portion 134 extends into the notch 122 of the cover ring 120 and does not contact the bottom surface of the notch 122 .

請回到第1圖，在一些實施例中，物理氣相沉積裝置100可以進一步包含環型的接地圈140環繞並安裝在基座110的支撐柱112。具體的說，接地圈140的直徑大於基座110之承載台的直徑。更詳細的說，接地圈140橫向延伸至屏障130之水平部分136的下方。在一些實施例中，支撐柱112包含鋁、不鏽鋼或銅。在一些實施例中，接地圈140包含鋁、不鏽鋼或銅。接地圈140可以將累積在基座110上多餘的電荷導出。Please return to FIG. 1 , in some embodiments, the physical vapor deposition apparatus 100 may further include a ring-shaped grounding ring 140 surrounding and mounted on the support column 112 of the base 110 . Specifically, the diameter of the grounding ring 140 is larger than the diameter of the supporting platform of the base 110 . In more detail, the ground ring 140 extends laterally below the horizontal portion 136 of the barrier 130 . In some embodiments, support posts 112 comprise aluminum, stainless steel, or copper. In some embodiments, ground ring 140 comprises aluminum, stainless steel, or copper. The grounding ring 140 can lead out excess electric charges accumulated on the base 110 .

在一些實施例中，物理氣相沉積裝置100還包含靶材160和電源供應器170。電源供應器170可電性連接至靶材160。在一些實施例中，電源供應器170為直流(direct current，DC) 供應器、射頻(radio frequency，RF)供應器或直流-射頻(DC-RF)供應器。靶材160包含待沉積至晶圓上的材料。在多個實施例中，靶材160可包含銅(Cu)、鈦(Ti)、鎳(Ni)、鋁(Al)、鈷(Co)、鎢(W)、鉭(Ta)、銀(Ag)、金(Au)、鎳鉑合金(Ni-Pt)、鎳鈦合金(Ni-Ti)或其他適當的金屬或金屬合金。電源供應器170可對靶材160施加偏壓，藉由所施加的電壓在腔室104內產生的電場激發濺鍍氣體以形成電漿，此電漿積極地撞擊並轟擊靶材160以從靶材160濺鍍出材料並沉積至晶圓上。In some embodiments, the physical vapor deposition apparatus 100 further includes a target 160 and a power supply 170 . The power supply 170 is electrically connected to the target 160 . In some embodiments, the power supply 170 is a direct current (DC) supply, a radio frequency (radio frequency, RF) supply or a direct current-radio frequency (DC-RF) supply. Target 160 contains the material to be deposited onto the wafer. In various embodiments, the target 160 may comprise copper (Cu), titanium (Ti), nickel (Ni), aluminum (Al), cobalt (Co), tungsten (W), tantalum (Ta), silver (Ag ), gold (Au), nickel-platinum alloy (Ni-Pt), nickel-titanium alloy (Ni-Ti), or other suitable metal or metal alloy. The power supply 170 can apply a bias voltage to the target material 160, and the electric field generated in the chamber 104 by the applied voltage excites the sputtering gas to form a plasma, which positively impacts and bombards the target material 160 to remove Material 160 is sputtered and deposited onto the wafer.

在一些實施例中，物理氣相沉積裝置100還包含一或多個泵(pump)180以自腔室104排氣。在多個實施例中，泵180可以受控制器(圖未示)控制，且可被用來將腔室104中的壓力維持在預期的壓力值。此外，在完成處理製程後，可使用泵180來抽除腔室104內的氣體以準備將晶圓自腔室104移出。在多個實施例中，泵180可包含低溫泵(cryopump)、渦輪分子泵(turbomolecular pump)、機械泵或其他合適的泵。In some embodiments, the physical vapor deposition apparatus 100 further includes one or more pumps 180 for exhausting the chamber 104 . In various embodiments, the pump 180 may be controlled by a controller (not shown) and may be used to maintain the pressure in the chamber 104 at a desired pressure value. In addition, the pump 180 may be used to evacuate the chamber 104 to prepare the wafers to be removed from the chamber 104 after the processing process is completed. In various embodiments, the pump 180 may comprise a cryopump, a turbomolecular pump, a mechanical pump, or other suitable pumps.

在一些實施例中，物理氣相沉積裝置100還包含氣體通道190。氣體通道190具有諸如質量流量控制器等氣流控制閥(圖未示)以使製程氣體以一設定流速通過。製程氣體可包含能夠碰撞靶材160並從靶材160濺鍍出材料的非活性氣體，諸如氬氣(Ar)或氙氣(Xe)。第1圖僅繪示出一個氣體通道190，但不以此為限，可視需求增加氣體通道190的數量，例如為2個、3個或4個。In some embodiments, the physical vapor deposition apparatus 100 further includes a gas channel 190 . The gas channel 190 has a gas flow control valve (not shown) such as a mass flow controller to allow the process gas to pass through at a set flow rate. The process gas may include an inactive gas, such as argon (Ar) or xenon (Xe), capable of colliding with the target 160 and sputtering material from the target 160 . FIG. 1 only shows one gas channel 190 , but it is not limited thereto, and the number of gas channels 190 can be increased as required, for example, 2, 3 or 4.

在一些實施例中，物理氣相沉積裝置100還包含電弧偵測元件210。電弧偵測元件210連接至腔室104，並藉由設置在腔室104內的感測元件(圖未示)將訊號傳送至電弧偵測元件210。在一些實施例中，電弧偵測元件210包含磁場感測器(圖未示)以及電弧分析電路系統(圖未示)。磁場感測器可包括由例如銅、鋁、鎳或其他金屬或合金等導電材料製成的線圈。在一些實施例中，所述線圈是閉合導電路徑(closed conductive path)。磁場感測器配置以產生例如呈電流或電壓形式的磁場訊號，其中所述磁場訊號的量值與通過磁場感測器的閉合導電路徑的磁通量成比例。電弧分析電路系統配置以評估所述磁場訊號並判斷在腔室104內是否已發生電弧。若偵測到電弧，則可移除晶圓並評估晶圓的缺陷，且可立即關閉電源供應器170直至腔室104可得到測試及/或修復為止。In some embodiments, the physical vapor deposition apparatus 100 further includes an arc detection element 210 . The arc detection element 210 is connected to the chamber 104 and transmits a signal to the arc detection element 210 through a sensing element (not shown) disposed in the chamber 104 . In some embodiments, the arc detection component 210 includes a magnetic field sensor (not shown) and an arc analysis circuit system (not shown). Magnetic field sensors may include coils made of conductive material such as copper, aluminum, nickel, or other metals or alloys. In some embodiments, the coil is a closed conductive path. The magnetic field sensor is configured to generate a magnetic field signal, for example in the form of a current or a voltage, wherein the magnitude of the magnetic field signal is proportional to the magnetic flux through the closed conductive path of the magnetic field sensor. Arc analysis circuitry is configured to evaluate the magnetic field signal and determine whether an arc has occurred within the chamber 104 . If arcing is detected, the wafer can be removed and evaluated for defects, and the power supply 170 can be shut down immediately until the chamber 104 can be tested and/or repaired.

在一些實施例中，物理氣相沉積裝置100可藉由一系統控制器(圖未示)協助控制及自動化。一般而言，系統控制器包含中央處理單元(圖未示)、支援電路(圖未示)或記憶體(圖未示)。中央處理單元可為任一型式的電腦處理器，其用於控制各種系統功能、晶圓移動、支援硬體(例如，感應器、機械手臂、馬達等)以及監控製程(例如，基座溫度、電源供應器變數、製程時間、支援電路訊號等)。記憶體連接中央處理單元，且為一種容易取得的記憶體，例如隨機存取記憶體(Random Access Memory，RAM)、唯讀記憶體(Read-Only Memory，ROM)、硬碟、軟碟或任何其他近端或遠端的數位存儲器。軟體指令與資料可加以編碼及存入記憶體，用以指示中央處理單元。支援電路連接中央處理單元。支援電路包含電源供應器、時鐘電路、輸出/輸入電路、高速緩衝存儲器、次系統等。In some embodiments, the physical vapor deposition apparatus 100 can be controlled and automated by a system controller (not shown). Generally, the system controller includes a central processing unit (not shown), supporting circuits (not shown) or memory (not shown). The central processing unit can be any type of computer processor used to control various system functions, wafer movement, support hardware (eg, sensors, robotic arms, motors, etc.), and monitor processes (eg, susceptor temperature, power supply variables, process time, support circuit signals, etc.). The memory is connected to the central processing unit and is an easily accessible memory, such as random access memory (Random Access Memory, RAM), read-only memory (Read-Only Memory, ROM), hard disk, floppy disk or any Other local or remote digital storage. Software instructions and data can be encoded and stored in memory for instructing the central processing unit. The support circuit is connected to the central processing unit. Supporting circuits include power supplies, clock circuits, I/O circuits, cache memory, subsystems, etc.

第3圖繪示根據本揭露某些實施例之物理氣相沉積裝置100在製程期間的示意圖。在物理氣相沉積的製程期間，支撐柱112會將基座110和接地圈140升高至一操作高度，此時，接地圈140會碰觸到屏障130，進而使整體的電荷迴路呈現均勻的接地(grounding)狀態。同時，沉積環150也會碰觸到蓋環120，而沉積環150用以將基座110與蓋環120電性絕緣。另一方面，製程氣體(諸如氬氣(Ar)或氙氣(Xe))藉由氣體通道190從基座110下方流經蓋環120的凹口122並通過第一垂直部分132與蓋環120外側壁之間的第一距離D1而向上進入腔室104中，如第3圖中箭號方向所示。由於製程氣體會流經第一垂直部分132與蓋環120外側壁之間的通道或空隙(即第一距離D1)，因此，製程氣體的流量的多寡會影響電漿的形成和/或電弧的產生。在一些實施例中，製程氣體流經通道或空隙(即第一距離D1)的流量可介於約400sccm至約450sccm的範圍。舉例來說，製程氣體流經通道或空隙(即第一距離D1)的流量可介於約410sccm至約440sccm的範圍或可介於約420sccm至約430sccm的範圍。當製程氣體的流量小於約400sccm時，進入腔室104內的製程氣體量不足，進而影響電漿生成的量。相反地，當製程氣體的流量大於約450sccm時，形成電漿後容易有大量的電荷積聚在第一垂直部分132與蓋環120的外側壁之間(即第一距離D1)，進而容易產生電弧。FIG. 3 illustrates a schematic diagram of a physical vapor deposition apparatus 100 during a process according to certain embodiments of the present disclosure. During the physical vapor deposition process, the supporting pillars 112 will raise the susceptor 110 and the grounding ring 140 to an operating height, and at this time, the grounding ring 140 will touch the barrier 130, thereby making the overall charge loop appear uniform. Grounding state. At the same time, the deposition ring 150 also touches the cover ring 120 , and the deposition ring 150 is used to electrically insulate the base 110 from the cover ring 120 . On the other hand, a process gas (such as argon (Ar) or xenon (Xe)) flows through the gas channel 190 from under the susceptor 110 through the recess 122 of the cover ring 120 and through the first vertical portion 132 and the outside of the cover ring 120 The first distance D1 between the walls goes up into the chamber 104, as shown in the direction of the arrow in FIG. 3 . Since the process gas will flow through the channel or gap (ie, the first distance D1) between the first vertical portion 132 and the outer wall of the cover ring 120, the flow rate of the process gas will affect the formation of the plasma and/or the arc. produce. In some embodiments, the flow rate of the process gas flowing through the channel or the gap (ie, the first distance D1 ) may range from about 400 sccm to about 450 sccm. For example, the flow rate of the process gas flowing through the channel or the gap (ie, the first distance D1 ) may range from about 410 sccm to about 440 sccm or may range from about 420 sccm to about 430 sccm. When the flow rate of the process gas is less than about 400 sccm, the amount of process gas entering the chamber 104 is insufficient, thereby affecting the amount of plasma generated. On the contrary, when the flow rate of the process gas is greater than about 450 sccm, a large amount of charge is likely to accumulate between the first vertical portion 132 and the outer sidewall of the cover ring 120 (ie, the first distance D1 ) after the plasma is formed, thereby easily generating an arc. .

第4圖繪示根據本揭露某些實施方式之沉積薄膜的方法30的流程圖。第5圖、第6圖、第7圖第8圖繪示根據本揭露某些實施方式之沉積薄膜的方法中不同階段的剖面示意圖。需理解的是，可在方法30之前、之中與之後，執行額外之操作，而對於方法30之額外實施例而言，操作的一些可被取代、排除或移動。沉積鈷薄膜的方法30僅為一示範之實施例，其包含操作310、操作320、操作330、操作340及操作350。FIG. 4 shows a flowchart of a method 30 of depositing a thin film according to certain embodiments of the present disclosure. FIG. 5 , FIG. 6 , FIG. 7 and FIG. 8 are schematic cross-sectional views of different stages in the method of depositing a thin film according to some embodiments of the present disclosure. It is to be understood that additional operations may be performed before, during, and after method 30 and that some of the operations may be substituted, excluded, or moved for additional embodiments of method 30 . The method 30 of depositing a cobalt thin film is only an exemplary embodiment, which includes operation 310 , operation 320 , operation 330 , operation 340 and operation 350 .

參閱第5圖，在操作310中，在一物理氣相沉積裝置(諸如上述物理氣相沉積裝置100)中接納一晶圓410。在一些實施例中，將放置於基座110上之晶圓410升高至一操作位置，使得沉積環150觸碰蓋環120。Referring to FIG. 5, in operation 310, a wafer 410 is received in a physical vapor deposition apparatus, such as physical vapor deposition apparatus 100 described above. In some embodiments, the wafer 410 placed on the susceptor 110 is raised to an operating position such that the deposition ring 150 touches the cover ring 120 .

在操作320中，藉由氣體通道190引入一製程氣體，此製程氣體由基座110下方流經蓋環120的底部的凹口122並通過屏障130(即第一垂直部分132)與蓋環120之外側壁之間的通道(即第一距離D1)後，流入腔室104，如第3圖所示。In operation 320, a process gas is introduced through the gas channel 190, and the process gas flows from under the susceptor 110 through the recess 122 at the bottom of the cover ring 120 and through the barrier 130 (ie, the first vertical portion 132) and the cover ring 120. After the passage between the outer sidewalls (ie, the first distance D1 ), it flows into the chamber 104 , as shown in FIG. 3 .

參閱第6圖，在操作330中，輸送一能量至物理氣相沉積裝置100中以形成一電漿510。具體的說，所述能量是由電源供應器170所提供，其中電源供應器170為一直流-射頻供應器。在一些實施例中，可藉由泵180將腔室104內的壓力調整至一預期壓力。再藉由氣體通道190將一製程氣體(諸如氬氣(Ar)或氙氣(Xe))引入至腔室104中，直至達到點燃電漿510的最佳條件。Referring to FIG. 6 , in operation 330 , an energy is delivered to the physical vapor deposition apparatus 100 to form a plasma 510 . Specifically, the energy is provided by the power supply 170, wherein the power supply 170 is a DC-RF supply. In some embodiments, the pressure in the chamber 104 can be adjusted to a desired pressure by the pump 180 . Then a process gas (such as argon (Ar) or xenon (Xe)) is introduced into the chamber 104 through the gas channel 190 until the optimum conditions for igniting the plasma 510 are reached.

參閱第7圖，在操作340中，使電漿510轟擊物理氣相沉積裝置100內的靶材160。具體的說，所述靶材160可為一鈷靶材。在一些實施例中，電源供應器170可對靶材160施加偏壓，進而可自靶材160產生原子、分子和/或離子。電漿510中的離子(諸如Ar離子或Xe離子)加速並撞擊靶材160。須說明的是，相較於常見的金屬材料(例如，鈦(Ti)或鋁(Al))，鈷材料具有較大的電阻，在PVD製程期間，其電荷的累積也相對較大，進而容易發生電弧現象。因此，有必要限制物理氣相沉積裝置100中屏障130之第一垂直部分132與蓋環120外側壁之間的第一距離D1(參閱第1圖)。Referring to FIG. 7 , in operation 340 , plasma 510 is made to bombard target 160 within physical vapor deposition apparatus 100 . Specifically, the target 160 may be a cobalt target. In some embodiments, the power supply 170 can apply a bias voltage to the target 160 so that atoms, molecules and/or ions can be generated from the target 160 . Ions in the plasma 510 , such as Ar ions or Xe ions, accelerate and strike the target 160 . It should be noted that, compared with common metal materials (for example, titanium (Ti) or aluminum (Al)), cobalt material has a larger resistance, and its charge accumulation is relatively larger during the PVD process, thereby easily Arcing occurs. Therefore, it is necessary to limit the first distance D1 between the first vertical portion 132 of the barrier 130 and the outer wall of the cover ring 120 in the physical vapor deposition apparatus 100 (see FIG. 1 ).

參閱第8圖，在操作350中，沉積一薄膜420至晶圓410的表面上。具體的說，所述薄膜420可為一鈷薄膜。Referring to FIG. 8 , in operation 350 , a thin film 420 is deposited on the surface of the wafer 410 . Specifically, the thin film 420 can be a cobalt thin film.

第9圖繪示根據本揭露某些實施方式之形成半導體結構的方法60的流程圖。第10圖、第11圖、第12圖、第13圖、第14圖、第15圖及第16圖繪示根據本揭露某些實施方式之形成半導體結構的方法60中不同階段的剖面示意圖。需理解的是，可在方法60之前、之中與之後，執行額外之操作，而對於方法60之額外實施例而言，操作的一些可被取代、排除或移動。形成半導體結構的方法60僅為一示範之實施例，其包含操作610、操作620、操作630、操作640、操作650及操作660。FIG. 9 shows a flowchart of a method 60 of forming a semiconductor structure according to certain embodiments of the present disclosure. 10 , 11 , 12 , 13 , 14 , 15 , and 16 schematically illustrate cross-sectional views at different stages in a method 60 of forming a semiconductor structure according to certain embodiments of the present disclosure. It is to be understood that additional operations may be performed before, during, and after method 60 and that some of the operations may be substituted, excluded, or moved for additional embodiments of method 60 . The method 60 of forming a semiconductor structure is only one exemplary embodiment, and includes operation 610 , operation 620 , operation 630 , operation 640 , operation 650 and operation 660 .

參閱第10圖，在操作610中，沉積一介電層720於一下層結構710上。在多個實施例中，介電層720包含一或多層介電材料，諸如氧化矽、氮化矽、氮化鈦、其他適宜介電材料、及/或其組合。高介電常數介電材料之實例包括HfO ₂、HfSiO、HfSiON、HfTaO、HfTiO、HfZrO、氧化鋯、氧化鋁、氧化鈦、二氧化鉿-氧化鋁(HfO ₂-Al ₂O ₃)合金、其他適宜的高介電常數介電材料、及/或其組合。在多個實施例中，介電層720可藉由化學氣相沉積(chemical vapor deposition，CVD)、原子層沉積(atomic layer deposition，ALD)或任何適宜的方法形成。 Referring to FIG. 10 , in operation 610 , a dielectric layer 720 is deposited on the underlying structure 710 . In various embodiments, the dielectric layer 720 includes one or more layers of dielectric materials, such as silicon oxide, silicon nitride, titanium nitride, other suitable dielectric materials, and/or combinations thereof. Examples of high-k dielectric materials include HfO ₂ , HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, zirconia, alumina, titania, hafnium dioxide-alumina (HfO ₂ -Al ₂ O ₃ ) alloys, others Suitable high-k dielectric materials, and/or combinations thereof. In various embodiments, the dielectric layer 720 can be formed by chemical vapor deposition (chemical vapor deposition, CVD), atomic layer deposition (atomic layer deposition, ALD), or any suitable method.

在一些實施例中，下層結構710為一典型且具有各種沉積預備金屬層或形成在其各別分離之介電層的半導體基板。例如，下層結構710可以為具活性特徵的矽基板，其中所述活性特徵例如為一層或多層的多晶矽層、場效隔離氧化層、閘極氧化層、氮化矽層、以及金屬化層。In some embodiments, the underlying structure 710 is typically a semiconductor substrate with various deposited pre-metal layers or separate dielectric layers formed thereon. For example, the underlying structure 710 may be a silicon substrate with active features, such as one or more layers of polysilicon layer, field isolation oxide layer, gate oxide layer, silicon nitride layer, and metallization layer.

在一些實施例中，為了形成下層結構710，首先將極純的單晶矽晶片暴露於高溫蒸氣並在其上形成一層氮化矽。接著於氮化矽層表面藉由CVD沉積反應氣體，例如鹽水和氨。值得注意的是，其他沉積步驟例如，常壓下CVD(Atmospheric Pressure CVD，APCVD)、低壓下CVD(Low Pressure CVD，LPCVD)、電漿增強CVD(Plasma Enhanced CVD，PECVD)、有機金屬CVD(Metal Organic CVD，MOCVD)、PVD、ALD、化學溶液沉積、濺射、以及其組合皆可以使用。將此結構塗佈上一光阻層，並通過微影技術圖案化以及乾式蝕刻流程蝕刻導孔以形成淺溝槽隔離(shallow trench isolation，STI)結構。下層結構710包含多種結構以及在金屬層前的層別於第10圖至第16圖中簡化地標示為一個單層。In some embodiments, to form the underlying structure 710, a very pure single crystal silicon wafer is first exposed to high temperature vapor and a layer of silicon nitride is formed thereon. Reactive gases, such as brine and ammonia, are then deposited on the surface of the silicon nitride layer by CVD. It is worth noting that other deposition steps such as atmospheric pressure CVD (Atmospheric Pressure CVD, APCVD), low pressure CVD (Low Pressure CVD, LPCVD), plasma enhanced CVD (Plasma Enhanced CVD, PECVD), organometallic CVD (Metal Organic CVD, MOCVD), PVD, ALD, chemical solution deposition, sputtering, and combinations thereof can all be used. The structure is coated with a photoresist layer, patterned by lithography technology and etched via a dry etching process to form a shallow trench isolation (STI) structure. The underlying structure 710 includes multiple structures and the layers before the metal layer are simplified as a single layer in FIGS. 10 to 16 .

參閱第11圖，在操作620中，形成一開口730貫穿介電層720。更詳細的說，開口730暴露出下層結構710的一部分。在多個實施例中，首先，可以先在介電層720上塗佈一光阻層(圖未示)，接著通過微影技術完成圖案化製程。在圖案化製程中，所述光阻層可選擇性地暴露於紫外線輻射下且顯影後在光阻光罩中形成孔洞圖案(圖未示)。然後，可以藉由使用反應氣體例如氟化物，氧，氯，三氯化硼之乾式蝕刻形成開口730貫穿介電層720。在其他實施例中，有時亦可添加氮氣，氬氣，氦氣以及其他氣體於反應氣體中。Referring to FIG. 11 , in operation 620 , an opening 730 is formed through the dielectric layer 720 . In more detail, the opening 730 exposes a portion of the underlying structure 710 . In various embodiments, firstly, a photoresist layer (not shown) may be coated on the dielectric layer 720, and then the patterning process is completed by photolithography. During the patterning process, the photoresist layer is selectively exposed to ultraviolet radiation and developed to form a pattern of holes in the photoresist mask (not shown). Then, an opening 730 may be formed through the dielectric layer 720 by dry etching using a reactive gas such as fluoride, oxygen, chlorine, boron trichloride. In other embodiments, nitrogen, argon, helium and other gases may also be added to the reaction gas sometimes.

參閱第12圖，在操作630中，形成一功函數層740於開口730的底部。功函數層740為由導電材料製成，諸如TiN、TaN、TaAlC、TiC、TaC、Co、Al、TiAl、HfTi、TiSi、TaSi、或TiAlC的單層，或者兩種或多種此等材料的多層。對於n通道場效電晶體(field-effect transistor，FET)，TaN、TaAlC、TiN、TiC、Co、TiAl、HfTi、TiSi及TaSi中的一或多個用作功函數層740，並且對於p通道FET，TiAlC、Al、TiAl、TaN、TaAlC、TiN、TiC及Co中的一或多個用作功函數層740。功函數層740可藉由ALD、PVD、CVD、電子束蒸發、或其他合適的製程來形成。另外，功函數層740可單獨地針對n通道FET及p通道FET形成，此等FET可使用不同的金屬層。Referring to FIG. 12 , in operation 630 , a work function layer 740 is formed at the bottom of the opening 730 . The work function layer 740 is made of a conductive material such as a single layer of TiN, TaN, TaAlC, TiC, TaC, Co, Al, TiAl, HfTi, TiSi, TaSi, or TiAlC, or a multilayer of two or more of these materials . For n-channel field-effect transistors (field-effect transistors, FETs), one or more of TaN, TaAlC, TiN, TiC, Co, TiAl, HfTi, TiSi, and TaSi are used as the work function layer 740, and for p-channel For FET, one or more of TiAlC, Al, TiAl, TaN, TaAlC, TiN, TiC, and Co is used as the work function layer 740 . The work function layer 740 can be formed by ALD, PVD, CVD, electron beam evaporation, or other suitable processes. In addition, the work function layer 740 can be formed separately for n-channel FETs and p-channel FETs, and these FETs can use different metal layers.

參閱第13圖，在操作640中，在一物理氣相沉積裝置(諸如上述物理氣相沉積裝置100)中沉積一第一鈷薄膜層750於開口730內，且第一鈷薄膜層750位於功函數層740上。應注意，沉積第一鈷薄膜層包含使一製程氣體流經屏障與蓋環間的空隙的流量介於約400sccm至約450sccm之間。Referring to Fig. 13, in operation 640, a first cobalt thin film layer 750 is deposited in the opening 730 in a physical vapor deposition device (such as the above-mentioned physical vapor deposition device 100), and the first cobalt thin film layer 750 is located at the working position. function layer 740. It should be noted that depositing the first cobalt thin film layer includes allowing a process gas to flow through the gap between the barrier and the cover ring at a flow rate between about 400 sccm and about 450 sccm.

參閱第14圖，在操作650中，形成一第二鈷薄膜層760覆蓋第一鈷薄膜層750及開口730之一側壁。在一些實施例中，第二鈷薄膜層760是藉由CVD製程共型地沉積在第一鈷薄膜層750及開口730的側壁上。Referring to FIG. 14 , in operation 650 , a second cobalt thin film layer 760 is formed to cover the first cobalt thin film layer 750 and a sidewall of the opening 730 . In some embodiments, the second cobalt thin film layer 760 is conformally deposited on the first cobalt thin film layer 750 and the sidewalls of the opening 730 by a CVD process.

參閱第15圖，在操作660中，形成一第三鈷薄膜層770覆蓋第二鈷薄膜層760。在一些實施例中，第三鈷薄膜層770是藉由電化學電鍍(electrochemical plating，ECP)法來將剩餘的開口730填滿。Referring to FIG. 15 , in operation 660 , a third cobalt thin film layer 770 is formed to cover the second cobalt thin film layer 760 . In some embodiments, the third cobalt thin film layer 770 fills up the remaining opening 730 by electrochemical plating (ECP) method.

在一些實施例中，在操作660之後，可以藉由平坦化第二鈷薄膜層760及第三鈷薄膜層770來形成金屬閘極810，如第16圖所示。由於第一鈷薄膜層750、第二鈷薄膜層760和第三鈷薄膜層770的材料皆為鈷，因此，實際上金屬閘極810並不存在如第16圖繪示之明顯的界面。可以使用例如化學機械平坦化(chemical-mechanical planarization，CMP)製程，使得金屬閘極810的頂表面與介電層720的頂表面平坦化。In some embodiments, after operation 660 , metal gate 810 may be formed by planarizing second cobalt thin film layer 760 and third cobalt thin film layer 770 , as shown in FIG. 16 . Since the first cobalt thin film layer 750 , the second cobalt thin film layer 760 and the third cobalt thin film layer 770 are all made of cobalt, the metal gate 810 actually does not have an obvious interface as shown in FIG. 16 . The top surface of the metal gate 810 and the top surface of the dielectric layer 720 can be planarized using, for example, a chemical-mechanical planarization (CMP) process.

本揭露之一態樣是提供一種物理氣相沉積裝置包含腔室、基座、蓋環以及屏障。基座設置於腔室內的底部。蓋環環繞基座並與基座電性絕緣。屏障環繞物理氣相沉積裝置的腔室壁。屏障包含第一垂直部分、第二垂直部分以及水平部分。第一垂直部分與物理氣相沉積裝置的腔室壁實質上平行，蓋環位於第一垂直部分與基座之間，其中第一垂直部分與蓋環的外側壁側壁間隔第一距離，第一距離介於2.3毫米至2.7毫米之間。第二垂直部分位於蓋環下方，其中第二垂直部分的頂端實質上接觸蓋環。水平部分位於該蓋環下方並連接第一垂直部分的第一底端和第二垂直部分的第二底端。One aspect of the present disclosure is to provide a physical vapor deposition apparatus including a chamber, a susceptor, a cover ring, and a barrier. The base is arranged at the bottom of the chamber. The cover ring surrounds the base and is electrically insulated from the base. A barrier surrounds a chamber wall of the physical vapor deposition apparatus. The barrier includes a first vertical section, a second vertical section and a horizontal section. The first vertical portion is substantially parallel to the chamber wall of the physical vapor deposition device, and the cover ring is located between the first vertical portion and the base, wherein the first vertical portion is spaced from the outer side wall of the cover ring by a first distance, the first The distance is between 2.3mm and 2.7mm. The second vertical portion is located below the cover ring, wherein the top end of the second vertical portion substantially contacts the cover ring. The horizontal portion is located below the cover ring and connects the first bottom end of the first vertical portion and the second bottom end of the second vertical portion.

根據本揭露多個實施例，物理氣相沉積裝置更包含一沉積環位於基座與蓋環之間，沉積環配置以將基座與蓋環電性絕緣。根據本揭露多個實施例，蓋環具有一凹口，由蓋環的下表面朝蓋環的上表面凹陷。根據本揭露多個實施例，凹口之一底角為倒角。根據本揭露多個實施例，第二垂直部分的頂端延伸進入凹口。根據本揭露多個實施例，凹口之底面具有第一寬度，第二垂直部分具有第二寬度，且第一寬度實質上大於或等於第二寬度。根據本揭露多個實施例，物理氣相沉積裝置更包含一接地圈環繞基座之支撐柱，且接地圈之直徑大於基座之承載台的直徑。根據本揭露多個實施例，接地圈橫向延伸至水平部分的下方。According to various embodiments of the present disclosure, the physical vapor deposition apparatus further includes a deposition ring disposed between the base and the cover ring, and the deposition ring is configured to electrically insulate the base and the cover ring. According to various embodiments of the present disclosure, the cover ring has a notch, which is recessed from the lower surface of the cover ring toward the upper surface of the cover ring. According to various embodiments of the present disclosure, a bottom corner of the notch is chamfered. According to various embodiments of the present disclosure, the top end of the second vertical portion extends into the notch. According to various embodiments of the present disclosure, the bottom surface of the notch has a first width, the second vertical portion has a second width, and the first width is substantially greater than or equal to the second width. According to various embodiments of the present disclosure, the physical vapor deposition apparatus further includes a grounding ring surrounding the support column of the pedestal, and the diameter of the grounding ring is larger than the diameter of the carrying platform of the pedestal. According to various embodiments of the present disclosure, the ground ring extends laterally below the horizontal portion.

本揭露之另一態樣是提供一種沉積薄膜的方法，包含以下操作。在物理氣相沉積裝置中接納一晶圓。藉由氣體通道引入製程氣體，且製程氣體由基座下方流經蓋環的凹口並通過屏障與蓋環之外側壁之間的一通道，而向上流入腔室。輸送能量至腔室中以使製程氣體形成電漿，其中所述能量是由射頻源和直流源提供。使電漿轟擊物理氣相沉積裝置內的靶材。沉積一薄膜至晶圓的表面上。Another aspect of the present disclosure provides a method for depositing a thin film, which includes the following operations. A wafer is received in a physical vapor deposition apparatus. The process gas is introduced through the gas channel, and the process gas flows from the bottom of the susceptor through the notch of the cover ring and through a channel between the barrier and the outer side wall of the cover ring, and flows upward into the chamber. Energy is delivered into the chamber to form a plasma of the process gas, wherein the energy is provided by an RF source and a DC source. A plasma is bombarded against a target in a physical vapor deposition apparatus. A thin film is deposited onto the surface of the wafer.

本揭露之又一態樣是提供一種形成半導體結構的方法，包含以下操作。沉積介電層於下層結構上。形成開口貫穿介電層。形成功函數層於開口中。在物理氣相沉積裝置中沉積第一鈷薄膜層於開口中，且第一鈷薄膜層位於功函數層上，其中沉積第一鈷薄膜層包含使一製程氣體流經屏障與蓋環間的空隙的流量介於約400sccm至約450sccm之間。形成第二鈷薄膜層覆蓋第一鈷薄膜層及開口之側壁。形成第三鈷薄膜覆蓋第二鈷薄膜層。Another aspect of the present disclosure provides a method of forming a semiconductor structure, including the following operations. A dielectric layer is deposited on the underlying structure. An opening is formed through the dielectric layer. A work function layer is formed in the opening. Depositing a first cobalt thin film layer in the opening in a physical vapor deposition apparatus, and the first cobalt thin film layer is located on the work function layer, wherein depositing the first cobalt thin film layer includes flowing a process gas through a gap between the barrier and the cover ring The flow rate is between about 400 seem to about 450 seem. A second cobalt thin film layer is formed to cover the first cobalt thin film layer and the sidewall of the opening. A third cobalt thin film is formed to cover the second cobalt thin film layer.

前述內文概述了許多實施例的特徵，使本技術領域中具有通常知識者可以從各個方面更佳地了解本揭露多個實施例。本技術領域中具有通常知識者應可理解，且可輕易地以本揭露多個實施例為基礎來設計或修飾其他製程及結構，並以此達到相同的目的及/或達到與在此介紹的實施例等相同之優點。本技術領域中具有通常知識者也應了解這些相等的結構並未背離本揭露多個實施例的發明精神與範圍。在不背離本揭露多個實施例的發明精神與範圍之前提下，可對本揭露多個實施例進行各種改變、置換或修改。The foregoing text summarizes the features of many embodiments, so that those skilled in the art can better understand the various embodiments of the present disclosure from various aspects. Those skilled in the art should be able to understand, and can easily design or modify other processes and structures based on the multiple embodiments of the present disclosure, so as to achieve the same purpose and/or achieve the same as described herein Embodiment etc. have the same advantages. Those skilled in the art should also understand that these equivalent structures do not depart from the spirit and scope of the inventions of the various embodiments of the present disclosure. Various changes, substitutions or modifications can be made to the various embodiments of the present disclosure without departing from the inventive spirit and scope of the various embodiments of the present disclosure.

100:物理氣相沉積裝置 102:腔室壁 104:腔室 110:基座 112:支撐柱 120:蓋環 122:凹口 124:底角 130:屏障 132:第一垂直部分 134:第二垂直部分 136:水平部分 138:附接部分 140:接地圈 150:沉積環 160:靶材 170:電源供應器 180:泵 190:氣體通道 210:電弧偵測元件 30:方法 310:操作 320:操作 330:操作 340:操作 350:操作 410:晶圓 420:薄膜 510:電漿 60:方法 610:操作 620:操作 630:操作 640:操作 650:操作 660:操作 710:下層結構 720:介電層 730:開口 740:功函數層 750:第一鈷薄膜層 760:第二鈷薄膜層 770:第三鈷薄膜層 810:金屬閘極 A-A’:剖線 D1:第一距離 R:區域 W1:第一寬度 W2:第二寬度 W3:第三寬度 100:Physical vapor deposition device 102: chamber wall 104: chamber 110: base 112: support column 120: cover ring 122: notch 124: bottom corner 130: Barrier 132: First vertical section 134:Second vertical section 136: Horizontal part 138: attachment part 140: Grounding ring 150: deposition ring 160: target 170: Power supply 180: pump 190: gas channel 210: arc detection element 30: method 310: Operation 320: operation 330: Operation 340: Operation 350: Operation 410: Wafer 420: film 510: Plasma 60: method 610: Operation 620: Operation 630: Operation 640: Operation 650: operation 660: Operation 710: Substructure 720: dielectric layer 730: opening 740: Work function layer 750: the first cobalt film layer 760: the second cobalt film layer 770: the third cobalt film layer 810: metal gate A-A': section line D1: first distance R: area W1: first width W2: second width W3: third width

當結合隨附圖式進行閱讀時，本揭露發明實施例之詳細描述將能被充分地理解。應注意，根據業界標準實務，各特徵並非按比例繪製且僅用於圖示目的。事實上，出於論述清晰之目的，可任意增加或減小各特徵之尺寸。在說明書及圖式中以相同的標號表示相似的特徵。 第1圖繪示根據本揭露某些實施例之物理氣相沉積裝置的示意圖。 第2A圖繪示根據本揭露某些實施例之屏障與蓋環的立體示意圖。 第2B圖繪示第2A圖沿剖線A-A’的剖面示意圖。 第2C圖繪示第2B圖區域R的局部放大圖。 第2D圖、第2E圖及第2F圖繪示根據本揭露各種實施例之第一距離與電荷的分佈關係圖。 第2G圖繪示根據本揭露另一實施例之第2B圖中區域R的局部放大圖。 第3圖繪示根據本揭露某些實施例之物理氣相沉積裝置在製程期間的示意圖。 第4圖繪示根據本揭露某些實施方式之沉積薄膜的方法的流程圖。 第5圖、第6圖、第7圖及第8圖繪示根據本揭露某些實施方式之沉積薄膜的方法中不同階段的剖面示意圖。 第9圖繪示根據本揭露某些實施方式之形成半導體結構的方法的流程圖。 第10圖、第11圖、第12圖、第13圖、第14圖、第15圖及第16圖繪示根據本揭露某些實施方式之形成半導體結構的方法中不同階段的剖面示意圖。 The detailed description of the embodiments of the disclosed invention will be fully understood when read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard industry practice, features are not drawn to scale and are used for illustration purposes only. In fact, the dimensions of the various features may be arbitrarily increased or decreased for clarity of discussion. Similar features are denoted by the same reference numerals in the description and drawings. FIG. 1 shows a schematic diagram of a physical vapor deposition apparatus according to some embodiments of the present disclosure. FIG. 2A shows a schematic perspective view of a barrier and a cover ring according to some embodiments of the present disclosure. Fig. 2B shows a schematic cross-sectional view of Fig. 2A along the section line A-A'. FIG. 2C shows a partially enlarged view of the region R in FIG. 2B. FIG. 2D , FIG. 2E , and FIG. 2F illustrate the relationship between the first distance and the distribution of charges according to various embodiments of the present disclosure. FIG. 2G shows a partially enlarged view of the region R in FIG. 2B according to another embodiment of the present disclosure. FIG. 3 illustrates a schematic diagram of a physical vapor deposition apparatus during a process according to certain embodiments of the present disclosure. FIG. 4 shows a flowchart of a method of depositing a thin film according to certain embodiments of the present disclosure. Figures 5, 6, 7 and 8 illustrate schematic cross-sectional views at different stages in a method of depositing a thin film according to certain embodiments of the present disclosure. FIG. 9 illustrates a flowchart of a method of forming a semiconductor structure according to certain embodiments of the present disclosure. 10 , 11 , 12 , 13 , 14 , 15 , and 16 schematically illustrate cross-sectional views at different stages in a method of forming a semiconductor structure according to certain embodiments of the present disclosure.

100:物理氣相沉積裝置 100:Physical vapor deposition device

102:腔室壁 102: chamber wall

104:腔室 104: chamber

110:基座 110: Base

112:支撐柱 112: support column

120:蓋環 120: cover ring

122:凹口 122: notch

124:底角 124: bottom corner

130:屏障 130: Barrier

132:第一垂直部分 132: First vertical section

134:第二垂直部分 134:Second vertical section

136:水平部分 136: Horizontal part

138:附接部分 138: attachment part

140:接地圈 140: Grounding ring

150:沉積環 150: deposition ring

160:靶材 160: target

170:電源供應器 170: Power supply

180:泵 180: pump

190:氣體通道 190: gas channel

210:電弧偵測元件 210: arc detection element

D1:第一距離 D1: first distance

W1:第一寬度 W1: first width

W2:第二寬度 W2: second width

W3:第三寬度 W3: third width

Claims (10)

一種物理氣相沉積裝置，包含: 一腔室； 一基座，設置於該腔室內的一底部； 一蓋環，環繞該基座並與該基座電性絕緣；以及 一屏障，環繞該物理氣相沉積裝置的一腔室壁，該屏障包含: 一第一垂直部分，與該物理氣相沉積裝置的該腔室壁實質上平行，該蓋環位於該第一垂直部分與該基座之間，其中該第一垂直部分與該蓋環的一外側壁間隔一第一距離，該第一距離介於約2.3毫米至約2.7毫米之間； 一第二垂直部分，位於該蓋環下方，該第二垂直部分的一頂端實質上接觸該蓋環；以及 一水平部分，位於該蓋環下方並連接該第一垂直部分的一第一底端和該第二垂直部分的一第二底端。 A physical vapor deposition device, comprising: a chamber; a base disposed on a bottom in the chamber; a cover ring surrounding and electrically insulated from the base; and a barrier surrounding a chamber wall of the physical vapor deposition apparatus, the barrier comprising: a first vertical portion substantially parallel to the chamber wall of the physical vapor deposition apparatus, the cover ring is located between the first vertical portion and the base, wherein the first vertical portion and a the outer sidewalls are separated by a first distance between about 2.3 millimeters and about 2.7 millimeters; a second vertical portion positioned below the cover ring, a top end of the second vertical portion substantially touching the cover ring; and A horizontal part is located below the cover ring and connects a first bottom end of the first vertical part and a second bottom end of the second vertical part. 如請求項1所述之物理氣相沉積裝置，更包含一沉積環位於該基座與該蓋環之間，該沉積環配置以將該基座與該蓋環電性絕緣。The physical vapor deposition device as claimed in claim 1, further comprising a deposition ring located between the base and the cover ring, the deposition ring configured to electrically insulate the base from the cover ring. 如請求項1所述之物理氣相沉積裝置，其中該蓋環具有一凹口，由該蓋環的一下表面朝該蓋環的一上表面凹陷。The physical vapor deposition device as claimed in claim 1, wherein the cover ring has a recess, which is recessed from a lower surface of the cover ring toward an upper surface of the cover ring. 如請求項3所述之物理氣相沉積裝置，其中該凹口之一底角為倒角。The physical vapor deposition device as claimed in claim 3, wherein a bottom corner of the notch is chamfered. 如請求項3所述之物理氣相沉積裝置，其中該第二垂直部分的該頂端延伸進入該凹口。The physical vapor deposition apparatus as claimed in claim 3, wherein the top end of the second vertical portion extends into the recess. 如請求項3所述之物理氣相沉積裝置，其中該凹口之一底面具有一第一寬度，該第二垂直部分具有一第二寬度，且該第一寬度實質上大於或等於該第二寬度。The physical vapor deposition device as claimed in claim 3, wherein a bottom surface of the recess has a first width, the second vertical portion has a second width, and the first width is substantially greater than or equal to the second width. 如請求項1所述之物理氣相沉積裝置，更包含一接地圈環繞該基座之一支撐柱，且該接地圈之一直徑大於該基座之一承載台的一直徑。The physical vapor deposition device as claimed in claim 1 further comprises a grounding ring surrounding a support column of the susceptor, and a diameter of the grounding ring is larger than a diameter of a supporting platform of the susceptor. 如請求項7所述之物理氣相沉積裝置，其中該接地圈橫向延伸至該水平部分的下方。The physical vapor deposition apparatus as claimed in claim 7, wherein the grounding ring extends laterally below the horizontal portion. 一種沉積薄膜的方法，包含: 在一物理氣相沉積裝置中接納一晶圓； 藉由一氣體通道引入一製程氣體，該製程氣體由一基座下方流經一蓋環的一凹口並通過一屏障與該蓋環之一外側壁之間的一通道，而向上流入一腔室； 輸送一能量至該腔室中以使該製程氣體形成一電漿，其中該能量是由一直流-射頻供應器所提供； 使該電漿轟擊該物理氣相沉積裝置內的一靶材；以及 沉積一薄膜至該晶圓的一表面上。 A method of depositing a thin film comprising: receiving a wafer in a physical vapor deposition apparatus; A process gas is introduced through a gas channel, the process gas flows from below a susceptor through a recess in a cover ring and through a channel between a barrier and an outer side wall of the cover ring, and upwardly into a cavity room; delivering energy into the chamber to cause the process gas to form a plasma, wherein the energy is provided by a DC-RF supply; bombarding a target within the physical vapor deposition apparatus with the plasma; and A thin film is deposited on a surface of the wafer. 一種形成一半導體結構的方法，包含： 沉積一介電層於一下層結構上； 形成一開口貫穿該介電層； 形成一功函數層於該開口中； 在一物理氣相沉積裝置中沉積一第一鈷薄膜層於該開口中，且該第一鈷薄膜層位於該功函數層上，其中沉積該第一鈷薄膜層包含使一製程氣體流經一屏障與一蓋環間的一空隙的一流量介於約400sccm至約450sccm之間； 形成一第二鈷薄膜層覆蓋該第一鈷薄膜層及該開口之一側壁；以及 形成一第三鈷薄膜層覆蓋該第二鈷薄膜層。 A method of forming a semiconductor structure, comprising: depositing a dielectric layer on the underlying structure; forming an opening through the dielectric layer; forming a work function layer in the opening; Depositing a first cobalt thin film layer in the opening in a physical vapor deposition device, and the first cobalt thin film layer is located on the work function layer, wherein depositing the first cobalt thin film layer includes flowing a process gas through a a flow rate of a gap between the barrier and a cover ring is between about 400 sccm and about 450 sccm; forming a second cobalt film layer covering the first cobalt film layer and a sidewall of the opening; and A third cobalt thin film layer is formed to cover the second cobalt thin film layer.

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