200836250 九、發明說明 【發明所屬之技術領域】 本發明是關於在半導體晶圓等之被處理體形成阻障膜 或遮蔽膜等時之薄膜形成方法及薄膜之疊層構造。 【先前技術】 一般而言，製造半導體裝置是對半導體晶圓重複執行 成膜處理或圖案鈾刻處理等之各種處理。依此，製造所欲 之裝置。近年來，由於半導體裝置要求更高積體化及高微 細化，線寬或孔徑也漸漸微細化。 就以配線材料或埋入材料而言，一般是使用鋁或鋁合 金。最近由於各種尺寸之微細化，而必須更縮小電阻，因 而有使用電阻非常小且便宜之鎢或銅當作配線材料或埋入 材料之傾向（參照特開2000-77365號公報、特開平10-74760號公報、特開平1 0-2 1 483 6號公報及特開 2 005 -285 820號公報）。 於使用鋁（含有A1合金）、鎢（W )、銅（Cu )等 當作配線材料之時，爲了防止配線材料本身矽化，並且提 高與基底層之密著性，於形成上述配線材料之前，一般形 成阻障層當作基底膜。配線材料爲鋁（包含A1合金）或 鎢之時，使用Ti膜或TiN膜當作該阻障層。另外，配線 材料爲銅之時，使用Ta膜或TaN膜等。當作阻障層之各 種薄膜是因應膜之種類，由熱 CVD ( Chenical Vapor Deposition)法或電漿CVD法或濺鍍等之成膜方法選擇最 200836250 佳成膜方法予以成膜。 但是，作爲成膜方法除熱CVD法之外，亦可使用電 漿CVD法或濺鍍法。電漿CVD法是成膜中晶圓本身容易 帶電，其結果，容易產生絕緣膜被破壞等之充電受損。因 此，有依膜種不同，使用晶圓本身比較不易產生帶電之濺 鍍法的傾向。 在此，針對藉由上述般之濺鍍法的成膜方法之一例予 以說明。第6圖A及第6圖B爲表示藉由濺鍍之以往成膜 方法之一例的說明圖。在第6圖A所示之半導體晶圓S之 表面形成例如由S i Ο 2膜等所構成之絕緣層2。在該絕緣層 2形成有通孔或貫穿孔或接觸孔般之孔狀的凹部4。在該 凹部4之底部露出應被電性連接之下層之接觸部6。該接 觸部6是對應於下層中之配線層或下層中之元件之電極， 例如電晶體之源極或汲極等。 於成膜時，如第6圖B所示般，首先在晶圓S表面包 含凹部4內之內面，藉由濺鍍法略均勻形成例如Ti膜。 接著，再使用濺鍍法，於先前所形成之Ti膜8上略均勻 形成TiN膜10。依此，形成由Ti膜8和TiN膜10之疊 層構造所構成之阻障層1 2。 若形成如此之阻障層1 2，藉由使用例如熱CVD法等 形成配線層14 ’埋入凹部4內，並且在晶圓S之上面全 體形成配線層1 4。該配線層丨4是藉由例如鋁（包含合金 )或鎢等所形成。以後，將配線層1 4或阻障層12触刻成 所欲之圖案，形成所欲之配線圖案。 200836250 【發明內容】 在使用上述般之濺鍍法的成膜方法中，產生充電受損 之頻率减少許多。但是，依狀況不同也有產生充電受損之 情形。當產生充電受損之時，則發生半導體元件特性惡化 或信賴性下降。尤其，電晶體特性惡化，會引起增加消耗 電力或使動作速度下降等之問題。 本發明是注目於以上之問題點，爲有效解決此而硏創 者。本發明之目的是提供濺鍍時可以大幅度抑制充電受損 之發生的薄膜形成方法。 本發明之薄膜形成方法是具備在被處理體之表面上藉 由濺鍍形成用以防止充電受損之充電受損防止膜的防止膜 形成工程；和在形成於被處理體之表面上的充電受損防止 膜之表面上，藉由濺鍍形成所欲之薄膜的薄膜形成工程。 若藉由本發明，於藉由濺鍍在被處理體之表面上形成 所欲之薄膜時，藉由濺鍍形成充電受損防止膜以當作其前 工程。依此’可以大幅度抑制濺鍍時產生充電受損。 充電受損防止膜是由Co (銘）、Ge (鍺）、Ru (钌 )中之任一材料所形成爲佳。 再者’在上述被處理體之表面事先形成絕緣層，在上 述防止膜形成工程中爲在絕緣層表面形成用以防止充電受 損之充電受損防止膜爲佳。 再者，例如在上述薄膜形成工程中，形成有1種類之 薄膜。或是’例如在上述薄膜形成工程中，依序形成種類 -6- 200836250 不同之多數薄膜。 再者’上述薄膜爲金屬膜或是金屬含有膜爲佳。 再者’本發明屬於形成在被處理體表面之薄膜之疊層 構造’具備藉由濺鍍形成在上述被處理體表面上之充電受 損防止膜’和藉由濺鍍形成在上述充電受損防止膜表面上 之1層薄膜。 上述1層薄膜是由TiN膜所構成爲佳。例如，上述 TiN膜形成阻障層。然後，例如在上述TiN膜上形成配線 層。該配線層是由例如A1 (包含A1合金）膜和W膜和 C u膜中之任一材料所形成。 再者’本發明是屬於形成在被處理體表面上之薄膜之 疊層構造’具備藉由濺鍍形成在上述被處理體表面上之充 電受損防止膜’和藉由濺鍍形成在上述充電受損防止膜表 面上之多數薄膜要素。 上述多數薄膜要素之種類互相爲不同爲佳。例如，上 述多數薄膜要素由下層往上層爲Ti膜要素和TiN膜要素 。或是’例如’上述多數薄膜要素由下層往上層爲TaN膜 要素和Ta膜要素。再者，例如，上述多數薄膜要素形成 阻障層。然後’例如，在上述多數薄膜要素上形成有配線 層。上述配線層是由例如A1 (包含A1合金）膜和W膜和 Cu膜中之任一材料所形成。 【實施方式】 以下是根據附件圖面詳細說明本發明所涉及之薄膜形 200836250 成方法及薄膜之疊層構造之實施形態。 第1圖爲表示用以實施本發明所涉及之薄膜形成方法 之電漿成膜裝置之一例的剖面圖。在此，以電漿成膜裝置 而言，係以 ICP( Inductively Coupled Plasma)型電漿濺 鍍裝置爲例予以說明。如第1圖所示般，該電漿成膜裝置 16具有例如藉由鋁等成形爲筒體狀之處理容器18。該處 理容器18爲接地，其底部20設置有排氣口 22。排氣口 22是經執行壓力調整之節流閥24而連接於真空泵26，可 對處理容器1 8之內部抽真空。 在處理容器18內設置圓板狀之載置台28。該載置台 2 8是由例如由鋁所構成之載置台本體2 8 A，和設置在該上 面之靜電夾28B所構成。靜電夾28B上可吸附保持屬於被 處理體之半導體晶圓S。再者，在靜電夾28B之上面形成 有用以流通熱傳導氣體之氣體溝3 0。因應所需，藉由將 Ar氣體等熱傳導氣體供給至該氣體溝3 0，可以提升晶圓 S和載置台2 8之間的熱傳導性。再者，因應所需在靜電 夾2 8 B施加無圖式之吸附用之直流電壓。 上述般之載置台28是藉由從該載置台28之下面中心 部延伸至下方之支柱3 2而支撐。支柱3 2之下部貫通處理 容器18之底部20。然後，支柱32是藉由無圖式之升降機 構而能夠上下移動，依此，可以升降載置台2 8。 再者，以包圍支柱3 2之方式，設置有能夠伸縮之蛇 腹狀之金屬伸縮管3 4。金屬伸縮管3 4之上端是氣密接合 於載置台2 8之下面，金屬伸縮管3 4之下端是氣密接合於 -8- 200836250 處理容器1 8之底部20之上面。依此，可一面維持處理容 器18內之氣密性，一面執行載置台28之升降移動。在載 置台28之載置台本體28A形成有流通用以冷卻晶圓S之 冷煤的冷煤循環路3 6以當作冷卻手段。冷煤是經支柱3 2 內之無圖式之流路而供給或排出。 在容器底部20朝向上方豎立設置有例如3根（在圖 中僅顯示兩根）之支撐銷3 8。再者，以對應於該支撐銷 38之方式，在載置台28形成有銷插通孔40。依此，於載 置台28下降時，貫通銷插通孔40之支撐銷38之上端部 接受晶圓S，在由外部侵入之無圖式之搬運臂之間，可執 行該晶圓S之移載。在處理容器1 8之下部側壁，爲了使 上述搬運臂侵入，設置有可開關之閘閥42。 再者，在設置於載置台本體28A上之靜電夾28B經配 線44，連接有由產生例如13.56 MHz之高頻之高頻電源所 構成之偏壓電源4 6。依此，可對載置台2 8施加特定偏壓 電力。再者，偏壓電源46可因應所需而以可變方式控制 屬於該輸出之偏壓電力。 另外，在處理容器1 8之天井部，經〇環等密封構件 5 〇氣密設置有例如由氧化鋁等之介電體所構成並且相對於 高頻具有透過性之透過板4 8。然後，相對於該透過板4 8 與處理容器1 8之處理空間5 2相反側，設置有用以使當作 例如電漿激勵用氣體之Ar氣體予以電漿化而產生電漿之 電漿產生源5 4。並且，即使以其他惰性氣體例如He、Ne 等取代Ar以當作電漿激勵用氣體亦可。具體而言，電漿 -9- 56 200836250 產生源54可具有設置在透過板48之上部的感應線圈部 。該誘導線圏部56連接電漿產生用之例如13.56MHz之 頻電源58，經透過板48可以將高頻導入至處理空間52 。在此，由高頻電源5 8所輸出之電漿電力也可以因應 需以可變方式予以控制。 再者，在透過板48之正下方設置有使導入之高頻 以擴散之例如由鋁所構成的阻板60。然後，在該阻板 之下方以包圍處理空間52上部之方式，設置有例如剖 朝向內側傾斜之環狀之（截頭圓錐殻狀之）金屬靶材62 在該金屬靶材62連接有供給放電用電力之靶材用之直 電源64。即使使用交流電源取代直流電源64亦可。在 ，自直流電源64輸出之直流電力也可以因應所需而以 變方式予以控制。再者，因應應形成之膜種類，使用例 鈷、鈦、鉬、銅等作爲金屬靶材62。該些金屬是藉由電 中之Ar離子，作爲金屬原子或是金屬原子團而被濺鍍 然後，該金屬原子或是金屬原子團之大部分是於通過電 中時被離子化。並且，鈦或鉅是於形成阻障層時被使用 銅是於形成遮蔽膜時被使用。 再者，在金屬靶材62之下部是以包圍處理空間5 2 方式，設置有由例如鋁所構成之圓筒狀之保護蓋66。該 護蓋66被接地。再者，保護蓋66之下部是彎曲至內側 位於載置台28之側部附近。 再者，在處理容器1 8之底部設置有例如氣體導入 68，以當作導入至處理容器18內之所需特定氣體的氣 尚 內 所 予 60 面 〇 流 此 可 如 漿 〇 漿 之 保 □ 體 -10- 200836250 導入手段。自該氣體導入口 68通過由氣體流量控制器、 閥等所構成之氣體控制部70，供給稀有氣體例如Ar氣體 或其他需要之氣體例如N2氣體等以當作電漿激勵用氣體 〇 在此，成膜裝置1 6之各構成部是連接於由例如電腦 等所構成之裝置控制部72，藉由該裝置控制部72而被控 制。具體而言，裝置控制部72是控制偏壓電源46、電漿 產生用之高頻電源58、可變直流電源64、氣體控制部70 、節流閥24、真空泵26等，以實施依循本發明方法之薄 膜形成方法之方式，執行以下之動作。 首先，在裝置控制部72之支配下，在動作真空泵26 而成爲真空之處理容器18內，一面動作氣體控制部70 — 面流動Ar氣體。然後，控制節流閥24，使處理容器18 內維持在特定之真空度。之後，經可變直流電源64，對金 屬靶材62施加直流電力，並且經高頻電源5 8對感應線圏 部56施加高頻電力（電漿電力）。另外，裝置控制部72 也對偏壓電源46發號指令，對載置台28施加特定偏壓電 力。 在以上所控制之處理容器1 8內，藉由被施加至感應 線圈部56之電漿電力形成氬電漿，生成氬離子。該些離 子衝撞至金屬靶材62。依此，濺鍍金屬靶材62，釋放金 屬粒子。 來自被濺鍍之金屬靶材62之金屬粒子之金屬原子或 金屬原子團大多數於通過電漿中時被離子化。然後，該些 -11 - 200836250 成爲被離子化之金屬離子和電性中性之中性金屬原子混合 之狀態，飛散至下方向。在此，處理容器18內之壓力設 定比較高，例如設定成50mTorr以上。依此，提高電漿密 度，能高效率使金屬粒子離子化。 然後，金屬離子是進入藉由被施加至載置台28之偏 壓電力而所產生之晶圓面上之厚度數mm左右之離子鞘之 區域。如此一來，金屬離子以持有強指向性而加速至晶圓 S側的方式予以吸附，而堆積於晶圓S。如此一來，藉由 持有高指向性之金屬離子而堆積之薄膜，基本上能夠取得 垂直形狀之覆蓋域。 在此，裝置之各構成部是根據作成以特定條件執行金 屬膜之成膜的程式，藉由裝置控制部72適當控制。此時 ，例如在軟碟（註冊商標）（FD )或光碟（註冊商標）（ CD)、快閃記憶體、硬碟等記憶媒體74儲存包含用以執 行各構成部之控制之命令的程式，以根據該程式由特定條 件執行處理之方式，控制各構成部。 接著，針對依循使用由上述所構成之電漿成膜裝置1 6 而所執行之本發明之薄膜形成方法予以說明。 本發明方法之特徵，是藉由濺鍍在半導體晶圓表面上 形成用以防止充電受損之充電受損防止膜之防止膜形成工 程，以當作形成薄膜之薄膜形成工程之前工程。 參照第2圖A至第2圖C及第3圖具體說明本發明方 法之實施形態。第2圖A至第2圖C爲表示藉由各實施形 態所形成之薄膜之疊層構造之例的剖面圖。第3圖爲各實 -12- 200836250 施形態之工程圖。 形成第2圖A至第2圖C所示之疊層構造之前的晶圓 構造是與第6圖A所示相同。即是，如第6圖A所示般 ，在半導體晶圓S之表面形成由例如Si〇2膜等所構成之 絕緣層2，在該絕緣層2形成通孔或貫穿孔或接觸孔般之 孔狀凹部4，在該凹部4之底部露出應電性連接之下層的 接觸部6。該接觸部6是對應於下層中之配線層或下層中 之元件之電極，例如電晶體之源極或汲極等。 然後，在如此所形成之晶圓S上面執行各種成膜處理 ，生成第2圖A至第2圖C所示之疊層構造。在此，表示 第1至第3實施形態。首先，如第3圖所示般，與第1至 第3各實施形態共通，執行防止膜形成工程（S 1 )以當作 薄膜形成工程之前工程。依此，藉由濺鍍形成充電受損防 止膜8 0。該防止膜8 0不僅在晶圓S之絕緣層2表面，也 形成在凹部4(參照第6圖）內之表面，即是形成在底面 及側面之整個表面。 接著，執行薄膜形成工程。 於第1實施形態之時，執行第1薄膜要素形成步驟（ S2)，依據濺鍍在表面全面形成第1薄膜82 (參照第2 圖A )。並且，埋入凹部4內，在全面形成配線層84 ( S3 )。此時，第1薄膜82之1層成爲阻障層。 再者，於第2實施形態之時，藉由上述濺鍍在表面全 面形成第1薄膜82之後，如第2圖B所示般，執行第2 薄膜要素形成步驟（S4)，形成在表面全面積層第2薄膜 -13- 200836250 86。並且，埋入凹部4內，在全面形成配線層88(S5) 。此時，第1薄膜782和第2薄膜86之層構造成爲阻障 層。再者，第2薄膜形成步驟（S4 )之處理即使以濺鍍執 行亦可，即使以熱CVD處理或電漿CVD處理執行亦可。 再者，於第3實施形態之時，執行上述第2薄膜要素 形成步驟（S4)，形成在表面全面疊層第2薄膜86之後 ，如第2圖C所示般，執行第3薄膜要素形成步驟（S 6 ) ，形成在表面全體疊層第3薄膜90。並且，埋入凹部4內 ’在全面形成配線層92 ( S 7 )。此時，第1至第2薄膜 82、86之層構造或是第1至第3之各層82、86、90之層 構造成爲阻障層。再者，第3薄膜要素形成步驟（S6 )之 處理即使由濺鍍執行亦可，即使由熱CVD處理或電漿處 理CVD處理亦可。 於必要之時，即使更疊層薄膜之後，再形成配線層亦 可。 在上述第1至第3之各實施形態中，各薄膜82、86、 90之膜種各爲不同。該些之各薄膜82、86、90是由金屬 膜或是金屬含有膜所構成。作爲金屬含有膜，適用金屬之 氮化膜等。於形成氮化膜之時，若使用例如N2氣體等當 作氮氣體即可。再者，以濺鍍形成各薄膜82、86、90之 時，即使共同使用第1圖所示之電漿成膜裝置1 6，因應堆 積之膜種類來交換金屬靶材62亦可，並且爲了防止異種 金屬污染即使按每堆積之膜種類而使用不同電漿成膜裝置 1 6亦可。 -14- 200836250 如上述般，藉由濺鍍於半導體晶圓S表面形成薄膜 86時’因藉由濺鍍形成充電受損防止膜8〇當作其前工程 ，故能夠大幅度抑制濺鍍時產生充電受損。 在此，可以使用由Co (鈷）、Ge (鍺）、Ru (釕） 所形成之群中所選擇出之一種材料以當作上述充電受損防 止膜80。該充電受損防止膜80之厚度是對形成在該上層 之第1薄膜82不引起充電受損，爲可以對平面方向確保 些許導電性之厚度即可。例如，數原子層位準之厚度具體 而言以10〜50A左右之厚度爲佳。如此一來，藉由薄化充 電受損防止膜8 0，即使以電阻比形成在該上層之配線層 84、88、92之構成材料高之材料形成充電受損防止膜80 ，亦可以極力抑制配線電阻上昇。再者，即使於蝕刻加工 配線層8 4、8 8、9 2時，亦可以以與該些配線層8 4、8 8、 92之蝕刻相同之製程條件，蝕刻充電受損防止膜80。 並且，當充電受損防止膜80之厚度比50A大時，則 引起配線電阻上昇或配線層之蝕刻加工上之問題點。另外 ，當充電受損防止膜8 0之厚度比1 〇 A小時，則無法充分 抑制充電受損之發生。 再者，於以防止膜形成工程形成充電受損防止膜80 之時，則以將濺鍍收率設定在0.9〜l.latomsWon之範圍內 爲佳。若爲該範圍內之濺鍍收率時，發生於濺鍍中之原子 和離子之量的平衡，難以產生因成膜中帶電之電荷偏移所 造成之充電，成爲電性中和狀態。換言之，於上述範圍外 之濺鍍收率時，在形成充電受損防止膜80之際，該充電 -15- 200836250 受損防止膜本體容易受到充電受損。在此，濺鍍收率是以 數値表示濺鍍之容易度。濺鍍收率是藉由電漿產生時所供 給之稀有氣體之種類和離子能（eV )而決定。離子能（eV )是依存於藉由第1圖中之直流電源64而施加在金屬靶 材62之電壓。 每各離子之濺鍍收率之一例表示於「新版真空手冊」 (OHMSHA，Ltd·、ULVAC，Inc·編輯，2002 年 8 月發行） 之第8章（第25 7頁至第2 5 8頁）。例如，離子能爲 4 00eV之時，濺鍍收率爲0.9〜l.latoms/ion之範圍內，並 且可以選擇產生金屬污染較少之材料例如Co、Ge、Ru等 以當作充電受損防止膜80之構成材料。 再者，若最初將如此之充電受損防止膜8 0當作基底 膜而予以形成時，即使在該上層藉由濺鍍形成容易產生充 電受損之金屬膜，例如A1膜（含有A1合金）、W (鎢） 膜、Cu (銅）膜、Ti (鈦）膜、Ta (鉬）膜，或是金屬氮 化膜例如TiN膜、TaN膜等，亦可以經位於下層之導電性 之上述充電受損防止膜8 0使經充電之電荷分散。即是， 不會引起充電受損。 在此，針對各實施形態予以更詳細說明。第2圖A所 示之第1實施形態是使用Co膜當作充電受損防止膜80， 使用TiN膜當作第1薄膜82，使用A1層或是W層當作配 線層84。並且，A1層包含例如含有Cu之A1合金層以當 作A1合金膜。此時’ TiN膜當作阻障層發揮功能。再者 ，在此至少充電受損防止膜80和第1薄膜82之TiN膜藉 -16- 200836250 由濺鍍成膜。 再者，第2圖B所示之第2實施形態是使用Co膜當 作充電受損防止膜80，使用Ti膜當作第1薄膜82，使用 TiN膜當作第2薄膜86，使用A1層或是W層當作配線層 88。並且，此時，A1層含有合金層例如含有Cu之A1合 金層，此時，由Ti膜和TiN膜所形成之層構造當作阻障 層發揮功能。再者，在此，至少充電受損防止膜8 0和第1 薄膜82之Ti膜藉由濺鍍成膜。 再者，第2圖C所不之第3實施形態是使用Co膜當 作充電受損防止膜80，使用TaN膜當作第1薄膜82，使 用Ta膜當作第2薄膜86，使用成爲遮蔽膜之Cu膜當作 第3薄膜，使用Cu層當作配線層92。並且，此時，由 TaN膜和Ta膜所構成之層構造當作阻障層而發揮功能。 再者，在此，至少充電受損防止膜80和屬於第1薄膜82 之TaN膜藉由濺鍍而成膜。再者，第3薄膜86爲由藉由 濺鍍形成薄Cu膜所構成之遮蔽膜。以該遮蔽膜爲起點， 藉由電鍍形成由C u層所構成之配線層9 2。 並且，各實施形態之疊層構造僅不過爲例示。即是， 本發明並不限定於上述般之各實施形態之疊層構造。 [用以確認本發明之效果的實驗] 在此，因執行用以確認上述本發明之效果的實驗，故 針對該評估結果予以說明。 在此，實驗是在半導體晶圓上形成第2圖A所示之第 -17- 200836250 1實施形態之薄膜疊層構造。具體而言，以濺鍍形成co 膜以當作充電受損防止膜80，在該上方藉由濺鍍形成TiN 膜當作第1薄膜82。形成該TiN膜之後，關於該TiN膜 測定洩漏電流。在此，屬於充電受損防止膜80之Co膜爲 10〜3 0A左右之膜厚。再者，屬於第1薄膜82之TiN膜 爲3 00A左右之膜厚。再者，當作施予成膜之半導體晶圓 因測量對充電之耐性，故使用特別之平面天線基板。該平 面天線基板之天線比（S1/S2 )爲”106”。該平面天線基板 被稱爲所謂之TEG (該天線構造表示於第5圖）。 並且，在此不形成配線層84。該理由是由於全體有無 發生充電受損僅依存於是否存在直接形成於充電受損防止 膜8 0上之第1薄膜82中之充電受損，故配線層84之成 膜不需要上述測量之故。 並且，在比較例中，在不形成Co膜之狀態下藉由濺 鍍直接形成TiN膜。 第4圖爲表示有無發生充電受損之曲線圖。橫軸爲洩 漏電流，縱軸爲度數分布。在第4圖中，曲線A是對應於 由TiN膜所形成之比較例之膜構造，曲線B是對應於由 TiN膜/Co膜所形成之依循本發明方法之膜構造。洩漏電 流成爲1(Γ9Α以上，爲N.G (不佳）不良品。 如第4圖所示般，爲曲線Α之比較例時，合格率爲 15%左右，不良率也到達85%左右，爲不佳。對此，爲曲 線B之本發明方法之時，合格率爲100%，不良率爲0%， 爲良好結果。 -18- 200836250 其他，即使在形成TaN膜當作第1薄膜82之時或形 成屬於良好導電性材料之Ti膜時，亦可以確認發揮與上 述實驗之TiN膜相等之作用效果或是該以上之良好作用效 果。 再者，在此雖然以半導體晶圓爲例說明被處理體’但 是並不限定於此，玻璃基板、L c D基板、陶瓷基板等亦可 以適用本發明。 【圖式簡單說明】 第1圖是表示用以實施本發明所涉及之薄膜形成方法 之電漿成膜裝置之一例的剖面圖。 第2圖A至第2圖C爲表示藉由本發明方法之各實施 形態所形成之薄膜之疊層構造之例之剖面圖。 第3圖爲本發明方法之各實施形態之工程圖。 第4圖爲表示有無發生充電受損之曲線圖。 第5圖爲表示被稱爲TEG之天線基板之天線構造之 平面圖。 第6圖A及第6圖B是表示藉由濺鍍之以往成膜方法 之一^例的說明圖。 [主要元件符號說明】 2 :絕緣層 4 :凹部 6 :接觸部 -19- 200836250 8 ·· Ti 膜 1 0 : TiN 膜 1 2 :阻障層 1 4 :配線層 1 8 :處理容器 2 0 :底部 22 :排氣口 24 :節流閥 26 :真空泵 2 8 :載置台 28A :載置台本體 2 8 B :靜電夾 3 0 :氣體溝 3 2 :支柱 34 :金屬伸縮管 3 6 :冷煤循環路 3 8 :支撐銷 4 0 :銷插通孔 42 :閘閥 44 :配線 4 6 :偏壓電源 48 :透過板 5 0 :密封構件 5 2 :處理空間 -20 200836250 5 4 :電漿產生源 5 6 :感應線圏 5 8 :局頻電源 6 0 :阻板 6 2 :金屬靶材 6 4 :直流電源 66 :保護蓋 68 :氣體導入口 70 :氣體控制部 72 :裝置控制部 74 :記憶媒體 8 0 :充電受損防止膜 82 :第1薄膜 84 :配線層 8 6 :第2薄膜 8 8 :配線層 90 :第3薄膜 9 2 :配線層 S :晶圓 -21 -[Technical Field] The present invention relates to a film forming method and a film lamination structure when a barrier film or a mask film is formed on a substrate to be processed such as a semiconductor wafer. [Prior Art] In general, manufacturing a semiconductor device is a process of repeatedly performing a film forming process or a pattern uranium process on a semiconductor wafer. Accordingly, the desired device is fabricated. In recent years, as semiconductor devices have been required to be more integrated and highly refined, the line width or the aperture has been gradually miniaturized. In the case of wiring materials or buried materials, aluminum or aluminum alloys are generally used. Recently, due to the miniaturization of various sizes, it has been necessary to reduce the electric resistance. Therefore, there is a tendency to use tungsten or copper which is very small in electrical resistance and inexpensive as a wiring material or a buried material (refer to Japanese Laid-Open Patent Publication No. 2000-77365, No. Hei 10-- Japanese Patent Publication No. 74760, Japanese Patent Application Laid-Open No. Hei No. Hei No. Hei No. Hei No. Hei 2 005-285 820). When aluminum (including A1 alloy), tungsten (W), copper (Cu), or the like is used as the wiring material, in order to prevent the wiring material itself from deteriorating and to improve the adhesion to the underlying layer, before forming the wiring material, A barrier layer is generally formed as a base film. When the wiring material is aluminum (including an A1 alloy) or tungsten, a Ti film or a TiN film is used as the barrier layer. Further, when the wiring material is copper, a Ta film or a TaN film or the like is used. Each of the films used as the barrier layer is formed by a film formation method such as a thermal CVD (Chenical Vapor Deposition) method or a plasma CVD method or a sputtering method to form a film by a film formation method of 200836250. However, as a film formation method, in addition to the thermal CVD method, a plasma CVD method or a sputtering method can also be used. In the plasma CVD method, the wafer itself is easily charged during film formation, and as a result, charging damage such as destruction of the insulating film is likely to occur. Therefore, depending on the type of film, the use of the wafer itself is less likely to cause a charged sputtering method. Here, an example of a film formation method by the above-described sputtering method will be described. Fig. 6A and Fig. 6B are explanatory views showing an example of a conventional film formation method by sputtering. On the surface of the semiconductor wafer S shown in Fig. 6A, an insulating layer 2 made of, for example, a Si 2 film or the like is formed. In the insulating layer 2, a recessed portion 4 having a through hole or a through hole or a contact hole is formed. At the bottom of the recess 4, the contact portion 6 to be electrically connected to the lower layer is exposed. The contact portion 6 is an electrode corresponding to a wiring layer in the lower layer or an element in the lower layer, such as a source or a drain of the transistor. At the time of film formation, as shown in Fig. 6B, first, the inner surface of the concave portion 4 is placed on the surface of the wafer S, and a Ti film is formed uniformly, for example, by sputtering. Next, the TiN film 10 is formed slightly uniformly on the previously formed Ti film 8 by sputtering. Accordingly, the barrier layer 12 composed of the stacked structure of the Ti film 8 and the TiN film 10 is formed. When such a barrier layer 12 is formed, the wiring layer 14' is buried in the recess 4 by using, for example, a thermal CVD method, and the wiring layer 14 is entirely formed on the wafer S. The wiring layer 丨4 is formed by, for example, aluminum (including an alloy) or tungsten. Thereafter, the wiring layer 14 or the barrier layer 12 is patterned into a desired pattern to form a desired wiring pattern. 200836250 SUMMARY OF THE INVENTION In the film forming method using the sputtering method as described above, the frequency of occurrence of charge damage is greatly reduced. However, depending on the situation, there is also a situation in which charging is damaged. When the charging is damaged, the deterioration of the characteristics of the semiconductor element or the decrease in reliability occur. In particular, deterioration of the transistor characteristics causes problems such as an increase in power consumption or a decrease in the operation speed. The present invention is directed to the above problems and is an effective solution to this problem. SUMMARY OF THE INVENTION An object of the present invention is to provide a film forming method which can greatly suppress the occurrence of damage during sputtering. The film forming method of the present invention is provided with an anti-film forming process for forming a charge damage preventing film for preventing damage from being damaged by sputtering on the surface of the object to be processed; and charging on the surface formed on the object to be processed On the surface of the damage preventing film, a film forming process of forming a desired film by sputtering is performed. According to the present invention, when a desired film is formed on the surface of the object to be processed by sputtering, a charge damage preventing film is formed by sputtering to be regarded as a front project. According to this, it is possible to greatly suppress the occurrence of charging damage during sputtering. The charge damage preventing film is preferably formed of any one of Co (Ming), Ge (锗), and Ru (钌). Further, it is preferable to form an insulating layer on the surface of the object to be processed in advance, and it is preferable to form a charge damage preventing film on the surface of the insulating layer to prevent charging damage in the above-mentioned film forming process. Further, for example, in the above film forming process, one type of film is formed. Or, for example, in the above film forming process, a plurality of films of different types -6 to 200836250 are sequentially formed. Further, the film is preferably a metal film or a metal-containing film. Further, the present invention relates to a laminated structure of a film formed on the surface of a target object, a charging damage preventing film formed on the surface of the object to be processed by sputtering, and a damaged charge formed by sputtering. Prevent a film on the surface of the film. The above-mentioned one-layer film is preferably composed of a TiN film. For example, the above TiN film forms a barrier layer. Then, for example, a wiring layer is formed on the above TiN film. The wiring layer is formed of, for example, an A1 (including an Al alloy) film and any of a W film and a Cu film. Further, the present invention relates to a laminated structure of a film formed on a surface of a target object, a charging damage preventing film formed on the surface of the object to be processed by sputtering, and a charge formation formed by sputtering. Damage prevents most of the film elements on the surface of the film. It is preferable that the types of the plurality of thin film elements are different from each other. For example, the above-mentioned majority of thin film elements are Ti film elements and TiN film elements from the lower layer to the upper layer. Or, for example, the plurality of thin film elements are TaN film elements and Ta film elements from the lower layer to the upper layer. Further, for example, most of the above thin film elements form a barrier layer. Then, for example, a wiring layer is formed on most of the above-described thin film elements. The above wiring layer is formed of, for example, an A1 (including an Al alloy) film and any of a W film and a Cu film. [Embodiment] Hereinafter, an embodiment of a film-formed method of forming a film of the invention and a laminated structure of a film according to the present invention will be described in detail based on the attached drawings. Fig. 1 is a cross-sectional view showing an example of a plasma film forming apparatus for carrying out the film forming method according to the present invention. Here, the plasma film forming apparatus is described by taking an ICP (Inductively Coupled Plasma) type plasma sputtering apparatus as an example. As shown in Fig. 1, the plasma film forming apparatus 16 has a processing container 18 which is formed into a cylindrical shape by, for example, aluminum. The processing vessel 18 is grounded and its bottom 20 is provided with an exhaust port 22. The exhaust port 22 is connected to the vacuum pump 26 via a throttle valve 24 that performs pressure adjustment, and can evacuate the inside of the processing container 18. A disk-shaped mounting table 28 is provided in the processing container 18. The mounting table 28 is composed of, for example, a mounting table main body 28A made of aluminum, and an electrostatic chuck 28B provided on the upper surface. The semiconductor wafer S belonging to the object to be processed can be adsorbed and held on the electrostatic chuck 28B. Further, a gas groove 30 for circulating a heat transfer gas is formed on the upper surface of the electrostatic chuck 28B. The heat conductivity between the wafer S and the mounting table 28 can be improved by supplying a heat conduction gas such as an Ar gas to the gas groove 30 as needed. Furthermore, a DC voltage for the non-patterned adsorption is applied to the electrostatic chuck 2 8 B as needed. The above-described mounting table 28 is supported by a pillar 3 2 extending from a lower central portion of the mounting table 28 to a lower portion. The lower portion of the post 3 2 penetrates the bottom portion 20 of the processing container 18. Then, the strut 32 can be moved up and down by the unillustrated elevating mechanism, whereby the mounting table 28 can be raised and lowered. Further, a bellows-like metal telescopic tube 34 that can be stretched and contracted is provided so as to surround the pillars 3 2 . The upper end of the metal telescopic tube 3 4 is hermetically joined to the underside of the mounting table 28, and the lower end of the metal telescopic tube 34 is hermetically bonded to the bottom 20 of the processing container 18 of -8-200836250. Accordingly, the lifting movement of the mounting table 28 can be performed while maintaining the airtightness in the processing container 18. A cooling coal circulation path 36 for circulating cold coal for cooling the wafer S is formed on the stage main body 28A of the mounting table 28 as a cooling means. Cold coal is supplied or discharged through a non-patterned flow path in the column 3 2 . On the bottom portion 20 of the container, for example, three support pins 38 (only two are shown in the figure) are erected upward. Further, a pin insertion hole 40 is formed in the mounting table 28 so as to correspond to the support pin 38. Accordingly, when the mounting table 28 is lowered, the wafer S is received at the upper end portion of the support pin 38 of the through-pin insertion hole 40, and the wafer S can be moved between the transfer arms of the non-patterned intrusion from the outside. Loaded. In the lower side wall of the processing container 18, a switchable gate valve 42 is provided in order to invade the transfer arm. Further, the electrostatic chuck 28B provided on the stage body 28A is connected to a bias power source 46 composed of a high-frequency power source generating a high frequency of, for example, 13.56 MHz via a wiring 44. Accordingly, a specific bias power can be applied to the stage 28. Moreover, bias power supply 46 can variably control the bias power belonging to the output as needed. Further, in the ceiling portion of the processing container 18, a sealing member 5 such as a crucible ring is airtightly provided with a transmissive plate 48 made of, for example, a dielectric material such as alumina and having transparency with respect to high frequencies. Then, a plasma generating source for plasma-generating Ar gas which is, for example, a plasma excitation gas, is generated on the opposite side to the processing space 52 of the processing container 18 from the permeating plate 48. 5 4. Further, even if Ar is replaced with another inert gas such as He, Ne or the like, it may be used as a plasma excitation gas. Specifically, the plasma -9-56 200836250 generation source 54 may have an induction coil portion disposed above the transmission plate 48. The induction coil crotch portion 56 is connected to a frequency power source 58 for generating plasma, for example, 13.56 MHz, and the high frequency can be introduced into the processing space 52 via the transmission plate 48. Here, the plasma power outputted by the high-frequency power source 58 can also be controlled in a variable manner as needed. Further, a barrier plate 60 made of, for example, aluminum which diffuses the introduced high frequency is provided directly under the transmission plate 48. Then, a ring-shaped (frustum-shell-shaped) metal target 62 that is inclined toward the inner side is disposed under the resisting plate so as to surround the upper portion of the processing space 52. A supply discharge is connected to the metal target 62. A direct power source 64 for use with a power target. Even if an AC power source is used instead of the DC power source 64. The DC power output from the DC power source 64 can also be controlled in a variable manner as needed. Further, in view of the type of film to be formed, cobalt, titanium, molybdenum, copper or the like is used as the metal target 62. The metals are sputtered as metal atoms or metal radicals by Ar ions in electricity. Then, the metal atoms or most of the metal radicals are ionized when passing through electricity. Also, titanium or giant is used when forming a barrier layer. Copper is used when forming a masking film. Further, a cylindrical protective cover 66 made of, for example, aluminum is provided on the lower portion of the metal target 62 so as to surround the processing space 52. The cover 66 is grounded. Further, the lower portion of the protective cover 66 is bent to the inner side in the vicinity of the side portion of the mounting table 28. Further, at the bottom of the processing container 18, for example, a gas introduction 68 is provided to treat the 60-side turbulence in the gas of the desired specific gas introduced into the processing container 18, which can be guaranteed as a slurry. Body-10-200836250 Introduction means. From the gas introduction port 68, a gas control unit 70 composed of a gas flow controller, a valve, or the like supplies a rare gas such as an Ar gas or another required gas such as N 2 gas to be used as a plasma excitation gas. Each component of the film forming apparatus 16 is connected to a device control unit 72 composed of, for example, a computer, and is controlled by the device control unit 72. Specifically, the device control unit 72 controls the bias power source 46, the high frequency power source 58 for generating plasma, the variable DC power source 64, the gas control unit 70, the throttle valve 24, the vacuum pump 26, and the like to implement the present invention. In the manner of the film forming method of the method, the following actions are performed. First, under the control of the device control unit 72, the gas control unit 70 is operated to flow the Ar gas while the vacuum pump 26 is operating in the vacuum processing container 18. Then, the throttle valve 24 is controlled to maintain the inside of the processing container 18 at a specific degree of vacuum. Thereafter, DC power is applied to the metal target 62 via the variable DC power source 64, and high frequency power (plasma power) is applied to the induction line portion 56 via the high frequency power source 58. Further, the device control unit 72 also issues a command to the bias power source 46 to apply a specific bias voltage to the mounting table 28. In the processing container 18 controlled above, argon plasma is generated by the plasma power applied to the induction coil portion 56 to generate argon ions. The ions collide with the metal target 62. Accordingly, the metal target 62 is sputtered to release the metal particles. Metal atoms or metal radicals from the metal particles of the sputtered metal target 62 are mostly ionized as they pass through the plasma. Then, these -11 - 200836250 are mixed with ionized metal ions and electrically neutral neutral metal atoms, and are scattered to the lower direction. Here, the pressure in the processing container 18 is set relatively high, for example, set to 50 mTorr or more. Accordingly, the plasma density is increased, and the metal particles can be ionized with high efficiency. Then, the metal ions are regions of the ion sheath which are formed to have a thickness of about several mm on the wafer surface by the bias voltage applied to the mounting table 28. As a result, the metal ions are adsorbed so as to be accelerated toward the wafer S side while holding strong directivity, and are deposited on the wafer S. In this way, the film deposited by the metal ions having high directivity can basically obtain the coverage of the vertical shape. Here, each component of the apparatus is a program for performing film formation of a metal film under specific conditions, and is appropriately controlled by the device control unit 72. At this time, for example, a memory medium 74 such as a floppy disk (registered trademark) (FD) or a compact disc (registered trademark) (CD), a flash memory, or a hard disk stores a program including a command for executing control of each component, Each component is controlled such that processing is executed by a specific condition according to the program. Next, a film forming method of the present invention which is carried out by using the plasma film forming apparatus 16 constructed as described above will be described. The method of the present invention is characterized in that a film formation process for forming a charge damage preventing film for preventing charge damage by sputtering on a surface of a semiconductor wafer is used as a film forming process for forming a film. Embodiments of the method of the present invention will be specifically described with reference to Figs. 2A to 2C and Fig. 3 . Fig. 2 to Fig. 2C are cross-sectional views showing an example of a laminated structure of a film formed by each embodiment. Figure 3 is a diagram of the construction of each -12-200836250. The wafer structure before the formation of the stacked structure shown in Figs. 2A to 2C is the same as that shown in Fig. 6A. That is, as shown in FIG. 6A, an insulating layer 2 made of, for example, a Si〇2 film or the like is formed on the surface of the semiconductor wafer S, and a through hole or a through hole or a contact hole is formed in the insulating layer 2. The hole-shaped recess 4 exposes the contact portion 6 of the lower layer to be electrically connected to the bottom of the recess 4. The contact portion 6 is an electrode corresponding to a wiring layer in the lower layer or an element in the lower layer, such as a source or a drain of a transistor. Then, various film forming processes are performed on the wafer S thus formed to form a laminated structure shown in FIGS. 2A to 2C. Here, the first to third embodiments are shown. First, as shown in Fig. 3, in common with the first to third embodiments, the film formation preventing process (S1) is performed to be used as a film forming process. Accordingly, the charge damage preventing film 80 is formed by sputtering. The film 80 is formed not only on the surface of the insulating layer 2 of the wafer S but also on the surface of the recess 4 (see Fig. 6), i.e., on the entire surface of the bottom surface and the side surface. Next, a film formation process is performed. In the first embodiment, the first thin film element forming step (S2) is performed, and the first thin film 82 is formed on the entire surface by sputtering (see Fig. 2A). Further, the wiring layer 84 is formed in the recessed portion 4 (S3). At this time, one layer of the first film 82 serves as a barrier layer. Further, in the second embodiment, after the first thin film 82 is entirely formed on the surface by the sputtering, the second thin film element forming step (S4) is performed as shown in Fig. 2B to form a comprehensive surface. Laminated second film-13- 200836250 86. Further, the wiring layer 88 is formed in the entire recessed portion 4 (S5). At this time, the layer structure of the first film 782 and the second film 86 serves as a barrier layer. Further, the second thin film forming step (S4) may be performed by sputtering or even by thermal CVD or plasma CVD. In the third embodiment, the second thin film element forming step (S4) is performed, and after the second thin film 86 is entirely laminated on the surface, the third thin film element is formed as shown in FIG. In the step (S6), the third film 90 is laminated on the entire surface. Further, the wiring layer 92 is completely formed in the recessed portion 4 (S7). At this time, the layer structure of the first to second films 82, 86 or the layer structures of the first to third layers 82, 86, 90 is a barrier layer. Further, the treatment of the third thin film element forming step (S6) may be performed by thermal CVD treatment or plasma treatment CVD treatment, even if it is performed by sputtering. When necessary, a wiring layer may be formed even after the film is laminated. In each of the first to third embodiments, the film types of the respective films 82, 86, and 90 are different. Each of the films 82, 86, and 90 is composed of a metal film or a metal-containing film. As the metal-containing film, a metal nitride film or the like is applied. When a nitride film is formed, for example, a nitrogen gas or the like may be used as the nitrogen gas. Further, when the respective films 82, 86, and 90 are formed by sputtering, even if the plasma film forming apparatus 1 shown in Fig. 1 is used in common, the metal target 62 may be exchanged depending on the type of film to be deposited, and It is also possible to prevent dissimilar metal contamination by using different plasma film forming apparatuses 16 for each type of film to be deposited. -14- 200836250 As described above, when the thin film 86 is formed by sputtering on the surface of the semiconductor wafer S, the charging damage preventing film 8 is formed by sputtering, and the sputtering process can be greatly suppressed. Damage to the charge. Here, a material selected from the group consisting of Co (cobalt), Ge (yttrium), and Ru (yttrium) may be used as the above-described charge damage preventing film 80. The thickness of the charge damage preventing film 80 is such that the first film 82 formed on the upper layer is not damaged by charging, and the thickness can be ensured to be slightly conductive in the planar direction. For example, the thickness of the atomic layer level is preferably about 10 to 50 A. In this way, by thinning the charge damage preventing film 80, even if the charge damage preventing film 80 is formed of a material having a higher electrical resistance than the constituent materials of the wiring layers 84, 88, 92 of the upper layer, the charge damage preventing film 80 can be suppressed as much as possible. The wiring resistance increases. Further, even when the wiring layers 8 4, 8 8 and 9 2 are etched, the charge damage preventing film 80 can be etched under the same processing conditions as those of the wiring layers 8.4, 88, 92. Further, when the thickness of the charge damage preventing film 80 is larger than 50 A, the wiring resistance is increased or the wiring layer is etched. Further, when the thickness of the charging damage preventing film 80 is less than 1 〇 A, the occurrence of charging damage cannot be sufficiently suppressed. Further, when the charge damage preventing film 80 is formed to prevent the film formation process, it is preferable to set the sputtering yield within the range of 0.9 to 1. latomsWon. In the case of the sputtering yield in this range, the balance between the amount of atoms and ions which occur during sputtering is difficult to cause charging due to charge displacement during charging in the film formation, and the state is electrically neutralized. In other words, at the time of the sputtering yield outside the above range, when the charge damage preventing film 80 is formed, the charge -15-200836250 is prevented from being damaged by the charging of the film body. Here, the sputtering yield indicates the easiness of sputtering in a number of 。. The sputtering yield is determined by the kind of rare gas and the ion energy (eV) supplied when the plasma is generated. The ion energy (eV) is dependent on the voltage applied to the metal target 62 by the DC power source 64 in Fig. 1. An example of the sputtering yield per ion is shown in Chapter 8 of the "New Vacuum Handbook" (OHMSHA, Ltd., ULVAC, Inc., edited in August 2002) (pages 25 to 258) ). For example, when the ion energy is 400 00 eV, the sputtering yield is in the range of 0.9 to 1. latoms/ion, and a material having less metal contamination such as Co, Ge, Ru, or the like can be selected to be used as a charge damage prevention. The constituent material of the film 80. Further, when such a charge damage preventing film 80 is initially formed as a base film, a metal film which is easily damaged by charging, such as an A1 film (containing an A1 alloy), is formed in the upper layer by sputtering. , W (tungsten) film, Cu (copper) film, Ti (titanium) film, Ta (molybdenum) film, or metal nitride film such as TiN film, TaN film, etc., may also be charged by the above-mentioned conductivity of the lower layer The damage preventing film 80 disperses the charged charges. That is, it does not cause damage to the charge. Here, each embodiment will be described in more detail. In the first embodiment shown in Fig. 2A, a Co film is used as the charge damage preventing film 80, a TiN film is used as the first film 82, and an A1 layer or a W layer is used as the wiring layer 84. Further, the A1 layer contains, for example, an Al alloy layer containing Cu as an Al alloy film. At this time, the 'TiN film functions as a barrier layer. Further, at least the TiN film for charging the damage preventing film 80 and the first film 82 is formed by sputtering from -16 to 200836250. In the second embodiment shown in Fig. 2B, a Co film is used as the charge damage preventing film 80, a Ti film is used as the first film 82, and a TiN film is used as the second film 86, and the A1 layer is used. Or the W layer is used as the wiring layer 88. Further, in this case, the A1 layer contains an alloy layer such as an A1 alloy layer containing Cu. In this case, the layer structure formed of the Ti film and the TiN film functions as a barrier layer. Here, at least the Ti film of the charge damage preventing film 80 and the first film 82 is formed by sputtering. Further, in the third embodiment, which is not shown in Fig. 2C, a Co film is used as the charge damage preventing film 80, a TaN film is used as the first film 82, and a Ta film is used as the second film 86. The Cu film of the film is used as the third film, and the Cu layer is used as the wiring layer 92. Further, at this time, the layer structure composed of the TaN film and the Ta film functions as a barrier layer. Here, at least the charge damage preventing film 80 and the TaN film belonging to the first film 82 are formed by sputtering. Further, the third film 86 is a mask film formed by forming a thin Cu film by sputtering. Starting from the masking film, a wiring layer 92 composed of a Cu layer is formed by electroplating. Further, the laminated structure of each embodiment is merely an example. That is, the present invention is not limited to the laminated structure of each of the above-described embodiments. [Experiment for confirming the effect of the present invention] Here, an experiment for confirming the effects of the present invention described above is performed, and the evaluation result will be described. Here, the experiment was to form a thin film laminated structure of the embodiment of -17-200836250 shown in Fig. 2A on a semiconductor wafer. Specifically, a co film is formed by sputtering to serve as the charge damage preventing film 80, and a TiN film is formed as a first film 82 by sputtering. After the TiN film was formed, a leakage current was measured with respect to the TiN film. Here, the Co film belonging to the charge damage preventing film 80 has a film thickness of about 10 to 30 A. Further, the TiN film belonging to the first film 82 has a film thickness of about 300 A. Further, as a semiconductor wafer to which film formation is applied, a special planar antenna substrate is used because of measurement resistance to charging. The antenna ratio (S1/S2) of the planar antenna substrate is "106". This planar antenna substrate is referred to as a so-called TEG (this antenna configuration is shown in Fig. 5). Further, the wiring layer 84 is not formed here. The reason for this is that the presence or absence of charging damage depends only on whether or not the charging of the first film 82 directly formed on the charging damage preventing film 80 is damaged. Therefore, the film formation of the wiring layer 84 does not require the above measurement. . Further, in the comparative example, the TiN film was directly formed by sputtering without forming a Co film. Figure 4 is a graph showing the presence or absence of charging damage. The horizontal axis is the leakage current and the vertical axis is the degree distribution. In Fig. 4, a curve A corresponds to a film structure of a comparative example formed of a TiN film, and a curve B corresponds to a film structure formed by a TiN film/Co film according to the method of the present invention. The leakage current is 1 (Γ9Α or more, which is NG (poor) defective product. As shown in Fig. 4, in the case of the comparative example of the curve ,, the pass rate is about 15%, and the defective rate is also about 85%. In the case of the method of the present invention of the curve B, the pass rate is 100%, and the defect rate is 0%, which is a good result. -18- 200836250 Others, even when the TaN film is formed as the first film 82 When a Ti film which is a good conductive material is formed, it is also confirmed that the effect of the TiN film equivalent to the above-described experiment or the above-described excellent effect is exhibited. Further, the semiconductor wafer is exemplified as being processed here. The present invention is not limited thereto, and the present invention can also be applied to a glass substrate, an L c D substrate, a ceramic substrate, etc. [Brief Description of the Drawing] Fig. 1 is a view showing the electric power for forming the thin film forming method according to the present invention. A cross-sectional view showing an example of a slurry film forming apparatus. Fig. 2 to Fig. 2C are cross-sectional views showing an example of a laminated structure of a film formed by each embodiment of the method of the present invention. Fig. 3 is a view showing the method of the present invention Engineering drawings of various embodiments Fig. 4 is a graph showing the presence or absence of charging damage. Fig. 5 is a plan view showing the antenna structure of an antenna substrate called TEG. Fig. 6A and Fig. 6B show the past by sputtering. Explanation of one of the film methods. [Explanation of main component symbols] 2: Insulation layer 4: Concave portion 6: Contact portion -19- 200836250 8 · Ti film 1 0 : TiN film 1 2 : Barrier layer 1 4 : Wiring layer 18: Processing container 20: Bottom 22: Exhaust port 24: Throttle valve 26: Vacuum pump 2 8: Mounting table 28A: Mounting table body 2 8 B: Electrostatic chuck 3 0: Gas channel 3 2: Strut 34 : metal telescopic tube 3 6 : cold coal circulation path 3 8 : support pin 4 0 : pin insertion hole 42 : gate valve 44 : wiring 4 6 : bias power supply 48 : transmission plate 5 0 : sealing member 5 2 : processing space - 20 200836250 5 4 : Plasma generation source 5 6 : Induction line 圏 5 8 : Local frequency power supply 6 0 : Resistor board 6 2 : Metal target 6 4 : DC power supply 66 : Protective cover 68 : Gas inlet 70 : Gas control Part 72: Device control unit 74: Memory medium 80: Charging damage preventing film 82: First film 84: Wiring layer 8 6 : Second film 8 8 : Wiring layer 90: Third film 9 2 : Wiring S: Wafer -21--