TW202143292A - 具有結晶矽與富阱多晶矽層的晶圓 - Google Patents

具有結晶矽與富阱多晶矽層的晶圓 Download PDF

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TW202143292A
TW202143292A TW109144121A TW109144121A TW202143292A TW 202143292 A TW202143292 A TW 202143292A TW 109144121 A TW109144121 A TW 109144121A TW 109144121 A TW109144121 A TW 109144121A TW 202143292 A TW202143292 A TW 202143292A
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安東尼Ｋ 史坦普
史蒂芬Ｍ 尚克
約翰Ｊ 貝肯瑞
威霍 詹恩
莫納漢 約翰Ｊ 詹艾立斯
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美商格芯（美國）集成電路科技有限公司
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Abstract

本發明關於半導體結構，更具體地，關於具有結晶矽和富阱多晶矽層的晶圓及其製造方法。結構包含：絕緣層上半導體(SOI)晶圓，其由下部結晶半導體層、在下部結晶半導體層之上的多晶矽層、在多晶矽層之上的上部結晶半導體層、在上部結晶半導體層之上的埋層絕緣體層、以及在埋層絕緣體層之上的頂部結晶半導體層所組成。

Description

具有結晶矽與富阱多晶矽層的晶圓
本發明關於半導體結構，且更具體地，關於具有結晶矽和富阱多晶矽區域的晶圓及其製造方法。
塊狀矽基板比絕緣層上矽(SOI)基板便宜。一般而言，SOI基板包含矽的薄元件層、處理基板、及薄埋層氧化物(BOX)層，其物理地分離並電性地隔離元件層與處理基板。
與內建在塊狀矽基板中的類似元件相比，使用SOI技術製造的元件可表現出某些性能改進。舉例來說，與SOI基板相反，塊狀矽基板的特徵在於元件與諧波產生之間的隔離不佳。高電阻率晶圓用於約1至10GHz射頻應用，以減少基板射頻耗損。
在本發明的一態樣中，一結構包含：一絕緣層上半導體(SOI)晶圓，其包含一下部結晶半導體層、在下部結晶半導體層之上的一多晶矽層、在多晶矽層之上的一上部結晶半導體層、在上部結晶半導體層之上的一埋層絕緣體層、以及在埋層絕緣體層之上的一頂部結晶半導體層。
在本發明的一態樣中，一結構包含：一晶圓，其由一富阱多晶矽層和在該阱多晶矽層上方的一結晶半導體材料所組成；一埋層氧化物 層，在結晶半導體材料的一表面上；以及一結晶半導體層，在埋層氧化物層之上。
在本發明的一態樣中，一方法包含：在一晶圓中在一單晶部分之下形成一富阱部分；在單晶部分之上形成一絕緣體層，單晶部分在富阱部分與絕緣體層之間提供一隔離；以及在絕緣體層之上形成一半導體層。
10:結構
10a:結構
12:晶圓
12a:單晶材料
12b:再結晶區域
14:氧化物
16:非晶區域
18:富阱多晶矽層
18a:富阱多晶矽層
20:氧化物層
22:基板
24:氧化物材料
100:氫佈植區域
120:晶圓
180:矽層
在下面的詳細描述中，藉由本發明的示例性具體實施例的非限制性示例，並參考所提到的複數個附圖來描述本發明。
圖1顯示了根據本發明各態樣的晶圓；
圖2顯示了根據本發明各態樣的晶圓中的非晶區域以及其他特徵以及相應的製造程序；
圖3顯示了根據本發明各態樣的晶圓的再結晶部分以及其他特徵以及相應的製造程序；
圖4顯示了根據本發明各態樣的絕緣層上基板技術的形成以及其他特徵以及相應的製造程序；
圖5顯示了根據本發明各態樣的具有與多晶矽層分離的單晶基板的絕緣層上基板技術以及其他特徵以及相應的製造程序；以及
圖6-8顯示了根據本發明其他態樣的晶圓和相應的製造程序。
本發明關於半導體結構，且更具體地，關於具有結晶矽和富阱多晶矽層的晶圓及其製造方法。更具體地，本發明提供了一種絕緣層上矽(SOI)晶圓，其具有將富阱多晶矽層與埋層氧化物層分離的結晶矽，且本發明提供了製造方法。有利地，除了其他優點之外，本發明為場效電晶體提供了改良的線性度(linearity)。
在具體實施例中，晶圓為絕緣層上基板(SOI)技術。晶圓包含薄矽層、埋層氧化物層、和具有富阱多晶矽層的單晶矽處理晶圓。薄矽層可為單晶材料，例如單晶矽。矽層和單晶矽也可由其他單晶基板材料組成。富阱多晶矽層在埋層氧化物層之下並與之分離。在另外的具體實施例中，在埋層氧化物層下方的結晶矽可用於FET或NPN本體接觸，且富阱多晶矽層將提供改良的線性度。
在更特定的具體實施例中，結構包含基板和富阱層。在富阱層之上設置第一結晶層，且在第一結晶層上方具有介電層(例如，埋層氧化物層)。第一結晶層將在富阱層和介電層之間提供隔離。在埋層介電層之上設置第二結晶層，從而形成具有與埋層氧化物層分離的富阱層的SOI晶圓。在具體實施例中，第一和第二結晶層可為單晶矽，且埋層介電層可為氧化物材料。此外，在具體實施例中，富阱層包含多晶矽結晶材料。
可使用多種不同的工具以多種方式來製造本發明的結構。但是，一般而言，使用方法和工具來形成尺寸在微米和奈米級的結構。已從積體電路(IC)技術採用了用於製造本發明結構的方法(即技術)。舉例來說，結構建立在晶圓上，並實現於晶圓頂部上藉由光學微影製程來圖案化的材料膜中。特別地，結構的製造使用三個基本的構建塊：(i)在基板上沉積材料的薄膜；(ii)藉由光學微影成像在膜的頂部施加圖案化光罩；以及(iii)對光罩選擇性地蝕刻膜。
圖1顯示了根據本發明各態樣的晶圓。更具體地，圖1的結構10包含使用作為前端模組的處理晶圓12，且在示例性具體實施例中，處理晶圓12具有用於RF元件應用的高電阻率。舉例來說，晶圓12的電阻率可為高電阻率，例如但不限於1000ohm-cm或更大。晶圓12可由單晶材料12a組成。舉例來說，單晶材料12a可為單晶Si材料。在進一步的具體實施例中，單晶材料12a可為其他單晶半導體材料，例如SiGe、SiC、Ge等，且可選擇性地接合至玻璃或藍寶石(也由參考符號12a表示)。可在晶圓12上形成選擇性的氧化物材料層14。在具體實施例中，作為示例，選擇性的氧化物材料14可具有約50nm的厚度，且可使用熱氧 化形成，例如使用在熔爐中1000℃的氧化來形成。
圖2顯示了延伸到晶圓12中的非晶區域16。在具體實施例中，非晶區域16由例如晶圓12的表面上的非晶矽組成，且延伸到晶圓的一定深度內。藉由使用佈植製程使晶圓12非晶化來製造非晶區域16，該佈植製程低於臨界劑量，其防止晶圓12(例如單晶材料12a)的再結晶。在具體實施例中，非晶區域16可通過塗層(例如氧化物材料14)或在晶圓12的裸露表面上植入。在具體實施例中，佈植製程可為氬佈植製程，其劑量等級為1E14至1.5E15，且在較佳具體實施例中為1.25E15。植入物可使用氬或其他植入元素，例如其他惰性氣體，像是其他稀有氣體(如氙、鍺、氮氣或氧氣等)。在具體實施例中，非晶區域16在其表面上具有幾十奈米厚的結晶矽層，其在隨後的退火步驟中形成用於非晶矽再結晶的晶種。
在圖3中，對晶圓12進行快速熱退火製程，以使晶圓12的表面再結晶，從而在晶圓12的表面處形成單晶區域12b。快速熱退火製程也將在再結晶區域(層)12b下方留下一或多個多晶矽或富阱多晶矽層18。本技術領域中具有通常知識者應理解到，富阱多晶矽層18將有利地提供改良的線性度，且將能夠固定閘極偏壓。快速熱退火製程可在900℃至1150℃之間的溫度下進行0到10秒。在具體實施例中，熱退火製程為在1000℃下的尖波退火(例如0秒)。在具體實施例中，多晶矽或富阱多晶矽層為10nm至500nm厚，且在一具體實施例中為50nm厚。
如圖4所示，顯示了矽晶圓120與圖3的晶圓。矽晶圓120包含矽層180與氧化的下表面層20，其中氧化的下表面層20係例如通過1000℃的熱氧化形成厚度為0.1至5微米，且在一具體實施例中的厚度為0.4微米。(儘管本文考慮了其他尺寸)。晶圓120包含氫佈植層100，其在下表面之下為數十奈米或數百奈米，如本技術領域中已知的。如箭頭所代表，將晶圓120接合到晶圓12。接著，使用例如本技術領域中已知的SmartcutTM製程，沿著氫佈植區域100分離晶圓120，並接著進行如本領域中已知的平坦化製程，其產生了圖5中代表性地示出 的結構。用以形成晶圓的製程進一步顯示於例如美國專利第5,374,564號，其整體內容併入本文作為參考。
參照圖5，應當理解，絕緣體層14和20將在完成的晶圓中形成埋層氧化物層(BOX)，如圖5所示。儘管在圖式中分別畫出了氧化物14和20，但它們在層20的氧化步驟過程中將合併成單一的氧化物層。可替代地，可省略氧化物層14，且可僅使用氧化物層20來形成BOX層。如果是這種情況，則可在晶圓(例如，施體晶圓)120或晶圓(例如，受體晶圓)12上形成氧化物層20。
此外，如圖5所示，在沿著氫佈值區域100將晶圓120分離之後，它將形成現在接合到絕緣體層14、20的基板22，例如，其形成了SOI技術的上部。基板22可為單晶矽或其他合適的單晶半導體材料，如本文中作為示例所描述的。以此方式，晶圓現在是絕緣層上矽(SOI)基板，在再結晶區域12b下方具有富阱多晶矽層18，並藉由再結晶區域12b與氧化物層14/20分離。亦即，再結晶區域12b為中間層，其防止了富阱多晶矽層18與絕緣體層20(例如BOX)之間的直接接觸。在富阱多晶矽層18之下還有一結晶底層，例如單晶矽層12a。
圖6至8顯示了根據本發明的其他態樣的晶圓和相應製造程序，其中富阱多晶矽區域18、18a延伸到區域18a中的處理晶圓12表面。更具體地，圖6中所示的結構10a包含在晶圓12上方的圖案化材料24。在具體實施例中，圖案化材料24為在佈植製程(如箭頭所示)之前沉積和圖案化的氧化物材料。圖案化為傳統的微影和蝕刻製程。舉例來說，在沉積氧化物材料24之後，在氧化物材料24上形成的抗蝕劑暴露於能量(光)，以形成圖案(開口)。使用具有選擇性化學反應的蝕刻製程(例如反應性離子蝕刻(RIE))，來經由開口移除氧化物材料，從而留下圖6所示的氧化物材料24的圖案。接著，可藉由傳統的氧灰化製程或其他已知的剝離技術來移除抗蝕劑。在圖案化製程之後，製造方法繼續進行如本文已描述的佈植製程，不同之處在於氧化物材料24將阻擋一些植入物到晶圓12中。
在圖7中，藉由使用選擇性化學反應的傳統蝕刻製程來移除氧化物材料。對晶圓12進行快速熱退火製程，以使晶圓12的表面再結晶，從而在晶 圓12的表面上形成單晶區域12b，並在單晶區域12b的下方形成與單晶區域12b相鄰的富阱多晶矽層18a。
在此具體實施例中，快速熱退火製程將留下富阱多晶矽延伸區域18a，其延伸到單晶區域12b的表面，其圖案對應於圖案化氧化物材料的圖案。富阱多晶矽延伸區域18a也由單晶區域12b所圍繞，一部分與埋層氧化物層20接觸(見圖8)，其餘部分藉由單晶區域12b而與埋層氧化物層20隔開。快速熱退火製程可在介於900℃至1150℃之間的溫度下進行0到10秒。在具體實施例中，熱退火製程為在1000℃下的尖波(例如，0秒)。
如圖8所示，絕緣體或介電層(例如，氧化物)20沉積在晶圓12上方，更具體為沉積在再結晶區域12b和延伸至再結晶區域12b的表面的富阱多晶矽層18a上方。層20可藉由任何傳統合適的製程形成，例如藉由氧的佈植(SIMOX)、沉積、熱氧化及/或其他合適的製程來進行分離。
仍參考圖8，基板22沉積在層20之上。基板22可為單晶矽或其他合適的單晶基板，如本文所述。在具體實施例中，基板22可直接接合至氧化物層20(例如BOX)，或可首先接合至單獨的氧化物材料，該氧化物材料繼而使用晶圓接合及/或其他合適的方式接合至層20，如本文所述。以此方式，晶圓現在為絕緣層上矽(SOI)基板，在其下方具有富阱多晶矽層18、18a且由再結晶區域12b所圍繞，並藉由再結晶區域12b而與氧化物層20部分地隔離。
本文所述的晶圓可用於晶片上系統(SoC)技術中。本領域技術中具有通常知識者應理解到，SoC為將電子系統的所有組件整合在單一晶片或基板上的積體電路(也稱作「晶片」)。由於組件整合在單一基板上，因此與具有相同功能的多晶片設計相比，SoC消耗的功率少得多，佔用的面積也少得多。因此，SoC正在成為移動計算(例如智能手機)和邊緣計算市場中的主導力量。SoC也常用於嵌入式系統和物聯網中。
上述方法用於積體電路晶片的製造中。所產生的積體電路晶片可由製造商以原始晶圓形式(即，具有多個未封裝晶片的單個晶圓)、裸露晶粒、 或以封裝形式來分佈。在後者情況下，晶片安裝在單晶片封裝中(例如塑料載體，其引線固定在主機板或其他更高階載體上)，或安裝在多晶片封裝中(例如陶瓷載體，其具有一或兩個表面互連或埋層互連)。在任何情況下，接著，晶片與其他晶片、離散電路元件、及/或其他信號處理裝置整合在一起，作為(a)中間產品(例如主機板)或(b)最終產品的一部分。最終產品可為包含積體電路晶片的任何產品，範圍從玩具和其他低端應用到具有顯示器、鍵盤或其他輸入裝置、及中央處理器的高端電腦產品。
為了說明的目的已經提出了對本發明的各種具體實施例的描述，但是這些描述並無意為窮盡性的或限於所揭露的具體實施例。在不脫離所描述的具體實施例的範疇和精神的情況下，許多修改和變化對於本技術領域中具有通常知識者將是顯而易見的。本文所使用的術語係選擇用以最佳地解釋具體實施例的原理、對市場上發現的技術的實際應用或技術上的改進、或使本技術領域中具有通常知識者能夠理解本文所揭露的具體實施例。
12:晶圓
12a:單晶材料
12b:再結晶區域
14:氧化物
18:富阱多晶矽層
20:氧化物層
22:基板

Claims (20)

  1. 一種結構，包含一絕緣層上半導體(SOI)晶圓，該SOI晶圓包含一下部結晶半導體層、在該下部結晶半導體層之上的一多晶矽層、在該多晶矽層之上的一上部結晶半導體層、在該上部結晶半導體層之上的一埋層絕緣體層、以及在該埋層絕緣體層之上的一頂部結晶半導體層。
  2. 如請求項1之結構，其中該埋層絕緣體層為一埋層氧化物層，該下部結晶半導體層為一單晶矽，且該上部結晶半導體層為一單晶矽。
  3. 如請求項2之結構，其中該單晶矽為高電阻率矽。
  4. 如請求項3之結構，其中該高電阻率矽係>1000ohm-cm。
  5. 如請求項1之結構，其中該多晶矽層為富阱(trap rich)。
  6. 如請求項1之結構，其中該上部結晶半導體層將該多晶矽層與該埋層絕緣體層隔開。
  7. 如請求項1之結構，其中該下部結晶半導體層和該上部結晶半導體層為一處理晶圓(handle wafer)，且該多晶矽層嵌入在該下部結晶半導體層和該上部結晶半導體層之間的該處理晶圓內。
  8. 如請求項1之結構，其中該多晶矽層包含一延伸區，該延伸區延伸到該上部結晶半導體層的一表面並與該埋層絕緣體層的一部分接觸。
  9. 一種結構，包含：
    一晶圓，其由一富阱多晶矽層和在該富阱多晶矽層上方的一結晶半導體材料所組成；
    一埋層氧化物層，在該結晶半導體材料的一表面上；以及
    一結晶半導體層，在該埋層氧化物層之上。
  10. 如請求項9之結構，其中在該富阱多晶矽層之上的該結晶半導體材料將該富阱多晶矽層與該埋層氧化物層隔離。
  11. 如請求項9之結構，其中該結晶半導體材料和該結晶半導體層為單晶材料。
  12. 如請求項11之結構，其中該單晶材料為單晶矽基材料。
  13. 如請求項12之結構，其中該晶圓、該埋層氧化物層和該結晶半導體層為絕緣層上半導體(SOI)技術。
  14. 如請求項12之結構，其中該晶圓為一處理晶圓，且該富阱多晶矽層嵌入在該處理晶圓內。
  15. 如請求項14之結構，其中該單晶基板材料在該富阱多晶矽層的上方和下方。
  16. 如請求項15之結構，其中該富阱多晶矽層包含延伸至其上方的該單晶部分的一表面的一延伸部分，並與該埋層氧化物層的一部分接觸。
  17. 如請求項15之結構，其中該富阱多晶矽層的該延伸部分在其側面上由該晶圓的該單晶半導體材料所包圍。
  18. 一種方法，包含：
    在一晶圓中在一單晶部分之下形成一富阱部分；
    在該單晶部分之上形成一絕緣體層，該單晶部分在該富阱部分與該絕緣體層之間提供一隔離；以及
    在該絕緣體層之上形成一半導體層。
  19. 如請求項18之方法，其中形成該富阱部分和該單晶部分包含非晶化該單晶部分，接著進行一快速熱退火製程。
  20. 如請求項19之方法，其中該非晶化為使用低於一臨界劑量的一惰性氣體的一佈植製程，其防止一晶圓的再結晶，且該快速熱退火製程使該晶圓再結晶，以在該富阱部分之上形成該單晶部分。
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TWI775241B (zh) 2022-08-21
US11271079B2 (en) 2022-03-08

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