TW202117973A - Semiconductor device and method for manufacturing semiconductor device - Google Patents

Semiconductor device and method for manufacturing semiconductor device Download PDF

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Publication number
TW202117973A
TW202117973A TW109137027A TW109137027A TW202117973A TW 202117973 A TW202117973 A TW 202117973A TW 109137027 A TW109137027 A TW 109137027A TW 109137027 A TW109137027 A TW 109137027A TW 202117973 A TW202117973 A TW 202117973A
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Taiwan
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lead frame
semiconductor device
sealing resin
wiring substrate
lead
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TW109137027A
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Chinese (zh)
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��田太
羽鳥行範
澤村芳行
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日商新光電氣工業股份有限公司
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Publication of TW202117973A publication Critical patent/TW202117973A/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49568—Lead-frames or other flat leads specifically adapted to facilitate heat dissipation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H01L23/14—Mountings, e.g. non-detachable insulating substrates characterised by the material or its electrical properties
    • H01L23/145—Organic substrates, e.g. plastic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/367—Cooling facilitated by shape of device
    • H—ELECTRICITY
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    • H01L23/00—Details of semiconductor or other solid state devices
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    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/373—Cooling facilitated by selection of materials for the device or materials for thermal expansion adaptation, e.g. carbon
    • H01L23/3736—Metallic materials
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    • H01L23/49541—Geometry of the lead-frame
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    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49579—Lead-frames or other flat leads characterised by the materials of the lead frames or layers thereon
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    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
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    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
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    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
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    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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    • H01L2224/732—Location after the connecting process
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    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
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  • Lead Frames For Integrated Circuits (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)

Abstract

A semiconductor device includes: a lead frame that is formed of metal; a wiring substrate that is opposed to the lead frame; an electronic component that is disposed between the lead frame and the wiring substrate; a connection member that connects lead frame and the wiring substrate; and encapsulating resin that is filled between the lead frame and the wiring substrate and covers the electronic component and the connection member. The lead frame includes: a first surface opposed to the wiring substrate and covered by the encapsulating resin; a second surface located on a back side of the first surface and exposed from the encapsulating resin; and a side surface neighboring first surface or the second surface, at least a portion of the side surface exposed from the encapsulating resin.

Description

半導體裝置、以及半導體裝置的製造方法 Semiconductor device and semiconductor device manufacturing method

本發明係關於半導體裝置、以及半導體裝置的製造方法。 The present invention relates to a semiconductor device and a method of manufacturing the semiconductor device.

近年來，為了實現高密度的零件安裝，例如在基板的內部內置有IC(Integrated Circuit，積體電路)晶片等電子零件的半導體裝置受到矚目。這種半導體裝置例如具有兩個有機基板，並在一方有機基板安裝有IC晶片等電子零件，這些電子零件夾在一方有機基板與另一方有機基板之間。在兩個有機基板之間的空間，例如填充有密封樹脂。 In recent years, in order to achieve high-density component mounting, for example, semiconductor devices in which electronic components such as IC (Integrated Circuit) chips are built in the inside of a substrate have attracted attention. Such a semiconductor device has, for example, two organic substrates, and electronic components such as an IC chip are mounted on one organic substrate, and these electronic components are sandwiched between one organic substrate and the other organic substrate. The space between the two organic substrates is filled with a sealing resin, for example.

如此，藉由在兩個有機基板之間內置電子零件，能夠實現三維的零件安裝，在有機基板的外側的表面也安裝電子零件，從而能夠實現半導體裝置的高密度化及小型化。 In this way, by embedding electronic components between the two organic substrates, three-dimensional component mounting can be achieved, and electronic components can also be mounted on the outer surface of the organic substrate, thereby enabling high-density and miniaturization of semiconductor devices.

[先前技術文獻] [Prior Technical Literature]

[專利文獻] [Patent Literature]

[專利文獻1]國際公開第2007/069606號 [Patent Document 1] International Publication No. 2007/069606

然而，在內置有電子零件的半導體裝置中，存在難以使由電子零件產生的熱充分散熱的問題。即，由於內置的電子零件的周圍由導熱性低的密封樹脂包覆，所以電子零件產生的熱，從導熱性高的金屬的端子經由有機基板而散熱。然而，在電子零件的表面積中端子所占的面積小，散熱效率不太高。因此，特別係在電子零件的發熱量較大的情況下，難以從這些電子零件的端子充分散熱。 However, in semiconductor devices incorporating electronic components, there is a problem that it is difficult to sufficiently dissipate heat generated by the electronic components. That is, since the surroundings of the built-in electronic components are covered with the low thermal conductivity sealing resin, the heat generated by the electronic components is radiated from the terminals of the high thermal conductivity metal via the organic substrate. However, the area occupied by the terminal in the surface area of the electronic component is small, and the heat dissipation efficiency is not very high. Therefore, it is difficult to sufficiently dissipate heat from the terminals of these electronic components, especially when the heat generation amount of electronic components is large.

本發明公開的技術鑒於上述問題而完成，其目的在於提供一種能夠提高散熱效率的半導體裝置、以及半導體裝置的製造方法。 The technology disclosed in the present invention has been completed in view of the above-mentioned problems, and its object is to provide a semiconductor device capable of improving heat dissipation efficiency, and a method of manufacturing the semiconductor device.

本發明公開的半導體裝置在一個形態中，包括：引線框架，其由金屬構成；佈線基板，其與上述引線框架相向；電子零件，其配置在上述引線框架與上述佈線基板之間；連接構件，其將上述引線框架與上述佈線基板連接；以及密封樹脂，其填充在上述引線框架與上述佈線基板之間，並包覆上述電子零件及上述連接構件，上述引線框架具有：第一面，其與上述佈線基板相向，並由上述密封樹脂包覆；第二面，其位於上述第一面的背面側，並從上述密封樹脂露出；以及側面，其與上述第一面或上述第二面相鄰，至少一部分從上述密封樹脂露出。 The semiconductor device disclosed in the present invention includes, in one form, a lead frame made of metal; a wiring substrate facing the lead frame; electronic components arranged between the lead frame and the wiring substrate; a connecting member, It connects the lead frame and the wiring substrate; and a sealing resin filled between the lead frame and the wiring substrate and covering the electronic components and the connecting member, the lead frame having: a first surface that is connected to The wiring board faces each other and is covered with the sealing resin; a second surface which is located on the back side of the first surface and is exposed from the sealing resin; and a side surface which is adjacent to the first surface or the second surface , At least a part is exposed from the above-mentioned sealing resin.

根據本發明公開的半導體裝置、以及半導體裝置的製造方法的一個形態，可實現能夠提高散熱效率的效果。 According to one aspect of the semiconductor device and the method of manufacturing the semiconductor device disclosed in the present invention, it is possible to achieve the effect of improving heat dissipation efficiency.

100:半導體裝置 100: Semiconductor device

100a:臺階 100a: Step

101:密封樹脂 101: Sealing resin

102:密封樹脂 102: Sealing resin

103:電子零件 103: Electronic parts

103a:端子 103a: Terminal

103b:焊料 103b: Solder

105:TIM 105: TIM

106:密封樹脂 106: Sealing resin

110:佈線基板 110: Wiring board

110a:集合體 110a: aggregate

110b:框體 110b: frame

111:基板 111: substrate

112:阻焊層 112: Solder mask

112a:開口部 112a: opening

113:上表面焊盤 113: Upper surface pad

114:保護絕緣層 114: Protective insulating layer

114a:開口部 114a: opening

115:下表面焊盤 115: bottom surface pad

115a:下表面焊盤 115a: bottom surface pad

115b:下表面焊盤 115b: bottom surface pad

115c:下表面焊盤 115c: bottom surface pad

120:引線框架 120: lead frame

120a:集合體 120a: aggregate

120b:框體 120b: frame

121:引線 121: Lead

121’:支承用引線 121’: Lead wire for support

121a:側面 121a: side

121b:槽部 121b: Groove

122:散熱板 122: heat sink

122a:縫隙 122a: gap

123:鍍層 123: Plating

124:鍍層 124: Plating

125:氧化膜 125: Oxide film

125a:位置 125a: location

126:引線 126: Lead

127:鍍層 127: Plating

128:鍍層 128: Plating

129:臺階面 129: Step Surface

130:連接構件 130: connecting member

131:芯 131: Core

132:焊料 132: Solder

135:連接構件 135: Connection member

136:焊料 136: Solder

140:IC晶片 140: IC chip

141:焊錫凸塊 141: Solder bump

142:底部填膠 142: bottom filling

143:焊錫凸塊 143: Solder bump

150:電子零件 150: electronic parts

150a:端子 150a: terminal

150b:焊料 150b: solder

200:安裝基板 200: mounting base

210:焊盤 210: pad

220:阻焊層 220: Solder mask

230:焊料 230: Solder

300:金屬板 300: metal plate

310:抗蝕劑膜 310: resist film

310a:空隙 310a: gap

320:抗蝕劑膜 320: resist film

320a:空隙 320a: gap

A:切割線 A: Cutting line

B:範圍 B: range

圖1(a)、圖1(b)係表示關於一實施形態的半導體裝置的外觀的圖。 1(a) and 1(b) are diagrams showing the appearance of a semiconductor device according to an embodiment.

圖2係表示關於一實施形態的半導體裝置的截面的示意圖。 FIG. 2 is a schematic diagram showing a cross-section of a semiconductor device according to an embodiment.

圖3係表示佈線基板的製造方法的流程圖。 Fig. 3 is a flowchart showing a method of manufacturing a wiring board.

圖4係表示佈線基板的截面的示意圖。 Fig. 4 is a schematic diagram showing a cross section of the wiring board.

圖5係說明零件的安裝的圖。 Fig. 5 is a diagram illustrating the installation of parts.

圖6係表示佈線基板的結構的平面圖。 Fig. 6 is a plan view showing the structure of the wiring board.

圖7係表示佈線基板的集合體的圖。 Fig. 7 is a diagram showing an assembly of wiring boards.

圖8係表示引線框架的製造方法的流程圖。 Fig. 8 is a flowchart showing a method of manufacturing a lead frame.

圖9係說明引線及散熱板的形成步驟的圖。 Fig. 9 is a diagram illustrating the steps of forming the leads and the heat sink.

圖10係說明鍍層的形成步驟的圖。 Fig. 10 is a diagram illustrating the steps of forming a plating layer.

圖11係說明氧化膜的形成步驟的圖。 FIG. 11 is a diagram illustrating the steps of forming an oxide film.

圖12係說明連接構件的搭載步驟的圖。 Fig. 12 is a diagram illustrating a mounting procedure of the connecting member.

圖13係表示引線框架的結構的俯視圖。 FIG. 13 is a plan view showing the structure of the lead frame.

圖14係表示引線框架的集合體的圖。 Fig. 14 is a diagram showing an assembly of lead frames.

圖15係表示半導體裝置的製造方法的流程圖。 FIG. 15 is a flowchart showing a method of manufacturing a semiconductor device.

圖16係說明接合步驟的圖。 Fig. 16 is a diagram illustrating the joining step.

圖17係說明模製步驟的圖。 Fig. 17 is a diagram illustrating the molding step.

圖18係說明零件的安裝的圖。 Fig. 18 is a diagram illustrating the installation of parts.

圖19係說明模製步驟的圖。 Fig. 19 is a diagram illustrating the molding step.

圖20係說明槽部的形成步驟的圖。 Fig. 20 is a diagram illustrating a formation step of a groove portion.

圖21係表示槽部的形成位置的一個示例的圖。 FIG. 21 is a diagram showing an example of the formation position of the groove portion.

圖22係說明分割化步驟的圖。 Fig. 22 is a diagram illustrating the step of segmentation.

圖23係表示切割位置的一個示例的圖。 FIG. 23 is a diagram showing an example of the cutting position.

圖24係說明半導體裝置的安裝的圖。 FIG. 24 is a diagram illustrating the mounting of the semiconductor device.

圖25係表示半導體裝置的變形例的圖。 FIG. 25 is a diagram showing a modification example of the semiconductor device.

圖26係表示半導體裝置的其他變形例的圖。 FIG. 26 is a diagram showing another modification example of the semiconductor device.

圖27係表示半導體裝置的其他變形例的圖。 FIG. 27 is a diagram showing another modification example of the semiconductor device.

圖28係表示半導體裝置的其他變形例的圖。 FIG. 28 is a diagram showing another modification example of the semiconductor device.

圖29(a)、圖29(b)、圖29(c)、圖29(d)係說明關於其他實施形態的引線框架的製造方法的圖。 29(a), FIG. 29(b), FIG. 29(c), and FIG. 29(d) are diagrams illustrating a method of manufacturing a lead frame according to another embodiment.

圖30係表示關於其他實施形態的半導體裝置的截面的示意圖。 FIG. 30 is a schematic diagram showing a cross section of a semiconductor device related to another embodiment.

圖31係表示關於其他實施形態的半導體裝置的截面的示意圖。 FIG. 31 is a schematic diagram showing a cross section of a semiconductor device related to another embodiment.

圖32係表示關於其他實施形態的半導體裝置的截面的示意圖。 FIG. 32 is a schematic diagram showing a cross section of a semiconductor device related to another embodiment.

圖33係說明抗蝕劑膜形成步驟的圖。 FIG. 33 is a diagram illustrating a step of forming a resist film.

圖34係說明蝕刻步驟的圖。 FIG. 34 is a diagram illustrating the etching step.

圖35係表示關於其他實施形態的引線框架的結構的仰視圖。 Fig. 35 is a bottom view showing the structure of a lead frame according to another embodiment.

以下，參照圖式，詳細地說明本發明公開的半導體裝置、以及半導體裝置的製造方法的一實施形態。此外，本發明並非由下述實施形態所限定。 Hereinafter, with reference to the drawings, an embodiment of the semiconductor device and the method of manufacturing the semiconductor device disclosed in the present invention will be described in detail. In addition, this invention is not limited by the following embodiment.

圖1(a)、圖1(b)係表示關於一實施形態的半導體裝置100的外觀的圖。圖1(a)係半導體裝置100的側視圖，圖1(b)係半導體裝置100的仰視圖。此外，在以下的說明中，將使半導體裝置100安裝於安裝基板時靠近安裝基板的面稱為“下表面”，且將遠離安裝基板的面稱為“上表面”，並且以此為基準來規定上下方向，但半導體裝置100可以例如上下翻轉來進行製造及使用，也可以以任意姿態來進行製造及使用。 1(a) and 1(b) are diagrams showing the appearance of a semiconductor device 100 according to an embodiment. FIG. 1(a) is a side view of the semiconductor device 100, and FIG. 1(b) is a bottom view of the semiconductor device 100. In addition, in the following description, the surface close to the mounting substrate when the semiconductor device 100 is mounted on the mounting substrate is referred to as the "lower surface", and the surface away from the mounting substrate is referred to as the "upper surface", and this is used as a reference. The vertical direction is specified, but the semiconductor device 100 may be manufactured and used by turning upside down, for example, or may be manufactured and used in any posture.

圖1(a)、圖1(b)所示的半導體裝置100具有佈線基板110及引線框架120，並具有密封樹脂101及密封樹脂102，該密封樹脂101用於包覆安裝於佈線基板110的上表面的電子零件，該密封樹脂102用於包覆配置成被佈線基板110和 引線框架120夾在中間的電子零件。具體而言，在佈線基板110的上表面，例如安裝有電容器及電感器等電子零件，這些電子零件由密封樹脂101包覆。此外，在佈線基板110的下表面，例如安裝有IC晶片等電子零件，這些電子零件由佈線基板110和引線框架120夾在中間，並且由密封樹脂102包覆。 The semiconductor device 100 shown in FIG. 1(a) and FIG. 1(b) has a wiring substrate 110 and a lead frame 120, and has a sealing resin 101 and a sealing resin 102. The sealing resin 101 is used to cover the wiring board 110 On the upper surface of the electronic components, the sealing resin 102 is used to cover the wiring board 110 and The lead frame 120 sandwiches the electronic part. Specifically, electronic components such as capacitors and inductors are mounted on the upper surface of the wiring board 110, and these electronic components are covered with the sealing resin 101. In addition, electronic components such as IC chips are mounted on the lower surface of the wiring substrate 110. These electronic components are sandwiched between the wiring substrate 110 and the lead frame 120 and covered with the sealing resin 102.

密封樹脂101、102例如為含有氧化鋁、二氧化矽、氮化鋁或碳化矽等無機填料的熱固性的環氧樹脂等絕緣性樹脂。此外，對於密封樹脂102，可以將無機填料的填充率設為70wt%(重量百分比)以上95wt%以下。藉由如此以較高的填充率含有填料，能夠提高密封樹脂102的導熱率。而且，也可以藉由使密封樹脂102含有例如銀等金屬填料，來提高散熱性。在使密封樹脂102含有金屬填料時，為了防止電子零件的短路，最佳使用對表面施加絕緣處理的金屬填料。 The sealing resins 101 and 102 are, for example, insulating resins such as thermosetting epoxy resin containing inorganic fillers such as alumina, silicon dioxide, aluminum nitride, or silicon carbide. In addition, for the sealing resin 102, the filling rate of the inorganic filler may be 70 wt% (weight percent) or more and 95 wt% or less. By containing the filler at a high filling rate in this way, the thermal conductivity of the sealing resin 102 can be improved. In addition, the sealing resin 102 may contain a metal filler such as silver to improve heat dissipation. When the sealing resin 102 contains a metal filler, in order to prevent short-circuiting of electronic parts, it is preferable to use a metal filler having an insulating treatment on the surface.

如圖1(b)所示，由密封樹脂102包覆的引線框架120，具有引線121及散熱板122。引線121及散熱板122的下表面，在半導體裝置100的下表面從密封樹脂102露出。此外，引線121的側方的端部在半導體裝置100的側面從密封樹脂102露出。引線121與佈線基板110的佈線層電性連接，另一方面，散熱板122形成於與安裝在佈線基板110的下表面的電子零件相向的位置。因此，電子零件產生的熱從密封樹脂102傳導至散熱板122，並從面積較大的散熱板122有效地散熱。 As shown in FIG. 1( b ), the lead frame 120 covered with the sealing resin 102 has leads 121 and a heat sink 122. The lower surfaces of the leads 121 and the heat sink 122 are exposed from the sealing resin 102 on the lower surface of the semiconductor device 100. In addition, the side end of the lead 121 is exposed from the sealing resin 102 on the side surface of the semiconductor device 100. The lead 121 is electrically connected to the wiring layer of the wiring substrate 110. On the other hand, the heat dissipation plate 122 is formed at a position facing the electronic components mounted on the lower surface of the wiring substrate 110. Therefore, the heat generated by the electronic component is conducted from the sealing resin 102 to the heat dissipation plate 122, and is effectively dissipated from the heat dissipation plate 122 having a larger area.

半導體裝置100在仰視時具有矩形形狀。在半導體裝置100的下表面的四邊，密封樹脂102及引線框架120被切去而形成有臺階100a。而且，在臺階100a的附近，引線121的側方的端部沿著半導體裝置100的下表面的四邊，從密封樹脂102露出。此外，也可以使引線121的側方的端部不是沿著半導體裝置100的下表面的四邊，而是沿著相向的兩邊，從密封樹脂102露出。 The semiconductor device 100 has a rectangular shape when viewed from the bottom. On the four sides of the lower surface of the semiconductor device 100, the sealing resin 102 and the lead frame 120 are cut away to form a step 100a. Furthermore, in the vicinity of the step 100 a, the side ends of the leads 121 are exposed from the sealing resin 102 along the four sides of the lower surface of the semiconductor device 100. In addition, the lateral ends of the leads 121 may be exposed from the sealing resin 102 along opposite sides instead of along the four sides of the lower surface of the semiconductor device 100.

圖2係表示關於一實施形態的半導體裝置100的截面的示意圖。如圖2所示，半導體裝置100藉由連接構件130使佈線基板110與引線框架120連接而 構成。而且，在佈線基板110的上表面，安裝有電子零件103，這些電子零件103由密封樹脂101密封。此外，在佈線基板110的下表面，安裝有IC晶片140及電子零件150，IC晶片140及電子零件150由密封樹脂102密封。在此，對IC晶片140和電子零件150進行區分，但IC晶片140也為電子零件的一種。 FIG. 2 is a schematic diagram showing a cross-section of a semiconductor device 100 according to an embodiment. As shown in FIG. 2, the semiconductor device 100 is connected to the wiring substrate 110 and the lead frame 120 by the connecting member 130. constitute. Furthermore, electronic components 103 are mounted on the upper surface of the wiring board 110, and these electronic components 103 are sealed with a sealing resin 101. In addition, an IC chip 140 and electronic components 150 are mounted on the lower surface of the wiring board 110, and the IC chip 140 and the electronic components 150 are sealed by the sealing resin 102. Here, the IC chip 140 and the electronic component 150 are distinguished, but the IC chip 140 is also a type of electronic component.

佈線基板110具有基板111、阻焊層112、上表面焊盤113、保護絕緣層114以及下表面焊盤115。此外，在圖2中省略了圖示，但上表面焊盤113與下表面焊盤115藉由設置於基板111中的通孔佈線來電性連接。 The wiring substrate 110 has a substrate 111, a solder resist layer 112, an upper surface pad 113, a protective insulating layer 114, and a lower surface pad 115. In addition, the illustration is omitted in FIG. 2, but the upper surface pad 113 and the lower surface pad 115 are electrically connected by via wiring provided in the substrate 111.

基板111係絕緣性的板狀構件，且係佈線基板110的基材。作為基板111的材料，例如能夠採用使以環氧樹脂為主要成分的熱固性的絕緣性樹脂含浸於作為加強材料的玻璃布(玻璃織布)而固化的玻璃環氧樹脂等。作為加強材料，不限於玻璃布，例如可以採用玻璃不織布、醯胺(aramid)織布、醯胺不織布、液晶聚合物(LCP：Liquid Crystal Polymer)織布、以及LCP不織布等。此外，作為熱固性的絕緣性樹脂，除了環氧樹脂之外，例如可以採用聚醯亞胺樹脂及氰酸酯樹脂等。 The substrate 111 is an insulating plate-shaped member, and is a base material of the wiring substrate 110. As the material of the substrate 111, for example, a glass epoxy resin obtained by impregnating a glass cloth (glass woven cloth) as a reinforcing material with a thermosetting insulating resin containing epoxy resin as a main component and curing it can be used. The reinforcing material is not limited to glass cloth, and for example, glass non-woven fabric, aramid woven fabric, amide non-woven fabric, liquid crystal polymer (LCP: Liquid Crystal Polymer) woven fabric, LCP non-woven fabric, etc. can be used. In addition, as thermosetting insulating resins, in addition to epoxy resins, for example, polyimide resins, cyanate ester resins, and the like can be used.

此外，基板111不限於單層的絕緣性構件，可以係疊層了絕緣層及佈線層的多層結構的疊層基板。在基板111為疊層基板的情況下，將該絕緣層夾在中間的佈線層，藉由貫穿絕緣層的通孔彼此電性連接。作為絕緣層的材料，例如能夠採用環氧樹脂及聚醯亞胺樹脂等絕緣性樹脂，或者在這些樹脂中摻入二氧化矽或氧化鋁等填料而成的樹脂材料。此外，作為佈線層的材料，例如能夠採用銅(Cu)或銅合金。 In addition, the substrate 111 is not limited to a single-layer insulating member, and may be a multilayer substrate having a multilayer structure in which an insulating layer and a wiring layer are laminated. In the case where the substrate 111 is a laminated substrate, the wiring layers sandwiching the insulating layer are electrically connected to each other through through holes penetrating the insulating layer. As the material of the insulating layer, for example, insulating resins such as epoxy resin and polyimide resin, or resin materials in which fillers such as silica or alumina are mixed into these resins can be used. In addition, as the material of the wiring layer, for example, copper (Cu) or a copper alloy can be used.

阻焊層112係包覆基板111的上表面的絕緣層。在阻焊層112的一部分設置有開口部，上表面焊盤113從開口部露出。作為阻焊層112的材料，例如能夠採用環氧類樹脂或丙烯酸類樹脂等絕緣性樹脂。 The solder resist layer 112 is an insulating layer covering the upper surface of the substrate 111. An opening is provided in a part of the solder resist layer 112, and the upper surface pad 113 is exposed from the opening. As the material of the solder resist layer 112, for example, insulating resin such as epoxy resin or acrylic resin can be used.

上表面焊盤113形成於基板111的上表面的佈線層，為了安裝電子零件103，從阻焊層112的開口部露出。在將電子零件103安裝於佈線基板110時，電子零件103的端子103a藉由焊料103b與上表面焊盤113連接。作為上表面焊盤113的材料，與佈線層同樣地，例如能夠採用銅或銅合金。 The upper surface pad 113 is formed on the wiring layer on the upper surface of the substrate 111 and is exposed from the opening of the solder resist layer 112 in order to mount the electronic component 103. When the electronic component 103 is mounted on the wiring board 110, the terminal 103a of the electronic component 103 is connected to the upper surface pad 113 by the solder 103b. As the material of the upper surface pad 113, similar to the wiring layer, for example, copper or copper alloy can be used.

保護絕緣層114係包覆基板111的下表面的絕緣層。在保護絕緣層114的一部分設置有開口部，下表面焊盤115從開口部露出。作為保護絕緣層114的材料，例如能夠採用環氧類樹脂或丙烯酸類樹脂等絕緣性樹脂。 The protective insulating layer 114 is an insulating layer covering the lower surface of the substrate 111. An opening is provided in a part of the protective insulating layer 114, and the lower surface pad 115 is exposed from the opening. As the material of the protective insulating layer 114, for example, insulating resin such as epoxy resin or acrylic resin can be used.

下表面焊盤115形成於基板111的下表面的佈線層，為了進行與連接構件130的連接、以及IC晶片140和電子零件150的安裝，從保護絕緣層114的開口部露出。也就是說，一部分的下表面焊盤115與連接構件130接合。此外，一部分的下表面焊盤115與IC晶片140連接。具體而言，例如藉由焊錫凸塊141來使IC晶片140與下表面焊盤115進行倒裝晶片(flip chip)連接。而且，在佈線基板110與IC晶片140之間填充有底部填膠142。並且，藉由焊料150b來使一部分的下表面焊盤115與電子零件150的端子150a連接。作為下表面焊盤115的材料，與佈線層同樣地，例如能夠採用銅或銅合金。 The lower surface pad 115 is formed on the wiring layer on the lower surface of the substrate 111 and is exposed from the opening of the protective insulating layer 114 for connection with the connection member 130 and mounting of the IC chip 140 and the electronic component 150. That is, a part of the lower surface pad 115 is bonded to the connection member 130. In addition, a part of the lower surface pad 115 is connected to the IC chip 140. Specifically, for example, the IC chip 140 and the lower surface pad 115 are flip-chip connected by solder bumps 141. Furthermore, an underfill 142 is filled between the wiring substrate 110 and the IC chip 140. In addition, a part of the lower surface pad 115 is connected to the terminal 150a of the electronic component 150 by the solder 150b. As the material of the lower surface pad 115, similar to the wiring layer, for example, copper or copper alloy can be used.

引線框架120例如係由銅或銅合金等金屬構成的導電性構件，具有引線121及散熱板122。在引線框架120的下表面，形成有鍍層123，並在半導體裝置100的下表面從密封樹脂102露出。鍍層123例如藉由鍍錫(Sn)或鍍錫鉛合金來形成。 The lead frame 120 is, for example, a conductive member made of metal such as copper or copper alloy, and has leads 121 and a heat sink 122. A plating layer 123 is formed on the lower surface of the lead frame 120 and is exposed from the sealing resin 102 on the lower surface of the semiconductor device 100. The plating layer 123 is formed by, for example, tin (Sn) plating or tin-lead alloy plating.

引線121藉由連接構件130與安裝於佈線基板110的IC晶片140或電子零件103、150電性連接。而且，引線121的下表面及側面121a從密封樹脂102露出而作為外部端子發揮功能。在形成有鍍層123的引線121的下表面的側方端部，設置有臺階。臺階的側方的側面121a在半導體裝置100的側面從密封樹脂102露出。 The lead 121 is electrically connected to the IC chip 140 or the electronic components 103 and 150 mounted on the wiring substrate 110 through the connecting member 130. Furthermore, the lower surface and side surface 121a of the lead 121 are exposed from the sealing resin 102 and function as an external terminal. A step is provided at the side end of the lower surface of the lead 121 on which the plating layer 123 is formed. The side surface 121 a on the side of the step is exposed from the sealing resin 102 on the side surface of the semiconductor device 100.

在引線121的上表面的與連接構件130對應的位置，形成有鍍層124。鍍層124例如由鍍銀(Ag)等貴金屬電鍍形成。而且，在引線121的上表面的鍍層124以外的部分、以及與散熱板122相向的側面，形成有氧化膜125。也就是說，在與密封樹脂102接觸的引線121的上表面及側面，形成有氧化膜125。由於鍍層124的周圍由氧化膜125包圍，所以連接構件130的焊料132不會擴散至鍍層124的周圍，能夠準確地進行引線框架120與連接構件130的位置對齊。此外，作為鍍層124，除了鍍銀之外，也可以採用鍍金(Au)。此外，在引線121的上表面，可以採用以鍍鎳(Ni)和鍍金的順序疊層而成的鍍層，或者以鍍鎳、鍍鈀(Pd)和鍍金的順序疊層而成的鍍層。 A plating layer 124 is formed at a position corresponding to the connection member 130 on the upper surface of the lead 121. The plating layer 124 is formed by noble metal plating such as silver (Ag) plating, for example. In addition, an oxide film 125 is formed on the upper surface of the lead 121 other than the plating layer 124 and the side surface facing the heat sink 122. In other words, the oxide film 125 is formed on the upper surface and the side surface of the lead 121 in contact with the sealing resin 102. Since the periphery of the plating layer 124 is surrounded by the oxide film 125, the solder 132 of the connecting member 130 will not diffuse to the periphery of the plating layer 124, and the position of the lead frame 120 and the connecting member 130 can be accurately aligned. In addition, as the plating layer 124, in addition to silver plating, gold plating (Au) may also be used. In addition, on the upper surface of the lead 121, a plating layer laminated in the order of nickel (Ni) plating and gold plating, or a plating layer laminated in the order of nickel plating, palladium (Pd) and gold plating may be used.

散熱板122與IC晶片140及電子零件150相向。而且，散熱板122將經由密封樹脂102從IC晶片140及電子零件150傳遞的熱，從下表面散熱。由於散熱板122係導熱性高的引線框架120的一部分，且係與IC晶片140及電子零件150相向的面積較大的板狀部分，所以能夠將從密封樹脂102傳遞來的熱高效地散熱。在散熱板122的下表面形成有鍍層123，在與密封樹脂102接觸的散熱板122的上表面及側面，形成有氧化膜125。 The heat dissipation plate 122 faces the IC chip 140 and the electronic components 150. Furthermore, the heat sink 122 dissipates the heat transferred from the IC chip 140 and the electronic component 150 via the sealing resin 102 from the lower surface. Since the heat sink 122 is a part of the lead frame 120 with high thermal conductivity, and is a plate-shaped portion with a large area facing the IC chip 140 and the electronic component 150, the heat transferred from the sealing resin 102 can be efficiently dissipated. A plating layer 123 is formed on the lower surface of the heat sink 122, and an oxide film 125 is formed on the upper surface and side surfaces of the heat sink 122 in contact with the sealing resin 102.

藉由在引線121及散熱板122的與密封樹脂102接觸的面形成氧化膜125，能夠提高引線框架120與密封樹脂102的緊密性。即，藉由氧化膜125所包含的氫氧化物(例如，Cu(OH)2)與密封樹脂102固化而生成的羥基(-OH)之間形成氫鍵，來產生較強的粘結力。由此，藉由在與密封樹脂102接觸的面形成氧化膜125，能夠防止引線框架120與密封樹脂102的剝離，並能夠提高半導體裝置100的可靠性。 By forming the oxide film 125 on the surfaces of the leads 121 and the heat sink 122 that are in contact with the sealing resin 102, the tightness between the lead frame 120 and the sealing resin 102 can be improved. That is, the hydroxide (for example, Cu(OH) 2 ) contained in the oxide film 125 and the hydroxyl group (-OH) generated by curing the sealing resin 102 form a hydrogen bond to generate a strong adhesive force. Thus, by forming the oxide film 125 on the surface in contact with the sealing resin 102, peeling of the lead frame 120 and the sealing resin 102 can be prevented, and the reliability of the semiconductor device 100 can be improved.

連接構件130例如由具有銅芯的錫球等形成，將佈線基板110與引線框架120連接。具體而言，連接構件130具有：大致呈球狀的芯131、以及包覆芯131的外周面的焊料132。作為芯131，能夠採用例如由銅(Cu)、金(Au)、鎳(Ni) 等金屬構成的金屬芯，或者由樹脂構成的樹脂芯等。作為焊料132，能夠採用例如含有鉛(Pb)的合金、錫(Sn)和銅(Cu)的合金、錫(Sn)和銻(Sb)的合金、錫(Sn)和銀(Ag)的合金、以及錫(Sn)、銀(Ag)和銅(Cu)的合金等。芯131的直徑能夠考慮IC晶片140及電子零件150相對於佈線基板110的下表面的高度來決定。例如，芯131的直徑可以設定為IC晶片140及電子零件150相對於佈線基板110的下表面的高度以上。此外，焊料132的量能夠考慮下表面焊盤115露出的面積、以及鍍層124的面積等來決定。 The connecting member 130 is formed of, for example, a solder ball having a copper core or the like, and connects the wiring substrate 110 and the lead frame 120. Specifically, the connecting member 130 has a core 131 having a substantially spherical shape and a solder 132 covering the outer peripheral surface of the core 131. As the core 131, for example, copper (Cu), gold (Au), nickel (Ni) Metal core made of other metals, or resin core made of resin, etc. As the solder 132, for example, an alloy containing lead (Pb), an alloy of tin (Sn) and copper (Cu), an alloy of tin (Sn) and antimony (Sb), an alloy of tin (Sn) and silver (Ag), And alloys of tin (Sn), silver (Ag) and copper (Cu). The diameter of the core 131 can be determined in consideration of the height of the IC chip 140 and the electronic component 150 with respect to the lower surface of the wiring board 110. For example, the diameter of the core 131 may be set to be greater than or equal to the height of the IC chip 140 and the electronic component 150 with respect to the lower surface of the wiring board 110. In addition, the amount of solder 132 can be determined in consideration of the exposed area of the lower surface pad 115, the area of the plating layer 124, and the like.

接著，說明如上構成的半導體裝置100的製造方法。以下，在說明佈線基板110的製造方法、以及引線框架120的製造方法之後，說明具有佈線基板110及引線框架120的半導體裝置100的製造方法。 Next, a method of manufacturing the semiconductor device 100 configured as above will be described. Hereinafter, after describing the manufacturing method of the wiring substrate 110 and the manufacturing method of the lead frame 120, the manufacturing method of the semiconductor device 100 having the wiring substrate 110 and the lead frame 120 will be described.

圖3係表示佈線基板110的製造方法的流程圖。 FIG. 3 is a flowchart showing a method of manufacturing the wiring board 110.

首先，在基板111的上表面及下表面形成佈線層(步驟S101)。具體而言，例如藉由半加成法(Semi-Additive Process)，依序形成基板111的上表面及下表面的佈線層。在基板111的上表面的佈線層包括上表面焊盤113，在基板下表面的佈線層包括下表面焊盤115。然後，在基板111的下表面，形成在下表面焊盤115的位置處具有開口部的保護絕緣層114(步驟S102)，在基板111的上表面，形成在上表面焊盤113的位置處具有開口部阻焊層112(步驟S103)。阻焊層112及保護絕緣層114例如藉由以下的方法來獲得，即：在基板111的上表面及下表面，層壓感光性的樹脂膜，或者塗敷液體狀或漿體狀的樹脂，並藉由光刻法來對層壓或塗敷的樹脂進行曝光、顯影而圖案化成需要的形狀。 First, wiring layers are formed on the upper and lower surfaces of the substrate 111 (step S101). Specifically, for example, by a semi-additive process (Semi-Additive Process), the wiring layers on the upper surface and the lower surface of the substrate 111 are sequentially formed. The wiring layer on the upper surface of the substrate 111 includes an upper surface pad 113, and the wiring layer on the lower surface of the substrate includes a lower surface pad 115. Then, on the lower surface of the substrate 111, a protective insulating layer 114 having an opening at the position of the pad 115 on the lower surface is formed (step S102), and on the upper surface of the substrate 111, a protective insulating layer 114 is formed at the position of the pad 113 on the upper surface. Part of the solder resist 112 (step S103). The solder resist layer 112 and the protective insulating layer 114 are obtained, for example, by the following method: laminating a photosensitive resin film on the upper and lower surfaces of the substrate 111, or applying a liquid or paste resin, The laminated or coated resin is exposed and developed by photolithography to pattern it into a desired shape.

藉由上述的步驟，例如，如圖4所示，形成出佈線基板110，在基板111的上表面，上表面焊盤113從阻焊層112的開口部112a露出，在基板111的下表面，下表面焊盤115a、115b、115c從保護絕緣層114的開口部114a露出。下表面焊盤115a係用於連接電子零件150的端子的焊盤，下表面焊盤115b係用於對 IC晶片140進行倒裝晶片連接的焊盤，下表面焊盤115c係用於與連接構件130連接的焊盤。因此，這些下表面焊盤115a、115b、115c露出的面積可以相互不同。 Through the above steps, for example, as shown in FIG. 4, a wiring substrate 110 is formed. On the upper surface of the substrate 111, the upper surface pad 113 is exposed from the opening 112a of the solder resist layer 112 and is on the lower surface of the substrate 111. The lower surface pads 115a, 115b, and 115c are exposed from the opening 114a of the protective insulating layer 114. The bottom surface pad 115a is used to connect the terminal of the electronic component 150, and the bottom surface pad 115b is used to connect The IC chip 140 is a pad for flip-chip connection, and the bottom surface pad 115c is a pad for connecting with the connection member 130. Therefore, the exposed areas of the lower surface pads 115a, 115b, and 115c may be different from each other.

在下表面焊盤115a、115b，為了搭載IC晶片140及電子零件150，印刷焊膏(步驟S104)。然後，在下表面焊盤115a的位置搭載電子零件150，並在下表面焊盤115b的位置搭載IC晶片140(步驟S105)。IC晶片140及電子零件150經由回流焊接處理(步驟S106)，安裝於佈線基板110。此外，根據需要，在IC晶片140與佈線基板110的下表面之間，填充由絕緣性樹脂構成的底部填膠142(步驟S107)。 In order to mount the IC chip 140 and the electronic component 150 on the lower surface pads 115a and 115b, solder paste is printed (step S104). Then, the electronic component 150 is mounted at the position of the lower surface pad 115a, and the IC chip 140 is mounted at the position of the lower surface pad 115b (step S105). The IC chip 140 and the electronic component 150 are mounted on the wiring board 110 through the reflow process (step S106). In addition, if necessary, an underfill 142 made of insulating resin is filled between the IC chip 140 and the lower surface of the wiring substrate 110 (step S107).

藉由上述的步驟，例如，如圖5所示，在佈線基板110的下表面，安裝IC晶片140及電子零件150，該IC晶片140藉由焊錫凸塊141與下表面焊盤115b進行倒裝晶片連接，該電子零件150的端子150a藉由焊料150b與下表面焊盤115a連接。由此，能夠得到形成半導體裝置100之上層的佈線基板110。 Through the above steps, for example, as shown in FIG. 5, an IC chip 140 and electronic components 150 are mounted on the lower surface of the wiring substrate 110, and the IC chip 140 is flip-chip mounted by solder bumps 141 and lower surface pads 115b For chip connection, the terminal 150a of the electronic component 150 is connected to the bottom surface pad 115a by solder 150b. In this way, the wiring substrate 110 forming the upper layer of the semiconductor device 100 can be obtained.

圖6係從下方向觀察佈線基板110的仰視圖。如圖6所示，在佈線基板110的下表面安裝有IC晶片140及電子零件150，從保護絕緣層114的開口部露出用於與連接構件130連接的下表面焊盤115c。此外，為了簡化圖示，在圖5和圖6中，IC晶片140及電子零件150的佈局不一定一致。此外，IC晶片140及電子零件150的佈局並不限於圖6所示的佈局。同樣地，下表面焊盤115c露出的位置也並不限於圖6所示的位置。其中，IC晶片140的位置與引線框架120的散熱板122的位置對應，下表面焊盤115c的位置與引線框架120的鍍層124的位置對應。 FIG. 6 is a bottom view of the wiring board 110 when viewed from below. As shown in FIG. 6, the IC chip 140 and electronic components 150 are mounted on the lower surface of the wiring board 110, and the lower surface pad 115 c for connection with the connection member 130 is exposed from the opening of the protective insulating layer 114. In addition, in order to simplify the illustration, in FIGS. 5 and 6, the layout of the IC chip 140 and the electronic components 150 are not necessarily the same. In addition, the layout of the IC chip 140 and the electronic components 150 is not limited to the layout shown in FIG. 6. Similarly, the position where the lower surface pad 115c is exposed is not limited to the position shown in FIG. 6. The position of the IC chip 140 corresponds to the position of the heat sink 122 of the lead frame 120, and the position of the bottom surface pad 115c corresponds to the position of the plating layer 124 of the lead frame 120.

較佳的是，這種佈線基板110藉由排列複數個佈線基板110而同時製造，而不是單體製造。即，例如，如圖7所示，較佳的是，製造為排列複數個佈線基板110而成的集合體110a。在集合體110a中，在由框體110b劃分出的各個分區，製造出佈線基板110。其中，在圖7中，省略佈線基板110的詳細結構的圖示。 Preferably, the wiring substrate 110 is manufactured at the same time by arranging a plurality of wiring substrates 110 instead of being manufactured individually. That is, for example, as shown in FIG. 7, it is preferable to manufacture as an assembly 110 a in which a plurality of wiring boards 110 are arranged. In the assembly 110a, the wiring board 110 is manufactured in each partition divided by the frame 110b. However, in FIG. 7, illustration of the detailed structure of the wiring substrate 110 is omitted.

接著，圖8係表示引線框架120的製造方法的流程圖。 Next, FIG. 8 is a flowchart showing a method of manufacturing the lead frame 120.

在製造引線框架120時，能夠使用例如厚度為50至200μm左右的銅或銅合金的金屬板。藉由金屬板的蝕刻加工或衝壓加工，來形成引線121及散熱板122(步驟S201)。也就是說，例如，如圖9所示，從金屬板成型出引線121及散熱板122。引線121設置於在引線框架120與佈線基板110接合時與下表面焊盤115c相向的位置，在俯視時例如具有細長的長方形狀。引線框架120具有複數個引線121，這些引線121的厚度均等。此外，散熱板122設置於在引線框架120與佈線基板110接合時與IC晶片140相向的位置，具有在俯視時面積較大的長方形狀。 When manufacturing the lead frame 120, for example, a metal plate of copper or copper alloy having a thickness of about 50 to 200 μm can be used. The lead 121 and the heat dissipation plate 122 are formed by etching or punching of the metal plate (step S201). That is, for example, as shown in FIG. 9, the lead 121 and the heat dissipation plate 122 are molded from a metal plate. The lead 121 is provided at a position facing the lower surface pad 115c when the lead frame 120 is bonded to the wiring substrate 110, and has, for example, an elongated rectangular shape in a plan view. The lead frame 120 has a plurality of leads 121, and the thickness of these leads 121 is uniform. In addition, the heat dissipation plate 122 is provided at a position facing the IC chip 140 when the lead frame 120 and the wiring substrate 110 are bonded, and has a rectangular shape with a large area in a plan view.

然後，在引線121形成鍍層124(步驟S202)。即，例如，如圖10所示，在引線121的上表面，例如藉由鍍銀來形成鍍層124。鍍層124形成於在引線框架120與佈線基板110接合時與下表面焊盤115c相向的位置。也就是說，在引線框架120與佈線基板110接合時，藉由連接構件130使彼此相向的下表面焊盤115c與鍍層124連接。如上所述，複數個引線121的厚度均等，特別係各引線121的形成有鍍層124的部分的厚度均等。此外，鍍層124的寬度(或者直徑)的大小最佳為比俯視時的引線121的短邊方向的寬度小。也就是說，最佳為鍍層124不超出引線121的上表面。 Then, a plating layer 124 is formed on the lead 121 (step S202). That is, for example, as shown in FIG. 10, the plating layer 124 is formed by, for example, silver plating on the upper surface of the lead 121. The plating layer 124 is formed at a position facing the lower surface pad 115c when the lead frame 120 and the wiring substrate 110 are joined. That is, when the lead frame 120 and the wiring substrate 110 are joined, the lower surface pad 115c and the plating layer 124 facing each other are connected by the connecting member 130. As described above, the thickness of the plurality of leads 121 is uniform, and in particular, the thickness of the portion where the plating layer 124 of each lead 121 is formed is uniform. In addition, the width (or diameter) of the plating layer 124 is preferably smaller than the width of the lead 121 in the short-side direction when viewed from above. In other words, it is best that the plating layer 124 does not exceed the upper surface of the lead 121.

在形成鍍層124時，例如藉由熱壓來使感光性的幹膜層壓在引線框架120的上表面，並藉由光刻法來對幹膜進行圖案化，從而形成抗蝕層。而且，藉由以抗蝕層作為電鍍掩膜的電鍍法或化學鍍法，來形成銀(Ag)等貴金屬的鍍層124。在形成鍍層124後，例如藉由鹼性的剝離液，來去除抗蝕層。 When forming the plating layer 124, a photosensitive dry film is laminated on the upper surface of the lead frame 120 by, for example, hot pressing, and the dry film is patterned by photolithography to form a resist layer. Furthermore, a plating layer 124 of a precious metal such as silver (Ag) is formed by a plating method or an electroless plating method using a resist layer as a plating mask. After the plating layer 124 is formed, the resist layer is removed by, for example, an alkaline stripping solution.

在形成鍍層124後，藉由引線框架120的陽極氧化處理，來形成氧化膜125(步驟S203)。也就是說，引線框架120被陽極氧化，例如，如圖11所示，在引線121及散熱板122的表面形成氧化膜125。此時，鍍層124例如為銀(Ag)等貴 金屬鍍層，所以不會被陽極氧化。因此，氧化膜125形成於除了形成有鍍層124的部分以外的引線121的表面及散熱板122的表面。 After the plating layer 124 is formed, the oxide film 125 is formed by the anodization treatment of the lead frame 120 (step S203). That is, the lead frame 120 is anodized. For example, as shown in FIG. 11, an oxide film 125 is formed on the surface of the lead 121 and the heat sink 122. At this time, the plating layer 124 is expensive such as silver (Ag). Metal plating, so it will not be anodized. Therefore, the oxide film 125 is formed on the surface of the lead 121 and the surface of the heat sink 122 except for the portion where the plating layer 124 is formed.

引線框架120的陽極氧化處理，例如藉由以下方式進行。即，使引線框架120作為陽極浸漬於電解液即陽極氧化處理液中，並將與引線框架120相向配置的鉑(Pt)等電極作為陰極進行通電(例如，施加脈衝電壓)。在引線框架120由銅或銅合金構成的情況下，能夠如下設定陽極氧化處理液的組成及處理條件。 The anodizing treatment of the lead frame 120 is performed in the following manner, for example. That is, the lead frame 120 is immersed in an anodizing treatment solution that is an electrolyte as an anode, and an electrode such as platinum (Pt) arranged opposite to the lead frame 120 is energized as a cathode (for example, a pulse voltage is applied). When the lead frame 120 is made of copper or a copper alloy, the composition and processing conditions of the anodizing treatment solution can be set as follows.

陽極氧化處理液： Anodizing treatment liquid:

亞氯酸鈉(NaClO2) 0至100g/L Sodium chlorite (NaClO 2 ) 0 to 100g/L

氫氧化鈉(NaOH) 5至60g/L Sodium hydroxide (NaOH) 5 to 60g/L

磷酸鈉(Na3PO4) 0至200g/L Sodium phosphate (Na 3 PO 4 ) 0 to 200g/L

處理條件： Processing conditions:

液溫 約50至80度 Liquid temperature about 50 to 80 degrees

處理時間 約1至20秒 Processing time: about 1 to 20 seconds

電流密度 約0.2至10A/dm2 Current density is about 0.2 to 10A/dm 2

根據上述條件，對引線框架120進行陽極氧化，從而形成例如厚度為0.1至0.2μm的氧化膜125。對於氧化膜125的厚度，能夠藉由改變陽極氧化處理液的組成、電壓及處理時間等處理條件來調整。氧化膜125係包含氫氧化物的銅氧化膜，具有針狀結晶。作為氫氧化物，包括氫氧化銅(Cu(OH)2)。此外，針狀結晶具有例如約0.5μm以下的粒徑。 According to the above conditions, the lead frame 120 is anodized, thereby forming an oxide film 125 having a thickness of, for example, 0.1 to 0.2 μm. The thickness of the oxide film 125 can be adjusted by changing processing conditions such as the composition, voltage, and processing time of the anodizing treatment solution. The oxide film 125 is a copper oxide film containing hydroxide, and has needle-like crystals. As the hydroxide, copper hydroxide (Cu(OH) 2 ) is included. In addition, needle-shaped crystals have a particle size of, for example, about 0.5 μm or less.

在氧化膜125形成於引線框架120後，在鍍層124的位置搭載連接構件130(步驟S204)。而且，藉由進行回流焊接處理(步驟S205)，由芯131周圍的焊料132來使連接構件130與鍍層124接合。此時，由於在鍍層124的周圍形成有氧化膜125，所以焊料132不會擴散至鍍層124的周圍，能夠準確地進行連接構件130的位置對齊。連接構件130的寬度(或直徑)的大小，最佳為比俯視時的引線121的 短邊方向的寬度小。也就是說，最佳為使連接構件130不超出引線121的上表面。由此，與相鄰的引線121的上表面接合的連接構件130彼此不會接觸，能夠防止短路。 After the oxide film 125 is formed on the lead frame 120, the connection member 130 is mounted at the position of the plating layer 124 (step S204). Then, by performing the reflow soldering process (step S205), the connecting member 130 and the plating layer 124 are joined by the solder 132 around the core 131. At this time, since the oxide film 125 is formed around the plating layer 124, the solder 132 does not diffuse to the circumference of the plating layer 124, and the position of the connecting member 130 can be accurately aligned. The width (or diameter) of the connecting member 130 is preferably larger than that of the lead 121 when viewed from above. The width in the short-side direction is small. In other words, it is best that the connecting member 130 does not protrude from the upper surface of the lead 121. Thereby, the connecting members 130 joined to the upper surfaces of the adjacent leads 121 do not come into contact with each other, and it is possible to prevent a short circuit.

在此，焊料132不會擴散至鍍層124的周圍的理由如下。即，在搭載連接構件130時，為了確保焊料132的潤濕性，對鍍層124塗敷助焊劑。由於助焊劑具有使金屬層的表面的自然氧化膜還原並去除的功能，若助焊劑流出至鍍層124周圍的氧化膜125，則氧化膜125被還原而助焊劑的活性降低。其結果，在鍍層124的周圍，不能得到焊料132的潤濕性，可抑制焊料132的漫流。如此，由於氧化膜125使助焊劑的活性降低，所以焊料132不會擴散至鍍層124的周圍，能夠準確地進行連接構件130的位置對齊。 Here, the reason why the solder 132 does not diffuse to the periphery of the plating layer 124 is as follows. That is, when the connecting member 130 is mounted, in order to ensure the wettability of the solder 132, a flux is applied to the plating layer 124. Since the flux has the function of reducing and removing the natural oxide film on the surface of the metal layer, if the flux flows out to the oxide film 125 around the plating layer 124, the oxide film 125 is reduced and the activity of the flux is reduced. As a result, around the plating layer 124, the wettability of the solder 132 cannot be obtained, and the overflow of the solder 132 can be suppressed. In this way, since the oxide film 125 reduces the activity of the flux, the solder 132 does not diffuse to the periphery of the plating layer 124, and the position of the connection member 130 can be accurately aligned.

此外，在氧化膜125的厚度過薄的情況下，不太會使助焊劑的活性降低。另一方面，在氧化膜125的厚度過厚的情況下，有可能在氧化膜125的內部產生剝離。因此，如上所述，藉由適當地設定陽極氧化處理的條件，來將氧化膜125的厚度調整為例如0.1至0.2μm。 In addition, in the case where the thickness of the oxide film 125 is too thin, the activity of the flux is less likely to decrease. On the other hand, if the thickness of the oxide film 125 is too thick, there is a possibility that peeling may occur inside the oxide film 125. Therefore, as described above, by appropriately setting the conditions of the anodizing treatment, the thickness of the oxide film 125 is adjusted to, for example, 0.1 to 0.2 μm.

藉由上述的步驟，例如，如圖12所示，連接構件130與引線121的鍍層124接合，在引線121的除了鍍層124以外的表面形成氧化膜125。此外，還在散熱板122的表面形成氧化膜125。由此，能夠得到形成半導體裝置100的下層的引線框架120。 Through the above-mentioned steps, for example, as shown in FIG. 12, the connecting member 130 is joined to the plating layer 124 of the lead 121, and an oxide film 125 is formed on the surface of the lead 121 except for the plating layer 124. In addition, an oxide film 125 is also formed on the surface of the heat dissipation plate 122. In this way, the lead frame 120 forming the lower layer of the semiconductor device 100 can be obtained.

圖13係從上方向觀察引線框架120的俯視圖。如圖13所示，引線框架120具有細長的長方形狀的複數個引線121、以及面積較大的長方形狀的散熱板122。散熱板122藉由支承用引線121’與周圍的框體120b連接而被支承。各引線121與一個或兩個連接構件130接合。對於與引線121接合的連接構件130的數量，例如考慮與佈線基板110的佈線層之間流過的電流的大小而決定。即，例如， 對於流過較大電流的引線121，可以增多連接構件130的數量，來使與佈線基板110的佈線層之間的電阻降低。 FIG. 13 is a plan view of the lead frame 120 viewed from above. As shown in FIG. 13, the lead frame 120 has a plurality of elongated rectangular leads 121 and a rectangular heat sink 122 with a large area. The heat sink 122 is supported by connecting the supporting lead 121' to the surrounding frame 120b. Each lead 121 is joined to one or two connecting members 130. The number of the connection members 130 to be joined to the leads 121 is determined in consideration of the magnitude of the current flowing between the wiring layers of the wiring substrate 110 and the wiring substrate 110, for example. That is, for example, For the lead 121 through which a relatively large current flows, the number of the connection members 130 can be increased to reduce the resistance between the wiring layer and the wiring substrate 110.

散熱板122由縫隙122a分割為兩個。由於存在縫隙122a，能夠提高填充在佈線基板110和引線框架120之間的密封樹脂102與引線框架120的緊密性。此外，例如在佈線基板110並排搭載有兩個IC晶片140的情況下，能夠在與各IC晶片140相向的位置設置散熱板122，獨立地進行散熱。 The heat dissipation plate 122 is divided into two by the slit 122a. Due to the existence of the gap 122a, the tightness between the sealing resin 102 filled between the wiring substrate 110 and the lead frame 120 and the lead frame 120 can be improved. In addition, for example, when two IC chips 140 are mounted side by side on the wiring board 110, a heat dissipation plate 122 can be provided at a position facing each IC chip 140 to independently dissipate heat.

此外，引線121及散熱板122的佈局不限於圖13所示的佈局。只是，需要滿足引線121的鍍層124及連接構件130的位置與佈線基板110的下表面焊盤115c的位置對應，散熱板122的位置與安裝於佈線基板110的IC晶片140的位置對應。此外，縫隙122a的位置也不限於圖13所示的位置，例如也可以對散熱板122的中央附近進行穿孔而形成縫隙。 In addition, the layout of the leads 121 and the heat dissipation plate 122 is not limited to the layout shown in FIG. 13. However, it is necessary to satisfy that the positions of the plating layer 124 of the lead 121 and the connection member 130 correspond to the position of the lower surface pad 115c of the wiring substrate 110, and the position of the heat sink 122 corresponds to the position of the IC chip 140 mounted on the wiring substrate 110. In addition, the position of the slit 122a is not limited to the position shown in FIG. 13, for example, a hole may be formed in the vicinity of the center of the heat dissipation plate 122 to form a slit.

較佳的是，這種引線框架120排列複數個引線框架120而同時製造，而不是單體製造。即，例如，如圖14所示，較佳的是，製造為排列複數個引線框架120而成的集合體120a。在集合體120a中，在由框體120b劃分出的各個分區，製造出引線框架120。其中，在圖14中，省略引線框架120的詳細結構的圖示。 Preferably, such a lead frame 120 is manufactured by arranging a plurality of lead frames 120 at the same time instead of being manufactured individually. That is, for example, as shown in FIG. 14, it is preferable to manufacture as an assembly 120a in which a plurality of lead frames 120 are arranged. In the assembly 120a, the lead frame 120 is manufactured in each partition divided by the frame 120b. However, in FIG. 14, illustration of the detailed structure of the lead frame 120 is omitted.

接著，圖15係表示半導體裝置100的製造方法的流程圖。半導體裝置100使用上述的佈線基板110及引線框架120來製造。 Next, FIG. 15 is a flowchart showing a method of manufacturing the semiconductor device 100. The semiconductor device 100 is manufactured using the wiring substrate 110 and the lead frame 120 described above.

佈線基板110與引線框架120例如藉由TCB(Thermal Compression Bonding，熱壓鍵合)法來接合(步驟S301)。具體而言，與引線框架120的引線121接合的連接構件130，藉由熱和壓力，與佈線基板110的下表面焊盤115c接合。此時，由於複數個引線121的、特別係設置有連接構件130的部分的厚度均等，所以所有的連接構件130及下表面焊盤115c被均勻加壓，能夠防止連接構件130與下表面焊盤115c的連接不良。由此，例如，如圖16所示，使佈線基板110與引線框架120一體化。在佈線基板110與引線框架120之間配置有IC晶片140及電子 零件150，IC晶片140及電子零件150與引線框架120的散熱板122相向。在IC晶片140的下表面與散熱板122的上表面之間，例如隔開40至50μm左右。該間隔能夠根據連接構件130的芯131的直徑來調整。 The wiring substrate 110 and the lead frame 120 are bonded by, for example, a TCB (Thermal Compression Bonding) method (step S301). Specifically, the connection member 130 bonded to the lead 121 of the lead frame 120 is bonded to the lower surface pad 115c of the wiring substrate 110 by heat and pressure. At this time, since the thickness of the plurality of leads 121, especially the part where the connecting member 130 is provided, is uniform, all the connecting members 130 and the lower surface pad 115c are uniformly pressurized, which can prevent the connecting member 130 and the lower surface pad from being uniformly pressed. The 115c has a bad connection. Thus, for example, as shown in FIG. 16, the wiring board 110 and the lead frame 120 are integrated. An IC chip 140 and electronic components are arranged between the wiring substrate 110 and the lead frame 120. The component 150, the IC chip 140 and the electronic component 150 face the heat sink 122 of the lead frame 120. The distance between the lower surface of the IC chip 140 and the upper surface of the heat dissipation plate 122 is, for example, about 40 to 50 μm. The interval can be adjusted according to the diameter of the core 131 of the connecting member 130.

然後，例如，藉由進行轉移模製(步驟S302)，將密封樹脂102填充在佈線基板110與引線框架120之間的空間。在轉移模製中，接合的佈線基板110及引線框架120收納於模具，並對模具內注塑流態化的密封樹脂102。然後，密封樹脂102被加熱成規定的溫度(例如，175℃)而固化。由此，例如，如圖17所示，密封樹脂102填充在佈線基板110與引線框架120之間的空間，從而，連接構件130、IC晶片140及電子零件150被密封。即使IC晶片140及電子零件150被密封，這些構件產生的熱也經由密封樹脂102傳遞至散熱板122。其結果，能夠提高半導體裝置100的散熱效率。 Then, for example, by performing transfer molding (step S302), the sealing resin 102 is filled in the space between the wiring substrate 110 and the lead frame 120. In the transfer molding, the bonded wiring substrate 110 and the lead frame 120 are housed in a mold, and the fluidized sealing resin 102 is injected into the mold. Then, the sealing resin 102 is heated to a predetermined temperature (for example, 175°C) and cured. Thereby, for example, as shown in FIG. 17, the sealing resin 102 fills the space between the wiring substrate 110 and the lead frame 120, and thereby the connection member 130, the IC chip 140, and the electronic component 150 are sealed. Even if the IC chip 140 and the electronic component 150 are sealed, the heat generated by these components is transferred to the heat dissipation plate 122 via the sealing resin 102. As a result, the heat dissipation efficiency of the semiconductor device 100 can be improved.

在IC晶片140及電子零件150被密封後，在佈線基板110的上表面搭載電子零件103(步驟S303)。電子零件103藉由回流焊接處理(步驟S304)，安裝於佈線基板110。也就是說，例如，如圖18所示，電子零件103的端子103a藉由焊料103b與上表面焊盤113連接，從而電子零件103安裝於佈線基板110的上表面。作為電子零件103，例如能夠採用電容器、電感器及電阻元件等無源零件。此外，電子零件103也可以係例如IC晶片等有源零件。 After the IC chip 140 and the electronic component 150 are sealed, the electronic component 103 is mounted on the upper surface of the wiring board 110 (step S303). The electronic component 103 is mounted on the wiring board 110 by the reflow soldering process (step S304). That is, for example, as shown in FIG. 18, the terminal 103a of the electronic component 103 is connected to the upper surface pad 113 by the solder 103b, so that the electronic component 103 is mounted on the upper surface of the wiring board 110. As the electronic component 103, passive components, such as a capacitor, an inductor, and a resistance element, can be used, for example. In addition, the electronic component 103 may also be an active component such as an IC chip.

然後，例如，藉由進行轉移模製(步驟S305)，佈線基板110的上表面的電子零件103由密封樹脂101密封。作為密封樹脂101，能夠採用例如含有填料的熱固性的環氧類樹脂等絕緣性樹脂。在轉移模製中，由安裝有電子零件103的佈線基板110及引線框架120構成的結構體收納於模具，並對模具內注塑流態化的密封樹脂101。然後，密封樹脂101被加熱成規定的溫度(例如，175℃)而固化。由此，例如，如圖19所示，佈線基板110的上表面及電子零件103由密封樹脂101包覆，電子零件103被密封。 Then, for example, by performing transfer molding (step S305), the electronic component 103 on the upper surface of the wiring substrate 110 is sealed with the sealing resin 101. As the sealing resin 101, for example, an insulating resin such as a thermosetting epoxy resin containing a filler can be used. In the transfer molding, a structure composed of the wiring board 110 on which the electronic component 103 is mounted and the lead frame 120 is housed in a mold, and the fluidized sealing resin 101 is injected into the mold. Then, the sealing resin 101 is heated to a predetermined temperature (for example, 175°C) and cured. Thereby, for example, as shown in FIG. 19, the upper surface of the wiring board 110 and the electronic component 103 are covered with the sealing resin 101, and the electronic component 103 is sealed.

接著，在引線框架120的下表面形成槽部(步驟S306)。具體而言，例如，如圖20所示，藉由僅對引線121的下表面的端部的厚度的一部分進行切割(半切)，來形成出槽部121b。此時，由於在引線121之間的密封樹脂102也同時被切割，所以在密封樹脂102也形成與槽部121b呈一體的槽部。由於槽部121b的深度大於氧化膜125的厚度，所以在形成槽部121b的過程中，會去除槽部121b的位置處的氧化膜125。因此，在槽部121b中，引線框架120的基材會露出。槽部121b形成於構成半導體裝置100的側面的位置。也就是說，能夠藉由對圖20所示的結構體在經過槽部121b的位置上沿上下方向進行切割，獲得半導體裝置100。 Next, a groove is formed on the lower surface of the lead frame 120 (step S306). Specifically, for example, as shown in FIG. 20, the groove 121b is formed by cutting (half-cutting) only a part of the thickness of the end of the lower surface of the lead 121. At this time, since the sealing resin 102 between the leads 121 is also cut at the same time, the sealing resin 102 is also formed with a groove portion integral with the groove portion 121b. Since the depth of the groove portion 121b is greater than the thickness of the oxide film 125, in the process of forming the groove portion 121b, the oxide film 125 at the position of the groove portion 121b is removed. Therefore, in the groove 121b, the base material of the lead frame 120 is exposed. The groove 121b is formed at a position constituting the side surface of the semiconductor device 100. That is, the semiconductor device 100 can be obtained by cutting the structure shown in FIG. 20 in the vertical direction at the position passing through the groove 121b.

在此，佈線基板110及引線框架120分別作為集合體110a、120a而形成，對於佈線基板110與引線框架120的接合或基於密封樹脂101、102的轉移模製等步驟，也以集合體110a、120a的狀態進行。因此，槽部121b可以橫跨在集合體120a中相鄰的引線框架120而形成。具體而言，例如，如圖21所示，也可以藉由對相鄰的兩個引線框架120的端部與框體120b的範圍進行切割(半切)，來形成槽部121b。藉由形成槽部121b，在半導體裝置100的側面露出的引線121的端部，形成有臺階。此外，在圖21中，僅示出了在圖示的兩個引線框架120之間形成的槽部121b，但槽部121b形成於所有相鄰的引線框架120之間。因此，槽部121b形成於各引線框架120的四邊。 Here, the wiring substrate 110 and the lead frame 120 are formed as aggregates 110a and 120a, respectively. For steps such as bonding of the wiring substrate 110 and the lead frame 120 or transfer molding based on the sealing resins 101 and 102, the aggregate 110a, The state of 120a progresses. Therefore, the groove 121b may be formed across the adjacent lead frames 120 in the assembly 120a. Specifically, for example, as shown in FIG. 21, the groove 121b may be formed by cutting (half-cutting) the ends of two adjacent lead frames 120 and the range of the frame 120b. By forming the groove 121b, a step is formed at the end of the lead 121 exposed on the side surface of the semiconductor device 100. In addition, in FIG. 21, only the groove portion 121 b formed between the two lead frames 120 shown in the figure is shown, but the groove portion 121 b is formed between all adjacent lead frames 120. Therefore, grooves 121b are formed on the four sides of each lead frame 120.

在形成槽部121b後，去除引線框架120的下表面的氧化膜125(步驟S307)。此外，在去除氧化膜125的同時，去除在引線121及散熱板122的下表面產生的密封樹脂102的殘渣。對於氧化膜125及密封樹脂102的殘渣的去除，例如藉由酸處理、鹼處理或濕噴砂處理來進行。藉由去除氧化膜125，引線框架120的基材在引線121及散熱板122的下表面露出。另一方面，與密封樹脂102接觸的、引線121及散熱板122的側面及上表面的氧化膜125殘留。 After the groove portion 121b is formed, the oxide film 125 on the lower surface of the lead frame 120 is removed (step S307). In addition, while removing the oxide film 125, the residue of the sealing resin 102 generated on the lower surface of the lead 121 and the heat dissipation plate 122 is removed. The removal of the residues of the oxide film 125 and the sealing resin 102 is performed, for example, by acid treatment, alkali treatment, or wet sandblasting. By removing the oxide film 125, the base material of the lead frame 120 is exposed on the lower surfaces of the leads 121 and the heat sink 122. On the other hand, the oxide film 125 on the side and upper surface of the lead 121 and the heat dissipation plate 122 in contact with the sealing resin 102 remains.

然後，在引線121及散熱板122的下表面形成鍍層123(步驟S308)。即，藉由電鍍法或化學鍍法，在引線框架120的下表面形成例如錫(Sn)或錫鉛合金的鍍層123。此時，在槽部121b的內部也形成鍍層123。 Then, a plating layer 123 is formed on the lower surface of the lead 121 and the heat sink 122 (step S308). That is, the plating layer 123 of, for example, tin (Sn) or tin-lead alloy is formed on the lower surface of the lead frame 120 by the electroplating method or the electroless plating method. At this time, the plating layer 123 is also formed inside the groove 121b.

藉由上述的步驟，例如，如圖22所示，能夠獲得具有與半導體裝置100等同的結構的結構體。該結構體由包括複數個佈線基板110的集合體110a、以及包括複數個引線框架120的集合體120a構成，所以進行用於切出各個佈線基板110及引線框架120的分割化(步驟S309)。具體而言，圖22所示的結構體在經過槽部121b的切割線A上由例如切塊機或切片機進行切割，從而得到半導體裝置100。由於切割線A經過槽部121b，所以在半導體裝置100的側面露出的引線121的端部，為比其他的部分薄的部分。 Through the above-mentioned steps, for example, as shown in FIG. 22, a structure having a structure equivalent to that of the semiconductor device 100 can be obtained. This structure is composed of an assembly 110a including a plurality of wiring substrates 110 and an assembly 120a including a plurality of lead frames 120, so the division for cutting out each wiring substrate 110 and the lead frame 120 is performed (step S309). Specifically, the structure shown in FIG. 22 is cut by, for example, a dicing machine or a dicing machine on the cutting line A passing through the groove portion 121 b to obtain the semiconductor device 100. Since the dicing line A passes through the groove portion 121b, the end portion of the lead 121 exposed on the side surface of the semiconductor device 100 is a portion thinner than other portions.

此外，在槽部121b橫跨相鄰的引線框架120而形成的情況下，例如，如圖23所示，藉由可對包含框體120b的範圍B進行切削的切割刀片來進行切割加工，從而能夠以一次切割分離出相鄰的半導體裝置100。在這種情況下，範圍B也包含於槽部121b的內部，所以在半導體裝置100的側面露出的引線121的端部為比其他的部分薄的部分。在圖23中，僅示出圖示的兩個引線框架120之間的切削範圍B，但這種切削範圍設定在所有相鄰的引線框架120之間。因此，各引線框架120的四邊在與切削範圍B相同的切削範圍內，與相鄰的引線框架120分離。 In addition, in the case where the groove portion 121b is formed across the adjacent lead frame 120, for example, as shown in FIG. 23, a cutting blade that can cut the range B including the frame body 120b is used to perform cutting processing. The adjacent semiconductor devices 100 can be separated by one cut. In this case, the range B is also included in the inside of the groove 121b, so the end of the lead 121 exposed on the side surface of the semiconductor device 100 is a thinner part than the other parts. In FIG. 23, only the cutting range B between the two lead frames 120 shown in the figure is shown, but this cutting range is set between all adjacent lead frames 120. Therefore, the four sides of each lead frame 120 are separated from the adjacent lead frame 120 within the same cutting range as the cutting range B.

能夠將藉由分割化而獲得的半導體裝置100，安裝於安裝基板。具體而言，能夠將引線框架120的引線121作為端子，來將半導體裝置100安裝於安裝基板。圖24係用於說明半導體裝置100的安裝的圖。 The semiconductor device 100 obtained by division can be mounted on a mounting substrate. Specifically, the semiconductor device 100 can be mounted on a mounting substrate using the leads 121 of the lead frame 120 as terminals. FIG. 24 is a diagram for explaining the mounting of the semiconductor device 100.

如圖24所示，在安裝基板200的上表面的佈線層形成有焊盤210，焊盤210從阻焊層220的開口部露出。在將半導體裝置100安裝於安裝基板200時，進行半導體裝置100的引線121及散熱板122與安裝基板200的焊盤210的位置對齊，藉由焊料230將引線121及散熱板122與焊盤210接合。此時，由於在引線 121的下表面的端部存在基於槽部121b的臺階，所以可促進焊料230的漫流，焊料230的圓角包覆引線121的側面121a。其結果，能夠使半導體裝置100與安裝基板200牢固地接合，提高連接的可靠性。在圖24所示的狀態下，IC晶片140產生的熱，經由密封樹脂102傳遞至散熱板122，並從散熱板122經由焊料230及焊盤210散熱。也就是說，能夠從IC晶片140的表面積的大部分有效散熱。 As shown in FIG. 24, a pad 210 is formed on the wiring layer on the upper surface of the mounting substrate 200, and the pad 210 is exposed from the opening of the solder resist layer 220. When the semiconductor device 100 is mounted on the mounting substrate 200, the positions of the leads 121 and the heat dissipation plate 122 of the semiconductor device 100 and the pad 210 of the mounting substrate 200 are aligned, and the leads 121 and the heat dissipation plate 122 are connected to the pad 210 by the solder 230. Splice. At this time, due to the lead Since the end of the lower surface of 121 has a step based on the groove 121b, the overflow of the solder 230 can be promoted, and the fillet of the solder 230 covers the side surface 121a of the lead 121. As a result, the semiconductor device 100 and the mounting substrate 200 can be firmly joined, and the reliability of the connection can be improved. In the state shown in FIG. 24, the heat generated by the IC chip 140 is transferred to the heat dissipation plate 122 through the sealing resin 102, and is radiated from the heat dissipation plate 122 through the solder 230 and the pad 210. That is, it is possible to efficiently dissipate heat from most of the surface area of the IC chip 140.

如上所述，根據本實施形態，將IC晶片安裝於以連接構件連接的佈線基板與引線框架之間，將引線框架的散熱板配置於與IC晶片相向的位置，並將密封樹脂填充在佈線基板與引線框架之間的空間。而且，使引線框架的引線從密封樹脂露出，作為用於外部連接的端子。因此，由IC晶片產生的熱，經由IC晶片的周圍的密封樹脂而傳遞至散熱板，並從散熱板散熱。其結果，能夠提高半導體裝置的散熱效率。 As described above, according to this embodiment, the IC chip is mounted between the wiring board and the lead frame connected by the connecting member, the heat sink of the lead frame is arranged at a position facing the IC chip, and the sealing resin is filled on the wiring board The space between and the lead frame. Furthermore, the leads of the lead frame are exposed from the sealing resin as terminals for external connection. Therefore, the heat generated by the IC chip is transferred to the heat dissipation plate via the sealing resin around the IC chip, and is radiated from the heat dissipation plate. As a result, the heat dissipation efficiency of the semiconductor device can be improved.

此外，在上述一實施形態中，將電子零件103安裝於佈線基板110的上表面，但也可以省略對佈線基板110的上表面的電子零件103的安裝、以及藉由密封樹脂101進行的密封。也就是說，例如，如圖25所示，半導體裝置100也可以在佈線基板110的上表面不具有電子零件，僅在佈線基板110與引線框架120之間，具有由密封樹脂102密封的IC晶片140及電子零件150。此外，在將電子零件103安裝於佈線基板110的上表面的情況下，也可以省略使用密封樹脂101的密封。在這種情況下，半導體裝置100具有安裝於佈線基板110的上表面並露出的電子零件103。 In addition, in the above-described embodiment, the electronic component 103 is mounted on the upper surface of the wiring substrate 110, but the mounting of the electronic component 103 on the upper surface of the wiring substrate 110 and the sealing by the sealing resin 101 may be omitted. That is, for example, as shown in FIG. 25, the semiconductor device 100 may not have electronic components on the upper surface of the wiring substrate 110, and only have an IC chip sealed by the sealing resin 102 between the wiring substrate 110 and the lead frame 120. 140 and electronic parts 150. In addition, when the electronic component 103 is mounted on the upper surface of the wiring board 110, the sealing using the sealing resin 101 may be omitted. In this case, the semiconductor device 100 has electronic components 103 mounted on the upper surface of the wiring board 110 and exposed.

此外，在上述一實施形態中，連接構件130例如為具有銅芯的錫球，且芯131大致呈球狀，但連接構件130的形狀可以係任意的形狀。具體而言，例如，如圖26所示，也可以係圓柱狀或角柱狀的、由銅或銅合金等金屬製成的連接構件135藉由焊料136與佈線基板110的下表面焊盤115及引線框架120的鍍層 124接合。藉由使連接構件135為圓柱狀或角柱狀，使連接構件135的上下各自的端面與下表面焊盤115及鍍層124接合，能夠增大接合面積而提高可靠性。 In addition, in the above-mentioned embodiment, the connecting member 130 is, for example, a tin ball with a copper core, and the core 131 is approximately spherical, but the shape of the connecting member 130 may be any shape. Specifically, for example, as shown in FIG. 26, a cylindrical or prismatic connecting member 135 made of metal such as copper or copper alloy may be connected to the lower surface pad 115 of the wiring substrate 110 by solder 136 and Plating of lead frame 120 124 joint. By making the connecting member 135 cylindrical or prismatic, the upper and lower end surfaces of the connecting member 135 are joined to the lower surface pad 115 and the plating layer 124, so that the joint area can be increased and the reliability can be improved.

進一步地，在上述一實施形態中，將密封樹脂102填充在佈線基板110與引線框架120之間的空間，但例如，如圖27所示，也可以將TIM(Thermal Interface Material，導熱介面材料)105配置於發熱量大的IC晶片140與散熱板122之間的空間，並將通常的密封樹脂106填充在佈線基板110與引線框架120之間的空間。作為TIM105，能夠採用例如使環氧類樹脂或聚醯亞胺類樹脂等絕緣性樹脂中包含氧化鋁、二氧化矽、氮化鋁或碳化矽等填料、或者銀等金屬填料的材料，作為密封樹脂106，能夠採用與密封樹脂101相同的樹脂。 Further, in the above-mentioned embodiment, the sealing resin 102 is filled in the space between the wiring substrate 110 and the lead frame 120. However, for example, as shown in FIG. 27, a TIM (Thermal Interface Material) may also be used. 105 is arranged in the space between the IC chip 140 that generates a large amount of heat and the heat dissipation plate 122, and the space between the wiring board 110 and the lead frame 120 is filled with a normal sealing resin 106. As the TIM105, for example, insulating resins such as epoxy resins or polyimide resins can contain fillers such as alumina, silicon dioxide, aluminum nitride, or silicon carbide, or metal fillers such as silver, as sealing materials. As the resin 106, the same resin as the sealing resin 101 can be used.

此外，在上述一實施形態中，在佈線基板110的下表面安裝IC晶片140，但也可以在引線框架120的上表面安裝IC晶片140。在這種情況下，例如，如圖28所示，在IC晶片140的安裝位置，形成有引線126。而且，在引線126的上表面，形成有與鍍層124相同的鍍層127，IC晶片140藉由焊錫凸塊143與鍍層127倒裝晶片連接。在與密封樹脂102接觸的引線126的表面形成有氧化膜125，並在從密封樹脂102露出的引線126的下表面形成有鍍層123，這一點與引線121相同。在該結構中，IC晶片140產生的熱經由焊錫凸塊143、鍍層127及引線126被散熱。此外，不僅係IC晶片140，也可以將電子零件150安裝於引線框架120的上表面。 In addition, in the above-described embodiment, the IC chip 140 is mounted on the lower surface of the wiring substrate 110, but the IC chip 140 may be mounted on the upper surface of the lead frame 120. In this case, for example, as shown in FIG. 28, the lead 126 is formed at the mounting position of the IC chip 140. Furthermore, on the upper surface of the lead 126, a plating layer 127 that is the same as the plating layer 124 is formed, and the IC chip 140 is flip-chip connected to the plating layer 127 by solder bumps 143. An oxide film 125 is formed on the surface of the lead 126 that is in contact with the sealing resin 102, and a plating layer 123 is formed on the lower surface of the lead 126 exposed from the sealing resin 102, which is the same as the lead 121. In this structure, the heat generated by the IC chip 140 is dissipated via the solder bumps 143, the plating layer 127, and the leads 126. In addition, not only the IC chip 140, but also the electronic component 150 can be mounted on the upper surface of the lead frame 120.

其他的實施方式 Other implementations

(1)鍍層 (1) Plating

在上述一實施形態中，藉由在引線框架120形成鍍層124，並在鍍層124的周圍形成氧化膜125，來準確地進行引線框架120與連接構件130的位置對齊。然而，由於氧化膜125會使助焊劑的活性下降，所以即使沒有鍍層124，也能夠控 制焊料132的漫流，來準確地進行連接構件130的位置對齊。在此，參照圖29(a)至圖29(d)，說明不具有鍍層124的引線框架120的製造方法。 In the above-mentioned embodiment, by forming the plating layer 124 on the lead frame 120 and forming the oxide film 125 around the plating layer 124, the lead frame 120 and the connecting member 130 are aligned accurately. However, since the oxide film 125 reduces the activity of the flux, it can be controlled even without the plating layer 124. The overflow of the solder 132 is made to accurately align the position of the connecting member 130. Here, referring to FIGS. 29(a) to 29(d), a method of manufacturing the lead frame 120 without the plating layer 124 will be described.

與上述一實施形態相同，在製造引線框架120時，能夠使用例如厚度為50至200μm左右的銅或銅合金的金屬板。如圖29(a)所示，藉由金屬板的蝕刻加工或衝壓加工，來形成引線121及散熱板122。然後，如圖29(b)所示，藉由引線框架120的陽極氧化處理，在引線121及散熱板122的表面形成氧化膜125。也就是說，在引線121及散熱板122的整個表面形成氧化膜125。 As in the above-mentioned embodiment, when manufacturing the lead frame 120, for example, a metal plate of copper or copper alloy having a thickness of about 50 to 200 μm can be used. As shown in FIG. 29(a), the lead 121 and the heat dissipation plate 122 are formed by etching or pressing of a metal plate. Then, as shown in FIG. 29( b ), an oxide film 125 is formed on the surface of the lead 121 and the heat sink 122 by the anodization treatment of the lead frame 120. In other words, the oxide film 125 is formed on the entire surface of the lead 121 and the heat dissipation plate 122.

如圖29(c)所示，在引線121的與連接構件130接合的位置125a，氧化膜125被去除。例如能夠藉由雷射加工或噴砂加工(blasting)等，來進行氧化膜125的去除。藉由去除氧化膜125，引線框架120的基材在位置125a露出。然後，如圖29(d)所示，將連接構件130搭載於位置125a並進行回流焊接處理。此時，若塗敷在位置125a的助焊劑向周圍的氧化膜125流出，則氧化膜125還原，助焊劑的活性會降低。因此，連接構件130的焊料132不會漫流至位置125a的周圍，能夠準確地進行連接構件130的位置對齊。 As shown in FIG. 29(c), the oxide film 125 is removed at the position 125a of the lead 121 where it is joined to the connection member 130. For example, the oxide film 125 can be removed by laser processing, blasting, or the like. By removing the oxide film 125, the base material of the lead frame 120 is exposed at the position 125a. Then, as shown in FIG. 29(d), the connecting member 130 is mounted at the position 125a, and the reflow soldering process is performed. At this time, if the flux applied to the position 125a flows out to the surrounding oxide film 125, the oxide film 125 will be reduced and the activity of the flux will decrease. Therefore, the solder 132 of the connecting member 130 does not flow around the position 125a, and the position of the connecting member 130 can be accurately aligned.

如此，在引線121不形成鍍層124的情況下，也能夠藉由利用氧化膜125，準確地進行引線框架120與連接構件130的位置對齊。此外，由於能夠省略鍍層124的形成步驟，所以能夠簡化引線框架120的製造步驟。 In this way, even when the lead 121 is not formed with the plating layer 124, the position of the lead frame 120 and the connection member 130 can be accurately aligned by using the oxide film 125. In addition, since the steps of forming the plating layer 124 can be omitted, the steps of manufacturing the lead frame 120 can be simplified.

(2)底部填膠 (2) Filling at the bottom

在上述一實施形態中，底部填膠142填充於佈線基板110的下表面與IC晶片140之間，但並不一定要填充底部填膠142。具體而言，例如，如圖30所示，在藉由焊錫凸塊141與佈線基板110的下表面進行倒裝晶片連接的IC晶片140、與佈線基板110的下表面之間，也可以不填充底部填膠。由於在安裝有IC晶片140的佈線基板110與引線框架120之間的空間，填充有密封樹脂102，所以即使省略了底部填膠的填充，在IC晶片140與佈線基板110之間的空間也填充了密封樹脂 102。其結果，不會發生IC晶片140從佈線基板110脫落等情況，不會降低IC晶片140的連接可靠性。 In the above-mentioned embodiment, the underfill 142 is filled between the lower surface of the wiring substrate 110 and the IC chip 140, but the underfill 142 is not necessarily filled. Specifically, for example, as shown in FIG. 30, the gap between the IC chip 140 that is flip-chip connected to the lower surface of the wiring substrate 110 by solder bumps 141 and the lower surface of the wiring substrate 110 may not be filled. Fill the bottom with glue. Since the space between the wiring substrate 110 on which the IC chip 140 is mounted and the lead frame 120 is filled with the sealing resin 102, even if underfill filling is omitted, the space between the IC chip 140 and the wiring substrate 110 is filled Sealing resin 102. As a result, the IC chip 140 does not fall off from the wiring substrate 110, and the connection reliability of the IC chip 140 does not decrease.

藉由省略底部填膠的填充，能夠簡化半導體裝置100的製造步驟，並能夠降低製造成本。此外，由於底部填膠不會擴散至IC晶片140的周圍，所以能夠縮小在佈線基板110的下表面用於搭載IC晶片140的區域的面積，能夠有效利用佈線基板110的表面。即，能夠在較窄範圍內安裝更多的電子零件，能夠實現半導體裝置100的小型化，並且能夠提高設計的自由度。 By omitting the filling of the underfill, the manufacturing steps of the semiconductor device 100 can be simplified, and the manufacturing cost can be reduced. In addition, since the underfill does not diffuse to the periphery of the IC chip 140, the area of the area where the IC chip 140 is mounted on the lower surface of the wiring substrate 110 can be reduced, and the surface of the wiring substrate 110 can be effectively used. That is, more electronic components can be mounted in a narrow range, the semiconductor device 100 can be reduced in size, and the degree of freedom of design can be improved.

此外，在此說明了在IC晶片140的安裝時省略底部填膠的填充的情況，但除了安裝IC晶片140的情況以外，例如，在藉由倒裝晶片連接而安裝於佈線基板110的電子零件與佈線基板110之間，也可以省略填充底部填膠。此外，對於安裝於佈線基板110的上表面的電子零件，由於其也被密封樹脂101包覆，所以能夠省略底部填膠的填充。 In addition, the case where the underfill filling is omitted during the mounting of the IC chip 140 is described here. However, in addition to the case of mounting the IC chip 140, for example, in the case of electronic parts mounted on the wiring board 110 by flip-chip connection Between the wiring substrate 110 and the wiring substrate 110, underfilling may also be omitted. In addition, since the electronic components mounted on the upper surface of the wiring board 110 are also covered with the sealing resin 101, the filling of the underfill can be omitted.

在省略了底部填膠的填充的情況下，例如，如圖31所示，也可以配置被夾持在IC晶片140與散熱板122之間的TIM105，在佈線基板110與引線框架120之間的空間填充一般的密封樹脂106。由此，由發熱量較大的IC晶片140產生的熱，藉由TIM105傳遞至散熱板122，能夠高效地進行散熱。此時，在散熱板122的上表面的與TIM105對應的位置，可以形成鍍層128。鍍層128例如由鍍銀(Ag)等貴金屬電鍍形成。即，鍍層128由與鍍層124相同的電鍍形成。 In the case where the underfill filling is omitted, for example, as shown in FIG. 31, a TIM 105 sandwiched between the IC chip 140 and the heat sink 122 may be arranged between the wiring substrate 110 and the lead frame 120. The space is filled with general sealing resin 106. As a result, the heat generated by the IC chip 140 with a large amount of heat can be transferred to the heat sink 122 by the TIM 105, so that the heat can be efficiently dissipated. At this time, a plating layer 128 may be formed on the upper surface of the heat sink 122 at a position corresponding to the TIM 105. The plating layer 128 is formed by noble metal plating such as silver (Ag) plating, for example. That is, the plating layer 128 is formed by the same electroplating as the plating layer 124.

由於鍍層128的表面與周圍的氧化膜125的表面相比，粗糙度低且平坦，所以藉由TIM105與鍍層128的接觸，與和氧化膜125接觸的情況相比，能夠使TIM105的厚度均勻。其結果，配置於IC晶片140與散熱板122之間的TIM105的厚度變得均勻，能夠使IC晶片140所產生的熱高效地傳遞至散熱板122。 Since the surface of the plating layer 128 has low roughness and flatness compared to the surface of the surrounding oxide film 125, the contact between the TIM 105 and the plating layer 128 makes it possible to make the thickness of the TIM 105 uniform compared to the case where it is in contact with the oxide film 125. As a result, the thickness of the TIM 105 arranged between the IC chip 140 and the heat dissipation plate 122 becomes uniform, and the heat generated by the IC chip 140 can be efficiently transferred to the heat dissipation plate 122.

在引線121的上表面形成鍍層124時，也可以同時形成鍍層128。即，在與下表面焊盤115c相對的位置形成鍍層124的同時，也可以在與IC晶片140相 對的位置形成鍍層128。並且，TIM105是藉由分配(dispense)或印刷等而塗敷於IC晶片140的背面的半固化狀態的高導熱樹脂在佈線基板110與引線框架120接合時固化而形成的。此外，作為TIM105的材料的高導熱樹脂，可以塗敷於鍍層128的表面，來取代塗敷於IC晶片140的背面。 When the plating layer 124 is formed on the upper surface of the lead 121, the plating layer 128 may also be formed at the same time. That is, while the plating layer 124 is formed at a position opposite to the lower surface pad 115c, it may also be positioned opposite to the IC chip 140. The plating layer 128 is formed at the right position. In addition, the TIM 105 is formed by curing the semi-cured highly thermally conductive resin applied to the back surface of the IC chip 140 by dispensing or printing or the like when the wiring substrate 110 and the lead frame 120 are bonded. In addition, the highly thermally conductive resin, which is the material of the TIM 105, may be coated on the surface of the plating layer 128 instead of being coated on the back surface of the IC chip 140.

(3)引線框架外邊緣的臺階 (3) Steps on the outer edge of the lead frame

在上述一實施形態中，在引線框架120的下表面的端部形成有臺階，但臺階也可以形成於端部以外的部分。具體而言，例如，如圖32所示，也可以在各引線121及散熱板122的周圍形成臺階面129。由此，密封樹脂102填充於引線121及散熱板122的臺階面129的下方，臺階面129被密封樹脂102包覆。其結果，能夠將引線框架120牢固地接合於半導體裝置100，並防止引線框架120的脫落等。在此，對在引線121及散熱板122的周圍形成有臺階面129的引線框架120的製造方法進行說明。 In the above-mentioned embodiment, a step is formed at the end of the lower surface of the lead frame 120, but the step may be formed at a portion other than the end. Specifically, for example, as shown in FIG. 32, a stepped surface 129 may be formed around each lead 121 and the heat dissipation plate 122. As a result, the sealing resin 102 is filled below the stepped surface 129 of the lead 121 and the heat sink 122, and the stepped surface 129 is covered with the sealing resin 102. As a result, the lead frame 120 can be firmly bonded to the semiconductor device 100, and the lead frame 120 can be prevented from falling off. Here, a method of manufacturing the lead frame 120 in which the stepped surface 129 is formed around the leads 121 and the heat dissipation plate 122 will be described.

與上述一實施形態相同，在製造引線框架120時，能夠使用例如厚度為50至200μm左右的銅或銅合金的金屬板。如圖33所示，在金屬板300的上表面及下表面，形成有抗蝕劑膜。即，在金屬板300的上表面形成有抗蝕劑膜310，並在下表面形成有抗蝕劑膜320。這些抗蝕劑膜310、320形成於作為引線121及散熱板122的位置而要留下來的位置。即，在不會作為金屬板300的引線121或散熱板122的位置而留下來的部分，形成有抗蝕劑膜的空隙。具體而言，在金屬板300的上表面形成有空隙310a，下表面形成有空隙320a。在此，下表面的空隙320a的寬度比上表面的空隙310a的寬度大。 As in the above-mentioned embodiment, when manufacturing the lead frame 120, for example, a metal plate of copper or copper alloy having a thickness of about 50 to 200 μm can be used. As shown in FIG. 33, a resist film is formed on the upper surface and the lower surface of the metal plate 300. As shown in FIG. That is, the resist film 310 is formed on the upper surface of the metal plate 300, and the resist film 320 is formed on the lower surface. These resist films 310 and 320 are formed at positions to be left as the positions of the leads 121 and the heat dissipation plate 122. That is, in the portion not left as the position of the lead 121 or the heat sink 122 of the metal plate 300, a gap of the resist film is formed. Specifically, a void 310a is formed on the upper surface of the metal plate 300, and a void 320a is formed on the lower surface. Here, the width of the gap 320a on the lower surface is larger than the width of the gap 310a on the upper surface.

藉由使形成有這種抗蝕劑膜的金屬板300浸漬於蝕刻液中，在空隙310a、320a曝露的金屬板300從表面起溶解，例如，如圖34所示，形成出引線121與散熱板122分離而成的引線框架120。然後，由於使下表面的空隙320a的寬度比上表面的空隙310a的寬度大，所以在下表面的空隙320a中與上表面的空隙310a 重合的區域，金屬板300從上表面及下表面起溶解，引線121及散熱板122完全分離。另一方面，在下表面的空隙320a中不與上表面的空隙310a重合的區域，金屬板300僅從下表面起溶解，從而形成出臺階面129。 By immersing the metal plate 300 on which such a resist film is formed in an etching solution, the metal plate 300 exposed in the voids 310a and 320a is dissolved from the surface. For example, as shown in FIG. 34, a lead 121 and a heat sink are formed. The lead frame 120 is formed by separating the board 122. Then, since the width of the gap 320a on the lower surface is made larger than the width of the gap 310a on the upper surface, the gap 320a on the lower surface is in line with the gap 310a on the upper surface. In the overlapping area, the metal plate 300 dissolves from the upper surface and the lower surface, and the lead 121 and the heat dissipation plate 122 are completely separated. On the other hand, in a region where the gap 320a on the lower surface does not overlap the gap 310a on the upper surface, the metal plate 300 only dissolves from the lower surface, and a step surface 129 is formed.

如此，藉由在金屬板300的上表面及下表面形成寬度不同的抗蝕劑膜，並使其浸漬於蝕刻液中，能夠形成在引線121及散熱板122的外邊緣具有臺階面129的引線框架。即，例如，如圖35所示，能夠在引線121及散熱板122中用斜線表示的外邊緣部，形成臺階面129。然後，具有臺階面129的引線框架120與佈線基板110接合，在佈線基板110與引線框架120之間的空間填充密封樹脂102時，密封樹脂102也填充於臺階面129的下方而對引線框架120進行支承，從而能夠防止引線框架120從半導體裝置100脫落。 In this way, by forming resist films with different widths on the upper and lower surfaces of the metal plate 300 and immersing them in an etching solution, it is possible to form leads with stepped surfaces 129 on the outer edges of the leads 121 and the heat sink 122. frame. That is, for example, as shown in FIG. 35, a stepped surface 129 can be formed at the outer edge portion indicated by diagonal lines in the lead 121 and the heat dissipation plate 122. Then, the lead frame 120 having the stepped surface 129 is joined to the wiring substrate 110. When the sealing resin 102 is filled in the space between the wiring substrate 110 and the lead frame 120, the sealing resin 102 is also filled under the stepped surface 129 and opposed to the lead frame 120. By supporting, it is possible to prevent the lead frame 120 from falling off the semiconductor device 100.

100:半導體裝置 100: Semiconductor device

101:密封樹脂 101: Sealing resin

102:密封樹脂 102: Sealing resin

103:電子零件 103: Electronic parts

103a:端子 103a: Terminal

103b:焊料 103b: Solder

110:佈線基板 110: Wiring board

111:基板 111: substrate

112:阻焊層 112: Solder mask

113:上表面焊盤 113: Upper surface pad

114:保護絕緣層 114: Protective insulating layer

115:下表面焊盤 115: bottom surface pad

120:引線框架 120: lead frame

121:引線 121: Lead

121a:側面 121a: side

122:散熱板 122: heat sink

123:鍍層 123: Plating

124:鍍層 124: Plating

125:氧化膜 125: Oxide film

130:連接構件 130: connecting member

131:芯 131: Core

132:焊料 132: Solder

140:IC晶片 140: IC chip

141:焊錫凸塊 141: Solder bump

142:底部填膠 142: bottom filling

150:電子零件 150: electronic parts

150a:端子 150a: terminal

150b:焊料 150b: solder

Claims (12)

一種半導體裝置，包括： A semiconductor device including: 引線框架，其由金屬構成； Lead frame, which is made of metal; 佈線基板，其與前述引線框架相向； A wiring substrate facing the aforementioned lead frame; 電子零件，其配置在前述引線框架與前述佈線基板之間； Electronic components, which are arranged between the aforementioned lead frame and the aforementioned wiring substrate; 連接構件，其將前述引線框架與前述佈線基板連接；以及 A connecting member that connects the lead frame and the wiring substrate; and 密封樹脂，其填充在前述引線框架與前述佈線基板之間，並包覆前述電子零件及前述連接構件， A sealing resin which is filled between the lead frame and the wiring board, and covers the electronic components and the connection member, 前述引線框架具有： The aforementioned lead frame has: 第一面，其與前述佈線基板相向，並由前述密封樹脂包覆； The first surface faces the aforementioned wiring substrate and is covered by the aforementioned sealing resin; 第二面，其位於前述第一面的背面側，並從前述密封樹脂露出；以及 The second surface is located on the back side of the first surface and is exposed from the sealing resin; and 側面，其與前述第一面或前述第二面相鄰，至少一部分從前述密封樹脂露出。 The side surface is adjacent to the first surface or the second surface, and at least a part is exposed from the sealing resin. 如請求項1之半導體裝置，其中， Such as the semiconductor device of claim 1, wherein 前述引線框架具有： The aforementioned lead frame has: 引線，其與前述連接構件連接；以及 A lead, which is connected to the aforementioned connecting member; and 散熱板，前述第一面與前述電子零件相向。 The first surface of the heat dissipation plate faces the electronic component. 如請求項2之半導體裝置，其中， Such as the semiconductor device of claim 2, in which, 前述引線框架具有分別與前述連接構件連接的複數個前述引線， The lead frame has a plurality of the leads connected to the connecting members, respectively, 複數個前述引線的與前述連接構件連接的部分的厚度均等。 The thicknesses of the portions connected to the connecting members of the plurality of leads are uniform. 如請求項1之半導體裝置，其中， Such as the semiconductor device of claim 1, wherein 前述第二面在前述側面附近的端部形成有臺階。 The second surface has a step formed at an end near the side surface. 如請求項1之半導體裝置，其中， Such as the semiconductor device of claim 1, wherein 前述第一面具有： The aforementioned first side has: 鍍層，其形成於與前述連接構件連接的位置；以及 A plating layer, which is formed at a position connected to the aforementioned connecting member; and 氧化膜，其形成於前述鍍層的周圍，並與前述密封樹脂接觸。 An oxide film is formed around the plating layer and is in contact with the sealing resin. 如請求項1之半導體裝置，其中， Such as the semiconductor device of claim 1, wherein 前述第一面具有氧化膜，其形成於與前述連接構件連接的位置的周圍，並與前述密封樹脂接觸。 The first surface has an oxide film, which is formed around the position connected to the connecting member and is in contact with the sealing resin. 如請求項1之半導體裝置，其中， Such as the semiconductor device of claim 1, wherein 前述密封樹脂含有填料。 The aforementioned sealing resin contains a filler. 如請求項1之半導體裝置，其中， Such as the semiconductor device of claim 1, wherein 前述密封樹脂填充於前述引線框架與前述佈線基板之間的空間，前述引線框架與前述佈線基板之間的空間包含前述電子零件與前述佈線基板之間的空間。 The sealing resin fills the space between the lead frame and the wiring substrate, and the space between the lead frame and the wiring substrate includes the space between the electronic component and the wiring substrate. 如請求項1之半導體裝置，其中，還包括： Such as the semiconductor device of claim 1, which also includes: 熱傳遞構件，其被夾持在前述引線框架與前述電子零件之間，將前述電子零件所產生的熱傳遞至前述引線框架。 The heat transfer member is sandwiched between the lead frame and the electronic component, and transfers the heat generated by the electronic component to the lead frame. 如請求項9之半導體裝置，其中， Such as the semiconductor device of claim 9, wherein 前述第一面具有在與前述熱傳遞構件接觸的位置形成的鍍層。 The first surface has a plating layer formed at a position in contact with the heat transfer member. 如請求項1之半導體裝置，其中， Such as the semiconductor device of claim 1, wherein 前述引線框架還具有臺階面，其與前述第二面之間具有臺階，並被前述密封樹脂包覆。 The lead frame further has a stepped surface, which has a stepped surface with the second surface, and is covered with the sealing resin. 一種半導體裝置的製造方法，包括： A method of manufacturing a semiconductor device includes: 將電子零件配置在由金屬構成的引線框架以及與該引線框架相向的佈線基板之間的步驟； A step of arranging electronic components between a lead frame made of metal and a wiring substrate facing the lead frame; 藉由連接構件，將前述引線框架與前述佈線基板接合的步驟；以及 The step of joining the lead frame and the wiring substrate by a connecting member; and 將密封樹脂填充在前述引線框架與前述佈線基板之間，並包覆前述電子零件及前述連接構件的步驟， The step of filling a sealing resin between the lead frame and the wiring substrate, and covering the electronic components and the connecting member, 前述包覆的步驟包括： The aforementioned coating steps include: 藉由前述密封樹脂，包覆前述引線框架的與前述佈線基板相向的第一面； The first surface of the lead frame facing the wiring substrate is covered by the sealing resin; 使前述引線框架的位於前述第一面的背面側的第二面，從前述密封樹脂露出；以及 Exposing the second surface of the lead frame on the back side of the first surface from the sealing resin; and 使前述引線框架的與前述第一面或前述第二面相鄰的側面的至少一部分，從前述密封樹脂露出。 At least a part of the side surface adjacent to the first surface or the second surface of the lead frame is exposed from the sealing resin.
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