TW202111886A - 封裝結構及其形成方法 - Google Patents

封裝結構及其形成方法 Download PDF

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TW202111886A
TW202111886A TW109122849A TW109122849A TW202111886A TW 202111886 A TW202111886 A TW 202111886A TW 109122849 A TW109122849 A TW 109122849A TW 109122849 A TW109122849 A TW 109122849A TW 202111886 A TW202111886 A TW 202111886A
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semiconductor device
protective layer
top surface
cover film
substrate
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TW109122849A
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TWI742749B (zh
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許峯誠
鄭心圃
陳碩懋
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台灣積體電路製造股份有限公司
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Abstract

本揭露之一些實施例提供了一種封裝結構及其形成方法。封裝結構包括一封裝基板、一中介基板、一第一半導體裝置、一第二半導體裝置以及一保護層。中介基板設置在封裝基板上方。第一半導體裝置以及第二半導體裝置設置在中介基板上方，其中第一半導體裝置以及第二半導體裝置係不同類型的電子裝置。保護層形成在中介基板上方，以包圍第一半導體裝置以及第二半導體裝置。第二半導體裝置自保護層暴露，而第一半導體裝置並未自保護層暴露。

Description

封裝結構及其形成方法
本揭露之一些實施例係有關於半導體封裝。
半導體積體電路（integrated circuit, IC）產業已經經歷了快速的成長。半導體製造製程中不斷的進步使得半導體裝置具有更精細的特徵及/或更高的積體程度。功能密度（亦即，每單位晶片面積的內連線結構之數量）通常增加，而特徵尺寸（亦即，使用製造製程所能產生的最小部件）則縮小。這樣的尺寸微縮化製程通常透過增加製造效率以及降低相關成本提供益處。
晶片封裝不僅為半導體裝置提供保護，以免受到環境汙染，而且，亦為封裝在其中的半導體裝置提供連接界面。已經發展出利用更少的面積或更低的高度的更小的封裝結構來封裝半導體裝置。
儘管現有的封裝技術已經通常適於其所欲達成的目的，不過現有的封裝技術並非在所有方面皆全然地令人滿意。
根據本揭露之一些實施例，提供了一種封裝結構。封裝結構包括一封裝基板、一中介基板、一第一半導體裝置、一第二半導體裝置以及一保護層。中介基板設置在封裝基板上方。第一半導體裝置以及第二半導體裝置設置在中介基板上方，其中第一半導體裝置以及第二半導體裝置係不同類型的電子裝置。保護層形成在中介基板上方，以包圍第一半導體裝置以及第二半導體裝置。第二半導體裝置自保護層暴露，而第一半導體裝置並未自保護層暴露。
根據本揭露之一些實施例，提供了一種封裝結構。封裝結構包括一封裝基板、一中介基板、一第一半導體裝置、一第二半導體裝置、一覆蓋膜以及一保護層。中介基板設置在封裝基板上方。第一半導體裝置以及一第二半導體裝置設置在中介基板上方。覆蓋膜形成在第一半導體裝置之一頂表面上。保護層形成在中介基板上方，以包圍第一半導體裝置、覆蓋膜以及第二半導體裝置。第二半導體裝置自保護層暴露，而第一半導體裝置並未自保護層暴露。
根據本揭露之一些實施例，提供了一種形成封裝結構之方法，方法包括堆疊設置在一封裝基板上方的一中介基板。方法亦包括在中介基板上方設置一第一半導體裝置以及一第二半導體裝置。方法進一步包括在中介基板上方形成一保護層，以包圍第一半導體裝置以及第二半導體裝置。除此之外，方法包括移除保護層之一部分，使得第二半導體裝置自保護層暴露，而第一半導體裝置並未自保護層暴露。
以下的揭露內容提供許多不同的實施例或範例以實施本案的不同特徵。以下描述具體的構件及其排列方式的實施例以闡述本揭露。當然，這些實施例僅作為範例，而不該以此限定本揭露的範圍。例如，在說明書中敘述了一第一特徵形成於一第二特徵之上或上方，其可能包含第一特徵與第二特徵是直接接觸的實施例，亦可能包含了有附加特徵形成於第一特徵與第二特徵之間，而使得第一特徵與第二特徵可能未直接接觸的實施例。另外，在本揭露不同範例中可能使用重複的參考符號及/或標記，此重複係為了簡化與清晰的目的，並非用以限定所討論的各個實施例及/或結構之間有特定的關係。
除此之外，所使用到的空間相關用語，例如「在…下方」、「下方」、「較低的」、「上方」、「較高的」及類似的用語，係為了便於描述圖示中一個元件或特徵與另一個（些）元件或特徵之間的關係。除了在圖式中繪示的方位外，這些空間相關用語意欲包含使用中或操作中的裝置之不同方位。設備/裝置可能被轉向不同方位（旋轉90度或其他方位），則在此使用的空間相關詞也可依此相同解釋。
說明書中的用語「實質上（substantially）」，例如「實質上平坦」或「實質上共平面」等可為本領域技術人員所能理解。在一些實施例中，形容詞實質上可被移除。在適用的情況下，用語「實質上」還可包括「全部（entirely）」、「完全（completely）」、「所有（all）」等的實施例。在適用的情況下，用語「實質上」還可涉及90%或更高，例如95%或更高，特別是99%或更高，包括100%。此外，例如「實質上平行」或「實質上垂直」之類的用語應解釋為不排除相較於特定佈置的微小偏差，並且例如可包括高達10°的偏差。用語「實質上」不排除「完全」，例如，「實質上不含（substantially free）」Y的組合物可能是完全不含Y。
與特定距離或尺寸結合使用的例如「約」的用語應解釋為不排除相較於特定距離或尺寸的微小偏差，並且例如可包括高達10%的偏差。相對於數值X的用語「約」可能表示X ±5或10%。
以下描述本揭露的一些實施例。可在這些實施例中描述的階段之前、之中及/或之後提供額外的操作。在不同的實施例中，可替換或消除所述的某些階段。可將附加特徵添加到版導體裝置結構中。在不同的實施例中，可替換或消除所述的某些特徵。儘管下文中以特定順序執行的操作來討論一些實施例，但是也可其他的邏輯順序來執行這些操作。
本揭露之一些實施例可能係有關於3D封裝或3D-IC裝置。亦可包括其他特徵以及製程。例如，可包括測試結構，以幫助對3D封裝或3D-IC裝置進行驗證測試。測試結構可包括例如形成在重分布層中或在基板上的測試墊，其允許測試3D封裝或3D-IC、使用探針及/或探針卡等。可對中間結構以及最終結構執行驗證測試。額外地，在此所揭露的結構以及方法可與結合已知良好的晶粒之中間驗證的測試方法一起使用，以增加良率並降低成本。
第1A圖至第1E圖係根據一些實施例來形成封裝結構的製程之各種階段之剖面圖。如第1A圖所示，根據一些實施例，在一承載基板100上方形成一封裝基板102。承載基板100可為玻璃基板、半導體基板或其他合適的基板。在後續階段（如第1E圖所繪示的）移除承載基板100之後，可使用封裝基板102來提供在封裝結構中的半導體裝置（將在以下內容描述）與外部電子裝置之間的電性連接。
封裝基板102可用於佈線（routing）。在一些實施例中，封裝基板102為重分布基板。在一些替代性實施例中，封裝基板102為包括核以及在核之相對側上的增層（build-up）層的一增層基板。在本揭露之實施例之後續討論中，繪示出重分布基板來作為封裝基板102之範例，不過，根據一些範例實施例透露出的教示亦可輕易的適用於增層基板。如第1A圖所示，重分布基板102包括多個層壓絕緣層104以及由絕緣層104包圍的多個導電特徵106。導電特徵106可包括導電線路、導電導孔及/或導電墊。在一些實施例中，一些導電導孔彼此堆疊。上導電導孔實質上與下導電導孔對齊。在一些實施例中，一些導孔為交錯排列的（staggered）導孔。上導電導孔與下導電導孔不對齊。
絕緣層104可包括或由一種或多種聚合物材料製成。聚合物材料可包括聚苯噁唑（polybenzoxazole, PBO）、聚醯亞胺（polyimide, PI）、環氧基樹脂或前述材料之組合。在一些實施例中，聚合物材料為光敏性的（photosensitive）。因此，可使用光微影製程，以在絕緣層104中形成具有期望圖案的開口。
在一些其他實施例中，絕緣層104之一部分或全部包括或由聚合物材料以外的介電質材料製成。介電質材料可包括氧化矽、碳化矽、氮化矽、氮氧化矽、一種或多種其他合適的材料或上述之組合。
導電特徵106可包括在水平方向上提供電性連接的導線以及在鉛直方向上提供電性連接的導電導孔。導電特徵106可包括或由銅、鋁、金、鈷、鈦、鎳、銀、石墨烯、一種或多種其他合適的導電材料或前述材料之組合製成。在一些實施例中，導電特徵106包括多個子層。例如，每個導電特徵106包含多個子層，包括鈦/銅、鈦/鎳/銅、鈦/銅/鈦、鋁/鈦/鎳/銀、其他合適的多個子層或前述子層之組合。
重分布基板102之形成可涉及多個沉積或塗布製程、多個圖案化製程及/或多個平坦化製程。
沉積或塗布製程可用於形成絕緣層及/或導電層。沉積或塗布製程可包括旋轉塗布製程、電鍍製程、化學鍍製程（electroless process）、化學氣相沉積（chemical vapor deposition, CVD）製程、物理氣相沉積（physical vapor deposition, PVD）製程、原子層沉積（atomic layer deposition, ALD）製程、一種或多種其他適用的製程或前述製程之組合。
圖案化製程可用於圖案化形成的絕緣層及/或形成的導電層。圖案化製程可包括光微影製程、能量束鑽孔製程（例如，雷射束鑽孔製程、離子束鑽孔製程或電子束鑽孔製程）、蝕刻製程、機械鑽孔製程、一種或多種其他適用的製程或前述製程之組合。
平坦化製程可用於為形成的絕緣層及/或形成的導電層提供平坦的頂表面，以利於後續的製程。平坦化製程可包括機械研磨（mechanical grinding）製程、化學機械研磨（chemical mechanical polishing , CMP）製程、一種或多種其他適用的製程或前述製程之組合。
如第1A圖所示，根據一些實施例，重分布基板102亦包括形成在其上的複數個導電元件108。每個導電元件108可能自絕緣層104之最頂部的表面暴露或突出，且可電性連接至導電特徵106之其中之一者。導電元件108可用於保持或接收諸如為導電柱及/或導電球的導電特徵。
導電元件108可包括或由銅、鋁、金、鈷、鈦、錫、一種或多種其他合適的材料或前述材料之組合製成。可使用電鍍製程、化學鍍製程、放置製程（placement process）、印刷製程、物理氣相沉積製程、化學氣相沉積製程、一種或多種其他適用的製程或前述製程之組合來形成導電元件108。
如第1B圖所示，根據一些實施例，在重分布基板102上方堆疊一中介基板110。在一些實施例中，中介基板110透過導電結構116接合至導電元件108上。導電結構116可包括焊料凸塊（solder bumps）、焊料球、導電柱、其他合適的導電元件或前述導電元件之組合。
在一些實施例中，中介基板110包括一板112以及複數個導電特徵114。導電特徵114可包括或由銅、鋁、鈷、鎳、金、銀、鎢、一種或多種其他合適的材料或前述材料之組合製成。板112可包括或由聚合物材料、陶瓷材料、金屬材料、半導體材料、一種或多種其他合適的材料或前述材料之組合製成。例如，板112包括樹脂、膠片（prepreg）、玻璃及/或陶瓷。在板112由金屬材料或半導體材料（例如，矽）製成的情況下，可在板112與導電特徵114之間形成介電層，以防止短路。
在板112包括或由聚合物材料製成的情況下，板112可進一步包括分散在聚合物材料中的填料。聚合物材料可包括或由環氧基樹脂、聚醯亞胺基樹脂、一種或多種其他合適的聚合物材料或前述材料之組合製成。填料之範例可包括纖維（例如，二氧化矽纖維及/或含碳纖維）、顆粒（例如，二氧化矽顆粒及/或含碳顆粒）或纖維以及顆粒之組合。
在一些實施例中，中介基板110比重分布基板102包含更多的填料。在一些實施例中，板112具有比重分布基板102之絕緣層104更高的填料重量百分比。在一些實施例中，重分布基板102之絕緣層104包括或由聚合物材料製成。在一些實施例中，重分布基板102之絕緣層104並未包含填料。在這些情況下，重分布基板102並未包含填料。
在一些實施例中，中介基板110以及承載基板100在高溫下彼此擠壓。結果，中介基板110透過導電結構116接合至重分布基板102。在一些實施例中，使用熱壓合（thermal compression）製程來達成前述接合製程。
之後，如第1B圖所示，根據一些實施例，形成一底部填充（underfill）元件118，以包圍並保護導電結構116。底部填充元件118可包括或由諸如底部填充材料的絕緣材料製成。底部填充材料可包括環氧樹脂、樹脂、填料材料、應力消除劑（stress release agent, SRA）、黏著促進劑、其他合適的材料或前述材料之組合。在一些實施例中，在中介基板110與重分布基板102之間的間隙分散液態底部填充材料，以強化導電結構116以及封裝結構之整體之強度。在前述分散之操作之後，固化底部填充材料，以形成底部填充元件118。底部填充元件118亦可為封裝結構提供熱傳導路徑。在一些其他實施例中，並未形成底部填充元件118。
如第1B圖所示，根據一些實施例，中介基板110亦包括形成在其上的複數個導電元件120以及複數個導電元件122。每個導電元件120、122可能自板112之頂表面暴露或突出，且可電性連接至導電特徵114之其中之一者。導電元件120以及導電元件122可用於保持或接收諸如為導電柱及/或導電球的導電特徵。導電元件120以及導電元件122之材料以及形成方法可等同於或類似於第1A圖中所繪示的導電元件108。
如第1C圖所示，根據一些實施例，在中介基板110上方堆疊複數個半導體裝置124以及複數個半導體裝置128，為了簡化，僅示出一個半導體裝置124以及一個半導體裝置128。在一些實施例中，半導體裝置124及/或半導體裝置128包括一個或多個半導體晶粒或晶片，其可為任何類型的積體電路，例如，處理器、邏輯電路、記憶體、類比電路、數位電路、混合訊號等。在一些實施例中，半導體裝置124及/或半導體裝置128包括一個或多個主動裝置，例如，電晶體、二極體、光二極體或其他合適的主動裝置。或者，在一些實施例中，半導體裝置124及/或半導體裝置128包括一個或多個被動裝置，例如，電阻、電容、電感或其他合適的被動裝置。
在一些實施例中，半導體裝置124以及半導體裝置128為提供不同功能的不同類型的半導體裝置。例如，半導體裝置124為記憶體裝置，而半導體裝置128為處理器裝置。然而，亦可使用其他組合的半導體裝置124以及半導體裝置128。
在一些實施例中，半導體裝置124以及半導體裝置128具有不同尺寸。例如，如第1C圖所示，半導體裝置124在實質上垂直於中介基板110之一頂表面110A的一方向D1上之一高度H1小於半導體裝置128在方向D1上之一高度H2。
在一些實施例中，每個半導體裝置124透過複數個導電結構126接合至導電元件120上，而每個半導體裝置128透過複數個導電結構130接合至導電元件122上。如此一來，各種半導體裝置124、128透過中介基板110彼此通訊。因此，改善了訊號傳輸速度。導電結構126及/或導電結構130可包括導電柱、焊料凸塊、焊料球、一種或多種其他合適的導電元件或前述導電元件之組合。導電結構126以及導電結構130之材料以及形成方法可等同於或類似於第1B圖中所繪示的導電結構116。在一些實施例中，形成一底部填充元件132，以包圍並保護導電結構126以及導電結構130。底部填充元件132之材料以及形成方法可等同於或類似於第1B圖中所繪示的底部填充元件118。
在一些未繪示的實施例中，省略了導電元件120及/或導電元件122，並透過焊料凸塊、焊料球、導電柱、一種或多種合適的導電元件或前述導電元件之組合將半導體裝置124及/或半導體裝置128接合至中介基板110之墊區域（由一些導電特徵114構成）上。
如第1D圖所示，根據一些實施例，形成一保護層134以包圍並保護半導體裝置124以及半導體裝置128。在一些實施例中，保護層134藉由底部填充元件132與半導體裝置124下方的導電結構126以及半導體裝置128下方的導電結構130分離。然而，本揭露之實施例不限於此。可對本揭露之實施例進行許多變化及/或修改。在一些其他實施例中，並未形成底部填充元件132。在這些情況下，保護層134可直接接觸半導體裝置124下方的導電結構126以及半導體裝置128下方的導電結構130。
在一些實施例中，保護層134包括或由絕緣材料製成，例如模製材料（molding material）。模製材料可包括聚合物材料，例如其中分散有填料的環氧基樹脂。在一些實施例中，將模製材料（例如，液態模製材料）分配至中介基板110之頂表面110A上及/或半導體裝置124以及半導體裝置128上方。之後，在一些實施例中，使用熱製程來固化液態模製材料並將其轉變成保護層134。
在一些實施例中，在保護層134上進行平坦化製程，以部分地移除保護層134。因此，如第1D圖所示，暴露出每個半導體裝置128之頂表面128A，但並未暴露出每個半導體裝置124之頂表面124A。在一些實施例中，在平坦化製程之後，每個半導體裝置128之頂表面128A實質上與保護層134之頂表面134A齊平，且每個半導體裝置124之頂表面124A與保護層134之頂表面134A相隔一距離G。平坦化製程可包括研磨製程、化學機械研磨製程、蝕刻製程、乾式研磨製程、一種或多種其他適用的製程或前述製程之組合。
之後，如第1E圖所示，根據一些實施例，移除承載基板100，以暴露出封裝基板102之表面。在一些實施例中，在形成封裝基板102之前，先在承載基板100上方形成一離型膜（release film）（未圖示）。離型膜101係暫時性接合材料，其有助於承載基板100與封裝基板102之間的分離操作。
如第1E圖所示，在一些實施例中，在封裝基板102的原來由承載基板100覆蓋之表面上方形成複數個導電凸塊136。每個導電凸塊136可電性連接至封裝基板102之導電特徵106之一者。導電凸塊136使得封裝結構能夠電性連接至一外部裝置（未圖示）。導電凸塊136包括或為焊料凸塊，例如，含錫焊料凸塊。含錫焊料凸塊可進一步包括銅、銀、金、鋁、鉛、一種或多種其他合適的材料或前述材料之組合。在一些實施例中，含錫焊料凸塊係無鉛的。
在一些實施例中，在移除承載基板100之後，將焊料球（或焊料元件）設置在暴露的導電特徵106上。之後，執行回焊（reflow）製程，以將焊球熔化成導電凸塊136。在一些其他實施例中，在設置焊料球之前，在暴露的導電特徵106上方形成凸塊下金屬化（under bump metallization, UBM）元件。在一些其他實施例中，將焊料元件電鍍至暴露的導電特徵106上。之後，使用回焊製程將焊料元件熔化，以形成導電凸塊136。
之後，在一些實施例中，執行分割（singulation）製程。因此，形成了多個分隔的封裝結構。在第1E圖中，示出了封裝結構之一者。保護層134具有暴露出每個半導體裝置128之頂表面128A的一開口134B。在操作中的半導體裝置128（例如，一處理器裝置）可能產生大量的熱的情況下，保護層134中的開口134B有助於自半導體裝置128快速的散熱並避免過熱。
額外地，如第1E圖所示，保護層134進一步具有覆蓋每個半導體裝置124之頂表面124A的一覆蓋部134C。在一些實施例中，覆蓋部134C實質上覆蓋半導體裝置124之頂表面124A之整體。在一些實施例中，覆蓋部134C直接地設置在半導體裝置124之頂表面124A上。因此，保護層134之覆蓋部134C可降低半導體裝置124中的翹曲（warpage），其將在以下內容中解釋。在一些實施例中，因為如前所述的回焊製程或熱製程中使用高溫，導致半導體裝置124易於翹曲或彎曲，且半導體裝置124中的翹曲可能導致下方的導電結構126中產生不規則的接縫（joint）或裂痕。因為覆蓋部134C覆蓋並擠壓半導體裝置124，可降低半導體裝置124中的翹曲。
因此，改善了封裝結構中的半導體裝置之性能以及可靠度。因此，亦改善了封裝結構之整體的性能（包括電性性能以及機械性能）以及可靠度。
可對本揭露之實施例進行許多變化及/或修改。第2A圖至第2C圖係根據一些實施例來形成封裝結構的製程之各種階段之剖面圖。
如第2A圖所示，提供了或接收了類似於如第1C圖中示出的一結構。之後，根據一些實施例，在每個半導體裝置124上方形成一覆蓋膜200。在一些實施例中，覆蓋膜200直接地設置（亦即，直接接觸）在半導體裝置124之頂表面124A上。在一些實施例中，覆蓋膜200實質上覆蓋半導體裝置124之頂表面124A之整體。如第2A圖所示，在一些實施例中，半導體裝置124在實質上垂直於中介基板110之頂表面110A的方向D1上之高度H1與覆蓋膜200在方向D1上之高度H3之總和（亦即，H1+H3）小於半導體裝置128在方向D1上之高度H2。
在一些實施例中，覆蓋膜200包括有機聚合物材料（例如，環氧樹脂、樹脂等），且有機聚合物材料具有或不具有硬化劑（hardeners）、填料（例如，二氧化矽填料、玻璃填料、氧化鋁、氧化矽等）、黏著促進劑、前述材料之組合等。或者，覆蓋膜200包括銅、鋁、金、鈦、其他合適的金屬材料、前述材料之合金或前述材料之組合。可使用放置製程（placement process）、印刷製程、物理氣相沉積製程、化學氣相沉積製程、一種或多種其他適用的製程或前述製程之組合來形成覆蓋膜200。
如第2B圖所示，根據一些實施例，形成保護層134以包圍並保護半導體裝置124、覆蓋膜200以及半導體裝置128。保護層134之材料以及形成方法可等同於或類似於第1D圖中所繪示的保護層134。在一些實施例中，覆蓋膜200包括不同於保護層134的材料。例如，保護層134包括如前所述的模製材料，而覆蓋膜200包括如前所述的有機聚合物材料或金屬材料。在一些實施例中，覆蓋膜200之硬度高於保護層134之硬度。
在一些實施例中，在保護層134上進行平坦化製程，以部分地移除保護層134。因此，如第2B圖所示，暴露出每個半導體裝置128之頂表面128A，但並未暴露出在相應的半導體裝置124上方的每個覆蓋膜200之頂表面200A。在一些實施例中，在平坦化製程之後，每個半導體裝置128之頂表面128A實質上與保護層134之頂表面134A齊平，且每個覆蓋膜200之頂表面200A與保護層134之頂表面134A相隔一距離G’。平坦化製程可包括研磨製程、化學機械研磨製程、蝕刻製程、乾式研磨製程、一種或多種其他適用的製程或前述製程之組合。
之後，如第2C圖所示，根據一些實施例，移除承載基板100，以暴露出封裝基板102之表面。如第2C圖所示，之後，在一些實施例中，在封裝基板102的原來由承載基板100覆蓋之表面上方形成導電凸塊136。導電凸塊136之材料以及形成方法可等同於或類似於第1E圖中所繪示的導電凸塊136。
之後，在一些實施例中，執行分割製程。因此，形成了多個分隔的封裝結構。在第2C圖中，示出了封裝結構之一者。類似於第1E圖中示出的封裝結構，保護層134具有暴露出每個半導體裝置128之頂表面128A的開口134B。開口134B有助於自半導體裝置128快速的散熱並避免過熱。
額外地，如第2C圖所示，保護層134進一步具有覆蓋每個覆蓋膜200之頂表面200A的覆蓋部134C，使得覆蓋膜200介於覆蓋部134C與相應的半導體裝置124之頂表面124A之間。因為覆蓋部134C以及覆蓋膜200覆蓋並擠壓半導體裝置124，可降低半導體裝置124中的翹曲。覆蓋膜200之剛性亦阻擋了半導體裝置124之彎曲。
因此，改善了封裝結構中的半導體裝置之性能以及可靠度。因此，亦改善了封裝結構之整體的性能（包括電性性能以及機械性能）以及可靠度。
可對本揭露之實施例進行許多變化及/或修改。第3圖係根據一些實施例的封裝結構之剖面圖。在第3圖中，覆蓋膜200被形成以覆蓋半導體裝置124之頂表面124A之一部分，而非頂表面124A之整體，而封裝結構之其他部分等同於第2C圖中示出的封裝結構之其他部分。在一些實施例中，覆蓋膜200可覆蓋半導體裝置124之頂表面124A之90%至95%。已經觀測到的是，在半導體裝置124上方提供這樣的覆蓋比例可有效地降低發生在半導體裝置124中的翹曲。然而，本揭露之實施例不限於此。只要可降低半導體裝置124中的翹曲，亦可在半導體裝置124上方使用其他覆蓋膜200之覆蓋率。
可對本揭露之實施例進行許多變化及/或修改。第4圖係根據一些實施例的封裝結構之剖面圖。在第4圖中，保護層134不僅具有暴露出每個半導體裝置128之頂表面128A的一開口134B，而且具有暴露出在相應的半導體裝置124上方的每個覆蓋膜200之頂表面200A的一開口134D，而且封裝結構之其他部分等同於第2C圖中示出的封裝結構之其他部分。
如第4圖所示，在一些實施例中，覆蓋膜200經選擇，使得半導體裝置124在實質上垂直於中介基板110之頂表面110A的方向D1上之高度H1與覆蓋膜200在方向D1上之高度H3之總和（亦即，H1+H3）等於半導體裝置128在方向D1上之高度H2。因此，在保護層134上進行平坦化製程來部分地移除保護層134之後，保護層134之頂表面134A實質上與覆蓋膜200之頂表面200A以及半導體裝置128之頂表面128A齊平。這有助於透過開口134B以及開口134D自半導體裝置128以及半導體裝置124快速的散熱並避免過熱。在一些其中覆蓋膜200包括金屬材料的實施例中，這進一步幫助自半導體裝置124移除熱。
儘管第4圖示出覆蓋膜200覆蓋半導體裝置124之頂表面124A之整體，不過，在其他未繪示的實施例中，覆蓋膜200亦可覆蓋半導體裝置124之頂表面124A之一部分。類似於第2C圖以及第3圖之實施例，覆蓋膜200之剛性亦阻擋了半導體裝置124之翹曲或彎曲。
可對本揭露之實施例進行許多變化及/或修改。例如，第1圖至第4圖中示出的封裝結構中的半導體裝置124及/或半導體裝置128亦可包括或為一個或多個封裝模組（例如，如第5圖所示）。
第5圖係根據一些實施例的一封裝模組之剖面圖。如第5圖所示，根據一些實施例，封裝模組包括一內連線結構500以及形成在內連線結構500上的一個或多個半導體晶粒502、504。在各種實施例中，半導體晶粒502、504可為如前所述的任何類型的半導體晶粒。半導體晶粒502、504可透過翻轉晶片（flip-chip）接合、線路接合及/或任何其他適用的接合方法來接合至內連線結構500。在一些實施例中，內連線結構500係一中介基板，其承載半導體晶粒502、504並提供在半導體晶粒502、504與中介基板110之間的電性連接（請見第1圖至第4圖）。在這些情況下，內連線結構500具有類似於中介基板110之結構的結構。如第5圖所示，根據一些實施例，封裝模組進一步包括形成在中介基板110上方的一保護層506，以包圍並保護半導體晶粒502、504。保護層506之材料以及形成方法可等同於或類似於第1D圖中所繪示的保護層134。
儘管在前述實施例之封裝結構中僅有二種類型的半導體裝置，在其他實施例中亦可使用更多類型的半導體裝置。
本揭露之一些實施例形成一封裝結構，封裝結構包括一封裝基板、在封裝基板上方的一中介基板以及在中介基板上方的多個半導體裝置。形成一保護層，以包圍並保護半導體裝置。透過保護層中的複數個開口暴露出一些半導體裝置，使得所產生的熱可快速的消散。一些其他半導體裝置內埋在保護層中或由額外的覆蓋膜覆蓋，使得可降低半導體裝置中的翹曲。改善了封裝結構中的半導體裝置之性能以及可靠度。因此，亦改善了封裝結構之整體的性能（包括電性性能以及機械性能）以及可靠度。
根據本揭露之一些實施例，提供了一種封裝結構。封裝結構包括一封裝基板、一中介基板、一第一半導體裝置、一第二半導體裝置以及一保護層。中介基板設置在封裝基板上方。第一半導體裝置以及第二半導體裝置設置在中介基板上方，其中第一半導體裝置以及第二半導體裝置係不同類型的電子裝置。保護層形成在中介基板上方，以包圍第一半導體裝置以及第二半導體裝置。第二半導體裝置自保護層暴露，而第一半導體裝置並未自保護層暴露。
在一些實施例中，保護層包括覆蓋第一半導體裝置之一頂表面的一覆蓋部以及暴露出第二半導體裝置之一頂表面的一開口。在一些實施例中，覆蓋部直接地設置在第一半導體裝置之頂表面上。在一些實施例中，封裝結構更包括形成在覆蓋部與第一半導體裝置之頂表面之間的一覆蓋膜，且覆蓋膜包括不同於保護層的材料。在一些實施例中，覆蓋膜直接地設置在第一半導體裝置之頂表面上。在一些實施例中，覆蓋膜覆蓋第一半導體裝置之頂表面之一部分。在一些實施例中，覆蓋膜具有較保護層高的硬度。
根據本揭露之一些實施例，提供了一種封裝結構。封裝結構包括一封裝基板、一中介基板、一第一半導體裝置、一第二半導體裝置、一覆蓋膜以及一保護層。中介基板設置在封裝基板上方。第一半導體裝置以及一第二半導體裝置設置在中介基板上方。覆蓋膜形成在第一半導體裝置之一頂表面上。保護層形成在中介基板上方，以包圍第一半導體裝置、覆蓋膜以及第二半導體裝置。第二半導體裝置自保護層暴露，而第一半導體裝置並未自保護層暴露。
在一些實施例中，保護層包括暴露出覆蓋膜之一頂表面的一第一開口以及暴露出第二半導體裝置之一頂表面的一第二開口。在一些實施例中，保護層之一頂表面與覆蓋膜之頂表面以及第二半導體裝置之頂表面齊平。在一些實施例中，覆蓋膜直接地設置在第一半導體裝置之頂表面上。在一些實施例中，覆蓋膜覆蓋第一半導體裝置之頂表面之一部分。在一些實施例中，覆蓋膜覆蓋第一半導體裝置之頂表面之整體。在一些實施例中，覆蓋膜包括不同於保護層的材料。在一些實施例中，覆蓋膜具有較保護層高的硬度。
根據本揭露之一些實施例，提供了一種形成封裝結構之方法，方法包括堆疊設置在一封裝基板上方的一中介基板。方法亦包括在中介基板上方設置一第一半導體裝置以及一第二半導體裝置。方法進一步包括在中介基板上方形成一保護層，以包圍第一半導體裝置以及第二半導體裝置。除此之外，方法包括移除保護層之一部分，使得第二半導體裝置自保護層暴露，而第一半導體裝置並未自保護層暴露。
在一些實施例中，在移除保護層之部分之後，保護層包括殘留在第一半導體裝置之一頂表面上的一覆蓋部以及暴露出第二半導體裝置之一頂表面的一開口。在一些實施例中，在形成保護層之前，形成封裝結構之方法更包括在第一半導體裝置上方形成一覆蓋膜，其中在移除保護層之部分之後，覆蓋膜位於覆蓋部與第一半導體裝置之頂表面之間。在一些實施例中，覆蓋膜直接接觸第一半導體裝置之頂表面。在一些實施例中，覆蓋膜被形成以覆蓋第一半導體裝置之該頂表面之一部分。
前面概述數個實施例之特徵，使得本技術領域中具有通常知識者可更好地理解本揭露之各方面。本技術領域中具有通常知識者應理解的是，可輕易地使用本揭露作為設計或修改其他製程以及結構的基礎，以實現在此介紹的實施例之相同目的及/或達到相同優點。本技術領域中具有通常知識者亦應理解的是，這樣的等效配置並不背離本揭露之精神以及範疇，且在不背離本揭露之精神以及範疇的情形下，可對本揭露進行各種改變、替換以及更改。
100:承載基板 102:封裝基板,重分布基板 104:絕緣層 106,114:導電特徵 108,120,122:導電元件 110:中介基板 110A:中介基板之頂表面 112:板 116,126,130:導電結構 118,132:底部填充元件 124,128:半導體裝置 124A,128A:半導體裝置之頂表面 134,506:保護層 134A:保護層之頂表面 134B,134D:開口 134C:覆蓋部 136:導電凸塊 200:覆蓋膜 200A:覆蓋膜之頂表面 500:內連線結構 502,504:半導體晶粒 D1:方向 G,G':距離 H1,H2,H3:高度
當閱讀所附圖式時，從以下的詳細描述能最佳理解本揭露之各方面。應注意的是，各種特徵並不一定按照比例繪製。事實上，可能任意地放大或縮小各種特徵之尺寸，以做清楚的說明。 第1A圖至第1E圖係根據一些實施例來形成封裝結構的製程之各種階段之剖面圖。 第2A圖至第2C圖係根據一些實施例來形成封裝結構的製程之各種階段之剖面圖。 第3圖係根據一些實施例的封裝結構之剖面圖。 第4圖係根據一些實施例的封裝結構之剖面圖。 第5圖係根據一些實施例的封裝模組之剖面圖。
無
102:封裝基板，重分布基板
104:絕緣層
106,114:導電特徵
108,120,122:導電元件
110:中介基板
112:板
116,126,130:導電結構
118,132:底部填充元件
124,128:半導體裝置
124A,128A:半導體裝置之頂表面
134:保護層
134A:保護層之頂表面
134B:開口
134C:覆蓋部
136:導電凸塊

Claims (20)

  1. 一種封裝結構，包括： 一封裝基板； 一中介基板，設置在該封裝基板上方； 一第一半導體裝置以及一第二半導體裝置，設置在該中介基板上方，其中該第一半導體裝置以及該第二半導體裝置係不同類型的電子裝置；以及 一保護層，形成在該中介基板上方，以包圍該第一半導體裝置以及該第二半導體裝置，其中該第二半導體裝置自該保護層暴露，而該第一半導體裝置並未自該保護層暴露。
  2. 如請求項1之封裝結構，其中該保護層包括覆蓋該第一半導體裝置之一頂表面的一覆蓋部以及暴露出該第二半導體裝置之一頂表面的一開口。
  3. 如請求項2之封裝結構，其中該覆蓋部直接地設置在該第一半導體裝置之該頂表面上。
  4. 如請求項2之封裝結構，更包括形成在該覆蓋部與該第一半導體裝置之該頂表面之間的一覆蓋膜，且該覆蓋膜包括不同於該保護層的材料。
  5. 如請求項4之封裝結構，其中該覆蓋膜直接地設置在該第一半導體裝置之該頂表面上。
  6. 如請求項4之封裝結構，其中該覆蓋膜覆蓋該第一半導體裝置之該頂表面之一部分。
  7. 如請求項4之封裝結構，其中該覆蓋膜具有較該保護層高的硬度。
  8. 一種封裝結構，包括： 一封裝基板； 一中介基板，設置在該封裝基板上方； 一第一半導體裝置以及一第二半導體裝置，設置在該中介基板上方； 一覆蓋膜，形成在該第一半導體裝置之一頂表面上；以及 一保護層，形成在該中介基板上方，以包圍該第一半導體裝置、該覆蓋膜以及該第二半導體裝置，其中該第二半導體裝置自該保護層暴露，而該第一半導體裝置並未自該保護層暴露。
  9. 如請求項8之封裝結構，其中該保護層包括暴露出該覆蓋膜之一頂表面的一第一開口以及暴露出該第二半導體裝置之一頂表面的一第二開口。
  10. 如請求項9之封裝結構，其中該保護層之一頂表面與該覆蓋膜之該頂表面以及該第二半導體裝置之該頂表面齊平。
  11. 如請求項8之封裝結構，其中該覆蓋膜直接地設置在該第一半導體裝置之該頂表面上。
  12. 如請求項8之封裝結構，其中該覆蓋膜覆蓋該第一半導體裝置之該頂表面之一部分。
  13. 如請求項8之封裝結構，其中該覆蓋膜覆蓋該第一半導體裝置之該頂表面之整體。
  14. 如請求項8之封裝結構，其中該覆蓋膜包括不同於該保護層的材料。
  15. 如請求項8之封裝結構，其中該覆蓋膜具有較該保護層高的硬度。
  16. 一種形成封裝結構之方法，包括： 堆疊設置在一封裝基板上方的一中介基板； 在該中介基板上方設置一第一半導體裝置以及一第二半導體裝置； 在該中介基板上方形成一保護層，以包圍該第一半導體裝置以及該第二半導體裝置；以及 移除該保護層之一部分，使得該第二半導體裝置自該保護層暴露，而該第一半導體裝置並未自該保護層暴露。
  17. 如請求項16之形成封裝結構之方法，其中在移除該保護層之該部分之後，該保護層包括殘留在該第一半導體裝置之一頂表面上的一覆蓋部以及暴露出該第二半導體裝置之一頂表面的一開口。
  18. 如請求項17之形成封裝結構之方法，其中在形成該保護層之前，形成封裝結構之方法更包括在該第一半導體裝置上方形成一覆蓋膜； 其中在移除該保護層之該部分之後，該覆蓋膜位於該覆蓋部與該第一半導體裝置之該頂表面之間。
  19. 如請求項18之形成封裝結構之方法，其中該覆蓋膜直接接觸該第一半導體裝置之該頂表面。
  20. 如請求項18之形成封裝結構之方法，其中該覆蓋膜被形成以覆蓋該第一半導體裝置之該頂表面之一部分。
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