TW202111866A - Conductive blind-hole structure, package substrate, and chip package structure - Google Patents
Conductive blind-hole structure, package substrate, and chip package structure Download PDFInfo
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Description
本發明是有關於一種導電盲孔結構及應用此導電盲孔結構的封裝基板以及晶片封裝結構。The invention relates to a conductive blind hole structure and a packaging substrate and a chip packaging structure using the conductive blind hole structure.
一般的封裝基板中,導電盲孔(via)大都是經由走線與接墊(bond pad)進行電性導通。然而,為滿足半導體封裝高積集度及微型化的需求,如何製作出適宜的導電盲孔以提升封裝基板與晶片封裝結構中可應用的空間,實為本領域的技術人員的一大挑戰。In general packaging substrates, conductive vias are mostly electrically conducted through traces and bond pads. However, in order to meet the requirements of high integration and miniaturization of semiconductor packages, how to make suitable conductive blind vias to increase the applicable space in the package substrate and chip package structure is actually a big challenge for those skilled in the art.
本發明提供一種導電盲孔結構,其具有較大的熱傳導截面積,可有效地減少導通阻抗。The present invention provides a conductive blind hole structure, which has a larger heat conduction cross-sectional area and can effectively reduce the conduction resistance.
本發明提供一種採用上述導電盲孔結構的封裝基板以及晶片封裝結構,其可節省佈局空間,進而達到增加線路密度。The present invention provides a packaging substrate and a chip packaging structure adopting the above-mentioned conductive blind hole structure, which can save layout space and further increase the line density.
本發明的導電盲孔結構適於與內埋於封裝膠體內的接墊電性連接。本發明的導電盲孔結構,包括圖案化盲孔、導電材料層以及接墊圖案。圖案化盲孔由封裝膠體的上表面延伸至接墊。圖案化盲孔圍繞部分封裝膠體,以於封裝膠體中定義出凸出部。導電材料層至少覆蓋圖案化盲孔的內壁。接墊圖案配置於封裝膠體的上表面上,且位於凸出部。接墊圖案接觸導電材料層,且透過導電材料層電性連接至接墊。The conductive blind hole structure of the present invention is suitable for electrical connection with the pads embedded in the packaging glue. The conductive blind hole structure of the present invention includes a patterned blind hole, a conductive material layer and a pad pattern. The patterned blind hole extends from the upper surface of the packaging compound to the pad. The patterned blind hole surrounds a part of the packaging glue to define protrusions in the packaging glue. The conductive material layer at least covers the inner wall of the patterned blind hole. The pad pattern is configured on the upper surface of the packaging glue and located at the protruding part. The pad pattern contacts the conductive material layer and is electrically connected to the pad through the conductive material layer.
在本發明的一實施例中,上述的導電材料層未填滿該圖案化盲孔,以使圖案化盲孔與凸出部之間具有間隙。In an embodiment of the present invention, the aforementioned conductive material layer does not fill the patterned blind hole, so that there is a gap between the patterned blind hole and the protrusion.
在本發明的一實施例中,以俯視觀之,上述的圖案化盲孔的形狀為圓形,且與接墊圖案呈共圓心設置。In an embodiment of the present invention, when viewed from a top view, the shape of the patterned blind hole is circular, and is arranged co-circularly with the pad pattern.
在本發明的一實施例中,上述的接墊圖案具有中央部與連接中央部相對兩側的延伸部,以俯視觀之,中央部的形狀為圓形,而各延伸部為類矩形。In an embodiment of the present invention, the aforementioned pad pattern has a central portion and extension portions connecting opposite sides of the central portion. In a plan view, the shape of the central portion is a circle, and each extension portion is a rectangle-like.
在本發明的一實施例中,以俯視觀之,上述的圖案化盲孔的形狀為圓形,且與接墊圖案呈不共圓心設置。In an embodiment of the present invention, when viewed from a top view, the shape of the patterned blind hole is circular, and is arranged non-concentrically with the pad pattern.
在本發明的一實施例中,上述的導電材料層具有開口,且開口暴露出部分封裝膠體的上表面,以俯視觀之,圖案化盲孔的形狀為具有開口的非封閉幾何形狀,而接墊圖案的形狀為圓形或水滴形。In an embodiment of the present invention, the above-mentioned conductive material layer has an opening, and the opening exposes a part of the upper surface of the encapsulant. In a plan view, the shape of the patterned blind hole is a non-closed geometric shape with an opening. The shape of the pad pattern is a circle or a drop shape.
在本發明的一實施例中,上述的接墊圖案延伸至圖案化盲孔的一端。In an embodiment of the present invention, the aforementioned pad pattern extends to one end of the patterned blind hole.
在本發明的一實施例中,以俯視觀之,上述的圖案化盲孔的形狀與接墊圖案的形狀相同且皆為矩形,且圖案化盲孔與接墊圖案呈共中心設置。In an embodiment of the present invention, from a top view, the shape of the patterned blind hole is the same as the shape of the pad pattern and both are rectangular, and the patterned blind hole and the pad pattern are arranged concentrically.
在本發明的一實施例中,上述的導電材料層更延伸覆蓋至封裝膠體的上表面,且環繞圖案化盲孔的一端。In an embodiment of the present invention, the above-mentioned conductive material layer further extends to cover the upper surface of the packaging compound and surrounds one end of the patterned blind hole.
在本發明的一實施例中,上述的導電材料層填滿圖案化盲孔。In an embodiment of the present invention, the aforementioned conductive material layer fills the patterned blind holes.
在本發明的一實施例中,以俯視觀之,上述的圖案化盲孔的形狀為圓形,且與接墊圖案呈不共圓心設置。In an embodiment of the present invention, when viewed from a top view, the shape of the patterned blind hole is circular, and is arranged non-concentrically with the pad pattern.
在本發明的一實施例中,上述的接墊圖案具有中央部與連接中央部相對兩側的延伸部,以俯視觀之,中央部的形狀為圓形,而各延伸部為類矩形。In an embodiment of the present invention, the aforementioned pad pattern has a central portion and extension portions connecting opposite sides of the central portion. In a plan view, the shape of the central portion is a circle, and each extension portion is a rectangle-like.
在本發明的一實施例中,上述的導電材料層更延伸覆蓋至該封裝膠體的該上表面,且環繞該圖案化盲孔的一端。In an embodiment of the present invention, the above-mentioned conductive material layer further extends to cover the upper surface of the encapsulant and surrounds one end of the patterned blind hole.
在本發明的一實施例中,上述的導電材料層具有開口,且開口暴露出部分封裝膠體的上表面,以俯視觀之,圖案化盲孔的形狀為具有開口的非封閉幾何形狀,而接墊圖案的形狀為圓形或水滴形。In an embodiment of the present invention, the above-mentioned conductive material layer has an opening, and the opening exposes a part of the upper surface of the encapsulant. In a plan view, the shape of the patterned blind hole is a non-closed geometric shape with an opening. The shape of the pad pattern is a circle or a drop shape.
在本發明的一實施例中,上述的接墊圖案延伸至圖案化盲孔的一端。In an embodiment of the present invention, the aforementioned pad pattern extends to one end of the patterned blind hole.
在本發明的一實施例中,以俯視觀之,上述的圖案化盲孔的形狀與接墊圖案的形狀相同且皆為圓形或矩形,且圖案化盲孔與接墊圖案呈共中心設置。In an embodiment of the present invention, from a top view, the shape of the patterned blind hole is the same as the shape of the pad pattern and both are circular or rectangular, and the patterned blind hole and the pad pattern are arranged concentrically .
本發明的導電盲孔結構適於與內埋於封裝膠體內的接墊電性連接。本發明的導電盲孔結構,包括圖案化盲孔以及導電材料層。圖案化盲孔由封裝膠體的上表面延伸至接墊。導電材料層至少覆蓋圖案化盲孔的內壁且電性連接至接墊。導電材料層更延伸至封裝膠體的上表面上而定義出盲孔接墊。The conductive blind hole structure of the present invention is suitable for electrical connection with the pads embedded in the packaging glue. The conductive blind hole structure of the present invention includes a patterned blind hole and a conductive material layer. The patterned blind hole extends from the upper surface of the packaging compound to the pad. The conductive material layer at least covers the inner wall of the patterned blind hole and is electrically connected to the pad. The conductive material layer further extends to the upper surface of the packaging compound to define a blind via pad.
在本發明的一實施例中,以俯視觀之,上述的盲孔接墊的形狀為葫蘆形或水滴形。In an embodiment of the present invention, in a plan view, the shape of the above-mentioned blind hole pad is a gourd shape or a drop shape.
在本發明的一實施例中,以俯視觀之,上述的圖案化盲孔的形狀為圓形,且與盲孔接墊呈不共圓心設置。In an embodiment of the present invention, when viewed from a top view, the shape of the patterned blind hole is circular, and it is arranged non-concentrically with the blind hole pad.
本發明的封裝基板,包括封裝膠體、至少一接墊以及至少一導電盲孔結構。封裝膠體具有彼此相對的上表面與下表面。至少一接墊內埋於封裝膠體內。接墊的底面外露於封裝膠體的下表面。至少一導電盲孔結構,包括圖案化盲孔、導電材料層以及接墊圖案。圖案化盲孔由封裝膠體的上表面延伸至接墊。圖案化盲孔圍繞部分封裝膠體,以於封裝膠體中定義出凸出部。導電材料層至少覆蓋圖案化盲孔的內壁。接墊圖案配置於封裝膠體的上表面上,且位於凸出部。接墊圖案接觸導電材料層,且透過導電材料層電性連接至接墊。The packaging substrate of the present invention includes a packaging glue, at least one pad, and at least one conductive blind hole structure. The encapsulant has an upper surface and a lower surface opposite to each other. At least one pad is embedded in the encapsulating gel. The bottom surface of the pad is exposed on the bottom surface of the packaging glue. At least one conductive blind hole structure includes a patterned blind hole, a conductive material layer, and a pad pattern. The patterned blind hole extends from the upper surface of the packaging compound to the pad. The patterned blind hole surrounds a part of the packaging glue to define protrusions in the packaging glue. The conductive material layer at least covers the inner wall of the patterned blind hole. The pad pattern is configured on the upper surface of the packaging glue and located at the protruding part. The pad pattern contacts the conductive material layer and is electrically connected to the pad through the conductive material layer.
在本發明的一實施例中,上述的封裝基板更包括至少一導電通孔。至少一導電通孔貫穿該封裝膠體。導電通孔的兩端分別外露於封裝膠體的上表面與下表面。In an embodiment of the present invention, the aforementioned packaging substrate further includes at least one conductive via. At least one conductive through hole penetrates the packaging compound. The two ends of the conductive through hole are respectively exposed on the upper surface and the lower surface of the packaging glue.
在本發明的一實施例中,上述的封裝基板更包括至少一連接走線。至少一連接走線配置於封裝膠體的上表面上,且連接導電盲孔結構與導電通孔。In an embodiment of the present invention, the above-mentioned package substrate further includes at least one connecting wire. At least one connecting wire is disposed on the upper surface of the packaging compound and connects the conductive blind via structure and the conductive via.
在本發明的一實施例中,上述的封裝基板更包括至少一連接走線。至少一連接走線配置於封裝膠體的上表面上,至少一導電盲孔結構為多個導電盲孔結構,連接走線連接多個導電盲孔結構。In an embodiment of the present invention, the above-mentioned package substrate further includes at least one connecting wire. At least one connection trace is arranged on the upper surface of the packaging compound, at least one conductive blind hole structure is a plurality of conductive blind hole structures, and the connection trace connects the plurality of conductive blind hole structures.
本發明的晶片封裝結構,包括封裝基板以及晶片。封裝基板,包括封裝膠體、至少一接墊以及至少一導電盲孔結構。封裝膠體具有彼此相對的上表面與下表面。至少一接墊內埋於封裝膠體內。接墊的底面外露於封裝膠體的下表面。至少一導電盲孔結構,包括圖案化盲孔、導電材料層以及接墊圖案。圖案化盲孔由封裝膠體的上表面延伸至接墊。圖案化盲孔圍繞部分封裝膠體,以於封裝膠體中定義出凸出部。導電材料層至少覆蓋圖案化盲孔的內壁。接墊圖案配置於封裝膠體的上表面上,且位於凸出部。接墊圖案接觸導電材料層,且透過導電材料層電性連接至接墊。晶片配置於封裝基板上,且位於封裝膠體的上表面。導電盲孔結構位於晶片旁,且晶片藉由金屬銲線電性連接至導電盲孔結構;導電盲孔結構位於晶片下方,且晶片藉由覆晶封裝方式電性連接至導電盲孔結構。The chip package structure of the present invention includes a package substrate and a chip. The packaging substrate includes a packaging glue, at least one pad, and at least one conductive blind hole structure. The encapsulant has an upper surface and a lower surface opposite to each other. At least one pad is embedded in the encapsulating gel. The bottom surface of the pad is exposed on the bottom surface of the packaging glue. At least one conductive blind hole structure includes a patterned blind hole, a conductive material layer, and a pad pattern. The patterned blind hole extends from the upper surface of the packaging compound to the pad. The patterned blind hole surrounds a part of the packaging glue to define protrusions in the packaging glue. The conductive material layer at least covers the inner wall of the patterned blind hole. The pad pattern is configured on the upper surface of the packaging glue and located at the protruding part. The pad pattern contacts the conductive material layer and is electrically connected to the pad through the conductive material layer. The chip is configured on the packaging substrate and located on the upper surface of the packaging glue. The conductive blind via structure is located beside the chip, and the chip is electrically connected to the conductive blind via structure by metal bonding wires; the conductive blind via structure is located under the chip, and the chip is electrically connected to the conductive via via flip chip packaging.
基於上述,在本發明的導電盲孔結構的設計中,圖案化盲孔圍繞部分封裝膠體,以於封裝膠體內定義出凸出部。接墊圖案配置於封裝膠體的上表面且位於凸出部,且接墊圖案透過覆蓋圖案化盲孔的導電材材料層與封裝膠體內的接墊電性連接。如此一來,本發明的導電盲孔結構具有較大的熱傳導截面積,可有效地減少導通阻抗。此外,採用本發明的導電盲孔結構的封裝基板以及晶片封裝結構,則可有效地節省佈局空間,進而達到增加線路密度。Based on the above, in the design of the conductive blind hole structure of the present invention, the patterned blind hole surrounds a part of the encapsulation body to define a protrusion in the encapsulation body. The pad pattern is disposed on the upper surface of the packaging glue and located at the protruding part, and the pad pattern is electrically connected to the pads in the packaging glue through the conductive material layer covering the patterned blind holes. In this way, the conductive blind hole structure of the present invention has a larger heat conduction cross-sectional area, which can effectively reduce the on-resistance. In addition, adopting the packaging substrate and chip packaging structure of the conductive blind via structure of the present invention can effectively save layout space, thereby increasing the line density.
為讓本發明的上述特徵和優點能更明顯易懂,下文特舉實施例,並配合所附圖式作詳細說明如下。In order to make the above-mentioned features and advantages of the present invention more comprehensible, the following specific embodiments are described in detail in conjunction with the accompanying drawings.
圖1A繪示為本發明的一實施例的一種封裝基板以俯視觀之的立體示意圖。圖1B是圖1A沿剖線A-A’的剖面示意圖。圖1C是圖1B的區域R1的放大示意圖。圖1D繪示為本發明的另一實施例的一種封裝基板以俯視觀之的立體示意圖。圖1E是圖1D的區域R2的放大示意圖。FIG. 1A is a three-dimensional schematic diagram of a package substrate viewed from a top view according to an embodiment of the present invention. Fig. 1B is a schematic cross-sectional view taken along the section line A-A' of Fig. 1A. FIG. 1C is an enlarged schematic diagram of the region R1 in FIG. 1B. FIG. 1D is a three-dimensional schematic diagram of a package substrate viewed from a top view according to another embodiment of the present invention. FIG. 1E is an enlarged schematic diagram of the area R2 in FIG. 1D.
請同時參考圖1A、圖1B以及圖1C,本實施例的封裝基板110包括封裝膠體112、至少一接墊(圖1B中示意地繪示多個接墊114)以及至少一導電盲孔結構(圖1A、1B中示意地繪示多個接墊116)。封裝膠體112具有彼此相對的上表面112a與下表面112b。接墊114內埋於封裝膠體112內,其中接墊114的底面114b外露於封裝膠體112的下表面112b。導電盲孔結構116包括圖案化盲孔1161、導電材料層1162以及接墊圖案1163,其中導電盲孔結構116可環繞晶片座10設置。於一實施例中,晶片座10的底部可外露,可用於與系統接地,同時亦兼具有熱傳導通路。圖案化盲孔1161由封裝膠體112的上表面112a延伸至接墊114,其中圖案化盲孔1161圍繞部分封裝膠體112,以於封裝膠體112中定義出凸出部1121。進一步而言,凸出部1121是由封裝膠體112所構成。導電材料層1162至少覆蓋圖案化盲孔1161的內壁,其中導電材料層1162覆蓋圖案化盲孔1161的內壁與凸出部1121的周圍表面。接墊圖案1163配置於封裝膠體112的上表面112a上,且位於凸出部1121,其中接墊圖案1163接觸導電材料層1162,且透過導電材料層1162電性連接至接墊114。1A, 1B and 1C at the same time, the
詳細來說,由於本實施例的導電盲孔結構116的接墊圖案1163配置於封裝膠體112的上表面112a上,且位於凸出部1121,其中接墊圖案1163接觸導電材料層1162,且透過導電材料層1162電性連接至接墊114,因此,本實施例的導電盲孔結構116可以增加熱傳導截面積,以減少導通阻抗。此外,採用本實施例的導電盲孔結構116的封裝基板110,則可以省略習知技藝中的部分導電盲孔與接墊之間的走線,因此可有效地節省佈局空間,進而達到增加線路密度。In detail, since the
在本實施例中,如圖1B與圖1C所示,導電材料層1162未填滿圖案化盲孔1161,以使圖案化盲孔1161與凸出部1121之間具有間隙S。此處,間隙S例如是一空氣間隙,但並不以此為限。此處,導電材料層1162的材質例如是銅,而接墊圖案1163的材料例如是金,但並不以此為限。In this embodiment, as shown in FIGS. 1B and 1C, the
在製程上,本實施例的圖案化盲孔1161的形成方法可以是藉由雷射加工移除部分封裝膠體112,以於封裝膠體112中定義出凸出部1121。接著,於圖案化盲孔1161的內壁以共形的方式形成導電材料層1162,其中導電材料層1162覆蓋圖案化盲孔1161的內壁以及凸出部1121的周圍表面。此處,導電材料層1162沒有填滿圖案化盲孔1161,因而使得圖案化盲孔1161與凸出部1121之間具有間隙S。最後,於凸出部1121上方電鍍接墊圖案1163,而使接墊圖案1163透過導電材料層1162與封裝膠體112內的接墊114電性連接。In terms of the manufacturing process, the method for forming the patterned
在本實施例中,導電盲孔結構116可以包括導電盲孔結構116a、導電盲孔結構116b、導電盲孔結構116c、導電盲孔結構116d與導電盲孔結構116e。請參照圖1B,以俯視觀之,導電盲孔結構116a中圖案化盲孔1161的形狀為圓形,且圖案化盲孔1161與接墊圖案1163呈共圓心設置。進一步而言,以俯視觀之,導電盲孔結構116a可以呈現甜甜圈狀。也就是說,導電盲孔結構116a的圖案化盲孔1161只做表面鍍金屬(即導電材料層1162),不做習知的塞孔程序,而後續程序中,間隙S可讓銲線(未繪示)後的模封樹脂(如封裝膠體)填入,可增加黏著力,藉此提升結構可靠度。此外,以覆晶封裝時,可迫使覆晶凸塊(bump)(材質例如是錫或金屬)填入間隙S內,可形成限位以避免位移。In this embodiment, the conductive
此外,為了增加接墊圖案1163的固持功能,降低後續因高溫產生電極脫落的現象,導電盲孔結構116b的接墊圖案1163可以具有中央部C與連接中央部C相對兩側的二延伸部E,以俯視觀之,中央部C的形狀為圓形,而各延伸部E為類矩形。進一步而言,在導電盲孔結構116b經由雷射加工方式所形成時,延伸部E與圖案化盲孔1161的外徑銜接處會有圓弧導角,因此延伸部E可以不是矩形的直線形狀,延伸部E為類矩形形狀,如圖1D與圖1E中所示的導電盲孔結構116j。凸出部1121將圖案化盲孔1161區分為第一部分P1與第二部分P2。In addition, in order to increase the holding function of the
為了降低導電材料層1162脫層的機率,導電材料層1162可以更延伸覆蓋至封裝膠體112的上表面112a,且環繞圖案化盲孔1161的一端。在此,導電材料層1162於封裝膠體112的上表面112a且環繞圖案化盲孔1161的部分可以稱為盲孔接墊(via land)。In order to reduce the probability of delamination of the
請參照圖1C,在本實施例中,導電盲孔結構116c與導電盲孔結構116d包括圖案化盲孔1161以及導電材料層1162。圖案化盲孔1161由封裝膠體112的上表面112a延伸至接墊114。導電材料層1162至少覆蓋圖案化盲孔1161的內壁且電性連接至接墊114,其中導電材料層1162更延伸至封裝膠體112的上表面112a上而定義出多個盲孔接墊118。為了提升打線或覆晶程序的接合空間,導電盲孔結構116c可以包括盲孔接墊118a;導電盲孔結構116c可以包括盲孔接墊118b;而導電盲孔結構116e可以包括盲孔接墊118c。盲孔接墊118a以俯視觀之,圖案化盲孔1161的形狀為圓形,且與盲孔接墊118a呈不共圓心設置;盲孔接墊118b以俯視觀之,盲孔接墊118b的形狀為葫蘆形;而盲孔接墊118c以俯視觀之,盲孔接墊118c的形狀為水滴形。1C, in this embodiment, the conductive
簡言之,本實施例的接墊圖案1163是位於圖案化盲孔1161內,即位於同一個位置,其中接墊圖案1163除了可與封裝膠體112內的接墊114電性連接外,亦可作為與晶片(未繪示)電性連接的接墊。上述的設計,除了可以有效地節省空間增加線路密度外,亦可具有較簡化的設計。In short, the
值得一提的是,導電材料層1162未填滿圖案化盲孔1161的導電盲孔結構116還可以具有其他不同態樣。舉例而言,於其他實施例中,如圖1D與圖1E所示,導電盲孔結構116可以包括導電盲孔結構116f、導電盲孔結構116g、導電盲孔結構116h與導電盲孔結構116i。It is worth mentioning that the conductive
進一步而言,以俯視觀之,導電盲孔結構116f的圖案化盲孔1161的形狀為圓形,且與接墊圖案1163呈不共圓心設置,其中接墊圖案1163與圖案化盲孔1161的一端直接接觸。進一步而言,如圖1E所示,導電盲孔結構116f的圖案化盲孔1161基於實際設計尖端可以為圓弧狀,但本發明不限於此。導電盲孔結構116g具有開口O,且開口O暴露出封裝膠體112的上表面112a。以俯視觀之,圖案化盲孔1161的形狀為具有開口O的非封閉幾何形狀(例如是C字形),而接墊圖案1163的形狀為圓形。導電盲孔結構116h具有開口O,且開口O暴露出封裝膠體112的上表面112a。以俯視觀之,圖案化盲孔1161的形狀為具有開口的非封閉幾何形狀(例如是C字形),而接墊圖案1163的形狀為水滴形。導電盲孔結構116i的接墊圖案1163延伸至圖案化盲孔1161的一端。Further, in a top view, the shape of the patterned
在此必須說明的是,下述實施例沿用前述實施例的元件標號與部分內容,其中採用相同的標號來表示相同或近似的元件,並且省略了相同技術內容的說明。關於省略部分的說明可參考前述實施例,下述實施例不再重複贅述。It must be noted here that the following embodiments use the element numbers and part of the content of the foregoing embodiments, wherein the same numbers are used to represent the same or similar elements, and the description of the same technical content is omitted. For the description of the omitted parts, reference may be made to the foregoing embodiments, and the following embodiments will not be repeated.
圖2A繪示為本發明的另一實施例的一種封裝基板以俯視觀之的立體示意圖。圖2B是圖2A沿剖線B-B’的剖面示意圖。請同時參考圖2A與圖2B,本實施例的封裝基板210與部分圖1A的封裝基板110相似,兩者的差異在於:多個導電盲孔結構216中的導電材料層2162填滿圖案化盲孔1161。在圖2A、圖2B的實施例中,多個導電盲孔結構216可以包括導電盲孔結構216a、導電盲孔結構216b、導電盲孔結構216c以及導電盲孔結構216d。2A is a three-dimensional schematic diagram of a package substrate viewed from a top view according to another embodiment of the present invention. Fig. 2B is a schematic cross-sectional view taken along the section line B-B' of Fig. 2A. 2A and 2B at the same time, the
請先參照圖2A,以俯視觀之,導電盲孔結構216a的圖案化盲孔1161的形狀為圓形,且與接墊圖案1163呈不共圓心設置。進一步而言,導電盲孔結構216a的接墊圖案與圖案化盲孔1161的外徑直接接觸。另外,導電盲孔結構216b的接墊圖案1163具有中央部C與連接中央部C相對兩側的二延伸部E,以俯視觀之,中央部C的形狀為圓形,而各延伸部E為類矩形。然而,本發明不限於此,中央部C與延伸部E的形狀與組合可以視實際設計需求而定。例如中央部為具有開口的非封閉幾何形狀。Please refer to FIG. 2A first. From a top view, the patterned
接著,請參照圖2B,導電盲孔結構216c具有開口O,且開口O暴露出封裝膠體112的上表面112a。以俯視觀之,圖案化盲孔1161的形狀為C字形,而接墊圖案1163的形狀為圓形。進一步而言,圖案化盲孔1161僅環繞部分接墊圖案1163。此外,為了增加接墊圖案1163的固持功能,導電盲孔結構216d的接墊圖案1163可更延伸至圖案化盲孔1161的一端,且連接至圖案化盲孔1161的外徑。進一步而言,導電盲孔結構216d的接墊圖案1163僅延伸至圖案化盲孔1161的一端,且僅連接至圖案化盲孔1161的外徑的一端。更進一步而言,接墊圖案1163可以是圓形與矩形的組合,但本發明不限於此,可以視實際設計需求而定。Next, referring to FIG. 2B, the conductive blind via
為了降低導電材料層2162脫層的機率,導電材料層2162可以更延伸覆蓋至封裝膠體112的上表面112a,且環繞圖案化盲孔1161的一端。In order to reduce the probability of delamination of the
圖3A繪示為本發明的另一實施例的一種晶片封裝結構以俯視觀之的立體示意圖。請參考圖3A,本實施例的晶片封裝結構300包括晶片120與封裝基板310。晶片120配置於封裝基板310上,且位於封裝膠體112的上表面112a,其中導電盲孔結構216位於晶片120旁,且晶片120電性連接至導電盲孔結構216。此處,導電盲孔結構216環繞晶片120設置。FIG. 3A is a three-dimensional schematic diagram of a chip package structure viewed from a top view according to another embodiment of the present invention. Referring to FIG. 3A, the
在圖3A的實施例中,多個導電盲孔結構216可以更包括導電盲孔結構216e以及導電盲孔結構216f。以俯視觀之,導電盲孔結構216e的圖案化盲孔1161的形狀與接墊圖案1163的形狀相同皆為圓形,且導電盲孔結構216e的圖案化盲孔1161與接墊圖案1163呈共中心設置。導電盲孔結構216f的圖案化盲孔1161的形狀與接墊圖案1163的形狀相同且皆矩形,且導電盲孔結構216f的圖案化盲孔1161與接墊圖案1163呈共中心設置。In the embodiment of FIG. 3A, the plurality of conductive
在本實施例中,晶片封裝結構300可更包括至少一導電通孔130與至少一連接走線(示意地繪示一連接走線140a)。進一步而言,為了增加晶片120的散熱路徑且可以與系統接地,導電通孔130貫穿封裝膠體112,其中導電通孔130的兩端分別外露於封裝膠體112的上表面112a與下表面112b。導電通孔130至封裝膠體112的周圍表面112p具有第一水平距離L1,導電盲孔結構216至封裝膠體112的周圍表面112p具有第二水平距離L2,第二水平距離L2小於第一水平距離L1。此外,本實施例的連接走線140a配置於封裝膠體112的上表面112a上。連接走線140a可以用於連接導電盲孔結構216與導電通孔130。In this embodiment, the
請繼續參考圖3A,本實施例的晶片120例如是透過打線接合的方式與封裝基板310電性連接。進一步而言,本實施例的金屬銲線140b配置於封裝膠體112的上表面112a上,且金屬銲線140b可以用於電性連接導電盲孔結構216與晶片120。Please continue to refer to FIG. 3A. The
圖3B繪示為本發明的另一實施例的一種晶片封裝結構於一視角的立體示意圖。請參考圖3B,本實施例的晶片120也可以是透過覆晶接合的方式與封裝基板310a電性連接。進一步而言,本實施例的晶片封裝結構300a的封裝基板310a的導電盲孔結構116a與導電盲孔結構116d位於晶片120下方,且晶片120藉由覆晶封裝方式電性連接至導電盲孔結構116a與導電盲孔結構116d。更進一步而言,晶片120可以包括焊球122,晶片120可以藉由焊球122與導電盲孔結構116a以及導電盲孔結構116d電性連接。應說明的是,儘管圖3B中僅繪示晶片120與導電盲孔結構116a與導電盲孔結構116d接合,然而,本發明不限於此,晶片120可以與上述任一導電盲孔結構以覆晶接合方式進行電性連接。此外,上述晶片封裝結構可以是四方扁平無外接腳封裝(Quad Flat Non-leaded Package, QFN),但本發明不限於此。FIG. 3B is a three-dimensional schematic diagram of a chip package structure in a viewing angle according to another embodiment of the present invention. Referring to FIG. 3B, the
圖4A繪示為本發明的一實施例的一種封裝基板以俯視觀之的立體示意圖。圖4B是圖4A沿剖線C-C’的剖面示意圖。本實施例與圖3的實施例兩者的主要差異在於:本實施例不包括晶片120,且本實施例的封裝基板410的連接走線140除了連接走線140a之外,還更包括連接走線140c。連接走線140c可連接二個導電盲孔結構216。進一步而言,本實施例的封裝基板410中可以具有多種不同結構型態的導電盲孔結構216、連接走線140與導電通孔130相互電性連接的組合,使封裝基板410具有更多的彈性可以做後續的應用。應說明的是,本發明不限制圖4A中的連接關係,可視實際設計需求而定。4A is a three-dimensional schematic diagram of a package substrate viewed from a top view according to an embodiment of the present invention. Fig. 4B is a schematic cross-sectional view taken along the section line C-C' of Fig. 4A. The main difference between this embodiment and the embodiment of FIG. 3 is that this embodiment does not include the
圖5A繪示為本發明的一實施例的一種封裝基板以俯視觀之的立體示意圖。圖5B是圖5A沿剖線D-D’的剖面示意圖。本實施例與圖4A的實施例兩者的主要差異在於:多個導電盲孔結構216可以進一步形成於封裝基板510的中心,且封裝基板510具有下方不具有圖案化盲孔1161的接墊圖案2161。進一步而言,本實施例的封裝基板510的連接走線140可更包括連接走線140d。連接走線140d可以連接導電盲孔結構216與接墊圖案2161。此外,圖5A的封裝基板510繪示出不同於圖4A的封裝基板410的線路佈局方式。FIG. 5A is a three-dimensional schematic diagram of a package substrate viewed from a top view according to an embodiment of the present invention. Fig. 5B is a schematic cross-sectional view taken along the line D-D' of Fig. 5A. The main difference between this embodiment and the embodiment of FIG. 4A is that a plurality of conductive blind via
請參照圖5B,在圖5B中繪示出部分導電盲孔結構216的剖面示意圖,部分導電盲孔結構216包括導電盲孔結構216c、導電盲孔結構216d以及導電盲孔結構216e。由圖5B所示,導電盲孔結構216c與導電盲孔結構216d的凸出部1121可以延伸至旁邊的封裝膠體112,而導電盲孔結構216e的凸出部1121與封裝膠體112被導電材料層2162隔開。Referring to FIG. 5B, FIG. 5B shows a schematic cross-sectional view of a part of the conductive
圖6A至圖6C是本發明的多種實施例的導電盲孔結構的俯視示意圖。6A to 6C are schematic top views of conductive blind via structures according to various embodiments of the present invention.
於其他實施例中,導電材料層1162未填滿圖案化盲孔1161的導電盲孔結構116還可以具有多種態樣。舉例而言,如圖6A所示,導電盲孔結構116k,圖案化盲孔1161的形狀與接墊圖案1163的形狀相同且為矩形,且圖案化盲孔1161與接墊圖案1163呈共中心設置。如圖6B所示,以俯視觀之,導電盲孔結構116l的圖案化盲孔1161的形狀為圓形,且與接墊圖案1163呈不共圓心設置,其中接墊圖案1163與圖案化盲孔1161的一端不直接接觸。此外,導電材料層1162填滿圖案化盲孔1161的導電盲孔結構116還可以具有其他態樣。舉例而言,如圖6C所示,導電盲孔結構216i具有開口O,且開口O暴露出封裝膠體112的上表面112a。以俯視觀之,圖案化盲孔1161的形狀為C字形,而接墊圖案1163的形狀為水滴形。應說明的是,本發明不限制於上述各實施例中導電盲孔結構的佈局與設計方式,上述各種態樣的導電盲孔結構可以依照使用者的設計需求,自行彈性地設計於封裝基板或晶片封裝結構中。In other embodiments, the conductive
綜上所述,本發明的導電盲孔結構可以增加導電盲孔結構的熱傳導截面積減少導通阻抗,提升散熱效率。再者,應用本發明的導電盲孔結構的封裝基板以及晶片封裝結構,其可以提升封裝基板以及晶片封裝結構中可應用的空間並簡化封裝基板以及晶片封裝結構的設計。此外,本發明的導電材料層可以是未填滿圖案化盲孔,以使形成打線接合的銲線後才形成的封裝膠體可以填入以增加黏著性提升可靠度或在覆晶接合的迴焊後可使焊料填入形成限位,降低位移發生機率。In summary, the conductive blind hole structure of the present invention can increase the heat conduction cross-sectional area of the conductive blind hole structure, reduce the conduction resistance, and improve the heat dissipation efficiency. Furthermore, applying the package substrate and chip package structure of the conductive blind via structure of the present invention can increase the applicable space in the package substrate and the chip package structure and simplify the design of the package substrate and the chip package structure. In addition, the conductive material layer of the present invention may not be filled with the patterned blind holes, so that the packaging compound formed after the wire bonding is formed can be filled to increase the adhesion, improve the reliability, or reflow in flip chip bonding. Later, the solder can be filled in to form a limit, which reduces the probability of displacement.
雖然本發明已以實施例揭露如上,然其並非用以限定本發明,任何所屬技術領域中具有通常知識者,在不脫離本發明的精神和範圍內,當可作些許的更動與潤飾,故本發明的保護範圍當視後附的申請專利範圍所界定者為準。Although the present invention has been disclosed in the above embodiments, it is not intended to limit the present invention. Anyone with ordinary knowledge in the relevant technical field can make some changes and modifications without departing from the spirit and scope of the present invention. The scope of protection of the present invention shall be determined by the scope of the attached patent application.
10:晶片座
110、210、310、310a、410、510:封裝基板
112:封裝膠體
112a:上表面
112b:下表面
112p:周圍表面
1121:凸出部
114:接墊
114b:底面
116、116a、116b、116c、116d、116e、116f、116g、116h、116i、116j、116k、116l、216、216a、216b、216c、216d、216e、216f、216i:導電盲孔結構
1161:圖案化盲孔
1162、2162:導電材料層
1163、2161:接墊圖案
118、118a、118b、118c:盲孔接墊
120:晶片
122:焊球
130:導電通孔
140、140a、140c、140d:連接走線
140b:金屬銲線
300、300a:晶片封裝結構
C:中央部
E:延伸部
L1:第一水平距離
L2:第二水平距離
O:開口
P1:第一部分
P2:第二部分
R1、R2:區域
S:間隙10:
圖1A繪示為本發明的一實施例的一種封裝基板以俯視觀之的立體示意圖。 圖1B是圖1A沿剖線A-A’的剖面示意圖。 圖1C是圖1B的區域R1的放大示意圖。 圖1D繪示為本發明的另一實施例的一種封裝基板以俯視觀之的立體示意圖。 圖1E是圖1D的區域R2的放大示意圖。 圖2A繪示為本發明的另一實施例的一種封裝基板以俯視觀之的立體示意圖。 圖2B是圖2A沿剖線B-B’的剖面示意圖。 圖3A繪示為本發明的另一實施例的一種晶片封裝結構以俯視觀之的立體示意圖。 圖3B繪示為本發明的另一實施例的一種晶片封裝結構於一視角的立體示意圖。 圖4A繪示為本發明的一實施例的一種封裝基板以俯視觀之的立體示意圖。 圖4B是圖4A沿剖線C-C’的剖面示意圖。 圖5A繪示為本發明的一實施例的一種封裝基板以俯視觀之的立體示意圖。 圖5B是圖5A沿剖線D-D’的剖面示意圖。 圖6A至圖6C是本發明的多種實施例的導電盲孔結構的俯視示意圖。FIG. 1A is a three-dimensional schematic diagram of a package substrate viewed from a top view according to an embodiment of the present invention. Fig. 1B is a schematic cross-sectional view taken along the section line A-A' of Fig. 1A. FIG. 1C is an enlarged schematic diagram of the region R1 in FIG. 1B. FIG. 1D is a three-dimensional schematic diagram of a package substrate viewed from a top view according to another embodiment of the present invention. FIG. 1E is an enlarged schematic diagram of the area R2 in FIG. 1D. 2A is a three-dimensional schematic diagram of a package substrate viewed from a top view according to another embodiment of the present invention. Fig. 2B is a schematic cross-sectional view taken along the section line B-B' of Fig. 2A. FIG. 3A is a three-dimensional schematic diagram of a chip package structure viewed from a top view according to another embodiment of the present invention. FIG. 3B is a three-dimensional schematic diagram of a chip package structure in a viewing angle according to another embodiment of the present invention. 4A is a three-dimensional schematic diagram of a package substrate viewed from a top view according to an embodiment of the present invention. Fig. 4B is a schematic cross-sectional view taken along the section line C-C' of Fig. 4A. FIG. 5A is a three-dimensional schematic diagram of a package substrate viewed from a top view according to an embodiment of the present invention. Fig. 5B is a schematic cross-sectional view taken along the line D-D' of Fig. 5A. 6A to 6C are schematic top views of conductive blind via structures according to various embodiments of the present invention.
110:封裝基板110: Package substrate
112:封裝膠體112: Encapsulation colloid
112a:上表面112a: upper surface
112b:下表面112b: lower surface
1121:凸出部1121: protrusion
114:接墊114: pad
114b:底面114b: bottom surface
116、116a、116b:導電盲孔結構116, 116a, 116b: conductive blind hole structure
1161:圖案化盲孔1161: Patterned blind holes
1162:導電材料層1162: Conductive material layer
1163:接墊圖案1163: pad pattern
C:中央部C: Central part
E:延伸部E: Extension
P1:第一部分P1: Part One
P2:第二部分P2: Part Two
R1:區域R1: area
S:間隙S: gap
Claims (23)
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TW108131961A TW202111866A (en) | 2019-09-04 | 2019-09-04 | Conductive blind-hole structure, package substrate, and chip package structure |
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CN113594326A (en) * | 2021-07-29 | 2021-11-02 | 厦门三安光电有限公司 | Light emitting diode, light emitting module and display device |
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CN113594326A (en) * | 2021-07-29 | 2021-11-02 | 厦门三安光电有限公司 | Light emitting diode, light emitting module and display device |
CN113594326B (en) * | 2021-07-29 | 2022-12-20 | 厦门三安光电有限公司 | Light emitting diode, light emitting module and display device |
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