TW202105716A - Display device and manufacturing method thereof - Google Patents

Display device and manufacturing method thereof Download PDF

Info

Publication number
TW202105716A
TW202105716A TW109124581A TW109124581A TW202105716A TW 202105716 A TW202105716 A TW 202105716A TW 109124581 A TW109124581 A TW 109124581A TW 109124581 A TW109124581 A TW 109124581A TW 202105716 A TW202105716 A TW 202105716A
Authority
TW
Taiwan
Prior art keywords
layer
display device
isolation
isolation layer
pattern
Prior art date
Application number
TW109124581A
Other languages
Chinese (zh)
Other versions
TWI755792B (en
Inventor
吳勝郁
李明機
杜尚耘
陳清暉
Original Assignee
台灣積體電路製造股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 台灣積體電路製造股份有限公司 filed Critical 台灣積體電路製造股份有限公司
Publication of TW202105716A publication Critical patent/TW202105716A/en
Application granted granted Critical
Publication of TWI755792B publication Critical patent/TWI755792B/en

Links

Images

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/1201—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/122—Pixel-defining structures or layers, e.g. banks
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/80—Constructional details
    • H10K59/87—Passivation; Containers; Encapsulations
    • H10K59/873—Encapsulations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K71/00—Manufacture or treatment specially adapted for the organic devices covered by this subclass
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K71/00—Manufacture or treatment specially adapted for the organic devices covered by this subclass
    • H10K71/10—Deposition of organic active material
    • H10K71/16—Deposition of organic active material using physical vapour deposition [PVD], e.g. vacuum deposition or sputtering
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K77/00—Constructional details of devices covered by this subclass and not covered by groups H10K10/80, H10K30/80, H10K50/80 or H10K59/80
    • H10K77/10—Substrates, e.g. flexible substrates
    • H10K77/111—Flexible substrates
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
    • Y02E10/00—Energy generation through renewable energy sources
    • Y02E10/50—Photovoltaic [PV] energy
    • Y02E10/549—Organic PV cells
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
    • Y02P70/50—Manufacturing or production processes characterised by the final manufactured product

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
  • Geometry (AREA)
  • Electroluminescent Light Sources (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)

Abstract

A display device includes a semiconductor substrate, an isolation layer, a light-emitting layer and a second electrode. The semiconductor substrate has a pixel region and a peripheral region located around the pixel region. The semiconductor substrate includes first electrodes and a driving element layer. The first electrodes are disposed in the pixel region and the first electrodes are electrically connected to the driving element layer. The isolation layer is disposed on the semiconductor substrate. The isolation layer includes a first isolation pattern disposed in the peripheral region, and the first isolation pattern has a first side surface and a second side surface opposite to the first side surface. The light-emitting layer is disposed on the isolation layer and the first electrodes, and covers the first side surface and the second side surface of the first isolation pattern. The second electrode is disposed on the light-emitting layer.

Description

顯示器件及其製造方法Display device and manufacturing method thereof

近年來，隨著半導體技術快速發展，近眼顯示器（near-eye display）受到歡迎。由於當前製作技術中的限制，難以減小顯示器件的發光元件之間的間距。用於晶圓級近眼顯示器中的顯示器件的製作技術的開發正在進行，以滿足對於尺寸減小及高解析度（resolution）的需求。In recent years, with the rapid development of semiconductor technology, near-eye displays have become popular. Due to limitations in the current manufacturing technology, it is difficult to reduce the spacing between the light-emitting elements of the display device. The development of manufacturing technology for display devices in wafer-level near-eye displays is underway to meet the demands for size reduction and high resolution.

以下公開提供用於實施所提供主題的不同特徵的許多不同實施例或實例。以下闡述組件、值、操作、材料、布置等的具體實例以簡化本公開。當然，這些僅為實例且不旨在進行限制。預期存在其他組件、值、操作、材料、布置等。舉例來說，以下說明中將第一特徵形成在第二特徵之上或第二特徵上可包括其中第一特徵與第二特徵被形成為直接接觸的實施例，且也可包括其中第一特徵與第二特徵之間可形成有附加特徵從而使得所述第一特徵與所述第二特徵可不直接接觸的實施例。另外，本公開內容可能在各種實例中重複使用參考編號和/或字母。這種重複使用是出於簡潔及清晰的目的，而不是自身指示所論述的各種實施例和/或配置之間的關係。The following disclosure provides many different embodiments or examples for implementing different features of the provided subject matter. Specific examples of components, values, operations, materials, arrangements, etc. are set forth below to simplify the present disclosure. Of course, these are only examples and are not intended to be limiting. Other components, values, operations, materials, arrangements, etc. are expected to exist. For example, the formation of the first feature on the second feature or the second feature in the following description may include an embodiment in which the first feature and the second feature are formed in direct contact, and may also include the first feature An embodiment in which an additional feature may be formed between the first feature and the second feature so that the first feature and the second feature may not directly contact. In addition, the present disclosure may reuse reference numbers and/or letters in various examples. This repeated use is for the purpose of brevity and clarity, rather than indicating the relationship between the various embodiments and/or configurations discussed by itself.

此外，為易於說明，本文中可能使用例如「在…之下」、「在…下方」、「下部的」、「在…上方」、「上部的」等空間相對性用語來闡述圖中所示的一個元件或特徵與另一（其他）元件或特徵的關係。所述空間相對性用語旨在除圖中所繪示的取向外更囊括器件在使用或操作中的不同取向。裝置可具有其他取向（旋轉90度或處於其他取向），且本文中所使用的空間相對性描述語可同樣相應地進行解釋。In addition, for ease of explanation, this article may use spatially relative terms such as "below", "below", "lower", "above", "upper" and other spatially relative terms to describe what is shown in the figure. The relationship of one element or feature to another (other) element or feature. The terms of spatial relativity are intended to cover different orientations of the device in use or operation in addition to the orientations depicted in the figures. The device can have other orientations (rotated by 90 degrees or in other orientations), and the spatial relativity descriptors used herein can also be interpreted accordingly.

另外，為易於說明，本文中可能使用例如「第一」、「第二」、「第三」、「第四」等用語來闡述圖中所示的相似的元件或特徵或者不同的元件或特徵，且可根據說明的存在次序或上下文互換地使用In addition, for ease of description, terms such as "first", "second", "third", and "fourth" may be used herein to describe similar elements or features or different elements or features shown in the figures. , And can be used interchangeably according to the order of existence or context of the description

圖1是根據本公開一些實施例的顯示器件10的示意性剖視圖。圖2是根據本公開一些實施例的顯示器件10的簡化俯視圖。具體來說，圖1是沿圖2所示線I-I’截取的剖視圖。為使例示簡潔及清晰，在圖2所示簡化俯視圖中僅示出顯示器件10的幾個元件，例如半導體基底、隔離層、第一電極及第二電極，且這些元件未必在同一平面中。FIG. 1 is a schematic cross-sectional view of a display device 10 according to some embodiments of the present disclosure. FIG. 2 is a simplified top view of the display device 10 according to some embodiments of the present disclosure. Specifically, Fig. 1 is a cross-sectional view taken along the line I-I' shown in Fig. 2. To make the illustration concise and clear, the simplified top view shown in FIG. 2 only shows a few elements of the display device 10, such as the semiconductor substrate, the isolation layer, the first electrode, and the second electrode, and these elements are not necessarily in the same plane.

參照圖1及圖2，顯示器件10包括半導體基底100、隔離層110、發光層120及第二電極130。在一些實施例中，顯示器件10更可包括介電包封體140。在一些實施例中，顯示器件10是自發光式顯示器件（self-luminescent display device）。在某些實施例中，顯示器件10是有機發光二極管（organic light-emitting diode，OLED）顯示器件。在一些替代實施例中，顯示器件10更包括其他所需元件，例如覆蓋板、玻璃和/或透明遮蔽罩（shielding）。也就是說，本公開的顯示器件10並不僅限於圖1中所繪示的顯示器件10。在一些實施例中，覆蓋板與半導體基底100彼此相對地設置。在一些實施例中，覆蓋板可為柔性基底，例如聚合物基底或塑料基底。然而，本公開並不僅限於此。在一些替代實施例中，覆蓋板是剛性基底，例如玻璃基底、石英基底或矽基底。1 and 2, the display device 10 includes a semiconductor substrate 100, an isolation layer 110, a light emitting layer 120, and a second electrode 130. In some embodiments, the display device 10 may further include a dielectric encapsulation body 140. In some embodiments, the display device 10 is a self-luminescent display device. In some embodiments, the display device 10 is an organic light-emitting diode (OLED) display device. In some alternative embodiments, the display device 10 further includes other required elements, such as a cover plate, glass, and/or a transparent shielding. In other words, the display device 10 of the present disclosure is not limited to the display device 10 shown in FIG. 1. In some embodiments, the cover plate and the semiconductor substrate 100 are disposed opposite to each other. In some embodiments, the cover plate may be a flexible substrate, such as a polymer substrate or a plastic substrate. However, the present disclosure is not limited to this. In some alternative embodiments, the cover plate is a rigid substrate, such as a glass substrate, a quartz substrate, or a silicon substrate.

在一些實施例中，半導體基底100具有像素區A及位於像素區A周圍的外圍區B。如圖2中所示，在俯視圖中，外圍區B具有環形形狀。在一些實施例中，半導體基底100包括基底102、驅動元件層104、內連線結構106、多個第一電極108a及共用電極108b。在一些實施例中，基底102由以下材料製成：元素半導體材料，例如結晶矽、金剛石或鍺；化合物半導體材料，例如碳化矽、砷化鎵、砷化銦或磷化銦；或者合金半導體材料，例如矽鍺、碳化矽鍺、磷化鎵砷或磷化鎵銦。在一些實施例中，基底102是塊狀半導體材料。舉例來說，基底102可為塊狀矽基底，例如由單晶矽形成的塊狀基底、經摻雜的矽基底、未經摻雜的矽基底或絕緣體上矽（silicon-on-insulator，SOI）基底，其中經摻雜的矽基底的摻雜劑可為N型摻雜劑、P型摻雜劑或其組合。In some embodiments, the semiconductor substrate 100 has a pixel area A and a peripheral area B located around the pixel area A. As shown in FIG. 2, in a plan view, the peripheral area B has a ring shape. In some embodiments, the semiconductor substrate 100 includes a substrate 102, a driving element layer 104, an interconnect structure 106, a plurality of first electrodes 108a and a common electrode 108b. In some embodiments, the substrate 102 is made of the following materials: elemental semiconductor materials, such as crystalline silicon, diamond, or germanium; compound semiconductor materials, such as silicon carbide, gallium arsenide, indium arsenide, or indium phosphide; or alloy semiconductor materials , Such as silicon germanium, silicon germanium carbide, gallium arsenide or gallium indium phosphide. In some embodiments, the substrate 102 is a bulk semiconductor material. For example, the substrate 102 may be a bulk silicon substrate, such as a bulk substrate formed of single crystal silicon, a doped silicon substrate, an undoped silicon substrate, or a silicon-on-insulator (SOI). ) The substrate, wherein the dopant of the doped silicon substrate can be an N-type dopant, a P-type dopant, or a combination thereof.

在一些實施例中，驅動元件層104設置在基底102上。在一些實施例中，驅動元件層104包括形成在驅動元件層104中的主動組件（例如，晶體管等）和/或被動組件（例如，電阻器、電容器、電感器等）。在一些實施例中，驅動元件層104是互補金屬氧化物半導體（complementary metal-oxide-semiconductor，CMOS）電路層。In some embodiments, the driving element layer 104 is disposed on the substrate 102. In some embodiments, the driving element layer 104 includes active components (for example, transistors, etc.) and/or passive components (for example, resistors, capacitors, inductors, etc.) formed in the driving element layer 104. In some embodiments, the driving element layer 104 is a complementary metal-oxide-semiconductor (CMOS) circuit layer.

在一些實施例中，內連線結構106用於連接到驅動元件層104中的主動組件（未示出）和/或被動組件（未示出）。在一些實施例中，內連線結構106包括絕緣層（未示出）及設置在絕緣層中的多個金屬特徵（未示出）。在一些實施例中，絕緣層包括位於驅動元件層104上的層間介電（inter-layer dielectric，ILD）層以及位於層間介電層之上的至少一個金屬間介電（inter-metal dielectric，IMD）層。在一些實施例中，絕緣層的材料包括氧化矽、氮氧化矽、氮化矽、低介電常數（低k）材料或其組合。絕緣層可為單層或多層式結構。在一些實施例中，金屬特徵包括金屬線及通孔（未示出）。在一些實施例中，金屬特徵的材料包括鎢（W）、銅（Cu）、銅合金、鋁（Al）、鋁合金或其組合。在一些實施例中，內連線結構106通過雙鑲嵌製程（dual damascene process）形成。在替代實施例中，內連線結構106通過多個單鑲嵌製程（single damascene process）形成。在又一些替代實施例中，內連線結構106通過電鍍製程形成。In some embodiments, the interconnect structure 106 is used to connect to active components (not shown) and/or passive components (not shown) in the driving element layer 104. In some embodiments, the interconnect structure 106 includes an insulating layer (not shown) and a plurality of metal features (not shown) disposed in the insulating layer. In some embodiments, the insulating layer includes an inter-layer dielectric (ILD) layer located on the driving element layer 104 and at least one inter-metal dielectric (IMD) layer located on the inter-layer dielectric layer. )Floor. In some embodiments, the material of the insulating layer includes silicon oxide, silicon oxynitride, silicon nitride, low dielectric constant (low-k) material, or a combination thereof. The insulating layer can be a single-layer or multi-layer structure. In some embodiments, the metal features include metal lines and vias (not shown). In some embodiments, the material of the metallic feature includes tungsten (W), copper (Cu), copper alloy, aluminum (Al), aluminum alloy, or a combination thereof. In some embodiments, the interconnect structure 106 is formed by a dual damascene process. In an alternative embodiment, the interconnect structure 106 is formed by multiple single damascene processes. In still other alternative embodiments, the interconnect structure 106 is formed by an electroplating process.

在一些實施例中，多個第一電極108a設置在像素區A中。在一些實施例中，多個第一電極108a中的一些第一電極108a設置在像素區A中且進一步延伸到外圍區B中，如圖1中所示。然而，本公開並不僅限於此。在一些替代實施例中，沒有第一電極108a設置在外圍區B中。在一些實施例中，第一電極108a通過內連線結構106電連接到驅動元件層104中的主動組件（未示出）和/或被動組件（未示出）。也就是說，驅動訊號可通過驅動元件層104中的主動組件（未示出）及內連線結構106傳送到第一電極108a。在一些實施例中，第一電極108a的材料包括透明導電材料。在某些實施例中，透明導電材料可包括金屬氧化物導電材料，例如氧化銦錫、氧化銦鋅、氧化鋁錫、氧化鋁鋅、氧化銦鎵鋅、其他合適的氧化物或者上述材料中的至少兩者形成的堆疊層。然而，本公開並不僅限於此。在一些替代實施例中，第一電極108a的材料包括不透明導電材料。在某些實施例中，不透明導電材料包括金屬。在一些實施例中，第一電極108a設置在內連線結構106的例示頂表面之上，如圖1中所示。然而，本公開並不僅限於此。在一些替代實施例中，第一電極108a嵌置在內連線結構106中。在一些實施例中，第一電極108a通過微影製程（photolithography process）及蝕刻製程形成。例如，形成第一電極108a的方法可包括：通過合適的製作技術（例如化學氣相沉積（chemical vapor deposition，CVD）、物理氣相沉積（physical vapor deposition，PVD）或蒸鍍）將導電材料層完全地形成在內連線結構106上；且接著執行微影製程及蝕刻製程以將導電材料層圖案化。在顯示器件10中，第一電極108a的數目可少於或多於圖2中所繪示的數目，且可基於需求和/或設計佈局來指定；本公開並不特別局限於此。In some embodiments, a plurality of first electrodes 108a are provided in the pixel area A. In some embodiments, some of the plurality of first electrodes 108a are disposed in the pixel area A and further extend into the peripheral area B, as shown in FIG. 1. However, the present disclosure is not limited to this. In some alternative embodiments, no first electrode 108a is provided in the peripheral region B. In some embodiments, the first electrode 108 a is electrically connected to an active component (not shown) and/or a passive component (not shown) in the driving element layer 104 through the interconnect structure 106. That is, the driving signal can be transmitted to the first electrode 108a through the active components (not shown) in the driving element layer 104 and the interconnection structure 106. In some embodiments, the material of the first electrode 108a includes a transparent conductive material. In some embodiments, the transparent conductive material may include metal oxide conductive materials, such as indium tin oxide, indium zinc oxide, aluminum oxide tin, aluminum oxide zinc, indium gallium zinc oxide, other suitable oxides, or any of the foregoing materials At least two stacked layers. However, the present disclosure is not limited to this. In some alternative embodiments, the material of the first electrode 108a includes an opaque conductive material. In some embodiments, the opaque conductive material includes metal. In some embodiments, the first electrode 108a is disposed on the exemplified top surface of the interconnect structure 106, as shown in FIG. 1. However, the present disclosure is not limited to this. In some alternative embodiments, the first electrode 108 a is embedded in the interconnect structure 106. In some embodiments, the first electrode 108a is formed by a photolithography process and an etching process. For example, a method of forming the first electrode 108a may include: applying a conductive material layer through a suitable manufacturing technique (such as chemical vapor deposition (CVD), physical vapor deposition (PVD), or evaporation) It is completely formed on the interconnect structure 106; and then a lithography process and an etching process are performed to pattern the conductive material layer. In the display device 10, the number of the first electrodes 108a may be less than or more than that shown in FIG. 2, and may be specified based on requirements and/or design layout; the present disclosure is not particularly limited thereto.

在一些實施例中，共用電極108b設置在外圍區B中。在一些實施例中，共用電極108b電性接地（例如，0 V）。在一些實施例中，共用電極108b的材料包括透明導電材料。在某些實施例中，透明導電材料包括金屬氧化物導電材料，例如氧化銦錫、氧化銦鋅、氧化鋁錫、氧化鋁鋅、氧化銦鎵鋅、其他合適的氧化物或者上述材料中的至少兩者形成的堆疊層。然而，本公開並不僅限於此。在一些替代實施例中，共用電極108b的材料包括不透明導電材料。在某些實施例中，不透明導電材料包括金屬。在某些實施例中，共用電極108b的材料與第一電極108a的材料相同。在某些實施例中，共用電極108b的材料不同於第一電極108a的材料。在一些實施例中，共用電極108b設置在內連線結構106的例示頂表面之上，如圖1中所示。然而，本公開並不僅限於此。在一些替代實施例中，共用電極108b嵌置在內連線結構106中。在一些實施例中，共用電極108b通過微影製程及蝕刻製程形成。形成共用電極108b的方法可包括：通過合適的製作技術（例如化學氣相沉積（CVD）、物理氣相沉積（PVD）或蒸鍍）將導電材料層完全地形成在內連線結構106上；接著執行微影製程及蝕刻製程以將導電材料層圖案化。在一些實施例中，共用電極108b與第一電極108a在同一製程中形成。也就是說，共用電極108b與第一電極108a均源自相同的導電材料層。然而，本公開並不僅限於此。在一些替代實施例中，共用電極108b與第一電極108a在獨自的製程中形成。如圖2中所示，在外圍區B中設置一個共用電極108b，但本公開並不僅限於此。共用電極108b的數目可多於圖2中所繪示的數目，且可基於需求和/或設計佈局來指定。In some embodiments, the common electrode 108b is disposed in the peripheral area B. In some embodiments, the common electrode 108b is electrically grounded (for example, 0 V). In some embodiments, the material of the common electrode 108b includes a transparent conductive material. In some embodiments, the transparent conductive material includes a metal oxide conductive material, such as indium tin oxide, indium zinc oxide, aluminum tin oxide, aluminum oxide zinc, indium gallium zinc oxide, other suitable oxides, or at least one of the foregoing materials The stacked layer formed by the two. However, the present disclosure is not limited to this. In some alternative embodiments, the material of the common electrode 108b includes an opaque conductive material. In some embodiments, the opaque conductive material includes metal. In some embodiments, the material of the common electrode 108b is the same as the material of the first electrode 108a. In some embodiments, the material of the common electrode 108b is different from the material of the first electrode 108a. In some embodiments, the common electrode 108b is disposed on the exemplified top surface of the interconnect structure 106, as shown in FIG. 1. However, the present disclosure is not limited to this. In some alternative embodiments, the common electrode 108b is embedded in the interconnect structure 106. In some embodiments, the common electrode 108b is formed by a photolithography process and an etching process. The method of forming the common electrode 108b may include: completely forming the conductive material layer on the interconnect structure 106 by a suitable manufacturing technique (such as chemical vapor deposition (CVD), physical vapor deposition (PVD) or evaporation); Then, a lithography process and an etching process are performed to pattern the conductive material layer. In some embodiments, the common electrode 108b and the first electrode 108a are formed in the same process. That is, the common electrode 108b and the first electrode 108a are both derived from the same conductive material layer. However, the present disclosure is not limited to this. In some alternative embodiments, the common electrode 108b and the first electrode 108a are formed in a separate process. As shown in FIG. 2, a common electrode 108b is provided in the peripheral area B, but the present disclosure is not limited to this. The number of common electrodes 108b can be more than that shown in FIG. 2, and can be specified based on requirements and/or design layout.

在一些實施例中，隔離層110設置在半導體基底100上。在一些實施例中，隔離層110的材料包括氧化矽、氮氧化矽、氮化矽或其組合。在某些實施例中，隔離層110是氧化物-氮化物-氧化物（oxide-nitride-oxide，ONO）層。在一些實施例中，隔離層110通過微影製程及蝕刻製程形成。In some embodiments, the isolation layer 110 is disposed on the semiconductor substrate 100. In some embodiments, the material of the isolation layer 110 includes silicon oxide, silicon oxynitride, silicon nitride, or a combination thereof. In some embodiments, the isolation layer 110 is an oxide-nitride-oxide (ONO) layer. In some embodiments, the isolation layer 110 is formed by a lithography process and an etching process.

在一些實施例中，隔離層110包括第一隔離圖案112及第二隔離圖案114，且第一隔離圖案112位於第二隔離圖案114周圍。在一些實施例中，第一隔離圖案112設置在外圍區B中。如圖2中所示，在俯視圖中，第一隔離圖案112具有環形形狀。在一些實施例中，第一隔離圖案112具有第一側表面S1及與第一側表面S1相對的第二側表面S2。第一隔離圖案112的第二側表面S2面朝第二隔離圖案114，如圖2中所示。第二側表面S2比第一側表面S1更靠近像素區A，如圖1中所示。在一些實施例中，如圖1中所示，第一側表面S1的橫截面輪廓與第二側表面S2的橫截面輪廓實質上彼此對稱。第一側表面S1的橫截面輪廓與第二側表面S2的橫截面輪廓可為彼此的鏡像。利用此種配置，第一側表面S1的橫截面輪廓與第二側表面S2的橫截面輪廓可被認為實質上相同。In some embodiments, the isolation layer 110 includes a first isolation pattern 112 and a second isolation pattern 114, and the first isolation pattern 112 is located around the second isolation pattern 114. In some embodiments, the first isolation pattern 112 is disposed in the peripheral region B. As shown in FIG. 2, in a top view, the first isolation pattern 112 has a ring shape. In some embodiments, the first isolation pattern 112 has a first side surface S1 and a second side surface S2 opposite to the first side surface S1. The second side surface S2 of the first isolation pattern 112 faces the second isolation pattern 114, as shown in FIG. 2. The second side surface S2 is closer to the pixel area A than the first side surface S1, as shown in FIG. 1. In some embodiments, as shown in FIG. 1, the cross-sectional profile of the first side surface S1 and the cross-sectional profile of the second side surface S2 are substantially symmetrical to each other. The cross-sectional profile of the first side surface S1 and the cross-sectional profile of the second side surface S2 may be mirror images of each other. With this configuration, the cross-sectional profile of the first side surface S1 and the cross-sectional profile of the second side surface S2 can be considered to be substantially the same.

在一些實施例中，第二隔離圖案114設置在像素區A中。在一些實施例中，第二隔離圖案114具有多個第一圖案部分114a及多個第二圖案部分114b。在一些實施例中，如圖2中所示，多個第一圖案部分114a沿與半導體基底100的厚度方向Z垂直的方向X排列，且多個第二圖案部分114b沿與厚度方向Z垂直的方向Y排列，其中方向X垂直於方向Y。在一些實施例中，每一第一圖案部分114a沿方向Y延伸，且每一第二圖案部分114b沿方向X延伸，如圖2中所示。如圖2中所示，多個第一圖案部分114a連接到多個第二圖案部分114b以構成網格結構（mesh structure）。In some embodiments, the second isolation pattern 114 is disposed in the pixel area A. In some embodiments, the second isolation pattern 114 has a plurality of first pattern portions 114a and a plurality of second pattern portions 114b. In some embodiments, as shown in FIG. 2, the plurality of first pattern portions 114a are arranged along a direction X perpendicular to the thickness direction Z of the semiconductor substrate 100, and the plurality of second pattern portions 114b are arranged along a direction perpendicular to the thickness direction Z. The direction Y is arranged, where the direction X is perpendicular to the direction Y. In some embodiments, each first pattern portion 114a extends along the direction Y, and each second pattern portion 114b extends along the direction X, as shown in FIG. 2. As shown in FIG. 2, the plurality of first pattern parts 114a are connected to the plurality of second pattern parts 114b to form a mesh structure.

在一些實施例中，每一第一圖案部分114a具有第三側表面S3及與第三側表面S3相對的第四側表面S4，且每一第二圖案部分114b具有第五側表面S5及與第五側表面S5相對的第六側表面S6。在一些實施例中，如圖1中所示，第三側表面S3的橫截面輪廓與第四側表面S4的橫截面輪廓實質上彼此對稱。第三側表面S3的橫截面輪廓與第四側表面S4的橫截面輪廓可為彼此的鏡像。利用此種配置，第三側表面S3的橫截面輪廓與第四側表面S4的橫截面輪廓可被認為實質上相同。相似地，如圖1中所示，第五側表面S5的橫截面輪廓與第六側表面S6的橫截面輪廓實質上彼此對稱，因此第五側表面S5的橫截面輪廓與第六側表面S6的橫截面輪廓可被認為實質上相同。此外，在一些實施例中，如圖1中所示，第三側表面S3的橫截面輪廓與第五側表面S5的橫截面輪廓實質上相同。也就是說，在第二隔離圖案114中，第一圖案部分114a與第二圖案部分114b具有實質上一致的側表面的橫截面輪廓。在一些實施例中，如圖1中所示，第一側表面S1的橫截面輪廓與第三側表面S3的橫截面輪廓實質上相同。也就是說，在隔離層110中，第一隔離圖案112與第二隔離圖案114具有實質上一致的側表面的橫截面輪廓。在某些實施例中，第一隔離圖案112的側表面的橫截面輪廓與第二隔離圖案114的側表面的橫截面輪廓之間的輪廓尺寸差小於約10%。In some embodiments, each first pattern portion 114a has a third side surface S3 and a fourth side surface S4 opposite to the third side surface S3, and each second pattern portion 114b has a fifth side surface S5 and The fifth side surface S5 is opposite to the sixth side surface S6. In some embodiments, as shown in FIG. 1, the cross-sectional profile of the third side surface S3 and the cross-sectional profile of the fourth side surface S4 are substantially symmetrical to each other. The cross-sectional profile of the third side surface S3 and the cross-sectional profile of the fourth side surface S4 may be mirror images of each other. With this configuration, the cross-sectional profile of the third side surface S3 and the cross-sectional profile of the fourth side surface S4 may be considered to be substantially the same. Similarly, as shown in FIG. 1, the cross-sectional profile of the fifth side surface S5 and the cross-sectional profile of the sixth side surface S6 are substantially symmetrical to each other, so the cross-sectional profile of the fifth side surface S5 is the same as that of the sixth side surface S6. The cross-sectional profile of can be considered to be substantially the same. In addition, in some embodiments, as shown in FIG. 1, the cross-sectional profile of the third side surface S3 is substantially the same as the cross-sectional profile of the fifth side surface S5. That is, in the second isolation pattern 114, the first pattern portion 114a and the second pattern portion 114b have substantially the same cross-sectional profile of the side surface. In some embodiments, as shown in FIG. 1, the cross-sectional profile of the first side surface S1 and the cross-sectional profile of the third side surface S3 are substantially the same. That is, in the isolation layer 110, the first isolation pattern 112 and the second isolation pattern 114 have substantially the same cross-sectional profile of the side surface. In some embodiments, the outline dimension difference between the cross-sectional profile of the side surface of the first isolation pattern 112 and the cross-sectional profile of the side surface of the second isolation pattern 114 is less than about 10%.

在一些實施例中，隔離層110具有位於外圍區B中的第一開口O1以及位於像素區A中的多個第二開口O2。在一些實施例中，多個第二開口O2中的一些第二開口O2設置在像素區A中且進一步延伸到外圍區B中，如圖1中所示。然而，本公開並不僅限於此。在一些替代實施例中，沒有第二開口O2設置在外圍區B中。In some embodiments, the isolation layer 110 has a first opening O1 in the peripheral region B and a plurality of second openings O2 in the pixel region A. In some embodiments, some of the plurality of second openings O2 are provided in the pixel area A and further extend into the peripheral area B, as shown in FIG. 1. However, the present disclosure is not limited to this. In some alternative embodiments, no second opening 02 is provided in the peripheral area B.

具體來說，一同參照圖1與圖2，第一開口O1是具有由隔離層110界定的單個側壁的未封閉式開口。第一隔離圖案112的第一側表面S1可被視為第一開口O1的側壁。在一些實施例中，如圖1中所示，共用電極108b沿半導體基底100的厚度方向Z在基底102上的垂直投影落在第一開口O1沿半導體基底100的厚度方向Z在基底102上的垂直投影的跨度內。也就是說，在製造顯示器件10的過程期間，在一些階段中，共用電極108b可被第一開口O1暴露出。Specifically, referring to FIGS. 1 and 2 together, the first opening O1 is an unclosed opening having a single sidewall defined by the isolation layer 110. The first side surface S1 of the first isolation pattern 112 may be regarded as a sidewall of the first opening O1. In some embodiments, as shown in FIG. 1, the vertical projection of the common electrode 108b on the substrate 102 along the thickness direction Z of the semiconductor substrate 100 falls on the first opening O1 along the thickness direction Z of the semiconductor substrate 100 on the substrate 102. Within the span of the vertical projection. That is, during the process of manufacturing the display device 10, in some stages, the common electrode 108b may be exposed by the first opening O1.

另外，一同參照圖1與圖2，每一第二開口O2是封閉式開口，所述封閉式開口沿厚度方向Z在基底102上的垂直投影呈矩形形狀。換句話說，每一第二開口O2具有四個側壁。然而，本公開並不僅限於此。在一些替代實施例中，每一第二開口O2沿厚度方向Z在基底102上的垂直投影在俯視圖中可呈現多邊形形狀或任何合適的形狀。在一些實施例中，每一第二開口O2的側壁由隔離層110界定。詳細來說，如圖2中所示，位於像素區A的邊緣處的多個第二開口O2中的每一者的側壁由第一隔離圖案112及第二隔離圖案114二者界定，且位於像素區A的中心處的多個第二開口O2中的每一者的側壁僅由第二隔離圖案114界定。也就是說，第一隔離圖案112的第二側表面S2、第一圖案部分114a的第三側表面S3及第四側表面S4以及第二圖案部分114b的第五側表面S5及第六側表面S6可被視為第二開口O2的側壁。一同參照圖1與圖2，第一隔離圖案112的第二側表面S2、第一圖案部分114a的第三側表面S3及第二圖案部分114b的第五側表面S5可被視為圖1中所示的例示左側第二開口O2的側壁，第一隔離圖案112的第二側表面S2，第一圖案部分114a的第三側表面S3、另一第一圖案部分114a的第四側表面S4及第二圖案部分114b的第五側表面S5可被視為圖1中所示的例示中心第二開口O2的側壁，且第一圖案部分114a的第三側表面S3、另一第一圖案部分114a的第四側表面S4、第二圖案部分114b的第五側表面S5及另一第二圖案部分114b的第六側表面S6可被視為圖1中所示的例示右側第二開口O2的側壁。In addition, referring to FIGS. 1 and 2 together, each second opening O2 is a closed opening, and the vertical projection of the closed opening on the substrate 102 along the thickness direction Z is a rectangular shape. In other words, each second opening O2 has four side walls. However, the present disclosure is not limited to this. In some alternative embodiments, the vertical projection of each second opening O2 on the substrate 102 along the thickness direction Z may present a polygonal shape or any suitable shape in a top view. In some embodiments, the sidewall of each second opening O2 is defined by the isolation layer 110. In detail, as shown in FIG. 2, the sidewall of each of the plurality of second openings O2 located at the edge of the pixel area A is defined by both the first isolation pattern 112 and the second isolation pattern 114, and is located The sidewall of each of the plurality of second openings O2 at the center of the pixel area A is only defined by the second isolation pattern 114. That is, the second side surface S2 of the first isolation pattern 112, the third side surface S3 and the fourth side surface S4 of the first pattern portion 114a, and the fifth side surface S5 and the sixth side surface of the second pattern portion 114b S6 can be regarded as the side wall of the second opening O2. 1 and 2 together, the second side surface S2 of the first isolation pattern 112, the third side surface S3 of the first pattern portion 114a, and the fifth side surface S5 of the second pattern portion 114b can be regarded as in FIG. The sidewall of the second opening O2 shown on the left side, the second side surface S2 of the first isolation pattern 112, the third side surface S3 of the first pattern portion 114a, the fourth side surface S4 of the other first pattern portion 114a and The fifth side surface S5 of the second pattern portion 114b can be regarded as the side wall of the illustrated central second opening O2 shown in FIG. 1, and the third side surface S3 of the first pattern portion 114a and the other first pattern portion 114a The fourth side surface S4 of the second pattern portion 114b, the fifth side surface S5 of the second pattern portion 114b, and the sixth side surface S6 of the other second pattern portion 114b can be regarded as the sidewalls of the right second opening O2 shown in FIG. .

在一些實施例中，如圖1及圖2中所示，多個第二開口O2對應於下伏的多個第一電極108a設置。詳細來說，如圖1及圖2中所示，第一電極108a沿半導體基底100的厚度方向Z在基底102上的垂直投影與對應的第二開口O2沿半導體基底100的厚度方向Z在基底102上的垂直投影的跨度局部地交疊。也就是說，在製造顯示器件10的過程期間，在形成第二開口O2的階段中，第一電極108a被第二開口O2局部地暴露出。如上所述，第一電極108a的數目並不僅限於圖2中所繪示的數目，因此與第一電極108a對應的第二開口O2的數目也並不僅限於圖2中所繪示的數目，且可基於需求和/或設計佈局來指定。In some embodiments, as shown in FIGS. 1 and 2, the plurality of second openings O2 are arranged corresponding to the plurality of underlying first electrodes 108a. In detail, as shown in FIGS. 1 and 2, the vertical projection of the first electrode 108a on the substrate 102 along the thickness direction Z of the semiconductor substrate 100 and the corresponding second opening O2 are on the substrate 102 along the thickness direction Z of the semiconductor substrate 100. The spans of the vertical projections on 102 overlap locally. That is, during the process of manufacturing the display device 10, in the stage of forming the second opening 02, the first electrode 108a is partially exposed by the second opening 02. As mentioned above, the number of first electrodes 108a is not limited to the number shown in FIG. 2, and therefore the number of second openings O2 corresponding to the first electrodes 108a is not limited to the number shown in FIG. 2, and It can be specified based on requirements and/or design layout.

在一些實施例中，發光層120設置在隔離層110及多個第一電極108a上。在一些實施例中，發光層120可為可用於顯示器件中且是所屬領域中具有通常知識者衆所周知的任何發光層。在一些實施例中，發光層120的材料可包括呈紅色、綠色、藍色、白色、其他合適顔色的有機發光材料或者所述發光材料的組合。例如，在某些實施例中，發光層120包含白色有機發光材料。在一些實施例中，發光層120更包括其他有機功能層，例如電子傳輸層、電子注入層、孔洞傳輸層、孔洞注入層或所述功能層的組合。In some embodiments, the light-emitting layer 120 is disposed on the isolation layer 110 and the plurality of first electrodes 108a. In some embodiments, the light-emitting layer 120 may be any light-emitting layer that can be used in a display device and is well-known to those with ordinary knowledge in the art. In some embodiments, the material of the light-emitting layer 120 may include organic light-emitting materials in red, green, blue, white, other suitable colors, or a combination of the light-emitting materials. For example, in some embodiments, the light-emitting layer 120 includes a white organic light-emitting material. In some embodiments, the light-emitting layer 120 further includes other organic functional layers, such as an electron transport layer, an electron injection layer, a hole transport layer, a hole injection layer, or a combination of the functional layers.

在一些實施例中，發光層120不連續地設置在隔離層110及多個第一電極108a上，如圖1中所示。具體來說，在形成發光層120的過程期間，由於側表面的橫截面輪廓，發光層120會被隔離層110切割。也就是說，隔離層110被配置成使發光層120不連續地設置。只要隔離層110可使發光層120不連續地設置，隔離層110的側表面的橫截面輪廓的配置可並不僅限於圖1中所繪示的配置，且可基於需求和/或設計佈局來指定。In some embodiments, the light-emitting layer 120 is discontinuously disposed on the isolation layer 110 and the plurality of first electrodes 108a, as shown in FIG. 1. Specifically, during the process of forming the light emitting layer 120, the light emitting layer 120 may be cut by the isolation layer 110 due to the cross-sectional profile of the side surface. That is, the isolation layer 110 is configured such that the light emitting layer 120 is discontinuously provided. As long as the isolation layer 110 can discontinuously dispose the light emitting layer 120, the configuration of the cross-sectional profile of the side surface of the isolation layer 110 may not be limited to the configuration shown in FIG. 1, and may be specified based on requirements and/or design layout .

在一些實施例中，發光層120的一些部分設置在多個第二開口O2中。詳細來說，如圖1中所示，設置在多個第二開口O2中的發光層120的一些部分直接接觸下伏的且被第二開口O2暴露出的多個第一電極108a。此外，如圖1中所示，設置在多個第二開口O2中的發光層120的一些部分覆蓋由隔離層110界定的多個第二開口O2的側壁。也就是說，第一隔離圖案112的第二側表面S2、第一圖案部分114a的第三側表面S3及第四側表面S4以及第二圖案部分114b的第五側表面S5及第六側表面S6被發光層120覆蓋。In some embodiments, some parts of the light-emitting layer 120 are disposed in the plurality of second openings O2. In detail, as shown in FIG. 1, some parts of the light-emitting layer 120 disposed in the plurality of second openings O2 directly contact the plurality of first electrodes 108a underlying and exposed by the second openings O2. In addition, as shown in FIG. 1, some parts of the light emitting layer 120 disposed in the plurality of second openings O2 cover the sidewalls of the plurality of second openings O2 defined by the isolation layer 110. That is, the second side surface S2 of the first isolation pattern 112, the third side surface S3 and the fourth side surface S4 of the first pattern portion 114a, and the fifth side surface S5 and the sixth side surface of the second pattern portion 114b S6 is covered by the light-emitting layer 120.

在一些實施例中，發光層120的一部分設置在第一開口O1中。詳細來說，如圖1中所示，設置在第一開口O1中的發光層120的所述部分覆蓋由隔離層110界定的第一開口O1的側壁（即，第一隔離圖案112的第一側表面S1）及被第一開口O1暴露出的半導體基底100的例示頂表面的一部分。也就是說，設置在第一開口O1中的發光層120的所述部分從第一隔離圖案112的第一側表面S1延伸到外圍區B中未被第一隔離圖案112覆蓋的半導體基底100的例示頂表面。此外，如圖1中所示，設置在第一開口O1中的發光層120的所述部分的外邊緣與第一隔離圖案112的第一側表面S1（即，第一開口O1的側壁）之間的最小距離D等於或大於隔離層110的高度H的一半。也就是說，設置在第一開口O1中的發光層120的所述部分的外邊緣向第一隔離圖案112的第一側表面S1突出最小距離D。換句話說，半導體基底100被設置在第一開口O1中的發光層120的所述部分覆蓋最小距離D的範圍。如圖1中所示，沿與半導體基底100的厚度方向Z垂直的方向X，在半導體基底100的例示頂表面上的垂直投影中，整個發光層120的最外邊緣的投影位置位於整個隔離層110的最外邊緣的投影位置旁邊的最小距離D處。In some embodiments, a part of the light emitting layer 120 is disposed in the first opening O1. In detail, as shown in FIG. 1, the portion of the light emitting layer 120 disposed in the first opening O1 covers the sidewall of the first opening O1 defined by the isolation layer 110 (ie, the first isolation pattern 112 The side surface S1) and a portion of the exemplary top surface of the semiconductor substrate 100 exposed by the first opening O1. That is, the portion of the light-emitting layer 120 disposed in the first opening O1 extends from the first side surface S1 of the first isolation pattern 112 to the portion of the semiconductor substrate 100 that is not covered by the first isolation pattern 112 in the peripheral region B. Illustrate the top surface. In addition, as shown in FIG. 1, the outer edge of the portion of the light-emitting layer 120 disposed in the first opening O1 is between the first side surface S1 of the first isolation pattern 112 (ie, the sidewall of the first opening O1). The minimum distance D between the two is equal to or greater than half of the height H of the isolation layer 110. That is, the outer edge of the portion of the light emitting layer 120 disposed in the first opening O1 protrudes toward the first side surface S1 of the first isolation pattern 112 by the minimum distance D. In other words, the portion of the light emitting layer 120 disposed in the first opening O1 of the semiconductor substrate 100 covers the range of the minimum distance D. As shown in FIG. 1, along the direction X perpendicular to the thickness direction Z of the semiconductor substrate 100, in the vertical projection on the exemplary top surface of the semiconductor substrate 100, the projection position of the outermost edge of the entire light emitting layer 120 is located in the entire isolation layer. At the minimum distance D next to the projection position of the outermost edge of 110.

在一些實施例中，第二電極130設置在發光層120上。在一些實施例中，第二電極130從像素區A朝外圍區B延伸，如圖2中所示。此外，在一些實施例中，第二電極130設置在第一開口O1及多個第二開口O2中，如圖1中所示。在一些實施例中，第二電極130直接接觸下伏的共用電極108b，以與半導體基底100電連接。如上所述，共用電極108b可電接地，使得第二電極130也可電接地。在一些實施例中，第二電極130的材料包括透明導電材料。在某些實施例中，透明導電材料包括或為金屬氧化物導電材料，例如氧化銦錫、氧化銦鋅、氧化鋁錫、氧化鋁鋅、氧化銦鎵鋅、其他合適的氧化物或者上述材料中的至少兩者形成的堆疊層。然而，本公開並不僅限於此。在一些替代實施例中，第二電極130的材料包括不透明導電材料。在某些實施例中，不透明導電材料包括金屬。In some embodiments, the second electrode 130 is disposed on the light-emitting layer 120. In some embodiments, the second electrode 130 extends from the pixel area A toward the peripheral area B, as shown in FIG. 2. In addition, in some embodiments, the second electrode 130 is disposed in the first opening O1 and the plurality of second openings O2, as shown in FIG. 1. In some embodiments, the second electrode 130 directly contacts the underlying common electrode 108 b to be electrically connected to the semiconductor substrate 100. As described above, the common electrode 108b may be electrically grounded, so that the second electrode 130 may also be electrically grounded. In some embodiments, the material of the second electrode 130 includes a transparent conductive material. In some embodiments, the transparent conductive material includes or is a metal oxide conductive material, such as indium tin oxide, indium zinc oxide, aluminum oxide tin, aluminum oxide zinc, indium gallium zinc oxide, other suitable oxides, or any of the foregoing materials At least two of the stacked layers. However, the present disclosure is not limited to this. In some alternative embodiments, the material of the second electrode 130 includes an opaque conductive material. In some embodiments, the opaque conductive material includes metal.

在一些實施例中，第一電極108a、設置在第二開口O2中且與下伏的所述第一電極108a直接接觸的發光層120的部分、以及沿厚度方向Z與所述發光層120的部分交疊的第二電極130的部分構成發光元件。在顯示器件10中，在像素區A中設置有多個發光元件。由於第一電極108a的數目並不僅限於圖2中所繪示的數目，因此顯示器件10中的發光元件的數目也並不僅限於圖2中所繪示的數目，且可基於需求和/或設計佈局來指定。在某些實施例中，發光元件可為OLED元件。詳細來說，發光元件的發光層120由在第一電極108a與第二電極130之間産生的電壓差驅動發光。由於驅動訊號可通過驅動元件層104中的主動組件（未示出）傳送到第一電極108a，因此顯示器件10中的發光元件可由驅動元件層104中的主動組件（未示出）控制。在一些實施例中，第一電極108a充當發光元件的陽極，且第二電極130充當發光元件的陰極。然而，本公開並不僅限於此。在一些替代實施例中，根據設計要求，第一電極108a充當發光元件的陰極，且第二電極130充當發光元件的陽極。In some embodiments, the first electrode 108a, the portion of the light-emitting layer 120 that is disposed in the second opening O2 and directly contacts the underlying first electrode 108a, and the portion of the light-emitting layer 120 that is in contact with the light-emitting layer 120 along the thickness direction Z The part of the second electrode 130 that is partially overlapped constitutes a light-emitting element. In the display device 10, a plurality of light emitting elements are provided in the pixel area A. Since the number of first electrodes 108a is not limited to the number shown in FIG. 2, the number of light-emitting elements in the display device 10 is also not limited to the number shown in FIG. 2, and can be based on requirements and/or designs. Layout to specify. In some embodiments, the light-emitting element may be an OLED element. In detail, the light emitting layer 120 of the light emitting element is driven to emit light by the voltage difference generated between the first electrode 108a and the second electrode 130. Since the driving signal can be transmitted to the first electrode 108a through the active components (not shown) in the driving element layer 104, the light emitting elements in the display device 10 can be controlled by the active components (not shown) in the driving element layer 104. In some embodiments, the first electrode 108a serves as the anode of the light-emitting element, and the second electrode 130 serves as the cathode of the light-emitting element. However, the present disclosure is not limited to this. In some alternative embodiments, according to design requirements, the first electrode 108a serves as the cathode of the light-emitting element, and the second electrode 130 serves as the anode of the light-emitting element.

在一些實施例中，第二電極130連續地設置在發光層120及共用電極108b上，如圖1中所示。具體來說，由於隔離層110的側表面（例如，第一隔離圖案112的第一側表面S1及第二側表面S2、第一圖案部分114a的第三側表面S3及第四側表面S4以及第二圖案部分114b的第五側表面S5及第六側表面S6）被發光層120覆蓋，第二電極130被下伏的發光層120抬高，使得第二電極130遠離將使層（例如，發光層120）不連續的隔離層110的側表面。此外，當設置在第一開口O1中的發光層120的部分的外邊緣與第一隔離圖案112的第一側表面S1之間的最小距離D等於或大於隔離層110的高度H的一半時，被下伏的發光層120提高的第二電極130可避免被隔離層110切割。這樣一來，第二電極130具有良好的連續性，且因此可確保顯示器件10的電良率。In some embodiments, the second electrode 130 is continuously disposed on the light-emitting layer 120 and the common electrode 108b, as shown in FIG. 1. Specifically, due to the side surfaces of the isolation layer 110 (for example, the first side surface S1 and the second side surface S2 of the first isolation pattern 112, the third side surface S3 and the fourth side surface S4 of the first pattern portion 114a, and The fifth side surface S5 and the sixth side surface S6 of the second pattern portion 114b are covered by the light-emitting layer 120, and the second electrode 130 is raised by the underlying light-emitting layer 120, so that the second electrode 130 is far away from the layer (for example, The light-emitting layer 120) is a discontinuous side surface of the isolation layer 110. In addition, when the minimum distance D between the outer edge of the portion of the light emitting layer 120 disposed in the first opening O1 and the first side surface S1 of the first isolation pattern 112 is equal to or greater than half of the height H of the isolation layer 110, The second electrode 130 raised by the underlying light-emitting layer 120 can avoid being cut by the isolation layer 110. In this way, the second electrode 130 has good continuity, and thus the electrical yield of the display device 10 can be ensured.

在一些實施例中，介電包封體140包封且覆蓋第二電極130。在一些實施例中，介電包封體140填充到第一開口O1中，以在側向上包封第二電極130。在一些實施例中，介電包封體140包封顯示器件10中的發光元件，以將發光元件與濕氣、雜質等隔離。在一些實施例中，介電包封體140的材料包括氧化矽、氮化矽、氧化鋁、碳氮化矽（SiCN）、氮氧化矽、丙烯酸樹脂（acrylic resin）、六甲基二矽氧烷（hexamethyl disiloxane，HMDSO）或玻璃，但本發明並不僅限於此。In some embodiments, the dielectric encapsulant 140 encapsulates and covers the second electrode 130. In some embodiments, the dielectric encapsulant 140 is filled into the first opening O1 to encapsulate the second electrode 130 in the lateral direction. In some embodiments, the dielectric encapsulant 140 encapsulates the light-emitting element in the display device 10 to isolate the light-emitting element from moisture, impurities, and the like. In some embodiments, the material of the dielectric encapsulant 140 includes silicon oxide, silicon nitride, aluminum oxide, silicon carbonitride (SiCN), silicon oxynitride, acrylic resin, hexamethyldisiloxy Hexamethyl disiloxane (HMDSO) or glass, but the present invention is not limited to this.

以下將參照圖3A到圖3F以及圖4詳細闡述製造顯示器件10的方法。圖3A到圖3F是根據本公開一些實施例的顯示器件10的製造方法中的各個階段的示意性剖視圖。圖4是根據本公開一些實施例的顯示器件10的製造方法中的中間階段的簡化俯視圖。具體來說，圖3A是沿圖4所示線II-II’截取的剖視圖。The method of manufacturing the display device 10 will be described in detail below with reference to FIGS. 3A to 3F and FIG. 4. 3A to 3F are schematic cross-sectional views of various stages in a method of manufacturing the display device 10 according to some embodiments of the present disclosure. FIG. 4 is a simplified top view of an intermediate stage in a method of manufacturing the display device 10 according to some embodiments of the present disclosure. Specifically, FIG. 3A is a cross-sectional view taken along the line II-II' shown in FIG. 4.

參照圖3A及圖4，提供半導體基底100。在一些實施例中，半導體基底100可為半導體晶圓。這樣一來，圖3A到圖3F中例示的顯示器件10的製造方法可被視為晶圓級製程（wafer level process）。在一些實施例中，如圖4中所示，半導體基底100具有排列成陣列的多個器件單元DU。每一器件單元DU對應於半導體晶圓的一部分。如圖4中所示，多個器件單元DU由多條切割道SL1及多條切割道SL2界定。在一些實施例中，如圖4中所示，多條切割道SL1沿與半導體基底100的厚度方向Z垂直的方向X排列，且多條切割道SL2沿與厚度方向Z垂直的方向Y排列，其中方向X垂直於方向Y。在一些實施例中，每一切割道SL1沿方向Y延伸，且每一切割道SL2沿方向X延伸，如圖4中所示。另外，如圖4中所示，多條切割道SL1交叉穿過多條切割道SL2以提供多個列及多個行。器件單元DU的數目、切割道SL1的數目及切割道SL2的數目可小於或大於圖4中所繪示的數目，且可基於需求和/或設計佈局來指定；本公開並不特別局限於此。3A and 4, a semiconductor substrate 100 is provided. In some embodiments, the semiconductor substrate 100 may be a semiconductor wafer. In this way, the manufacturing method of the display device 10 illustrated in FIGS. 3A to 3F can be regarded as a wafer level process. In some embodiments, as shown in FIG. 4, the semiconductor substrate 100 has a plurality of device units DU arranged in an array. Each device unit DU corresponds to a part of the semiconductor wafer. As shown in FIG. 4, the plurality of device units DU are defined by a plurality of dicing lanes SL1 and a plurality of dicing lanes SL2. In some embodiments, as shown in FIG. 4, a plurality of scribe lines SL1 are arranged along a direction X perpendicular to the thickness direction Z of the semiconductor substrate 100, and a plurality of scribe lines SL2 are arranged along a direction Y perpendicular to the thickness direction Z. The direction X is perpendicular to the direction Y. In some embodiments, each scribe lane SL1 extends in the direction Y, and each scribe lane SL2 extends in the direction X, as shown in FIG. 4. In addition, as shown in FIG. 4, a plurality of dicing lanes SL1 cross the plurality of dicing lanes SL2 to provide a plurality of columns and a plurality of rows. The number of device units DU, the number of dicing lanes SL1, and the number of dicing lanes SL2 may be less than or greater than that shown in FIG. 4, and may be specified based on requirements and/or design layout; the present disclosure is not particularly limited to this .

在一些實施例中，如圖4中所示，多個器件單元DU中的每一者內部是像素區A及外圍區B。在圖3A所示的階段處，半導體基底100可具有排列成陣列的多個像素區A。以上已闡述了像素區A及外圍區B的細節，且在本文中將不再予以贅述。在一些實施例中，如圖3A中所示，多個器件單元DU中的每一者可包括基底102、驅動元件層104、內連線結構106、多個第一電極108a及共用電極108b。在一些實施例中，在圖3A所示的階段處，多個器件單元DU的基底102彼此連接。相似地，在一些實施例中，在圖3A所示的階段處，多個器件單元DU的驅動元件層104彼此連接，且多個器件單元DU的內連線結構106彼此連接。以上已闡述了基底102、驅動元件層104、內連線結構106、第一電極108a及共用電極108b的細節，且在本文中將不再予以贅述。In some embodiments, as shown in FIG. 4, inside each of the plurality of device units DU is a pixel area A and a peripheral area B. At the stage shown in FIG. 3A, the semiconductor substrate 100 may have a plurality of pixel regions A arranged in an array. The details of the pixel area A and the peripheral area B have been described above, and will not be repeated here. In some embodiments, as shown in FIG. 3A, each of the plurality of device units DU may include a substrate 102, a driving element layer 104, an interconnect structure 106, a plurality of first electrodes 108a and a common electrode 108b. In some embodiments, at the stage shown in FIG. 3A, the substrates 102 of the plurality of device units DU are connected to each other. Similarly, in some embodiments, at the stage shown in FIG. 3A, the driving element layers 104 of the multiple device units DU are connected to each other, and the interconnection structures 106 of the multiple device units DU are connected to each other. The details of the substrate 102, the driving element layer 104, the interconnection structure 106, the first electrode 108a and the common electrode 108b have been described above, and will not be repeated here.

參照圖3B，在半導體基底100上形成隔離層110’，以覆蓋第一電極108a及共用電極108b。在一些實施例中，隔離層110’的材料包括氧化矽、氮氧化矽、氮化矽或其組合。在某些實施例中，隔離層110’是氧化物-氮化物-氧化物（ONO）層。在一些實施例中，通過化學氣相沉積（CVD）或任何其他合適的膜沉積方法形成隔離層110’。3B, an isolation layer 110' is formed on the semiconductor substrate 100 to cover the first electrode 108a and the common electrode 108b. In some embodiments, the material of the isolation layer 110' includes silicon oxide, silicon oxynitride, silicon nitride, or a combination thereof. In some embodiments, the isolation layer 110' is an oxide-nitride-oxide (ONO) layer. In some embodiments, the isolation layer 110' is formed by chemical vapor deposition (CVD) or any other suitable film deposition method.

參照圖3C，將隔離層110’圖案化以形成隔離層110。在一些實施例中，通過執行微影製程及蝕刻製程形成隔離層110。在一些實施例中，通過至少以下步驟形成隔離層110。首先，在隔離層110’之上形成光阻層（未示出）。在一些實施例中，可通過旋轉塗佈或其他合適的方法形成光阻層。此後，將光阻層圖案化以形成經圖案化的光阻層，且使用經圖案化的光阻層作為罩幕對隔離層110’進行蝕刻，以形成隔離層110。接著移除或剝離經圖案化的光阻層。在一些實施例中，通過乾式蝕刻製程、濕式蝕刻製程或其組合來對隔離層110’進行蝕刻。在一些實施例中，可通過例如蝕刻、灰化或其他合適的移除製程來移除或剝離經圖案化的光阻層。3C, the isolation layer 110' is patterned to form the isolation layer 110. In some embodiments, the isolation layer 110 is formed by performing a lithography process and an etching process. In some embodiments, the isolation layer 110 is formed by at least the following steps. First, a photoresist layer (not shown) is formed on the isolation layer 110'. In some embodiments, the photoresist layer may be formed by spin coating or other suitable methods. Thereafter, the photoresist layer is patterned to form a patterned photoresist layer, and the isolation layer 110' is etched using the patterned photoresist layer as a mask to form the isolation layer 110. Then, the patterned photoresist layer is removed or stripped. In some embodiments, the isolation layer 110' is etched by a dry etching process, a wet etching process, or a combination thereof. In some embodiments, the patterned photoresist layer can be removed or stripped by, for example, etching, ashing, or other suitable removal processes.

在一些實施例中，如圖3C中所示，隔離層110包括第一隔離圖案112及第二隔離圖案114，且第二隔離圖案114具有多個第一圖案部分114a及多個第二圖案部分114b。在圖3C中，為簡潔起見，示出一個第一圖案部分114a及一個第二圖案部分114b。基於上述對圖1及圖2的說明，所屬領域中具有通常知識者可理解，可形成多個第一圖案部分114a及多個第二圖案部分114b以提供網格結構。In some embodiments, as shown in FIG. 3C, the isolation layer 110 includes a first isolation pattern 112 and a second isolation pattern 114, and the second isolation pattern 114 has a plurality of first pattern portions 114a and a plurality of second pattern portions 114b. In FIG. 3C, for the sake of brevity, a first pattern portion 114a and a second pattern portion 114b are shown. Based on the above description of FIGS. 1 and 2, those skilled in the art can understand that a plurality of first pattern portions 114 a and a plurality of second pattern portions 114 b can be formed to provide a grid structure.

在一些實施例中，如圖3C中所示，第一隔離圖案112的第一側表面S1的橫截面輪廓與第一隔離圖案112的第二側表面S2的橫截面輪廓實質上彼此對稱。第一圖案部分114a的第三側表面S3的橫截面輪廓與第一圖案部分114a的第四側表面S4的橫截面輪廓實質上彼此對稱。第二圖案部分114b的第五側表面S5的橫截面輪廓與第二圖案部分114b的第六側表面S6的橫截面輪廓實質上彼此對稱。第一側表面S1的橫截面輪廓、第三側表面S3的橫截面輪廓及第五側表面S5的橫截面輪廓實質上彼此相同。第二側表面S2的橫截面輪廓、第四側表面S4的橫截面輪廓及第六側表面S6的橫截面輪廓實質上彼此相同。以此種方式進行配置，第一側表面S1的橫截面輪廓、第二側表面S2的橫截面輪廓、第三側表面S3的橫截面輪廓、第四側表面S4的橫截面輪廓、第五側表面S5的橫截面輪廓及第六側表面S6的橫截面輪廓可被認為實質上彼此相同。鑒於此，可通過使用單個罩幕執行微影製程來形成隔離層110。這樣一來，隔離層110的形成過程簡單且成本低。In some embodiments, as shown in FIG. 3C, the cross-sectional profile of the first side surface S1 of the first isolation pattern 112 and the cross-sectional profile of the second side surface S2 of the first isolation pattern 112 are substantially symmetrical to each other. The cross-sectional profile of the third side surface S3 of the first pattern portion 114a and the cross-sectional profile of the fourth side surface S4 of the first pattern portion 114a are substantially symmetrical to each other. The cross-sectional profile of the fifth side surface S5 of the second pattern portion 114b and the cross-sectional profile of the sixth side surface S6 of the second pattern portion 114b are substantially symmetrical to each other. The cross-sectional profile of the first side surface S1, the cross-sectional profile of the third side surface S3, and the cross-sectional profile of the fifth side surface S5 are substantially the same as each other. The cross-sectional profile of the second side surface S2, the cross-sectional profile of the fourth side surface S4, and the cross-sectional profile of the sixth side surface S6 are substantially the same as each other. Configured in this way, the cross-sectional profile of the first side surface S1, the cross-sectional profile of the second side surface S2, the cross-sectional profile of the third side surface S3, the cross-sectional profile of the fourth side surface S4, the fifth side The cross-sectional profile of the surface S5 and the cross-sectional profile of the sixth side surface S6 may be considered to be substantially the same as each other. In view of this, the isolation layer 110 can be formed by performing a lithography process using a single mask. In this way, the formation process of the isolation layer 110 is simple and low in cost.

此外，在一些實施例中，如圖3C中所示，在對隔離層110’執行圖案化步驟之後，在隔離層110中形成第一開口O1及多個第二開口O2。詳細來說，如圖3C中所示，共用電極108b被第一開口O1暴露出，且多個第一電極108a的一些部分被多個第二開口O2暴露出。以上已闡述了隔離層110的其他細節，且在本文中將不再予以贅述。In addition, in some embodiments, as shown in FIG. 3C, after performing a patterning step on the isolation layer 110', a first opening O1 and a plurality of second openings O2 are formed in the isolation layer 110. In detail, as shown in FIG. 3C, the common electrode 108b is exposed by the first opening O1, and some parts of the plurality of first electrodes 108a are exposed by the plurality of second openings O2. The other details of the isolation layer 110 have been described above, and will not be repeated here.

參照圖3D，在隔離層110上以及第一開口O1及多個第二開口O2中形成發光層120。發光層120設置在像素區A及外圍區B二者中。在一些實施例中，通過蒸鍍或任何其他合適的膜沉積方法形成發光層120。如圖3D中所示，利用具有第一開口圖案OP1的第一罩幕M1來形成發光層120。在圖3D中，為簡潔起見，示出一個第一開口圖案OP1。基於上述對圖3A及圖4的說明，所屬領域中具有通常知識者可理解，在第一罩幕M1中形成與多個器件單元DU對應的多個第一開口圖案OP1。Referring to FIG. 3D, a light emitting layer 120 is formed on the isolation layer 110 and in the first opening O1 and the plurality of second openings O2. The light emitting layer 120 is disposed in both the pixel area A and the peripheral area B. In some embodiments, the light-emitting layer 120 is formed by evaporation or any other suitable film deposition method. As shown in FIG. 3D, the light emitting layer 120 is formed using a first mask M1 having a first opening pattern OP1. In FIG. 3D, for the sake of brevity, a first opening pattern OP1 is shown. Based on the above description of FIGS. 3A and 4, a person with ordinary knowledge in the field can understand that a plurality of first opening patterns OP1 corresponding to a plurality of device units DU are formed in the first mask M1.

在一些實施例中，提供第一開口圖案OP1以界定發光層120的位置。在一些實施例中，第一開口圖案OP1在半導體基底100的厚度方向Z上暴露出隔離層110。如圖3D中所示，由於隔離層110的側表面的橫截面輪廓，發光層120不連續地形成在隔離層110上。也就是說，即使整個隔離層110被第一開口圖案OP1暴露出，隔離層110的一些部分110p仍不會被發光層120覆蓋。在一些實施例中，第一開口圖案OP1的邊界與第一隔離圖案112的第一側表面S1之間的最小距離D2等於或大於隔離層110的高度H的一半。使用第一罩幕M1與隔離層110之間的此種位置關係，設置在第一開口O1中的發光層120的部分的外邊緣與第一隔離圖案112的第一側表面S1之間的最小距離D等於或大於隔離層110的高度H的一半。以上已闡述了發光層120的其他細節，且在本文中將不再予以贅述。In some embodiments, the first opening pattern OP1 is provided to define the position of the light emitting layer 120. In some embodiments, the first opening pattern OP1 exposes the isolation layer 110 in the thickness direction Z of the semiconductor substrate 100. As shown in FIG. 3D, the light emitting layer 120 is discontinuously formed on the isolation layer 110 due to the cross-sectional profile of the side surface of the isolation layer 110. That is, even if the entire isolation layer 110 is exposed by the first opening pattern OP1, some parts 110p of the isolation layer 110 will not be covered by the light emitting layer 120. In some embodiments, the minimum distance D2 between the boundary of the first opening pattern OP1 and the first side surface S1 of the first isolation pattern 112 is equal to or greater than half of the height H of the isolation layer 110. Using this positional relationship between the first mask M1 and the isolation layer 110, the distance between the outer edge of the portion of the light emitting layer 120 disposed in the first opening O1 and the first side surface S1 of the first isolation pattern 112 is the smallest The distance D is equal to or greater than half of the height H of the isolation layer 110. The other details of the light-emitting layer 120 have been described above, and will not be repeated here.

參照圖3E，在發光層120上形成第二電極130。在一些實施例中，通過蒸鍍、化學氣相沉積（CVD）、物理氣相沉積（PVD）或任何其他合適的膜沉積方法形成第二電極130。詳細來說，如圖3E中所示，利用具有第二開口圖案OP2的第二罩幕M2來形成第二電極130。在圖3E中，為簡潔起見，示出一個第二開口圖案OP2。如圖3A及圖4中例示以及如上所述，在第二罩幕M2中可形成與多個器件單元DU對應的多個第二開口圖案OP2。Referring to FIG. 3E, a second electrode 130 is formed on the light emitting layer 120. In some embodiments, the second electrode 130 is formed by evaporation, chemical vapor deposition (CVD), physical vapor deposition (PVD), or any other suitable film deposition method. In detail, as shown in FIG. 3E, the second electrode 130 is formed using a second mask M2 having a second opening pattern OP2. In FIG. 3E, for the sake of brevity, a second opening pattern OP2 is shown. As illustrated in FIGS. 3A and 4 and as described above, a plurality of second opening patterns OP2 corresponding to a plurality of device units DU may be formed in the second mask M2.

在一些實施例中，提供第二開口圖案OP2以界定第二電極130的位置。在一些實施例中，第二開口圖案OP2在半導體基底100的厚度方向Z上暴露出發光層120。如圖3E中所示，第二電極130被形成為在半導體基底100之上從像素區A連續地延伸到外圍區B。具體來說，第二電極130被下伏的發光層120抬高，使得第二電極130遠離導致所述層（例如，發光層120）的不連續性的隔離層110的側表面。此外，在某些實施例中，發光層120延伸到外圍區B中的半導體基底100的例示頂表面上的最小距離D等於或大於隔離層110的高度H的一半，使得被下伏的發光層120抬高的第二電極130可避免被隔離層110切割。這樣一來，第二電極130被形成為具有良好的連續性，且因此可確保顯示器件10的電良率。通過將最小距離D布置成等於或大於隔離層110的高度H的一半，即使使用單個罩幕形成隔離層110以使所有側表面具有會破壞形成在隔離層110上的層的一致的橫截面輪廓，第二電極130仍可連續地形成在半導體基底100之上，以確保顯示器件10的電良率。因此，製造顯示器件10的複雜性及成本得到降低，且顯示器件10的良率及性能得到改善。In some embodiments, the second opening pattern OP2 is provided to define the position of the second electrode 130. In some embodiments, the second opening pattern OP2 exposes the light emitting layer 120 in the thickness direction Z of the semiconductor substrate 100. As shown in FIG. 3E, the second electrode 130 is formed to continuously extend from the pixel area A to the peripheral area B over the semiconductor substrate 100. Specifically, the second electrode 130 is elevated by the underlying light-emitting layer 120 so that the second electrode 130 is away from the side surface of the isolation layer 110 that causes discontinuity of the layer (for example, the light-emitting layer 120). In addition, in some embodiments, the minimum distance D of the light emitting layer 120 extending to the exemplary top surface of the semiconductor substrate 100 in the peripheral region B is equal to or greater than half of the height H of the isolation layer 110, so that the underlying light emitting layer The second electrode 130 raised by 120 can avoid being cut by the isolation layer 110. In this way, the second electrode 130 is formed to have good continuity, and thus the electrical yield of the display device 10 can be ensured. By arranging the minimum distance D to be equal to or greater than half of the height H of the isolation layer 110, even if a single mask is used to form the isolation layer 110 so that all side surfaces have a uniform cross-sectional profile that would destroy the layer formed on the isolation layer 110 The second electrode 130 can still be continuously formed on the semiconductor substrate 100 to ensure the electrical yield of the display device 10. Therefore, the complexity and cost of manufacturing the display device 10 are reduced, and the yield and performance of the display device 10 are improved.

在一些實施例中，第二開口圖案OP2在半導體基底100的厚度方向Z上暴露出共用電極108b。利用第二罩幕M2形成的第二電極130直接接觸下伏的共用電極108b，以提供與半導體基底100的電連接。以上已闡述了第二電極130的其他細節，且在本文中將不再予以贅述。In some embodiments, the second opening pattern OP2 exposes the common electrode 108 b in the thickness direction Z of the semiconductor substrate 100. The second electrode 130 formed by the second mask M2 directly contacts the underlying common electrode 108 b to provide electrical connection with the semiconductor substrate 100. The other details of the second electrode 130 have been described above, and will not be repeated here.

參照圖3F，在第二電極130之上形成介電包封體140。在一些實施例中，如圖3F中所示，介電包封體140完全地形成在半導體基底100之上。在一些實施例中，通過化學氣相沉積（CVD）、蒸鍍或任何其他合適的製作技術形成介電包封體140。以上已闡述了介電包封體140的其他細節，且在本文中將不再予以贅述。3F, a dielectric encapsulant 140 is formed on the second electrode 130. In some embodiments, as shown in FIG. 3F, the dielectric encapsulant 140 is completely formed on the semiconductor substrate 100. In some embodiments, the dielectric encapsulation body 140 is formed by chemical vapor deposition (CVD), evaporation, or any other suitable manufacturing technique. The other details of the dielectric encapsulation body 140 have been described above, and will not be repeated here.

在形成介電包封體140之後，執行單體化製程來切割半導體基底100及介電包封體140，以提供多個顯示器件10。舉例來說，通過沿如圖4中所示的排列在多個器件單元DU之間的多條切割道SL1及多條切割道SL2進行切割來執行單體化製程以將各別顯示器件10隔開。單體化製程可為雷射切割製程、機械切割製程或其他合適的製程。在一些實施例中，單體化製程是通過旋轉刀片或雷射束進行切分。在一些實施例中，顯示器件10適用於近眼顯示應用。After the dielectric encapsulation body 140 is formed, a singulation process is performed to cut the semiconductor substrate 100 and the dielectric encapsulation body 140 to provide a plurality of display devices 10. For example, the singulation process is performed by cutting along the plurality of dicing lanes SL1 and the plurality of dicing lanes SL2 arranged between the plurality of device units DU as shown in FIG. 4 to separate the individual display devices 10 open. The singulation process can be a laser cutting process, a mechanical cutting process, or other suitable processes. In some embodiments, the singulation process is performed by rotating blades or laser beams. In some embodiments, the display device 10 is suitable for near-eye display applications.

儘管各個製程被示出並闡述為一系列動作或事件，然而應理解，此種動作或事件的例示次序不被解釋為具有限制性意義。另外，並不要求所有所例示的製程均實施本公開的一個或多個實施例。Although each process is shown and described as a series of actions or events, it should be understood that the illustrated sequence of such actions or events is not to be construed as having a restrictive meaning. In addition, it is not required that all the illustrated processes implement one or more embodiments of the present disclosure.

在圖3A到圖3F中所示的顯示器件10的製造方法中，將發光層120形成為以最小距離D的範圍覆蓋外圍區B中的半導體基底100，同時將隔離層110的第一隔離圖案112形成為不直接接觸共用電極108b。可通過使用罩幕回拉製程（mask pull-back process）來完成隔離層110的形成。在一些實施例中，罩幕回拉製程包括對用於界定隔離層110的第一開口O1的罩幕中的開口圖案進行加寬。然而，本公開並不僅限於此。在下文中，將參照圖5闡述其他實施例。In the manufacturing method of the display device 10 shown in FIGS. 3A to 3F, the light-emitting layer 120 is formed to cover the semiconductor substrate 100 in the peripheral region B with a minimum distance D, and the first isolation pattern of the isolation layer 110 112 is formed so as not to directly contact the common electrode 108b. The formation of the isolation layer 110 can be completed by using a mask pull-back process. In some embodiments, the mask pull-back process includes widening the opening pattern in the mask used to define the first opening O1 of the isolation layer 110. However, the present disclosure is not limited to this. Hereinafter, other embodiments will be explained with reference to FIG. 5.

圖5是根據本公開一些替代實施例的顯示器件的示意性剖視圖。參照圖5及圖1，圖5所示顯示器件20與被例示為沿圖2所示線I-I’截取的橫截面的圖1所示顯示器件10相似。因此，使用相同的參考編號指代相同或類似的部件，且在本文中不再對其予以贅述。以下闡述顯示器件20與顯示器件10之間的差異。FIG. 5 is a schematic cross-sectional view of a display device according to some alternative embodiments of the present disclosure. 5 and 1, the display device 20 shown in FIG. 5 is similar to the display device 10 shown in FIG. 1 exemplified as a cross-section taken along the line I-I' shown in FIG. 2. Therefore, the same reference numbers are used to refer to the same or similar components, and they will not be repeated here. The difference between the display device 20 and the display device 10 is explained below.

參照圖5，在顯示器件20中，發光層120以最小距離D的範圍覆蓋外圍區B中的半導體基底100，同時隔離層110的第一隔離圖案112被形成為直接接觸共用電極108b。在此種情形中，可通過使用罩幕回拉製程來完成發光層120的形成。在用以形成發光層120的罩幕回拉製程中，用於界定發光層120的位置的第一罩幕M1的第一開口圖案OP1（如圖3D中所示）可被加寬以暴露出隔離層110及共用電極108b二者。5, in the display device 20, the light emitting layer 120 covers the semiconductor substrate 100 in the peripheral region B with a minimum distance D, while the first isolation pattern 112 of the isolation layer 110 is formed to directly contact the common electrode 108b. In this case, the formation of the light-emitting layer 120 can be completed by using a mask pull-back process. In the mask pull-back process for forming the light-emitting layer 120, the first opening pattern OP1 (as shown in FIG. 3D) of the first mask M1 used to define the position of the light-emitting layer 120 may be widened to expose Both the isolation layer 110 and the common electrode 108b.

根據一些實施例，一種顯示器件包括半導體基底、隔離層、發光層及第二電極。所述半導體基底具有像素區及位於所述像素區周圍的外圍區，其中所述半導體基底包括多個第一電極及驅動元件層。所述多個第一電極設置在所述像素區中且所述多個第一電極電連接到所述驅動元件層。所述隔離層設置在所述半導體基底上，其中所述隔離層包括設置在所述外圍區中的第一隔離圖案，所述第一隔離圖案具有第一側表面及與所述第一側表面相對的第二側表面。所述發光層設置在所述隔離層及所述多個第一電極上，且覆蓋所述第一隔離圖案的所述第一側表面及所述第二側表面。所述第二電極設置在所述發光層上。According to some embodiments, a display device includes a semiconductor substrate, an isolation layer, a light emitting layer, and a second electrode. The semiconductor substrate has a pixel area and a peripheral area located around the pixel area, wherein the semiconductor substrate includes a plurality of first electrodes and driving element layers. The plurality of first electrodes are disposed in the pixel region and the plurality of first electrodes are electrically connected to the driving element layer. The isolation layer is disposed on the semiconductor substrate, wherein the isolation layer includes a first isolation pattern disposed in the peripheral region, and the first isolation pattern has a first side surface and is connected to the first side surface. Opposite second side surface. The light-emitting layer is disposed on the isolation layer and the plurality of first electrodes, and covers the first side surface and the second side surface of the first isolation pattern. The second electrode is disposed on the light-emitting layer.

根據一些實施例，一種顯示器件包括半導體基底、隔離層、發光層及第二電極。所述半導體基底具有像素區及位於所述像素區周圍的外圍區，其中所述半導體基底包括多個第一電極及驅動元件層。所述多個第一電極設置在所述像素區中，且所述多個第一電極電連接到所述驅動元件層。所述隔離層設置在所述半導體基底上，其中所述隔離層包括位於所述外圍區中的第一開口及位於所述像素區中的多個第二開口。所述發光層設置在所述隔離層上以及所述第一開口及所述多個第二開口中。所述第二電極設置在所述發光層上。According to some embodiments, a display device includes a semiconductor substrate, an isolation layer, a light emitting layer, and a second electrode. The semiconductor substrate has a pixel area and a peripheral area located around the pixel area, wherein the semiconductor substrate includes a plurality of first electrodes and driving element layers. The plurality of first electrodes are disposed in the pixel region, and the plurality of first electrodes are electrically connected to the driving element layer. The isolation layer is disposed on the semiconductor substrate, wherein the isolation layer includes a first opening in the peripheral region and a plurality of second openings in the pixel region. The light-emitting layer is disposed on the isolation layer and in the first opening and the plurality of second openings. The second electrode is disposed on the light-emitting layer.

根據一些實施例，一種顯示器件的製造方法包括至少以下步驟。提供具有多個器件單元的半導體基底，其中所述多個器件單元中的每一者具有像素區及位於所述像素區周圍的外圍區，且所述半導體基底包括多個第一電極及驅動元件層。所述多個第一電極設置在所述像素區中，且所述多個第一電極電連接到所述驅動元件層。在所述半導體基底上形成隔離層。將所述隔離層圖案化，以在所述外圍區中形成第一開口且在所述像素區中形成多個第二開口，其中所述多個第二開口暴露出所述多個第一電極。在經圖案化的所述隔離層上以及在所述第一開口及所述多個第二開口中形成發光層。在所述發光層上形成第二電極。According to some embodiments, a method of manufacturing a display device includes at least the following steps. A semiconductor substrate having a plurality of device units is provided, wherein each of the plurality of device units has a pixel area and a peripheral area located around the pixel area, and the semiconductor substrate includes a plurality of first electrodes and driving elements Floor. The plurality of first electrodes are disposed in the pixel region, and the plurality of first electrodes are electrically connected to the driving element layer. An isolation layer is formed on the semiconductor substrate. The isolation layer is patterned to form a first opening in the peripheral region and a plurality of second openings in the pixel region, wherein the plurality of second openings expose the plurality of first electrodes . A light emitting layer is formed on the patterned isolation layer and in the first opening and the plurality of second openings. A second electrode is formed on the light-emitting layer.

以上概述了若干實施例的特徵，以使所屬領域中具有通常知識者可更好地理解本公開的各個方面。所屬領域中具有通常知識者應理解，他們可容易地使用本公開作為設計或修改其他製程及結構的基礎來施行與本文中所介紹的實施例相同的目的和/或實現與本文中所介紹的實施例相同的優點。所屬領域中具有通常知識者還應認識到，這些等效構造並不背離本公開的精神及範圍，而且他們可在不背離本公開的精神及範圍的條件下對其作出各種改變、代替及變更。The features of several embodiments are summarized above, so that those with ordinary knowledge in the field can better understand various aspects of the present disclosure. Those with ordinary knowledge in the field should understand that they can easily use the present disclosure as a basis for designing or modifying other processes and structures to perform the same purpose as the embodiments described herein and/or achieve the same purpose as the embodiments described herein. The same advantages as the embodiment. Those with ordinary knowledge in the field should also realize that these equivalent structures do not depart from the spirit and scope of the present disclosure, and they can make various changes, substitutions and alterations to it without departing from the spirit and scope of the present disclosure. .

10、20:顯示器件 100:半導體基底 102:基底 104:驅動元件層 106:內連線結構 108a:第一電極 108b:共用電極 110、110’:隔離層 110p:部分 112:第一隔離圖案 114:第二隔離圖案 114a:第一圖案部分 114b:第二圖案部分 120:發光層 130:第二電極 140:介電包封體 A:像素區 B:外圍區 D、D2:最小距離 DU:器件單元 H:高度 I-I’、II-II’:線 M1:第一罩幕 M2:第二罩幕 O1:第一開口 O2:第二開口 OP1:第一開口圖案 OP2:第二開口圖案 S1:第一側表面 S2:第二側表面 S3:第三側表面 S4:第四側表面 S5:第五側表面 S6:第六側表面 SL1、SL2:切割道 X、Y:方向 Z:厚度方向10, 20: display device 100: Semiconductor substrate 102: Base 104: drive component layer 106: internal connection structure 108a: first electrode 108b: Common electrode 110, 110’: Isolation layer 110p: partial 112: The first isolation pattern 114: second isolation pattern 114a: The first pattern part 114b: The second pattern part 120: luminescent layer 130: second electrode 140: Dielectric encapsulation body A: Pixel area B: Peripheral area D, D2: minimum distance DU: device unit H: height I-I’, II-II’: Line M1: The first curtain M2: Second veil O1: first opening O2: second opening OP1: The first opening pattern OP2: The second opening pattern S1: First side surface S2: second side surface S3: Third side surface S4: Fourth side surface S5: Fifth side surface S6: Sixth side surface SL1, SL2: cutting lane X, Y: direction Z: thickness direction

結合附圖閱讀以下詳細說明，會最好地理解本公開的各個方面。應注意，根據本行業中的標準慣例，各種特徵並非按比例繪製。事實上，為使論述清晰起見，可任意增大或減小各種特徵的尺寸。 圖1是根據本公開一些實施例的顯示器件的示意性剖視圖。 圖2是根據本公開一些實施例的顯示器件的簡化俯視圖。 圖3A到圖3F是根據本公開一些實施例的顯示器件的製造方法中的各個階段的示意性剖視圖。 圖4是根據本公開一些實施例的顯示器件的製造方法中的中間階段的簡化俯視圖。 圖5是根據本公開一些替代實施例的顯示器件的示意性剖視圖。Read the following detailed description in conjunction with the accompanying drawings to best understand all aspects of the present disclosure. It should be noted that the various features are not drawn to scale according to standard practices in this industry. In fact, in order to make the discussion clear, the size of various features can be increased or decreased arbitrarily. FIG. 1 is a schematic cross-sectional view of a display device according to some embodiments of the present disclosure. FIG. 2 is a simplified top view of a display device according to some embodiments of the present disclosure. 3A to 3F are schematic cross-sectional views of various stages in a method of manufacturing a display device according to some embodiments of the present disclosure. 4 is a simplified top view of an intermediate stage in a method of manufacturing a display device according to some embodiments of the present disclosure. FIG. 5 is a schematic cross-sectional view of a display device according to some alternative embodiments of the present disclosure.

10:顯示器件 10: Display device

100:半導體基底 100: Semiconductor substrate

102:基底 102: Base

104:驅動元件層 104: drive component layer

106:內連線結構 106: internal connection structure

108a:第一電極 108a: first electrode

108b:共用電極 108b: Common electrode

110:隔離層 110: isolation layer

112:第一隔離圖案 112: The first isolation pattern

114:第二隔離圖案 114: second isolation pattern

114a:第一圖案部分 114a: The first pattern part

114b:第二圖案部分 114b: The second pattern part

120:發光層 120: luminescent layer

130:第二電極 130: second electrode

140:介電包封體 140: Dielectric encapsulation body

A:像素區 A: Pixel area

B:外圍區 B: Peripheral area

D:最小距離 D: minimum distance

H:高度 H: height

I-I’:線 I-I’: line

O1:第一開口 O1: first opening

O2:第二開口 O2: second opening

S1:第一側表面 S1: First side surface

S2:第二側表面 S2: second side surface

S3:第三側表面 S3: Third side surface

S4:第四側表面 S4: Fourth side surface

S5:第五側表面 S5: Fifth side surface

S6:第六側表面 S6: Sixth side surface

X:方向 X: direction

Z:厚度方向 Z: thickness direction

Claims (20)

一種顯示器件，包括： 半導體基底，具有像素區及位於所述像素區周圍的外圍區，其中所述半導體基底包括多個第一電極及驅動元件層，所述多個第一電極設置在所述像素區中，且所述多個第一電極電連接到所述驅動元件層； 隔離層，設置在所述半導體基底上，其中所述隔離層包括設置在所述外圍區中的第一隔離圖案，且所述第一隔離圖案具有第一側表面及與所述第一側表面相對的第二側表面； 發光層，設置在所述隔離層及所述多個第一電極上，且覆蓋所述第一隔離圖案的所述第一側表面及所述第二側表面；以及 第二電極，設置在所述發光層上。A display device including: The semiconductor substrate has a pixel region and a peripheral region located around the pixel region, wherein the semiconductor substrate includes a plurality of first electrodes and a driving element layer, the plurality of first electrodes are arranged in the pixel region, and The plurality of first electrodes are electrically connected to the driving element layer; An isolation layer disposed on the semiconductor substrate, wherein the isolation layer includes a first isolation pattern disposed in the peripheral region, and the first isolation pattern has a first side surface and a first side surface Opposite second side surface; A light-emitting layer disposed on the isolation layer and the plurality of first electrodes, and covering the first side surface and the second side surface of the first isolation pattern; and The second electrode is arranged on the light-emitting layer. 如請求項1所述的顯示器件，其中所述第二側表面比所述第一側表面更靠近所述像素區，且所述發光層的外邊緣與所述第一側表面之間的最小距離等於或大於所述隔離層的高度的一半。The display device according to claim 1, wherein the second side surface is closer to the pixel area than the first side surface, and the distance between the outer edge of the light-emitting layer and the first side surface is the smallest The distance is equal to or greater than half of the height of the isolation layer. 如請求項1所述的顯示器件，其中所述隔離層更包括設置在所述像素區中的第二隔離圖案，所述第二隔離圖案具有多個第一圖案部分及多個第二圖案部分，所述多個第一圖案部分沿第一方向排列，所述多個第二圖案部分沿第二方向排列，所述第一方向垂直於所述第二方向，且所述多個第一圖案部分中的每一者具有第三側表面及與所述第三側表面相對的第四側表面。The display device according to claim 1, wherein the isolation layer further includes a second isolation pattern disposed in the pixel region, the second isolation pattern having a plurality of first pattern portions and a plurality of second pattern portions , The plurality of first pattern parts are arranged along a first direction, the plurality of second pattern parts are arranged along a second direction, the first direction is perpendicular to the second direction, and the plurality of first patterns Each of the parts has a third side surface and a fourth side surface opposite to the third side surface. 如請求項3所述的顯示器件，其中所述第一側表面的橫截面輪廓、所述第二側表面的橫截面輪廓、所述第三側表面的橫截面輪廓及所述第四側表面的橫截面輪廓實質上相同。The display device according to claim 3, wherein the cross-sectional profile of the first side surface, the cross-sectional profile of the second side surface, the cross-sectional profile of the third side surface, and the fourth side surface The cross-sectional profile of is substantially the same. 如請求項1所述的顯示器件，其中所述半導體基底更包括共用電極，所述共用電極設置在所述外圍區中且電連接到所述第二電極。The display device according to claim 1, wherein the semiconductor substrate further includes a common electrode, and the common electrode is provided in the peripheral region and is electrically connected to the second electrode. 如請求項1所述的顯示器件，其中所述發光層不連續地設置在所述隔離層及所述多個第一電極上，且所述第二電極連續地設置在所述發光層上。The display device according to claim 1, wherein the light-emitting layer is discontinuously provided on the isolation layer and the plurality of first electrodes, and the second electrode is continuously provided on the light-emitting layer. 如請求項1所述的顯示器件，其中所述第一隔離圖案具有環形形狀。The display device according to claim 1, wherein the first isolation pattern has a ring shape. 如請求項1所述的顯示器件，更包括介電包封體，所述介電包封體包封且覆蓋所述第二電極。The display device according to claim 1, further comprising a dielectric encapsulation body that encapsulates and covers the second electrode. 一種顯示器件，包括： 半導體基底，具有像素區及位於所述像素區周圍的外圍區，其中所述半導體基底包括多個第一電極及驅動元件層，所述多個第一電極設置在所述像素區中，且所述多個第一電極電連接到所述驅動元件層； 隔離層，設置在所述半導體基底上，其中所述隔離層包括位於所述外圍區中的第一開口及位於所述像素區中的多個第二開口； 發光層，設置在所述隔離層上以及所述第一開口及所述多個第二開口中；以及 第二電極，設置在所述發光層上。A display device including: The semiconductor substrate has a pixel region and a peripheral region located around the pixel region, wherein the semiconductor substrate includes a plurality of first electrodes and a driving element layer, the plurality of first electrodes are arranged in the pixel region, and The plurality of first electrodes are electrically connected to the driving element layer; An isolation layer disposed on the semiconductor substrate, wherein the isolation layer includes a first opening in the peripheral region and a plurality of second openings in the pixel region; A light-emitting layer disposed on the isolation layer and in the first opening and the plurality of second openings; and The second electrode is arranged on the light-emitting layer. 如請求項9所述的顯示器件，其中所述發光層覆蓋由所述隔離層界定的所述第一開口的側壁及由所述隔離層界定的所述多個第二開口的多個側壁。The display device according to claim 9, wherein the light-emitting layer covers the sidewalls of the first opening defined by the isolation layer and the plurality of sidewalls of the second openings defined by the isolation layer. 如請求項9所述的顯示器件，其中設置在所述多個第二開口中的所述發光層接觸所述多個第一電極。The display device according to claim 9, wherein the light-emitting layer provided in the plurality of second openings contacts the plurality of first electrodes. 如請求項10所述的顯示器件，其中設置在所述第一開口中的所述發光層的外邊緣與由所述隔離層界定的所述第一開口的所述側壁之間的最小距離等於或大於所述隔離層的高度的一半。The display device according to claim 10, wherein the minimum distance between the outer edge of the light emitting layer provided in the first opening and the sidewall of the first opening defined by the isolation layer is equal to Or more than half of the height of the isolation layer. 如請求項10所述的顯示器件，其中由所述隔離層界定的所述第一開口的所述側壁的橫截面輪廓與由所述隔離層界定的所述多個第二開口的所述多個側壁中的每一者的橫截面輪廓實質上相同。The display device according to claim 10, wherein the cross-sectional profile of the sidewall of the first opening defined by the isolation layer and the plurality of second openings defined by the isolation layer The cross-sectional profile of each of the side walls is substantially the same. 如請求項9所述的顯示器件，更包括介電包封體，所述介電包封體包封所述第二電極且填充在所述第一開口中。The display device according to claim 9, further comprising a dielectric encapsulation body that encapsulates the second electrode and is filled in the first opening. 一種顯示器件的製造方法，包括： 提供具有多個器件單元的半導體基底，其中所述多個器件單元中的每一者具有像素區及位於所述像素區周圍的外圍區，所述半導體基底包括多個第一電極及驅動元件層，所述多個第一電極設置在所述像素區中，且所述多個第一電極電連接到所述驅動元件層； 在所述半導體基底上形成隔離層； 將所述隔離層圖案化，以在所述外圍區中形成第一開口且在所述像素區中形成多個第二開口，其中所述多個第二開口暴露出所述多個第一電極； 在經圖案化的所述隔離層上以及在所述第一開口及所述多個第二開口中形成發光層；以及 在所述發光層上形成第二電極。A method for manufacturing a display device includes: A semiconductor substrate having a plurality of device units is provided, wherein each of the plurality of device units has a pixel area and a peripheral area located around the pixel area, and the semiconductor substrate includes a plurality of first electrodes and a driving element layer , The plurality of first electrodes are arranged in the pixel area, and the plurality of first electrodes are electrically connected to the driving element layer; Forming an isolation layer on the semiconductor substrate; The isolation layer is patterned to form a first opening in the peripheral region and a plurality of second openings in the pixel region, wherein the plurality of second openings expose the plurality of first electrodes ； Forming a light emitting layer on the patterned isolation layer and in the first opening and the plurality of second openings; and A second electrode is formed on the light-emitting layer. 如請求項15所述的顯示器件的製造方法，其中將所述隔離層圖案化包括：使用單個罩幕對所述隔離層執行微影製程。The method for manufacturing a display device according to claim 15, wherein patterning the isolation layer includes: performing a lithography process on the isolation layer using a single mask. 如請求項15所述的顯示器件的製造方法，其中形成所述發光層包括： 提供具有第一開口圖案的第一罩幕；以及 執行第一沉積製程，以對應於所述第一罩幕的所述第一開口圖案而在經圖案化的所述隔離層上形成所述發光層，其中所述第一開口圖案在所述半導體基底的厚度方向上暴露出經圖案化的所述隔離層。The method for manufacturing a display device according to claim 15, wherein forming the light-emitting layer includes: Providing a first mask with a first opening pattern; and A first deposition process is performed to form the light-emitting layer on the patterned isolation layer corresponding to the first opening pattern of the first mask, wherein the first opening pattern is in the semiconductor The patterned isolation layer is exposed in the thickness direction of the substrate. 如請求項17所述的顯示器件的製造方法，其中在所述第一沉積製程期間，所述第一罩幕的所述第一開口圖案的邊界與由經圖案化的所述隔離層界定的所述第一開口的側壁之間的最小距離等於或大於經圖案化的所述隔離層的高度的一半。The method of manufacturing a display device according to claim 17, wherein during the first deposition process, the boundary of the first opening pattern of the first mask is defined by the patterned isolation layer The minimum distance between the sidewalls of the first opening is equal to or greater than half of the height of the patterned isolation layer. 如請求項17所述的顯示器件的製造方法，其中形成所述第二電極包括： 提供具有第二開口圖案的第二罩幕；以及 執行第二沉積製程，以對應於所述第二罩幕的所述第二開口圖案而在所述發光層上形成所述第二電極，其中所述第二開口圖案在所述半導體基底的所述厚度方向上暴露出所述發光層。The method for manufacturing a display device according to claim 17, wherein forming the second electrode includes: Providing a second mask with a second opening pattern; and A second deposition process is performed to form the second electrode on the light-emitting layer corresponding to the second opening pattern of the second mask, wherein the second opening pattern is formed on all the semiconductor substrates. The light-emitting layer is exposed in the thickness direction. 如請求項15所述的顯示器件的製造方法，更包括： 在所述第二電極之上形成介電包封體；以及 執行單體化製程，以切割所述半導體基底及所述介電包封體。The manufacturing method of the display device as described in claim 15 further includes: Forming a dielectric encapsulation body on the second electrode; and A singulation process is performed to cut the semiconductor substrate and the dielectric encapsulation body.
TW109124581A 2019-07-24 2020-07-21 Display device and manufacturing method thereof TWI755792B (en)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US201962877846P 2019-07-24 2019-07-24
US62/877,846 2019-07-24
US16/866,519 US11239305B2 (en) 2019-07-24 2020-05-04 Display device and manufacturing method thereof
US16/866,519 2020-05-04

Publications (2)

Publication Number Publication Date
TW202105716A true TW202105716A (en) 2021-02-01
TWI755792B TWI755792B (en) 2022-02-21

Family

ID=74098709

Family Applications (1)

Application Number Title Priority Date Filing Date
TW109124581A TWI755792B (en) 2019-07-24 2020-07-21 Display device and manufacturing method thereof

Country Status (5)

Country Link
US (2) US11239305B2 (en)
KR (1) KR102356843B1 (en)
CN (1) CN112289828A (en)
DE (1) DE102020113613A1 (en)
TW (1) TWI755792B (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI757097B (en) * 2021-02-17 2022-03-01 友達光電股份有限公司 Display panel

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11239305B2 (en) * 2019-07-24 2022-02-01 Taiwan Semiconductor Manufacturing Company, Ltd. Display device and manufacturing method thereof
KR20210063508A (en) * 2019-11-22 2021-06-02 삼성디스플레이 주식회사 Manufacturing method of display device

Family Cites Families (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4752818B2 (en) * 2007-07-06 2011-08-17 ソニー株式会社 Organic EL display device, electronic device, substrate for organic EL display device, and method for manufacturing organic EL display device
JP4506810B2 (en) * 2007-10-19 2010-07-21 ソニー株式会社 Display device
KR101182673B1 (en) 2009-05-13 2012-09-14 네오뷰코오롱 주식회사 Organic light emitting diode and manufacturing method thereof
TWI463986B (en) 2012-08-29 2014-12-11 Univ China Medical New use of lactobacillus plantarum cmu995 strain
US9444050B2 (en) 2013-01-17 2016-09-13 Kateeva, Inc. High resolution organic light-emitting diode devices, displays, and related method
US9614191B2 (en) 2013-01-17 2017-04-04 Kateeva, Inc. High resolution organic light-emitting diode devices, displays, and related methods
KR102076666B1 (en) 2013-04-11 2020-02-12 엘지디스플레이 주식회사 Flexible display panel
KR102362189B1 (en) * 2015-04-16 2022-02-11 삼성디스플레이 주식회사 Organic light emitting diode display
KR102446425B1 (en) * 2015-11-17 2022-09-23 삼성디스플레이 주식회사 Display device and method of manufacturing display device
JP2017174606A (en) * 2016-03-23 2017-09-28 株式会社ジャパンディスプレイ Organic el display device and manufacturing method for the same
KR102651136B1 (en) * 2016-04-12 2024-03-25 삼성디스플레이 주식회사 Organic light emitting diode display and method for manufacturing the same
KR102373441B1 (en) * 2017-03-31 2022-03-14 삼성디스플레이 주식회사 Display apparatus
US10818856B2 (en) * 2017-05-18 2020-10-27 Shenzhen China Star Optoelectronics Semiconductor Display Technology Co., Ltd. Method for fabricating thin film transistor, method for fabricating array substrate, and a display apparatus
CN109148592B (en) * 2017-06-27 2022-03-11 乐金显示有限公司 Thin film transistor including oxide semiconductor layer, method of manufacturing the same, and display device including the same
JP6742277B2 (en) * 2017-07-03 2020-08-19 株式会社Ｊｏｌｅｄ Display device and method of manufacturing display device
CN110911440B (en) * 2018-09-14 2020-10-16 云谷（固安）科技有限公司 Display panel, display screen and display terminal
KR20200047941A (en) * 2018-10-26 2020-05-08 삼성디스플레이 주식회사 Display apparatus and method of manufacturing the same
JP7086822B2 (en) * 2018-11-08 2022-06-20 株式会社ジャパンディスプレイ Display device and its manufacturing method
US11239305B2 (en) * 2019-07-24 2022-02-01 Taiwan Semiconductor Manufacturing Company, Ltd. Display device and manufacturing method thereof

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI757097B (en) * 2021-02-17 2022-03-01 友達光電股份有限公司 Display panel

Also Published As

Publication number Publication date
US11239305B2 (en) 2022-02-01
US11812646B2 (en) 2023-11-07
TWI755792B (en) 2022-02-21
DE102020113613A1 (en) 2021-01-28
KR102356843B1 (en) 2022-02-07
CN112289828A (en) 2021-01-29
US20220149141A1 (en) 2022-05-12
US20210028266A1 (en) 2021-01-28
KR20210013532A (en) 2021-02-04

Similar Documents

Publication Publication Date Title
TWI755792B (en) Display device and manufacturing method thereof
TWI531053B (en) Semiconductor device and method of manufacturing the same and image sensor device
TW201828442A (en) Light emitting diode display and fabricating method thereof
CN109390372B (en) Pixel structure, forming method thereof and display screen
US11329207B2 (en) Emissive display device comprising LEDs
US10879217B1 (en) Multi-color LED pixel unit and micro-LED display panel
US11362133B2 (en) Multi-color LED pixel unit and micro-LED display panel
TW202006944A (en) Integrated chip
US20150263063A1 (en) Integrated circuit process
TW201803020A (en) Method for manufacturing semiconductor device
US11329088B2 (en) Semiconductor apparatus and equipment
US11114419B2 (en) Multi-color LED pixel unit and micro-LED display panel
TWI419336B (en) Semiconductor device and method of making the same
US10930814B1 (en) Method of manufacturing multi-color light emitting pixel unit
CN111081140B (en) Display panel and manufacturing method thereof
CN111627933A (en) Active element substrate and manufacturing method thereof
US20220392952A1 (en) Multi-color led pixel unit and micro-led display panel
JP7091598B2 (en) Manufacturing method of light emitting device
CN110571358B (en) Semiconductor device and method for manufacturing the same
CN110571357B (en) Semiconductor device and method for manufacturing the same
US20240145306A1 (en) Method of manufacturing a semiconductor device
US20220375987A1 (en) Multi-color led pixel unit and micro-led display panel
CN116828891A (en) Light emitting device and method for manufacturing the same
CN117063629A (en) Display substrate, preparation method thereof and display device
JP2024002572A (en) Semiconductor device and method of manufacturing semiconductor device