CN116828891A - Light emitting device and method for manufacturing the same - Google Patents

Abstract

A light emitting device comprises a substrate, a first conductive layer arranged on the substrate, a first bump seat arranged on the first conductive layer, a second bump seat arranged on the first conductive layer and separated from the first bump seat, and a first electrode layer arranged on the first bump seat, the first conductive layer and the second bump seat, wherein the first electrode layer comprises side walls of the first bump seat and the second bump seat and a first concave part between the first bump seat and the second bump seat, and the first concave part is provided with a first side wall, a second side wall opposite to the first side wall and a bottom between the first side wall and the second side wall. The light-emitting device further comprises a first bump arranged on the first bump seat and covering at least a part of the first side wall; a second bump disposed on the second bump seat and covering at least a portion of the second sidewall; and a light emitting unit formed on the bottom of the first recess and located between the first bump and the second bump.

Description

Light emitting device and method for manufacturing the same

Technical Field

The present disclosure relates to a light emitting device and a method for manufacturing the same, and more particularly, to a light emitting device including bumps and bump seats and a method for manufacturing the same.

Background

Organic light emitting devices have been widely used in displays of the highest-end electronic devices. However, due to the limitations of the related art, the brightness of the light emitting device is limited. Accordingly, light emitting devices having higher brightness are a target of efforts for display manufacturers.

Disclosure of Invention

The light-emitting device comprises a substrate, a first conductive layer arranged on the substrate, a first bump seat arranged on the first conductive layer, a second bump seat arranged on the first conductive layer and separated from the first bump seat, and a first electrode layer arranged on the first bump seat, the first conductive layer and the second bump seat. The first electrode layer comprises a side wall of the first bump seat, a side wall of the second bump seat, a first concave part between the first bump seat and the second bump seat, wherein the first concave part is provided with a first side wall, a second side wall opposite to the first side wall and a bottom part between the first side wall and the second side wall. The light-emitting device further comprises a first bump arranged on the first bump seat and covering at least a part of the first side wall, a second bump arranged on the second bump seat and covering at least a part of the second side wall, and a light-emitting unit formed on the bottom of the first concave part and located between the first bump and the second bump.

In some embodiments, the first bump pad includes a dielectric layer disposed on the first conductive layer, a second conductive layer disposed on the dielectric layer, and a second electrode layer disposed on the second conductive layer.

In some embodiments, a radius angle is formed between a sidewall and a lower surface of the first bump holder, and the radius angle ranges from 10 degrees to 90 degrees.

In some embodiments, the light emitting device further includes a third bump holder disposed on the first conductive layer and separated from the first bump holder and the second bump holder; and a second concave part formed between the second bump seat and the third bump seat, wherein the second bump fills the second concave part.

In some embodiments, the light emitting device further comprises an etching stop layer disposed between the substrate and the first conductive layer; the second concave part extends into the first conductive layer, and the second bump is contacted with the etching stop layer.

A light emitting device comprises a first bump arranged on a first bump seat and covering at least a part of an upper surface and a side wall of the first bump seat, a second bump arranged on a second bump seat separated from the first bump seat and a third bump seat separated from the second bump seat, the second bump covering at least a part of an upper surface and a side wall of the second bump seat, the side wall of the first bump seat and the side wall of the second bump seat being arranged opposite to each other, a first electrode layer arranged between the first bump and the second bump and extending between the first bump and the side wall of the first bump seat and between the second bump and the side wall of the second bump seat; and a light emitting unit disposed on the first electrode layer between the first bump and the second bump.

In some embodiments, the light emitting device further includes a second recess disposed between the second bump seat and the third bump seat, and the second bump fills the second recess.

A method for preparing a light-emitting device comprises forming a first conductive layer on a substrate; forming a dielectric layer on the first conductive layer and forming a second conductive layer on the dielectric layer; forming a first electrode layer on the second conductive layer; patterning the first electrode layer, the second conductive layer and the dielectric layer to form a first opening exposing the first conductive layer. The method for manufacturing the light-emitting device further comprises forming a second electrode layer on the first opening and the first electrode layer to form a first concave portion co-formed with the first opening, wherein the first concave portion is provided with a first side wall, a second side wall opposite to the first side wall and a bottom located between the first side wall and the second side wall; forming a first bump on the first sidewall of the first recess; forming a second bump on the second sidewall of the first recess; forming a light emitting unit between the bottom of the first concave portion and the first bump and the second bump.

In some embodiments, the method further comprises patterning the first electrode layer, the second conductive layer, and the dielectric layer to form a second opening exposing the first conductive layer, the first opening and the second opening being separated from each other; forming the second electrode layer on the second opening; and removing the second electrode layer positioned in the second opening to expose part of the first conductive layer.

In some embodiments, the method further comprises patterning the first conductive layer exposed from the second opening to form a second recess; and forming the second bump in the second sidewall and the second recess of the first recess.

Drawings

Fig. 1 is a top view of an intermediate product of a lighting device, according to some embodiments.

Fig. 2 is a cross-sectional view of a lighting device, according to some embodiments.

Fig. 3 is a cross-sectional view of a lighting device, according to some embodiments.

Fig. 4 is a cross-sectional view of a lighting device, according to some embodiments.

Fig. 5 is a cross-sectional view of a lighting device, according to some embodiments.

Fig. 6 is a flow chart of a method of making a light emitting device according to some embodiments.

Fig. 7-22 are schematic diagrams illustrating light emitting devices at various stages of manufacture according to methods of certain embodiments of the present disclosure.

Detailed Description

The following disclosure provides many different embodiments, or examples, for implementing different features of the application. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to limit the application from that described above. For example, the following description of forming a first feature over or on a second feature may include embodiments in which first and second features are formed in direct contact, and may also include embodiments in which other features are formed between the first and second features, such that the first and second features are not in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or architectures discussed.

Furthermore, the present application may be described using the brief description of spatially relative terms such as "lower," "between," "below," "lower," "above," "higher," and the like in order to describe one element or feature's relationship to another element or feature in the figures. Spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be positioned (rotated 90 degrees or other orientations) and the spatially relative descriptors used herein interpreted accordingly.

Notwithstanding that the numerical ranges and parameters setting forth the broad scope of the disclosure are approximations, the numerical values set forth in the specific examples are reported as precisely as possible. Any numerical value, however, inherently contains certain errors necessarily resulting from the standard deviation found in their respective testing measurements. Further, as used herein, "about" generally refers to within 10%, 5%, 1%, or 0.5% of a given value or range. Alternatively, the term "about" refers to within an acceptable standard error of average value considered by one of ordinary skill in the art. Except in the operating/working examples, or where otherwise indicated, all numerical ranges, amounts, values, and ratios of materials, time periods, temperatures, operating conditions, amounts, and the like disclosed herein are to be understood as modified in all instances by the term "about. Accordingly, unless indicated to the contrary, the numerical parameters set forth in the present disclosure and claims are approximations that may vary as desired. Each numerical parameter should at least be construed in light of the number of reported significant digits and by applying ordinary rounding techniques. Ranges can be expressed herein as from one end point to another, or between two end points. Unless specifically stated otherwise, all ranges disclosed herein are inclusive of the endpoints.

Fig. 1 is a top view illustrating an intermediate product of a light emitting device 100. The light emitting device 100 has a plurality of light emitting units 350 and a cover layer 380 over the light emitting units 350. For the light emitting unit 350, the light emitting unit 350 may be disposed between the plurality of bumps 340, for example, the first recess 331 disposed between the first bump 341 and the second bump 342, and the first recess 331 provides an array of recesses for accommodating the array of light emitting units 350. In order to make the light emitting device 100 have better brightness, the second concave portion 361 is disposed under the second bump 342. In some embodiments, the plurality of second recesses 361 form an array of recesses for reflecting light emitted by the array of light emitting units 350. In some embodiments, the plurality of light emitting units 350 are separated by the plurality of bumps 340.

Fig. 2 is a cross-sectional view of a light emitting device according to aspects of certain embodiments of the present disclosure. Fig. 2 is a sectional view illustrating a line AA in fig. 1 and illustrates only this region. The cover layer 380 is omitted here for brevity. The light emitting device has a plurality of bumps 340 to define a light emitting pixel pattern. The first recess 331 is located between two adjacent bumps 340 and provides a space for accommodating a light emitting pixel.

Referring to fig. 2, the light emitting device 100 includes a substrate 110 and a first conductive layer 310 disposed on the substrate 110. In some embodiments, the substrate 110 is located under the first conductive layer 310. In some embodiments, the substrate 110 may include a transistor array configured to correspond to the light emitting unit 350. The substrate 110 may include a plurality of capacitors. In some implementations, more than one transistor is configured to form a circuit with a capacitor and a light emitting unit 350.

In some embodiments, the substrate 110 includes a substrate 111, a dielectric layer 112, and one or more circuits disposed on the substrate 111. In certain embodiments, the substrate 111 is a transparent substrate, or at least a portion of the substrate is transparent. In some embodiments, the substrate 111 is a non-flexible substrate, and the material of the substrate 111 may include glass, quartz, low Temperature Polysilicon (LTPS), or other suitable materials. In some embodiments, the substrate 111 is a flexible substrate, and the material of the substrate 111 may include transparent epoxy, polyimide, polyvinyl chloride, methyl methacrylate, or other suitable materials. The dielectric layer 112 may be optionally disposed on the substrate 110 as shown in FIG. 1. In some embodiments, the dielectric layer 112 may comprise silicon oxide, silicon nitride, silicon oxynitride, or other suitable material.

In some embodiments, the circuit may comprise a CMOS circuit, or may comprise a plurality of transistors 210 and a plurality of capacitors 220 adjacent to the transistors, wherein the transistors 210 and the capacitors 220 are formed on the dielectric layer 112. In some embodiments, the transistor 210 is a Thin Film Transistor (TFT). Each transistor 210 includes source/drain regions 212 (including at least a source region and a drain region), a channel region 213 between the source/drain regions 212, a gate electrode 214 disposed over the channel region 213, and a gate insulator 215 between the channel region 213 and the gate electrode 214. The gate electrode 214 may be made of a conductive material, such as a metal, silicide, or metal alloy. In some embodiments, the gate electrode 214 may be a composite structure that includes several different layers that are distinguishable from each other by the application of an etchant and microscopic observation. In some embodiments, the gate electrode 214 and the first metal layer of the interlayer dielectric structure 230 are formed simultaneously. An interlayer dielectric structure 230 is disposed over the circuit or transistor 210. The interlayer dielectric structure 230 may include several layers of metal wires and dielectric materials for electrical connection and insulation. The channel region 213 of the transistor 210 may be made of a semiconductor material, such as silicon or other elements selected from group IV or group III and group V. In some embodiments, the interlayer dielectric structure 230 has a thickness between about 100nm and 1000 nm. In some embodiments, the interlayer dielectric structure 230 has a thickness between about 200nm and 500 nm.

In some embodiments, the gate insulator 215 covers the channel region 213 and the source/drain regions 212 of the transistor 210, and the gate insulator 215 is disposed between adjacent capacitors 220 and the dielectric layer 112. In some embodiments, after forming the source/drain regions 212 and the channel regions 213 on the dielectric layer 112, a gate insulator 215 is formed. Source/drain regions 212 are provided on opposite sides of channel region 213 to provide carriers. In some embodiments, the capacitor 220 is disposed between the transistors 210. Each capacitor 220 includes a lower electrode 221, an upper electrode 222, and an insulating layer 223 between the upper electrode 222 and the lower electrode 221. In some embodiments, the lower electrode 221 and the metal layer of the interlayer dielectric structure 230 on the dielectric layer 112 are formed simultaneously. In some embodiments, the insulating layer 223 is formed on the transistor 210 after the metal layer is formed. In some embodiments, an insulating layer 223 is disposed over and conformal to the lower electrode 221 and the transistor 210. The upper electrode 222 is disposed on an insulating layer 223 in the interlayer dielectric structure 230. The upper electrode 222 may comprise titanium, aluminum, copper, titanium nitride, combinations thereof, or other suitable materials. In some embodiments, the upper electrode 222 and the metal layer of the interlayer dielectric structure 230 are formed simultaneously. In some embodiments, after forming the insulating layer 223, the upper electrode 222 and the metal layers of the upper electrode 222 and the interlayer dielectric structure 230 are formed.

In some embodiments, a connection structure 240 electrically connects the transistor 210 to the capacitor 220. The connection structure 240 includes a plurality of connection vias and a plurality of connection wires. The connection via may be connected to the source/drain region 212 of the transistor 210, the gate electrode 214 of the transistor 210, and the lower and/or upper electrodes 221 and 222 of the capacitor 220 to connect to the connection line, and form an integrated circuit on the substrate 111. The connection structure 240 may include some connection vias 241, one end of which is connected to the drain region 212 of the transistor 210. The connection structure 240 may include some connection vias 242, one end of which is connected to the source region 212 of the transistor 210. The connection structure 240 may include some connection paths 243, one end of which is connected to the lower electrode 221 of the capacitor 220. The connection structure 240 may include some connection lines 244, one ends of which are respectively connected to the connection paths 241. The connection structure 240 may include some connection lines (not shown) having one ends connected to the connection passages 242 only, respectively. The connection structure 240 may further include some connection wires 245, one end of which is connected to the connection passages 242 and 243. In some embodiments, the connection line is formed at the same time as the metal layer (e.g., the third metal layer) of the interlayer dielectric structure 230 is formed. The connection structure 240 is electrically connected to a conductive plug 246. In some embodiments, the conductive plugs 246 electrically connect the connection lines 244 and/or the connection vias 241.

The data line (not shown) is disposed above the connection line of the connection structure 240 to be electrically connected to the source/drain region 212.

In the light emitting device 100, the first conductive layer 310 is disposed above the interlayer dielectric structure 230 and the connection structure 240, wherein a portion of the first conductive layer 310 is electrically connected to the connection structure 240. In some embodiments, the first conductive layer 310 has a flat surface, such as the substrate 110, and is electrically connected to the transistor 210 and/or the capacitor 220 through a conductive plug 246 and the connection structure 240 (including the connection vias 242, 243 and the connection line 245). In some embodiments, the first conductive layer 310 is discontinuously disposed on the substrate 110. In some embodiments, the first conductive layer 310 is disconnected by the second recess 361.

In some embodiments, the first conductive layer 310 includes Al. In some embodiments, the thickness of the first conductive layer 310 ranges from 50nm to 300nm.

In some embodiments, the etching stop layer 311 is disposed between the substrate 110 and the first conductive layer 310. In some embodiments, a portion of the etch stop layer 311 is exposed from the first conductive layer 310 to contact the second bump 341. In some embodiments, the etch stop layer 311 comprises a material having a different etch selectivity than aluminum. In some embodiments, etch stop layer 311 comprises Ti. In some embodiments, the thickness of the etch stop layer 311 ranges from 300nm to 800nm. In some embodiments, etch stop layer 311 surrounds conductive plug 246.

In some embodiments, the first bump pad 321 and the second bump pad 322 are respectively disposed on the first conductive layer 310 and separated from each other. In some embodiments, the sidewall 3212 and the lower surface of the first bump holder 321 have a radius angle σ1 therebetween, and the radius angle σ1 ranges from 10 degrees to 90 degrees. In some embodiments, the first bump holder 321 is ladder-shaped when viewed from a cross-sectional view. In some embodiments, the side wall 3212 of the first bump seat 321 is an arc surface. In some embodiments, the side wall 3212 of the first bump seat 321 is a concave arc surface.

In some embodiments, the first bump pad 321 comprises a stack of at least three different layers. In some embodiments, the first bump pad 321 includes a dielectric layer 324 disposed on the first conductive layer 310, a second conductive layer 325 disposed on the dielectric layer 324, and a second electrode layer 326 disposed on the second conductive layer 325. In some embodiments, the dielectric layer 324 comprises a dielectric material. In some embodiments, dielectric layer 324 comprises SiN. In some embodiments, the thickness of the dielectric layer 324 is less than the thickness of the first conductive layer 310, for example, having a thickness ranging from 5nm to 50nm. In some embodiments, the second conductive layer 325 includes aluminum. In some embodiments, the thickness of the second conductive layer 325 is greater than the thickness of the dielectric layer 324, for example, having a thickness in the range of 50nm to 300nm, and in some embodiments, the thickness of the first conductive layer 310 is greater than the thickness of the second conductive layer 325. In some embodiments, the second electrode layer 326 is transparent. In some embodiments, the second electrode layer 326 comprises an electrode material such as, but not limited to, indium Tin Oxide (ITO), molybdenum, or a combination of the foregoing. In some embodiments, the thickness of the second electrode layer 326 ranges from 5nm to 50nm.

In some embodiments, the first sidewall 3222 and the lower surface of the second bump seat 322 have a radius angle σ2 therebetween, and the radius angle σ2 ranges from 10 degrees to 90 degrees. In some embodiments, the second bump pad 322 is trapezoidal when viewed from a cross-sectional view. In some embodiments, the first side wall 3222 of the second bump seat 322 is an arc surface. In some embodiments, the first side wall 3222 of the second bump seat 322 is a concave arc surface. In some embodiments, the second bump pad 322 comprises a stack of at least three different layers. In some embodiments, the second bump pad 322 includes a dielectric layer 324 disposed on the first conductive layer 310, a second conductive layer 325 disposed on the dielectric layer 324, and a second electrode layer 326 disposed on the second conductive layer 325. In some embodiments, the second bump pad 322 includes the same stacking structure as the first bump pad 321. In some embodiments, the second bump pad 322 is the same height as the first bump pad 321. In some embodiments, the widths of the second bump pad 322 and the first bump pad 321 may be the same or different.

In the light emitting device 100, the first electrode layer 330 is disposed on the first bump pad 321, the second bump pad 322, and the first conductive layer 310 between the first bump pad 321 and the second bump pad 322. In some embodiments, the first electrode layer 330 is disposed on the first bump pad 321, the first conductive layer 310 and the second bump pad 322 in succession. In some embodiments, the first electrode layer 330 is in contact with the first bump pad 321, the first conductive layer 310, and the second bump pad 322. In some embodiments, the first electrode layer 330 contacts the first conductive layer 310 between the first bump pad 321 and the second bump pad 322. In some embodiments, the first electrode layer 330 contacts the sidewall 3212 and the upper surface 3211 of the first bump pad 321. In some embodiments, the first electrode layer 330 contacts the first sidewall 3222 and the upper surface 3221 of the second bump pad 322.

In some embodiments, the first electrode layer 330 is transparent. In some embodiments, the first electrode layer 330 comprises an electrode material such as, but not limited to, indium Tin Oxide (ITO), molybdenum, or a combination of the foregoing. In some embodiments, the thickness of the first electrode layer 330 ranges from 5nm to 50nm. In some embodiments, the thickness of the first electrode layer 330 and the thickness of the second electrode layer 326 may be the same or different. In some embodiments, the refractive index of the first electrode layer 330 is different from the refractive index of the second electrode layer 326. In some embodiments, the first electrode layer 330 and the second electrode layer 326 comprise electrode materials with different crystalline phases, and the brightness of the light emitting device 100 is increased by the material arrangement with different crystalline phases and different refractive indexes.

In some embodiments, the first electrode layer 330 includes a first recess 331 between the first bump pad 321 and the second bump pad 322. In some embodiments, the first recess 331 is located on the side wall 3212 of the first bump holder 321 and the first side wall 3222 of the second bump holder 322. In some embodiments, the first recess 331 has a first sidewall 332 and a second sidewall 333 opposite to the first sidewall 332, and a bottom 334 between the first sidewall 332 and the second sidewall 333. In some embodiments, the first sidewall 332 of the first recess 331 is disposed on the sidewall 3212 of the first bump seat 321, and the second sidewall 333 of the first recess 331 is disposed on the first sidewall 3222 of the second bump seat 322. In some embodiments, the bottom 334 of the first recess 331 is in contact with the first conductive layer 310.

In the light emitting device 100, a first bump 341 and a second bump 342 are respectively disposed on two opposite sidewalls 332 and 333 of the first recess 331. The first bump 341 and the second bump 342 are separated from each other. In some embodiments, the first bump holder 321 and the second bump holder 322 are used to have the bump 340 disposed thereon. In some embodiments, the first bump 341 is disposed on the first bump pad 321 and covers at least a portion of the first sidewall 332 of the first recess 331 of the first electrode layer 330. In some embodiments, the first bump 341 covers the upper surface 3211 and the side wall 3212 of the first bump holder 321. The first bump 341 and the second bump 342 have curved surfaces protruding from the substrate 110, respectively. In some embodiments, bump 340 serves as a pattern defining layer. In some embodiments, the area between the first bump 341 and the second bump 342 is configured to accommodate the light emitting unit 350. In some embodiments, the first bump 341 and/or the second bump 342 comprise a photosensitive material. In some embodiments, the first bump 341 and/or the second bump 342 comprise a light absorbing material. In some embodiments, the first bump 341 and/or the second bump 342 comprise a light-transmitting material. In some embodiments, first bump 341 and/or second bump 342 do not include fluorine. In some embodiments, the first bump 341 and the second bump 342 comprise the same material. In some embodiments, the thickness T1 of the first bump 341 (corresponding to the distance from the top surface of the first electrode layer 330 on the first bump holder 321 to the top of the first bump 341) ranges from 100nm to 500nm.

In some embodiments, the second bump 342 is disposed on the second bump holder 322 and covers at least a portion of the second sidewall 333. In some embodiments, the second bump 342 covers the upper surface 3221 and the side wall 3222 of the second bump holder 322. In some embodiments, the first electrode layer 330 is disposed between the first bump 341 and the second bump 342, and extends between the first bump 341 and the sidewall 3212 of the first bump holder 321, and extends between the second bump 342 and the first sidewall 3222 of the second bump holder 322. In some embodiments, the thickness T2 of the second bump 342 (corresponding to the distance from the top surface of the first electrode layer 330 on the second bump holder 322 to the top of the second bump 342) ranges from 100nm to 500nm.

In the light emitting device 100, the light emitting unit 350 is formed on the bottom 334 of the first recess 331 and located between the first bump 341 and the second bump 342. In some embodiments, the light emitting unit 350 is co-molded with the first recess 331. In some embodiments, the light emitting unit 350 contacts the first bump 341 and the second bump 342. In some embodiments, the upper surface of the light emitting unit 350 is higher than the upper surface 3211 of the first bump seat 321 and lower than the vertex of the first bump 341. When the upper surface of the light emitting unit 350 is lower than the top of the first bump 341, the light emitting device 100 is less prone to breaking, and is beneficial to lateral light emission of the light emitting unit 350.

In some embodiments, the light emitting unit 350 includes a carrier injection layer 351. The carrier injection layer 351 is disposed on the exposed surface of the bottom surface 334 of the first recess 331 of the first electrode layer 330. The carrier injection layer 351 is lined along the bottom surface 334. More specifically, the area between the first bump 341 and the second bump 342 is configured as the effective light emitting area of the light emitting unit 350. In some embodiments, each light emitting cell 350 has a respective carrier injection layer 351. In some embodiments, the carrier injection layer 351 is in contact with the bottom surface 334 of the first recess 331 of the first electrode layer 330. In some embodiments, the carrier injection layer 351 is in contact with the first bump 341 and the second bump 342. In some embodiments, the carrier injection layer 351 is used for hole injection or electron injection. In some embodiments, the carrier injection layer 351 includes an organic material.

In some embodiments, the light emitting unit 350 includes a carrier transport layer 352 (or first type carrier transport layer). The carrier injection layer 351 is disposed under the carrier transport layer 352. In some embodiments, carrier transport layer 352 lines carrier injection layer 351. Each light emitting cell has an individual carrier transport layer 352. In some embodiments, carrier transport layer 352 is used for hole transport or electron transport. In some embodiments, the carrier transport layer 352 is in contact with the carrier injection layer 351. In some embodiments, the carrier transport layer 352 is in contact with the first bump 341 and the second bump 342. In some embodiments, the carrier transport layer 352 comprises an organic material.

In some embodiments, the light emitting unit 350 includes an organic light Emitting (EM) layer 353. In some embodiments, the organic light emitting layer 353 covers the carrier transport layer 352. In some embodiments, the organic light emitting layer 353 lines the carrier transport layer 352. In some embodiments, the organic light emitting layer 263 is configured to emit a color, such as red, green, or blue. In some embodiments, the organic light emitting layer 263 includes an organic light emitting material.

In some embodiments, the light emitting unit 350 includes a carrier transporting layer 354 (or second type carrier transporting layer). In some embodiments, a carrier transporting layer 354 (or second type carrier transporting layer) is disposed on the organic light emitting layer 353. In some embodiments, the carrier transport layer 354 may be a hole transport layer or an electron transport layer. In some embodiments, carrier transport layer 354 and carrier transport layer 352 are each configured to be of opposite valence states. In some embodiments, the carrier transport layer 354 comprises an organic material.

In some embodiments, the light emitting unit 350 includes a second electrode 355. In some embodiments, a second electrode 355 is disposed on the organic carrier transport layer 354. In some embodiments, the second electrode 355 extends to the side surfaces of the first bump 341 and the second bump 342. The second electrode 355 may be a metal material, such as Ag, mg, or the like. In some embodiments, the second electrode 355 includes ITO or IZO (indium zinc oxide). In some embodiments, each light emitting unit 350 has an independent second electrode 355. In some embodiments, the plurality of light emitting units 350 share a common second electrode 355.

The light emitting device 100 further includes a second recess 361, and the second recess 361 and the first recess 331 are separated from each other. In some embodiments, the second concave portion 361 is used to reflect the light emitted by the light emitting unit 350 through the second concave portion 361, so as to increase the brightness of the light emitting device 100. The second recess 361 is formed between the second bump seat 322 and the third bump seat 323, and the second bump 342 fills the second recess 361. In some embodiments, the third bump pad 323 is disposed on the first conductive layer 310 and separated from the first bump pad 321 and the second bump pad 322. In some embodiments, the second bump holder 342 is located between the first bump holder 341 and the third bump holder 343.

In some embodiments, the sidewall 3232 and the lower surface of the third bump holder 322 have a radius angle σ3 therebetween, and the radius angle σ3 ranges from 10 degrees to 90 degrees. In some embodiments, the third bump pad 323 is trapezoidal when viewed from a cross-sectional view. In some embodiments, the sidewall 3232 of the third bump pad 323 is an arc surface. In some embodiments, the sidewall 3232 of the third bump pad 323 is a concave arc surface. In some embodiments, the third bump pad 323 comprises a stack of at least three different layers. In some embodiments, the third bump pad 323 includes a dielectric layer 324 disposed on the first conductive layer 310, a second conductive layer 325 disposed on the dielectric layer 324, and a second electrode layer 326 disposed on the second conductive layer 325. In some embodiments, the third bump pad 323 includes the same stacked structure as the first bump pad 321. In some embodiments, the third bump pad 323 is the same height as the first bump pad 321 or the second bump pad 322. In some embodiments, the widths of the third bump pad 323 and the first bump pad 321 or the first bump pad 322 may be the same or different.

In some embodiments, the first electrode layer 330 is disposed on the upper surface 3221 of the second bump pad 322 and the upper surface 3231 of the third bump pad 323. In some embodiments, the first electrode layer 330 is not disposed in the second recess 361. In some embodiments, the first electrode layer 330 does not contact the second sidewall 3223 of the second bump pad 322 and the sidewall 3232 of the third bump pad 323. The first side wall 3222 and the second side wall 3223 of the second bump seat 322 are respectively located at two opposite sides of the second bump seat 322. In some embodiments, the second side wall 3223 of the second bump holder 322 is an arc surface. In some embodiments, the second side wall 3223 of the second bump holder 322 is a concave arc surface.

In some embodiments, the light emitted by the light emitting unit 350 includes a lateral light, and the light enters the second recess 362 after passing through the second bump 342, and then exits the second recess 361 after being reflected by the second sidewall 3223 of the second bump seat 322 and the sidewall 3232 of the third bump seat 323. In some embodiments, a second bump seat 322 is disposed between the second recess 361 and the first recess 331. In some embodiments, a portion of the second bump 342 is further disposed between the second recess 361 and the first recess 331. In some embodiments, the distance between the second recess 361 and the first recess 331 for disposing the light emitting unit 350 is not particularly limited, as long as the second recess 361 can reflect the light emitted from the light emitting unit 350 through the second recess 361 or can increase the brightness of the light emitting device 100.

In some embodiments, the second recess 361 is deeper than the first recess 331. In some embodiments, the second recess 361 extends between the first conductive layers 310. In some embodiments, the second recess 361 is surrounded by the first electrode layer 330, the second bump pad 322, the third bump pad 323, and the first metal layer 310. In some embodiments, the bottom of the second recess 361 is the etching stop layer 311.

The second bump 342 is disposed on the second bump holder 322 and in the second recess 361. In some embodiments, the second bump 342 is disposed on the second bump holder 322 and the third bump holder 323, and in the second recess 361. In some embodiments, the second bump 342 covers at least a portion of the upper surface 3221 and the first sidewall 3222 of the second bump holder 322, and the second bump 342 also covers the second sidewall 3223 of the second bump holder 322. In some embodiments, the second bump 342 is in contact with at least a portion of the upper surface 3221 and the first side wall 3222 of the second bump holder 322, and the second bump 342 is also in contact with the second side wall 3223 of the second bump holder 322. In some embodiments, the second bump 342 is in contact with the upper surface 3231 and the sidewall 3232 of the third bump holder 323. In some embodiments, the second bump 342 penetrates into the second recess 361 and contacts the etching stop layer 311.

Fig. 3 is a cross-sectional view of a light emitting device according to aspects of certain embodiments of the present disclosure. Fig. 3 is a sectional view illustrating a line AA in fig. 1 and illustrates only this region. In some embodiments, the upper surface of the light emitting unit 350 is lower than or equal to the upper surface of the first bump holder 321. When the upper surface of the light emitting unit 350 is lower than or equal to the upper surface of the first bump holder 321, the upward light emission of the light emitting unit 350 is facilitated.

Fig. 4 is a cross-sectional view of a light emitting device according to aspects of certain embodiments of the present disclosure. Fig. 4 is a sectional view illustrating a line AA in fig. 1 and illustrates only this region. In some embodiments, the upper surface of the light emitting unit 350 is higher than the top surface of the first bump 341 and/or the top surface of the second bump 342. When the upper surface of the light emitting unit 350 is higher than the top surface of the first bump 341 and/or the top surface of the second bump 342, the lateral light emitted from the light emitting unit 350 is better to enter the second recess 361, and the light emitting device 100 is less prone to wire breakage. In some embodiments, the second electrode 355 extends to the top surfaces of the first bump 341 and the second bump 342. In some embodiments, the second electrode 355 is continuously lined along the organic current carrier transport layer 354, the first bump 341, and the second bump 342. In some embodiments, the second electrode 355 is a segment disposed only on the organic carrier transport layer 354.

Fig. 5 is a cross-sectional view of a light emitting device according to aspects of certain embodiments of the present disclosure. In some embodiments, the light emitting device 200 further includes a third conductive layer 370 disposed on the light emitting unit 350. In some embodiments, the third conductive layer 370 is disposed on the second electrode 355. In some embodiments, the third conductive layer 370 is disposed on the first bump 341, the second bump 342, and the light emitting unit 350. In some embodiments, the third conductive layer 370 is co-formed with the light emitting unit 350, the first bump 341 and the second bump 342. In some embodiments, the third conductive layer 370 comprises Ag, mg, and combinations thereof. In some embodiments, the third conductive layer 370 and the second electrode 355 include materials with different crystal phases, and the brightness of the light emitting device 200 is increased by the material arrangement with different crystal phases and different refractive indexes. In some embodiments, the third conductive layer 370 comprises a multi-layer structure, such as, but not limited to, a combination of an Ag layer (not shown) and an Mg layer (not shown). The thickness of the third conductive layer 370 ranges fromTo->。

In some embodiments, the display device 100 further includes a cover layer 380 disposed on the first bump 341, the second bump 342 and the light emitting unit 350. In some embodiments, the cover layer 380 comprises an organic material. In some embodiments, the cover 380 has a penetration rate greater than 99%.

To further illustrate the present disclosure, fig. 6 is a flow chart of a method 400 of preparing a light emitting device according to some embodiments. The method 400 of preparing a light emitting device, such as light emitting device 100, includes the steps of: 401 forming a first conductive layer on a substrate; 402 forming a dielectric layer over the first conductive layer; 403 forming a second conductive layer over the dielectric layer; 404 forming a second electrode layer on the second conductive layer; patterning 405 the second electrode layer, the second conductive layer, and the dielectric layer to form a first opening exposing the first conductive layer; 406 forming a first electrode layer over the first opening and the second electrode layer to form a first recess co-formed with the first opening, the first recess having a first sidewall and a second sidewall opposite the first sidewall, and a bottom portion between the first sidewall and the second sidewall; 407 forming a first bump on the first sidewall of the first recess; 408 forming a second bump on the second sidewall of the first recess; and 409 forming a light emitting unit at the bottom of the first concave part and between the first bump and the second bump. It should be noted that the flow chart shown in fig. 6 is for illustration purposes only and is not intended to limit the steps to a particular order. According to different embodiments, different orders of steps 401 to 409 may be arranged.

Referring to fig. 7-21, fig. 7-21 illustrate methods for preparing a light emitting device according to certain embodiments of the present disclosure. Fig. 7 to 21 are sectional views taken along line AA in fig. 1.

As shown in fig. 7, step 401 forms a first conductive layer 310 on a substrate 110. The substrate 110 may include a substrate 111, a dielectric layer 112, a transistor 210, a capacitor 220, an interlayer dielectric structure 230, a connection structure 240, a dielectric layer 310 and a planar layer 320, which are similar to those described above for the light emitting device 100, and thus are not repeated here. The first conductive layer 310 is formed on the substrate 110. In some embodiments, the first conductive layer 310 is formed on the top surface of the substrate 110 using a deposition technique such as, but not limited to, atomic layer deposition (Atomic Layer Deposition, ALD), chemical vapor deposition (Chemical Vapor Deposition, CVD), physical vapor deposition (Physical Vapor Deposition, PVD), sputtering (sputtering), electroplating (plating), laser thermal imaging (Laser Induced Thermal Imaging, LITI), inkjet printing (ink jet printing), shadow masking (shadow mask), or wet coating (wet coating). In some embodiments, the method 400 further includes forming an etch stop layer 311 between the substrate 110 and the first conductive layer 310 and forming a conductive plug 246 surrounded by the etch stop layer 311 and electrically connecting the first conductive layer 310 and the substrate 110. In some embodiments, the etch stop layer 311 is formed on the top surface of the substrate 110 using a deposition technique.

As shown in fig. 8, step 402 forms a dielectric layer 324 on the first conductive layer 310, step 403 forms a second conductive layer 325 on the dielectric layer 324, and step 404 forms a second electrode layer 326 on the second conductive layer 325. In some embodiments, the dielectric layer 324 is formed on the top surface of the first conductive layer 310 using a deposition technique. In some embodiments, the second conductive layer 325 is formed on the top surface of the dielectric layer 324 using a deposition technique. In some embodiments, the second electrode layer 326 is formed on the top surface of the second conductive layer 325 using a deposition technique. In some embodiments, forming the first bump pad 321, the second bump pad 322, and the third bump pad 323 includes forming a dielectric layer 324, a second conductive layer 325, and a second electrode layer 326 sequentially stacked on the first conductive layer 310.

As shown in fig. 9-13, step 405 patterns the second electrode layer 326, the second conductive layer 325, and the dielectric layer 324 to form a first opening 502 exposing the first conductive layer 326. In some embodiments, as shown in fig. 9, a photosensitive (photo) layer 501 is formed over the second electrode layer 326. In some embodiments, a photosensitive layer 501 is coated on the top surface of the second electrode layer 326. In some embodiments, the photosensitive layer 501 is provided by spin coating or spray coating. In some embodiments, the photosensitive layer 501 may comprise a positive photoresist or a negative photoresist. In some embodiments, the photosensitive layer 501 may include organic materials and inorganic materials. In certain embodiments, the organic material may comprise, for example, phenol formaldehyde resins, epoxy resins, ethers, amines, rubbers, acrylic resins, acrylic epoxy resins, melamine acrylates. In certain embodiments, the inorganic material may include, for example, metal oxides and silicides. In some embodiments, the photosensitive layer 501 may comprise a layer composed of a material. In some embodiments, the photosensitive layer 501 may comprise several layers of several different materials, such as an organic material layer stacked on an inorganic material layer.

In some embodiments, the photosensitive layer 501 is further patterned by an etching process, such that a portion of the photosensitive layer 501 is removed, and the remaining portion of the photosensitive layer 501 is used to locate the first bump pad 321 and the second bump pad 322 shown in fig. 2, and such that the removed portion of the photosensitive layer 501 is used to provide the light emitting unit 350 shown in fig. 2 in a subsequent step. In some embodiments, the remaining portion of the photosensitive layer 501 is further used to position the third bump pad 323 as shown in fig. 2, and the removed portion of the photosensitive layer 501 is further used to form the second recess 361 as shown in fig. 2 in a subsequent step. In some embodiments, the pattern of the photosensitive layer 501 is designed to form the first bump pads 321 and the second bump pads 322 arranged in an array.

In some embodiments, as shown in fig. 10, the first recess 502 and the second recess 503 are formed by patterning the photosensitive layer 501 by dry etching such that a portion of the photosensitive layer 501, a portion of the second electrode layer 326, and a portion of the second conductive layer 325 are removed. In some embodiments, the sidewall and the lower surface of the photosensitive layer 501 have a radius angle σ4 therebetween, and the radius angle σ4 ranges from 60 degrees to 90 degrees. In some embodiments, the first groove 502 and the second groove 503 are each U-shaped when viewed from a cross-sectional view. In some embodiments, the sidewall and the lower surface of the second conductive layer 325 have a radius angle σ5 therebetween, and the radius angle σ5 ranges from 10 degrees to 90 degrees.

In some embodiments, as shown in fig. 11, the first recess 502 and the second recess 503 are formed by patterning the photosensitive layer 501 by wet etching such that a portion of the photosensitive layer 501, a portion of the second electrode layer 326, and a portion of the second conductive layer 325 are removed. In some embodiments, an undercut (not shown) may occur when the second electrode layer 326 and the second conductive layer 325 are patterned. In some embodiments, the sidewall and the lower surface of the photosensitive layer 501 have a radius angle σ6 therebetween, and the radius angle σ6 ranges from 45 degrees to 90 degrees. In some embodiments, the radius angle σ6 ranges from 55 degrees to 80 degrees from the cross-sectional view. In some embodiments, the sidewall and the lower surface of the second conductive layer 325 have a radius angle σ7 therebetween, and the radius angle σ7 ranges from 10 degrees to 90 degrees. In some embodiments, the radius angle σ5 formed by the dry etching process is greater than the radius angle σ7 formed by the wet etching process.

In some embodiments, as shown in fig. 12, a portion of the dielectric layer 324 is further removed by an etching process, and the remaining second electrode layer 326, the second conductive layer 325 and the dielectric layer 324 form a first bump pad 321 and a second bump pad 322 that are separated from each other, and form a first opening 504 between the first bump pad 321 and the second bump pad 322. In some embodiments, a portion of the first conductive layer 310 is exposed between the first bump pad 321 and the second bump pad 322. In some embodiments, a portion of the dielectric layer 324 is removed using a dry etch process. In some embodiments, a radius angle σ1 is formed between the sidewall 3212 and the lower surface of the first bump holder 321 when viewed from a cross-sectional view, and the radius angle σ1 ranges from 10 degrees to 90 degrees. In some embodiments, a radius angle σ2 is formed between the sidewall 3222 and the lower surface of the second bump holder 322 when viewed from a cross-sectional view, and the radius angle σ2 ranges from 10 degrees to 90 degrees.

In some embodiments, the patterned second electrode layer 326, the second conductive layer 325 and the dielectric layer 324 further form a third bump pad 323 separated from the second bump pad 322, and form a second opening 505 between the second bump pad 322 and the third bump pad 323. The first opening 504 and the second opening 505 are separated from each other. In some embodiments, the first opening 504 is formed simultaneously with the second opening 505. In some embodiments, a portion of the first conductive layer 310 is exposed between the third bump pad 323 and the second bump pad 322. In some embodiments, a radius angle σ3 is formed between the sidewall 3232 and the lower surface of the third bump holder 323 when viewed from a cross-sectional view, and the radius angle σ3 ranges from 10 degrees to 90 degrees. In some embodiments, a first bump pad 321, a second bump pad 322, and a third bump pad 323 are formed on the first conductive layer 310.

In some embodiments, as shown in fig. 13, the photosensitive layer 501 is removed. In some embodiments, after removing the photosensitive layer 501, the upper surface 3211 of the first bump pad 321, the upper surface 3221 of the second bump pad 322, and the upper surface 3231 of the third bump pad 323 are exposed. In some embodiments, the first opening 504 and the second opening 505 have the same depth.

As shown in fig. 14, step 406 forms a first electrode layer 330 on the first opening 504 and the second electrode layer 326 to form a first recess 331 that is conformal to the first opening 504. The first recess 331 has a first sidewall 332, a second sidewall 333 opposite to the first sidewall 332, and a bottom 334 between the first sidewall 332 and the second sidewall 333. In some embodiments, the first electrode layer 330 is further formed on the second opening 505. In some embodiments, a conformal deposition is performed to form the first electrode layer 330 on the first opening 504, the upper surface 3211 and the side surface 3212 of the first bump pad 321, and the upper surface 3221 and the first side surface 3221 and the second side surface 3223 of the second bump pad 322.

In some embodiments, the method 400 further includes conformally depositing the first electrode layer 330 on the upper surface 3231 and the side surfaces 3232 of the second opening 505 and the third bump pad 323. In some embodiments, the first electrode layer 330 has a recess 360 formed between the second opening 505 and the third bump pad 323, and the recess 360 is conformal with the second opening 505. In some embodiments, the first electrode layer 330 is formed on the first opening 504, the second opening 505, the first bump pad 321, the second bump pad 322, and the third bump pad 323 in succession.

In some embodiments, as shown in fig. 15-17, the method 400 further includes removing the first electrode layer 330 located in the second opening 505. In some embodiments, the recess 360 of the first electrode layer 330 is removed. In some embodiments, as shown in fig. 15, a photosensitive layer 510 is formed over the first electrode layer 330, and the photosensitive layer 510 in the recess 360 is removed. In some embodiments, the photosensitive layer 510 is coated on the top surface of the first electrode layer 330 and in the first recesses 331 and 360, and the photosensitive layer 510 is patterned such that the recesses 360 of the first electrode layer 330 are exposed from the photosensitive layer 510. In some embodiments, the photosensitive layer 510 is provided by spin coating or spray coating. In some embodiments, the photosensitive layer 510 may comprise a positive photoresist or a negative photoresist. In some embodiments, the photosensitive layer 510 is patterned by an etching process such that a portion of the photosensitive layer 510 is removed, and the removed portion of the photosensitive layer 510 is used to form the second recess 361 as shown in fig. 2 in a subsequent step.

In some embodiments, as shown in fig. 16, the first electrode layer 330 exposed from the photosensitive layer 510 is removed by patterning through an etching process, thereby forming a recess 511. In some embodiments, the recess 511 is formed after patterning by wet etching to remove the recess 360 of the first electrode layer 330.

In some embodiments, as shown in fig. 17, the photosensitive layer 510 is removed, exposing the second sidewall 3223 of the second bump pad 322 and the sidewall 3232 of the third bump pad 323, and a portion of the first metal layer 310. In some embodiments, the periphery of the recess 511 includes the first electrode layer 330, the second bump pad 322, the third bump pad 323, and the first metal layer 310.

In some embodiments, as shown in fig. 18-19, the method 400 further includes patterning the first conductive layer 310 exposed from the recess 511 to form a second recess 361. In some embodiments, as shown in fig. 18, a photosensitive layer 520 is formed over the first electrode layer 330, and the photosensitive layer 520 over the first electrode layer 330 in the recess 511 is removed. In some embodiments, the photosensitive layer 520 contacts the second sidewall 3223 of the second bump pad 322 and the sidewall 3232 of the third bump pad 323. In some embodiments, the photosensitive layer 510 is coated on the top surface of the first electrode layer 330 and in the first recess 331 and the groove 511, and the photosensitive layer 520 is patterned, so that the first electrode layer 330 in the groove 511 is exposed from the photosensitive layer 520, and then the first conductive layer 310 in the groove 511 is removed. In some embodiments, the photosensitive layer 520 is provided by spin coating or spray coating. In some embodiments, the photosensitive layer 520 may include a positive photoresist or a negative photoresist.

In some embodiments, the first conductive layer 310 exposed from the recess 511 is removed by patterning by dry etching. In some embodiments, the first conductive layer 310 is patterned such that the depth of the second recess 361 is greater than the depth of the first recess 331. In some embodiments, patterning the first conductive layer 310 exposes the etch stop layer 311 from the second recess 361.

In some embodiments, as shown in fig. 19, the photosensitive layer 520 is removed to form a second recess 361. In some embodiments, after removing the photosensitive layer 520, the second sidewalls 3223 of the second bump pad 322 and the sidewalls 3232 of the third bump pad 323, a portion of the first metal layer 310, and a portion of the etching stop layer 311 are exposed.

As shown in fig. 20, step 407 forms a first bump 341 on a first sidewall 332 of the first recess 331, and step 408 forms a second bump 342 on a second sidewall 333 of the first recess 331. In some embodiments, the first bump 341 and the second bump 342 are formed simultaneously. In some embodiments, the bottom 334 of the first recess 331 is exposed between the first bump 341 and the second bump 342. In some embodiments, the second bump 342 is further formed in the second recess 361 and on the third bump 323. In some embodiments, the second bump 342 fills the second recess 361.

As shown in fig. 21, step 409 forms the light emitting unit 350 between the bottom 334 of the first recess 331 of the first electrode layer 330 and the first bump 341 and the second bump 342. In some embodiments, conformal deposition is performed to form the light emitting unit 350. In some embodiments, the light emitting unit 350 contacts the first electrode layer 330, the first bump 341 and the second bump 342. In some embodiments, a carrier injection layer 351, a carrier transport layer 352, an organic light emitting layer 353, a carrier transport layer 354, and a second electrode 355 are sequentially formed on the bottom portion 334.

Accordingly, one embodiment of the present disclosure provides a light emitting device including a substrate, a first conductive layer disposed on the substrate, a first bump pad disposed on the first conductive layer, a second bump pad disposed on the first conductive layer and separated from the first bump pad, and a first electrode layer disposed on the first bump pad, the first conductive layer and the second bump pad. The first electrode layer comprises a side wall of the first bump seat, a side wall of the second bump seat, a first concave part between the first bump seat and the second bump seat, wherein the first concave part is provided with a first side wall, a second side wall opposite to the first side wall and a bottom part between the first side wall and the second side wall. The light-emitting device further comprises a first bump arranged on the first bump seat and covering at least a part of the first side wall, a second bump arranged on the second bump seat and covering at least a part of the second side wall, and a light-emitting unit formed on the bottom of the first concave part and located between the first bump and the second bump.

One embodiment of the present disclosure provides a light emitting device including a first bump disposed on a first bump holder and covering at least a portion of an upper surface and a sidewall of the first bump holder, a second bump disposed on a second bump holder separated from the first bump holder and a third bump holder separated from the second bump holder, the second bump covering at least a portion of an upper surface and a sidewall of the second bump holder, the sidewall of the first bump holder being disposed opposite to the sidewall of the second bump holder, a first electrode layer disposed between the first bump and the second bump and extending between the first bump and the sidewall of the first bump holder, and extending between the second bump and the sidewall of the second bump holder; and a light emitting unit disposed on the first electrode layer between the first bump and the second bump.

One embodiment of the present disclosure provides a method of manufacturing a light emitting device, comprising forming a first conductive layer on a substrate; forming a dielectric layer on the first conductive layer and forming a second conductive layer on the dielectric layer; forming a first electrode layer on the second conductive layer; patterning the first electrode layer, the second conductive layer and the dielectric layer to form a first opening exposing the first conductive layer. The method for manufacturing the light-emitting device further comprises forming a second electrode layer on the first opening and the first electrode layer to form a first concave portion co-formed with the first opening, wherein the first concave portion is provided with a first side wall, a second side wall opposite to the first side wall and a bottom located between the first side wall and the second side wall; forming a first bump on the first sidewall of the first recess; forming a second bump on the second sidewall of the first recess; forming a light emitting unit between the bottom of the first concave portion and the first bump and the second bump.

The foregoing outlines features of some embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments described herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.

Claims (10)

1. A light emitting device, comprising:

a substrate;

a first conductive layer disposed on the substrate;

a first bump seat disposed on the first conductive layer;

a second bump seat arranged on the first conductive layer and separated from the first bump seat;

the first electrode layer is arranged on the first bump seat, the first conductive layer and the second bump seat, and comprises a side wall of the first bump seat, a side wall of the second bump seat and a first concave part between the first bump seat and the second bump seat, wherein the first concave part is provided with a first side wall, a second side wall opposite to the first side wall and a bottom part between the first side wall and the second side wall;

A first bump disposed on the first bump seat and covering at least a portion of the first sidewall;

a second bump disposed on the second bump seat and covering at least a portion of the second sidewall; a kind of electronic device with high-pressure air-conditioning system

A light emitting unit is formed on the bottom of the first concave portion and is located between the first bump and the second bump.

2. The light emitting device of claim 1, wherein the first bump pad comprises a dielectric layer disposed on the first conductive layer, a second conductive layer disposed on the dielectric layer, and a second electrode layer disposed on the second conductive layer.

3. The light-emitting device according to claim 1, wherein a radius angle is formed between a sidewall and a lower surface of the first bump holder, and the radius angle ranges from 10 degrees to 90 degrees.

4. The light emitting device of claim 1, further comprising:

a third bump seat disposed on the first conductive layer and separated from the first bump seat and the second bump seat; a kind of electronic device with high-pressure air-conditioning system

And a second concave part formed between the second bump seat and the third bump seat, wherein the second bump fills the second concave part.

5. The light emitting device of claim 4, further comprising:

an etching stop layer arranged between the substrate and the first conductive layer;

The second concave part extends into the first conductive layer, and the second bump is contacted with the etching stop layer.

6. A light emitting device, comprising:

a first bump disposed on a first bump seat and covering an upper surface of the first bump seat and at least a portion of a sidewall;

a second bump disposed on a second bump seat separated from the first bump seat and a third bump seat separated from the second bump seat, the second bump covering at least a portion of an upper surface and a sidewall of the second bump seat, the sidewall of the first bump seat being disposed opposite to the sidewall of the second bump seat; a kind of electronic device with high-pressure air-conditioning system

A first electrode layer disposed between the first bump and the second bump and extending between the first bump and the sidewall of the first bump holder and between the second bump and the sidewall of the second bump holder; a kind of electronic device with high-pressure air-conditioning system

A light-emitting unit is arranged on the first electrode layer between the first bump and the second bump.

7. The light emitting device of claim 6, further comprising:

the second concave part is arranged between the second bump seat and the third bump seat, and the second bump fills the second concave part.

8. A method of making a light emitting device, comprising:

Forming a first conductive layer on a substrate;

forming a dielectric layer on the first conductive layer;

forming a second conductive layer on the dielectric layer;

forming a first electrode layer on the second conductive layer;

patterning the first electrode layer, the second conductive layer and the dielectric layer to form a first opening exposing the first conductive layer;

forming a second electrode layer on the first opening and the first electrode layer to form a first concave part which is in a same type with the first opening, wherein the first concave part is provided with a first side wall, a second side wall opposite to the first side wall and a bottom part positioned between the first side wall and the second side wall;

forming a first bump on the first sidewall of the first recess;

forming a second bump on the second sidewall of the first recess; a kind of electronic device with high-pressure air-conditioning system

Forming a light emitting unit between the bottom of the first concave portion and the first bump and the second bump.

9. The method of making a light emitting device of claim 8, further comprising:

patterning the first electrode layer, the second conductive layer and the dielectric layer to form a second opening exposing the first conductive layer, wherein the first opening and the second opening are separated from each other;

forming the second electrode layer on the second opening; a kind of electronic device with high-pressure air-conditioning system

And removing the second electrode layer positioned in the second opening to expose part of the first conductive layer.

10. The method of making a light emitting device of claim 9, further comprising:

patterning the first conductive layer exposed from the second opening to form a second recess; a kind of electronic device with high-pressure air-conditioning system

Forming the second bump in the second sidewall and the second recess of the first recess.