TW202042317A - 半導體裝置的製備方法 - Google Patents

半導體裝置的製備方法 Download PDF

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TW202042317A
TW202042317A TW108126990A TW108126990A TW202042317A TW 202042317 A TW202042317 A TW 202042317A TW 108126990 A TW108126990 A TW 108126990A TW 108126990 A TW108126990 A TW 108126990A TW 202042317 A TW202042317 A TW 202042317A
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Taiwan
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wafer
substrate
layer
conductors
interlayer dielectric
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TW108126990A
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TWI716051B (zh
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吳珮甄
丘世仰
施江林
張慶弘
羅翊仁
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南亞科技股份有限公司
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Abstract

本揭露提供一種半導體裝置的製備方法。該製備方法包括提供一第一晶圓，該第一晶圓具有一第一基底以及複數個第一導體，該等導體配置在該第一基底上方；形成一第一互連結構，以穿經該第一基底並接觸該等導體其中之一；在該第一基底與該第一互連結構上形成一接合介電質；將一第二晶圓接合在該第一晶圓上，其中該第二晶圓具有一第二基底、一第二層間介電層以及複數個第二導體，該第二層間介電層配置在該第二基底的一第二前表面上，該等第二導體配置在該第二層間介電層內，其中該第二層間介電層接觸該接合介電質；以及形成一第二互連結構，以穿經該第二基底，並穿入該第二層間介電層，且接觸該第二導體與該第一互連結構。

Description

半導體裝置的製備方法
本申請案主張2019/05/07申請之美國正式申請案第16/404,830號的優先權及益處，該美國正式申請案之內容以全文引用之方式併入本文中。
本揭露係關於一種半導體裝置的製備方法。特別是有關於一種推疊式積體電路裝置的製備方法。
當積體電路技術持續進步，不間斷的努力尋找提升效能與密度、改善形狀因數(form factor)，並降低成本。由許多設計者所探索出來的實現如此優勢的一方法係由層疊式三維(3D)積體電路所實現。三維積體電路的一些區域係為一適合考慮的事，其係具有二或多個晶片的疊置，所述的疊置係使用不同製造流程(fabrication process)所製造，或者是經電的疊置係使用相同的製造流程所製造，以減少積體電路設備的佔用面積(footprint)。
上文之「先前技術」說明僅係提供背景技術，並未承認上文之「先前技術」說明揭示本揭露之標的，不構成本揭露之先前技術，且上文之「先前技術」之任何說明均不應作為本案之任一部分。
本揭露之一實施例提供一種半導體裝置的製備方法。該製備方法包括提供一第一晶圓，該晶圓包括一第一基底、一第一層間介電層(first inter-layer dielectric (ILD) layer)以及複數個第一導體，該第一層間介電層配置在該第一基底的一第一前表面，該等第一導體配置在該第一層間介電層內；形成一第一互連結構，該互連結構穿經該第一基底並穿入該第一層間介電層，且接觸該等第一導體的其中之一；在相對該第一前表面設置的一第一後表面上以及在該第一互連結構上形成一接合介電質；在該第一晶圓上接合一第二晶圓，其中該第二晶圓包括一第二基底、一第二層間介電層以及複數個第二導體，該第二層間介電層配置在該第二基底的一第二前表面上，該等第二導體配置在該第二層間介電層內，其中該第二層間介電層接觸該接合介電質；以及形成一第二互連結構，該第二互連結構穿經該第二基底並穿入該第二層間介電層，且接觸該等第二導體其中之一以及該第一互連結構。
依據本揭露之一些實施例，該第一互連結構的形成步驟包括：形成一第一開口，該第一開口穿經該第一基底並穿入該第一層間介電層，以暴露該等第一導體其中之一；以及在該第一開口內沉積一第一金屬材料。
依據本揭露之一些實施例，該第二互連結構的形成步驟還包括：形成一第一切槽，該第一切槽穿經該第二基底、該第二層間介電層以及該接合介電質，以暴露該第一金屬材料；形成一第二切槽，該第二切槽穿經該第二基底並穿入該第二層間介電層，以暴露該等第二導體其中之一；形成一凹口，該凹口連通該第一切槽與該第二切槽；以及在該第一切槽、該第二切槽以及該凹口內沉積一第二金屬材料。
依據本揭露之一些實施例，該製備方法還包括：在沉積該第一金屬材料之前，沿著該第一後表面與該第一開口沉積一第一隔離層；移除該第一隔離層的一部份，以暴露該等第一導體其中之一；在該第二金屬材料沉積之前，沿著該第二基底的一第二後表面、該凹口、該第一切槽以及該第二切槽沉積一第二隔離層；以及移除該第二隔離層的多個部分，以暴露該等第二導體其中之一以及該第一金屬材料。
依據本揭露之一些實施例，該製備方法還包括：在該第一金屬材料沉積之前，在該第一隔離層上與該等第一導體其中之一上沉積一第一阻障層(first barrier layer)；以及在該第二金屬材料沉積之前，在該第二金屬材料上與該等第二金屬接觸點其中之一上沉積一第二阻障層(second barrier layer)。
依據本揭露之一些實施例，該製備方法還包括：執行一第一平坦化製程，以移除位在該第一隔離層上的該第一金屬材料與該第一阻障層的該等部分；以及執行一第二平坦化製程，以移除位在該第二隔離層上的該第二金屬材料與該第二阻障層的該等部分。
依據本揭露之一些實施例，該第一互連結構的形成步驟還包括：在該第一金屬材料沉積之前，形成一第二開口，該第二開口連通在該第一基底內的該第一開口；以及在該第二開口內沉積該第一金屬材料。
依據本揭露之一些實施例，該第二開口具有一大致前後一致的直徑，且該第一開口具有一直徑，其係朝向遠離該第一後表面的方向遞減，其中該第一開口的該直徑小於該第二開口的該直徑。
依據本揭露之一些實施例，該第一開口具有一中線，其係偏離該第二開口的一中線。
依據本揭露之一些實施例，該製備方法還包括：在該第二後表面上沉積一鈍化層(passivation layer)；以及形成一外部接觸點(external contact)，該外部接觸點接觸該第二互連結構。
依據本揭露之一些實施例，該製備方法還包括：在提供該第一晶圓之前，提供一載體晶圓(carrier wafer)；在該載體晶圓上形成一接合層(bonding layer)；以及在該載體晶圓上接合該第一晶圓，其中該第一層間介電層接觸該接合層。
依據本揭露之一些實施例，該製備方法還包括在將該第一晶圓接合到該載體晶圓之後，使該第一基底變薄。
依據本揭露之一些實施例，該製備方法還包括在該第二金屬材料形成之後，研磨該載體晶圓。
依據本揭露之一些實施例，該第一互連結構(first interconnect structure)包括：一平台(mesa)；以及一突出物(protrusion)，從該平台延伸並接觸該第一導體。
依據本揭露之一些實施例，該第二互連結構(second interconnect structure)包括：一基座(base)；一第一支腳(first leg)，從該基座延伸並接觸該等第二導體其中之一；以及一第二支腳(second leg)，從該基座延伸並接觸該第一互連結構。
上文已相當廣泛地概述本揭露之技術特徵及優點，俾使下文之本揭露詳細描述得以獲得較佳瞭解。構成本揭露之申請專利範圍標的之其它技術特徵及優點將描述於下文。本揭露所屬技術領域中具有通常知識者應瞭解，可相當容易地利用下文揭示之概念與特定實施例可作為修改或設計其它結構或製程而實現與本揭露相同之目的。本揭露所屬技術領域中具有通常知識者亦應瞭解，這類等效建構無法脫離後附之申請專利範圍所界定之本揭露的精神和範圍。
本揭露之以下說明伴隨併入且組成說明書之一部分的圖式，說明本揭露之實施例，然而本揭露並不受限於該實施例。此外，以下的實施例可適當整合以下實施例以完成另一實施例。
「一實施例」、「實施例」、「例示實施例」、「其他實施例」、「另一實施例」等係指本揭露所描述之實施例可包含特定特徵、結構或是特性，然而並非每一實施例必須包含該特定特徵、結構或是特性。再者，重複使用「在實施例中」一語並非必須指相同實施例，然而可為相同實施例。
為了使得本揭露可被完全理解，以下說明提供詳細的步驟與結構。顯然，本揭露的實施不會限制該技藝中的技術人士已知的特定細節。此外，已知的結構與步驟不再詳述，以免不必要地限制本揭露。本揭露的較佳實施例詳述如下。然而，除了詳細說明之外，本揭露亦可廣泛實施於其他實施例中。本揭露的範圍不限於詳細說明的內容，而是由申請專利範圍定義。
本文中使用之術語僅是為了實現描述特定實施例之目的，而非意欲限制本發明。如本文中所使用，單數形式「一(a)」、「一(an)」，及「該(the)」意欲亦包括複數形式，除非上下文中另作明確指示。將進一步理解，當術語「包括(comprises)」及/或「包括(comprising)」用於本說明書中時，該等術語規定所陳述之特徵、整數、步驟、操作、元件，及/或組件之存在，但不排除存在或增添一或更多個其他特徵、整數、步驟、操作、元件、組件，及/或上述各者之群組。
圖1為依據本揭露一些實施例的一種半導體裝置10之剖視示意圖。請參考圖1，半導體裝置10包括一第一晶圓(first wafer)20以及一第二晶圓(second wafer)30，第二晶圓30疊置(stacked)並接合(bonded)在第一晶圓20的一頂部(top)。在一些實施例中，第一晶圓20與第二晶圓30係可使用相同的製造流程(fabrication process)進行製造。舉例來說，第一晶圓20與第二晶圓30係可形成一記憶體堆疊(memory stack)。在一些實施例中，第一晶圓20與第二晶圓30係可使用不同製造流程進行製造。舉例來說，第一晶圓20與第二晶圓30其中之一係可為一記憶體堆疊，第一晶圓20與第二晶圓30其中的另一個係可為一處理器(processor)、一影像感測器(image sensor)或是一應用專用積體電路(application-specific integrated circuit，ASIC)裝置。
第一晶圓20與第二晶圓30係可使用介電質與介電質接合(dielectric-to-dielectric bonding)製程進行接合。舉例來說，第二晶圓30係以一氧化物與氧化物接合(oxide-to-oxide bonding)製程接合在第一晶圓20上。在一些實施例中，第一晶圓20的一後表面(back surface)214係可塗佈一或多個接合介電質(bonding dielectrics)44，所述接合介電質44包含氧化物，以提供一高品質接合界面(high-quality bonding interface)。在一些實施例中，第一晶圓20係可以一介電質與介電質接合製程疊置且接合在一載體晶圓(carrier wafer)42上，其中一接合層(bonding layer)40係可夾置在第一晶圓20與載體晶圓40之間，以提供一高品質接合界面。
在一些實施例中，第一晶圓20具有一第一基底210、一第一層間介電層(first inter-layer dielectric (ILD) layer)220以及複數個第一導體230，基底210具有相對後表面214設置的一前表面212，第一層間介電層220配置在前表面212上，複數個導體230配置在第一層間介電層220內。在一些實施例中，第一基底210可還包括多個不同層，其並未分開描繪，而是組合在一起，以形成不同微電子元件(microelectronic elements)，微電子元件可包括電晶體(transistors)、電阻器(resistors)、二極體(diodes)、電容器(capacitors)、電感器(inductors)、熔絲(fuses)，或其他適合元件，或是其組合。所述多個不同層係可包括高介電常數(high-k)的介電層(dielectric layers)、閘極層(gate layers)、介面層(interfacial layers)、擴散/阻障層(diffusion/barrier layers)、介電層(dielectric layers)、導電層(conductive layers)、其他適合層，或是其組合。第一基底210的多個不同層係亦可包括不同摻雜區(doped regions)、隔離特徵(isolation features)、其他特徵，或是其組合。再者，如此的微電子元件係可互相互連(interconnect)，以形成第一基底210的一部分，例如一邏輯裝置(logic device)、一記憶體裝置(memory device)、一射頻(radio frequency)裝置、一輸入/輸出(input/output)裝置、一系統整合晶片(system-on-chip)裝置、其他適合形態之裝置，或是其組合。在一些實施例中，第一層間介電層220覆蓋所述微電子元件、所述摻雜區以及所述格離特徵。
第一晶圓20還包括至少一第一互連結構(first interconnect structure)292，係穿經第一基底210並穿入第一層間介電層220，且接觸所述複數個第一導體230其中之一。在一些實施例中，第一互連結構292具有一平台(mesa)2920以及一突出物(protrusion)2922，突出物2922從平台2920延伸並接觸所述複數個第一導體230其中之一。在一些實施例中，第一互連結構292包含金屬，例如銅(copper)或鋁(aluminum)。
在一些實施例中，第一晶圓20還包括一第一隔離層(first insulating layer)270，係沿著第一後表面214延伸，並貼合到平台2920的側壁2921、2923以及突出物2922。形成第一隔離層270以避免擴散尖峰(diffusion spikes)，而所述的擴散尖峰係造成穿過第一基底210與第一互連結構292的短路(shorts)。
在一些實施例中，第一晶圓20可還包括一第一阻障層(first barrier layer)280，係夾置在第一互連結構292與第一隔離層270之間，以及夾置在第一互連結構292與第一導體230之間。在一些實施例中，第一阻障層280的作用係如一膠黏層(glue layer)。在一些實施例中，耐火金屬(refractory metals)、耐火金屬氮化物(refractory metal nitrides)、耐火金屬氮化矽(refractory metal silicon nitrides)，以及其組合，係典型地使用於第一阻障層280。在一些實施例中，第一阻障層280係可包含鈦(Ti)、氮化鈦(TiN)、鉭(Ta)、氮化鉭(TaN)、氮化矽鈦(titanium silicon nitride，TiSiN)、氮化矽鉭(tantalum silicon nitride，TaSiN)，或其類似物。
第二晶圓30具有一第二基底310、一第二層間介電層320以及複數個第二導體330，第二層間介電層320配置在第二基底310的一前表面312上，所述複數個第二導體330配置在第二層間介電層320內。在一些實施例中，第二基底310係可還包括多個不同層，其並未分開描繪，而是組合在一起，以形成如上所述的不同微電子元件、摻雜區、隔離特徵。在一些實施例中，第二層間介電層320覆蓋所述微電子元件、所述摻雜區以及所述格離特徵。
第二晶圓30還包括至少一第二互連結構392，係連接所述複數個第一導體230其中之一，以提供一外部電性連接(external electrical connection)，且所述至少一第二互連結構392亦連接所述複數個第二導體330其中之一，以提供一內部連接(internal connection)。在一些實施例中，第二互連結構392具有一基座(base)3920、一第一支腳(first leg)3922以及一第二支腳3924，第一支腳3922從基座3920延伸並接觸第二導體330，第二支腳3824從基座3920延伸並接觸第一互連結構292。在一些實施例中，基座3920、第一支腳3922以及第二支腳3924係為一體成形(integrated)，且由包含如銅或鋁之金屬的材料所形成。
第二晶圓30還包括一第二隔離層370，第二隔離層370係配置在第二基底310的前表面312上，第二隔離層370亦配置在基座3920的側壁3921上、配置在第一支腳3922的側壁3923上以及配置在第二支腳3924的側壁3925上。形成第二隔離層370以避免擴散尖峰，而所述的擴散尖峰係造成穿過第二基底310與第二互連結構392的短路(shorts)。
第二晶圓30可還包括一第二阻障層380，係配置在第二互連結構392與第二隔離層370之間以及配置在第二互連結構392與第二導體330之間。
在一些實施例中，半導體裝置10還包括一鈍化層(passivation layer)46以及至少一外部接觸點(external contact)48，鈍化層46係配置在第二隔離層370上，所述至少一外部接觸點48係配置在第二互連結構392上。鈍化層36係使用來保護第二晶圓30避免受到環境影響。
圖2為依據本揭露一些實施例的一種半導體裝置10的製備方法50之流程示意圖。圖3至圖28為依據本揭露一些實施例一半導體裝置10於所述製備方法50的各中間階段之剖視示意圖。接下來的討論中，在圖3至圖28中的各製備階段係參考圖2中的流程步驟進行討論。
請參考圖3，依據圖2中一步驟502，提供一載體晶圓42。在一些實施例中，載體晶圓42係可為一赤裸矽晶圓(bare silicon wafer)，係沒有任何電路配置在其上。在一些實施例中，載體晶圓42具有一第一表面422以及一第二表面424，第二表面424係與第一表面422相對設置。在一些實施例中，載體晶圓42具有一厚度T1，舉例來說，厚度T1係可大於750μm，例如775μm。
接下來，依據圖2中一步驟504，在第一表面422上形成一接合層40。在一些實施例中，接合層40包含氧化物，例如氧化矽。在一些實施例中，接合層40係可由一熱氧化製程(thermal oxidation process)或是一化學氣相沉積(chemical vapor deposition，CVD)製程所形成。
請參考圖4及圖5，依據圖2中一步驟506，提供接合在在體晶圓42上的一第一晶圓20。在一些實施例中，第一晶圓20係以介電質與介電質接合(dielectric-to-dielectric bonding)製程接合在載體晶圓42上，例如一氧化物融熔接合(oxide fusion bonding)製程。在一些實施例中，第一晶圓20具有一第一基底210、一第一層間介電層220以及複數個第一導體230，第一層間介電層220配置在第一基底210的一第一前表面212上，所述複數個第一導體230配置在第一層間介電層220內。在第一晶圓20與載體晶圓42接合後，第一晶圓20疊置在載體晶圓42上，且第一層間介電層220接觸接合層40。舉例來說，第一基底210可包含摻雜或未摻雜塊狀矽(doped or undoped bulk silicon)，或是一半導體上絕緣體(semiconductor-on-insulator，SOI)基底的一主動層(active layer)。在一些實施例中，第一基底210可還包括多個不同層，其並未分開描繪，而是組合在一起，以形成如上所述的不同微電子元件、摻雜區、隔離特徵。在一些實施例中，第一層間介電層220覆蓋所述微電子元件、所述摻雜區以及所述格離特徵。
請參考圖6，依據圖2中一步驟508，係可執行一薄化製程(thinning process)，以使第一晶圓20變薄。據此，係暴露一第一後表面214'。在一些實施例中，在相對前表面212設置的一初始後表面214(如圖4及圖5所示)上執行所述薄化製程，以使第一基底210變薄。在圖6中，虛線係表示第一基底210的一原始厚度(original thickness)。所述薄化製程係可使用適合的技術實現，例如一磨製製程(grinding process)、一研磨製程(polishing process)及/或一化學蝕刻製程(chemical etching process)。
請參考圖7及圖8，依據圖2中一步驟510，在一些實施例中，係形成一第一開口(first opening)240，以暴露所述複數個第一導體230其中之一。在一些實施例中，透過在第一後表面214'上塗佈一第一光阻圖案62，並執行一蝕刻製程以移除第一基底210與第一層間介電層220的一些部分來形成第一開口240。在一些實施例中，第一光阻圖案62的形成係可以在完全覆蓋第一後表面214'的一第一光阻材料上執行一曝光製程(exposure process)以及一顯影製程(develop process)所實現。在一些實施例中，係透過第一光阻圖案62暴露第一後表面214'被蝕刻的一部分。在一些實施例中，第一開口240停止在所述複數個第一導體230的其中之一。在一些實施例中，第一蝕刻製程係可利用多個蝕刻劑(etchants)來蝕刻第一基底210與第一層間介電層220，其中所述蝕刻劑係根據被蝕刻的材料來選擇。在一些實施例中，係可使用一乾蝕刻製程、一非等向性濕蝕刻製程(anisotropic wet etching process)或任何其他適合的非等向性蝕刻製程蝕刻第一基底210與第一層間介電層220。在第一蝕刻製程之後，舉例來說，係以一灰化製程(ashing process)或一濕式剝除製程(wet strip process)移除第一光阻圖案62，其中所述濕式剝除製程係可在化學上改變第一光阻圖案62，以是其不再貼合第一基底210。
請參考圖9及圖10，依據圖2中一步驟512，在一些實施例中，形成連通第一開口240的一第二開口250。在一些實施例中，透過在第一後表面214'上塗佈一第二光阻圖案64並執行一第二蝕刻製程以移除第一基底210的一部分來形成第二開口250。在一些實施例中，透過第二光阻圖案64暴露第一開口240以及第一後表面214'的一部分。在一些實施例中，第一開口240與第二開口250構成一階層孔(stepped hole)260。在一些實施例中，第一開口240具有一直徑D1，係朝向遠離第一後表面214'的方遞減。在一些實施例中，第二開口250具有一大致前後一致的直徑D2，其係大於第一開口240的直徑D1。在一些實施例中，第一開口240具有一中線242，且第二開口250具有一中線252，中線252係偏離中線242。在第二蝕刻製程之後，舉例來說，係以一灰化製程(ashing process)或一濕式剝除製程(wet strip process)移除第二光阻圖案64。
請參考圖11，依據圖2中一步驟514，一第一隔離層270係沉積在第一後表面214'上，並沉積在階層孔260內。在此結構中，第一隔離層270係覆蓋透過階層孔260暴露的第一導體230。在一些實施例中，第一隔離層270係為一大致保形層(conformal layer)。在一些實施例中，第一隔離層270包含氧化物，例如氧化矽。在一些實施例中，係可以一高密度電漿化學氣相沉積製程(high-density plasma CVD process)形成第一隔離層270。
接下來，如圖12所示，移除第一隔離層270的一部分，以暴露第一導體230。在一些實施例中，係透過例如一些蝕刻製程的一適合的製程移除第一隔離層270的所述部分。
請參考圖13，依據圖2中一步驟516，在一些實施例中，一第一阻障層280可選擇地沉積在第一隔離層270與第一導體230上。在一些實施例中，第一阻障層280係為一大致保形層(conformal layer)。在一些實施例中，第一阻障層280係可為一單層結構，其係包含耐火金屬、耐火金屬氮化物或耐火金屬氮化矽。在一些實施例中，第一阻障層280係可具有一多層結構，其係包含一或多個耐火金屬、耐火金屬氮化物或耐火金屬氮化矽。在一些實施例中，舉例來說，係可使用一物理氣相沉積(physical vapor deposition，PVD)製程或是一原子層沉積(atomic layer deposition)製程形成第一阻障層280。
請參考圖14，依據圖2中一步驟518，一第一金屬材料290沉積在第一阻障層280上。在一些實施例中，第一金屬材料290具有一厚度，其係足以填滿階層孔260。在一些實施例中，係以一鍍覆製程(plating process)形成第一金屬材料290。
請參考圖15，依據圖2中一步驟520，執行一第一平坦化製程以暴露第一隔離層270。據此，係形成一第一互連結構292。在一些實施例中，平坦化第一金屬材料290與第一阻障層280，以暴露第一隔離層270。在一些實施例中，第一平坦化製程包括一化學機械研磨(chemical mechanical polishing，CMP)製程。
請參考圖16，依據圖2中一步驟522，在一些實施例中，一接合介電質(bonding dielectric)44係沉積在第一隔離層270、第一阻障層280與第一互連結構292上。在一些實施例中，接合介電質44包含氧化物，例如氧化矽。在一些實施例中，以類似於使用來形成接合層40的方法形成接合介電質44。
請參考圖17，依據圖2中一步驟524，提供一第二晶圓30，並使用接合介電質44接合在第一晶圓20上。在一些實施例中，第二晶圓30以介電質與介電質接合製程接合在第一晶圓20上。在一些實施例中，第二晶圓30包括一第二基底310、一第二層間介電層320以及複數個第二導體330，第二層間介電層320配置在第二基底310的一第二前表面312上，所述複數個第二導體330配置在第二層間介電層320內。在第二晶圓30接合到第一晶圓20之後，第二晶圓30係疊置在第一晶圓20上，且第二層間介電層320接觸接合介電質44。
請參考圖18及圖19，依據圖2中一步驟526，在一些實施例中，形成一第一切槽(first trench)340以暴露所述複數個第二導體330其中之一，並形成一第二切槽342以暴露第一互連結構292。在一些實施例中，係使用微影技術(photolithography techniques)形成第一切槽340與第二切槽342。詳而言之，微影技術包含在第二後表面314上沉積一光阻材料66，其係依序地照射(曝光)並顯影，以移除光阻材料66的一部分。在後續的蝕刻製程期間，餘留的光阻材料66係保護下層第二基底310。執行例如反應性離子束蝕刻(reactive ion beam etch，RIE)製程的蝕刻製程，以移除第二基底310與第二層間介電層320鋪設在第二導體330與第一互連結構292其中之一的所述部分。舉例來說，之後，以一灰化製程或一濕式剝除製程移除餘留的光阻材料66。
請參考圖20及圖21，依據圖2中一步驟528，在一些實施例中，在第二基底310內形成連通第一切槽340與第二切槽342的一凹口(recess)350。在一些實施例中，舉例來說，使用微影技術形成凹口350，以沉積並圖案化在第二後表面314上的一光阻材料68，以暴露第二後表面314、第一切槽340以及第二切槽342的所述部分。係可使用例如非等向性乾蝕刻製程的一蝕刻製程，以在第二基底310內產生凹口350。舉例來說，之後係以一灰化製程或一濕式剝除製程移除光阻材料68。
請參考圖22，依據圖2中一步驟530，一大致保形第二隔離層370係沉積在第二後表面314上，並沉積在第一切槽340、第二切槽342以及凹口350內。在一些實施例中，係以類似於使用來形成第一隔離層270的方法形成第二隔離層370。
請參考圖23，係以例如一蝕刻製程的一適合的製程，移除沉積在第一互連結構292與第二導體330上的第二隔離層370的一些部分。
請參考圖24，依據圖2中一步驟532，一大致保形的第二阻障層380係可選擇地沉積在第一互連結構292、第二導體330以及第二隔離層370上。在一些實施例中，係使用類似於形成第一阻障層280的方法形成第二阻障層380。
請參考圖25，依據圖2中一步驟534，一第二金屬材料390沉積在第二阻障層380上。在一些實施例中，第二金屬材料390具有一厚度，係足以填滿第一切槽340、第二切槽342以及凹口350。在一些實施例中，係以使用類似於形成第一金屬材料290的方法形成第二金屬材料390。
請參考圖26，依據圖2中一步驟536，在一些實施例中，執行一第二平坦化製程，以暴露第二隔離層370。據此，形成一第二互連結構392。在一些實施例中，平坦化第二將屬材料390與第二阻障層380，以暴露第二隔離層370。
請參考圖27，依據圖2中一步驟538，一或多個鈍化層46係形成在第二隔離層270上，且一或多個外部接觸點48係形成在第二互連結構392上。在一些實施例中，外部接觸點48係使用來傳送第一晶圓20與第二晶圓30的輸入/輸出、接地，或電源訊號。
請參考圖28，依據圖2中一步驟540，係執行一磨覆製程(grinding process)，以使載體晶圓42變薄。據此，完整地形成半導體裝置10。在一些實施例中，薄化載體晶圓42至一厚度T2，例如小於或等於50μm。
本揭露之一實施例提供一種半導體裝置的製備方法。該製備方法包括提供一第一晶圓，該晶圓包括一第一基底、一第一層間介電層(first inter-layer dielectric (ILD) layer)以及複數個第一導體，該第一層間介電層配置在該第一基底的一第一前表面，該等第一導體配置在該第一層間介電層內；形成一第一互連結構，該互連結構穿經該第一基底並穿入該第一層間介電層，且接觸該等第一導體的其中之一；在相對該第一前表面設置的一第一後表面上以及在該第一互連結構上形成一接合介電質；在該第一晶圓上接合一第二晶圓，其中該第二晶圓包括一第二基底、一第二層間介電層以及複數個第二導體，該第二層間介電層配置在該第二基底的一第二前表面上，該等第二導體配置在該第二層間介電層內，其中該第二層間介電層接觸該接合介電質；以及形成一第二互連結構，該第二互連結構穿經該第二基底並穿入該第二層間介電層，且接觸該等第二導體其中之一以及該第一互連結構。
雖然已詳述本揭露及其優點，然而應理解可進行各種變化、取代與替代而不脫離申請專利範圍所定義之本揭露的精神與範圍。例如，可用不同的方法實施上述的許多製程，並且以其他製程或其組合替代上述的許多製程。
再者，本申請案的範圍並不受限於說明書中所述之製程、機械、製造、物質組成物、手段、方法與步驟之特定實施例。該技藝之技術人士可自本揭露的揭示內容理解可根據本揭露而使用與本文所述之對應實施例具有相同功能或是達到實質上相同結果之現存或是未來發展之製程、機械、製造、物質組成物、手段、方法、或步驟。據此，此等製程、機械、製造、物質組成物、手段、方法、或步驟係包含於本申請案之申請專利範圍內。
10:半導體裝置 20:第一晶圓 30:第二晶圓 40:接合層 42:載體晶圓 44:接合介電質 46:鈍化層 48:外部接觸點 50:製備方法 62:第一光阻圖案 64:第二光阻圖案 66:光阻材料 68:光阻材料 210:第一基底 212:前表面 214:後表面 214':後表面 220:第一層間介電層 230:第一導體 240:第一開口 242:中線 250:第二開口 252:中線 260:階層孔 270:第一隔離層 280:第一阻障層 292:第一互連結構 310:第二基底 312:前表面 314:後表面 320:第二層間介電層 330:第二導體 340:第一切槽 342:第二切槽 350:凹口 370:第二隔離層 380:第二阻障層 392:第二互連結構 422:第一表面 424:第二表面 502:步驟 504:步驟 506:步驟 508:步驟 510:步驟 512:步驟 514:步驟 516:步驟 518:步驟 520:步驟 522:步驟 524:步驟 526:步驟 528:步驟 530:步驟 532:步驟 534:步驟 536:步驟 538:步驟 540:步驟 2920:平台 2921:側壁 2922:突出物 2923:側壁 3920:基座 3921:側壁 3922:第一支腳 3923:側壁 3924:第二支腳 3925:側壁 D1:直徑 D2:直徑 T1:厚度 T2:厚度
參閱實施方式與申請專利範圍合併考量圖式時，可得以更全面了解本申請案之揭示內容，圖式中相同的元件符號係指相同的元件。 圖1為依據本揭露一些實施例的一種半導體裝置之剖視示意圖。 圖2為依據本揭露一些實施例的一種半導體裝置的製備方法之流程示意圖。 圖3至圖28為依據本揭露一些實施例一半導體裝置於製備的各中間階段之剖視示意圖。
50:製備方法
502:步驟
504:步驟
506:步驟
508:步驟
510:步驟
512:步驟
514:步驟
516:步驟
518:步驟
520:步驟
522:步驟
524:步驟
526:步驟
528:步驟
530:步驟
532:步驟
534:步驟
536:步驟
538:步驟
540:步驟

Claims (15)

  1. 一種半導體裝置的製備方法，包括： 提供一第一晶圓，該晶圓包括一第一基底、一第一層間介電層以及複數個第一導體，該第一層間介電層配置在該第一基底的一第一前表面，該等第一導體配置在該第一層間介電層內； 形成一第一互連結構，該互連結構穿經該第一基底並穿入該第一層間介電層，且接觸該等第一導體的其中之一； 在相對該第一前表面設置的一第一後表面上以及在該第一互連結構上形成一接合介電質； 在該第一晶圓上接合一第二晶圓，其中該第二晶圓包括一第二基底、一第二層間介電層以及複數個第二導體，該第二層間介電層配置在該第二基底的一第二前表面上，該等第二導體配置在該第二層間介電層內，其中該第二層間介電層接觸該接合介電質；以及 形成一第二互連結構，該第二互連結構穿經該第二基底並穿入該第二層間介電層，且接觸該等第二導體其中之一以及該第一互連結構。
  2. 如請求項1所述之製備方法，其中該第一互連結構的形成步驟包括： 形成一第一開口，該第一開口穿經該第一基底並穿入該第一層間介電層，以暴露該等第一導體其中之一；以及 在該第一開口內沉積一第一金屬材料。
  3. 如請求項2所述之製備方法，其中該第二互連結構的形成步驟還包括： 形成一第一切槽，該第一切槽穿經該第二基底、該第二層間介電層以及該接合介電質，以暴露該第一金屬材料； 形成一第二切槽，該第二切槽穿經該第二基底並穿入該第二層間介電層，以暴露該等第二導體其中之一； 形成一凹口，該凹口連通該第一切槽與該第二切槽；以及 在該第一切槽、該第二切槽以及該凹口內沉積一第二金屬材料。
  4. 如請求項3所述之製備方法，還包括： 在沉積該第一金屬材料之前，沿著該第一後表面與該第一開口沉積一第一隔離層； 移除該第一隔離層的一部份，以暴露該等第一導體其中之一； 在該第二金屬材料沉積之前，沿著該第二基底的一第二後表面、該凹口、該第一切槽以及該第二切槽沉積一第二隔離層；以及 移除該第二隔離層的多個部分，以暴露該等第二導體其中之一以及該第一金屬材料。
  5. 如請求項4所述之製備方法，還包括： 在該第一金屬材料沉積之前，在該第一隔離層上與該等第一導體其中之一上沉積一第一阻障層；以及 在該第二金屬材料沉積之前，在該第二金屬材料上與該等第二金屬接觸點其中之一上沉積一第二阻障層。
  6. 如請求項5所述之製備方法，還包括： 執行一第一平坦化製程，以移除位在該第一隔離層上的該第一金屬材料與該第一阻障層的該等部分；以及 執行一第二平坦化製程，以移除位在該第二隔離層上的該第二金屬材料與該第二阻障層的該等部分。
  7. 如請求項2所述之製備方法，其中該第一互連結構的形成步驟還包括： 在該第一金屬材料沉積之前，形成一第二開口，該第二開口連通在該第一基底內的該第一開口；以及 在該第二開口內沉積該第一金屬材料。
  8. 如請求項7所述之製備方法，其中該第二開口具有一大致前後一致的直徑，且該第一開口具有一直徑，其係朝向遠離該第一後表面的方向遞減，其中該第一開口的該直徑小於該第二開口的該直徑。
  9. 如請求項8所述之製備方法，其中該第一開口具有一中線，其係偏離該第二開口的一中線。
  10. 如請求項1所述之製備方法，還包括： 在該第二後表面上沉積一鈍化層；以及 形成一外部接觸點，該外部接觸點接觸該第二互連結構。
  11. 如請求項1所述之製備方法，還包括： 在提供該第一晶圓之前，提供一載體晶圓； 在該載體晶圓上形成一接合層；以及 在該載體晶圓上接合該第一晶圓，其中該第一層間介電層接觸該接合層。
  12. 如請求項11所述之製備方法，還包括在將該第一晶圓接合到該載體晶圓之後，使該第一基底變薄。
  13. 如請求項12所述之製備方法，還包括在該第二金屬材料形成之後，研磨該載體晶圓。
  14. 如請求項1所述之製備方法，其中該第一互連結構包括： 一平台；以及 一突出物，從該平台延伸並接觸該第一導體。
  15. 如請求項1所述之製備方法，其中該第二互連結構包括： 一基座； 一第一支腳，從該基座延伸並接觸該等第二導體其中之一；以及 一第二支腳，從該基座延伸並接觸該第一互連結構。
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