TW202036728A - Processing method of a wafer - Google Patents
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- TW202036728A TW202036728A TW108136971A TW108136971A TW202036728A TW 202036728 A TW202036728 A TW 202036728A TW 108136971 A TW108136971 A TW 108136971A TW 108136971 A TW108136971 A TW 108136971A TW 202036728 A TW202036728 A TW 202036728A
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- 238000003672 processing method Methods 0.000 title claims description 18
- 238000000034 method Methods 0.000 claims abstract description 55
- 239000000758 substrate Substances 0.000 claims abstract description 49
- 229920000728 polyester Polymers 0.000 claims abstract description 9
- 229920000098 polyolefin Polymers 0.000 claims abstract description 9
- 238000007906 compression Methods 0.000 claims abstract description 4
- 230000006835 compression Effects 0.000 claims abstract description 3
- -1 polyethylene Polymers 0.000 claims description 32
- 238000010438 heat treatment Methods 0.000 claims description 30
- 239000004698 Polyethylene Substances 0.000 claims description 12
- 229920000573 polyethylene Polymers 0.000 claims description 12
- 229920000139 polyethylene terephthalate Polymers 0.000 claims description 12
- 239000005020 polyethylene terephthalate Substances 0.000 claims description 12
- 239000004743 Polypropylene Substances 0.000 claims description 7
- 229920001155 polypropylene Polymers 0.000 claims description 7
- 239000004793 Polystyrene Substances 0.000 claims description 6
- 239000011112 polyethylene naphthalate Substances 0.000 claims description 6
- 229920003207 poly(ethylene-2,6-naphthalate) Polymers 0.000 claims description 5
- 229920002223 polystyrene Polymers 0.000 claims description 5
- 239000004642 Polyimide Substances 0.000 claims description 3
- 239000004744 fabric Substances 0.000 claims description 3
- 229920001721 polyimide Polymers 0.000 claims description 3
- 238000000926 separation method Methods 0.000 abstract description 2
- 230000015572 biosynthetic process Effects 0.000 abstract 1
- 235000012431 wafers Nutrition 0.000 description 138
- 239000000463 material Substances 0.000 description 22
- 238000003825 pressing Methods 0.000 description 12
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- 238000002844 melting Methods 0.000 description 4
- 230000008018 melting Effects 0.000 description 4
- 238000001816 cooling Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
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- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 2
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- 239000002313 adhesive film Substances 0.000 description 1
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- H—ELECTRICITY
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/67005—Apparatus not specifically provided for elsewhere
- H01L21/67011—Apparatus for manufacture or treatment
- H01L21/67132—Apparatus for placing on an insulating substrate, e.g. tape
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02002—Preparing wafers
- H01L21/02005—Preparing bulk and homogeneous wafers
- H01L21/02008—Multistep processes
- H01L21/0201—Specific process step
- H01L21/02013—Grinding, lapping
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02002—Preparing wafers
- H01L21/02005—Preparing bulk and homogeneous wafers
- H01L21/02008—Multistep processes
- H01L21/0201—Specific process step
- H01L21/02016—Backside treatment
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/185—Joining of semiconductor bodies for junction formation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/324—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/67005—Apparatus not specifically provided for elsewhere
- H01L21/67011—Apparatus for manufacture or treatment
- H01L21/67092—Apparatus for mechanical treatment
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- H01L21/67005—Apparatus not specifically provided for elsewhere
- H01L21/67011—Apparatus for manufacture or treatment
- H01L21/67098—Apparatus for thermal treatment
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- H—ELECTRICITY
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/67005—Apparatus not specifically provided for elsewhere
- H01L21/67242—Apparatus for monitoring, sorting or marking
- H01L21/67248—Temperature monitoring
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
- H01L21/6836—Wafer tapes, e.g. grinding or dicing support tapes
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
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- H—ELECTRICITY
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- H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
- H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
- H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
- H01L2221/68327—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used during dicing or grinding
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
- H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
- H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
- H01L2221/68381—Details of chemical or physical process used for separating the auxiliary support from a device or wafer
- H01L2221/68386—Separation by peeling
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Power Engineering (AREA)
- Mechanical Treatment Of Semiconductor (AREA)
- Container, Conveyance, Adherence, Positioning, Of Wafer (AREA)
- Constituent Portions Of Griding Lathes, Driving, Sensing And Control (AREA)
- Grinding Of Cylindrical And Plane Surfaces (AREA)
- Dicing (AREA)
Abstract
Description
本發明係關於對晶圓的背面進行加工之晶圓的加工方法。The present invention relates to a wafer processing method for processing the back side of the wafer.
IC、LSI等的複數裝置藉由預定分割線區劃,並形成於表面的晶圓,係藉由磨削裝置來磨削背面,加工成所定厚度之後,藉由切割裝置分割成各個裝置晶片,利用於手機、電腦等的電氣機器。Plural devices such as IC, LSI, etc. are divided by predetermined dividing lines, and the wafer formed on the surface is ground by a grinding device, and after processing to a predetermined thickness, it is divided into each device chip by a dicing device. Electrical equipment such as mobile phones and computers.
近年來,為了謀求電器設備的小型化、輕量化,晶圓有加工成較薄的50μm、30μm的傾向。為了讓被磨削成如此薄的晶圓在搬送至下個工程時不破損,本發明人提案以將聚對苯二甲酸乙二脂(PET)、玻璃等作為素材,具有可獲得剛性程度之後度的基材來支持晶圓,對晶圓的背面進行磨削的技術(例如參照專利文獻1)。 [先前技術文獻] [專利文獻]In recent years, in order to achieve the miniaturization and weight reduction of electrical equipment, wafers tend to be processed into thinner 50μm and 30μm. In order to prevent the wafer that has been ground into such a thin thickness from being damaged when being transported to the next process, the inventors proposed to use polyethylene terephthalate (PET), glass, etc. as materials to achieve a degree of rigidity. A technology that supports a wafer with a high-degree substrate and grinds the back surface of the wafer (for example, refer to Patent Document 1). [Prior Technical Literature] [Patent Literature]
[專利文獻1] 日本特開2004-296839號公報[Patent Document 1] JP 2004-296839 A
[發明所欲解決之課題][The problem to be solved by the invention]
在藉由基材支持晶圓時,採取於晶圓與基材的對合面塗布液狀樹脂、蠟等,或使用雙面膠帶來黏合的方法。但是,藉由液狀樹脂、蠟、雙面膠帶等,以基材支持晶圓的狀況中,難謂基材所致之保持力足夠,有在對晶圓的背面進行磨削時晶圓在基材上移動,導致磨削中晶圓破損的問題。尤其,於裝置的表面形成複數個稱為凸塊的突起電極的狀況中,有磨削時的應力會集中於突起電極而造成破損的問題。When the wafer is supported by the substrate, a liquid resin, wax, etc. are applied to the mating surface of the wafer and the substrate, or a double-sided tape is used for bonding. However, with liquid resin, wax, double-sided tape, etc., when the substrate is used to support the wafer, it is difficult to say that the holding force due to the substrate is sufficient. The movement on the substrate causes the problem of wafer breakage during grinding. In particular, in a situation where a plurality of protruding electrodes called bumps are formed on the surface of the device, there is a problem that the stress during grinding will concentrate on the protruding electrodes and cause damage.
進而,磨削結束,從晶圓的表面剝離基材的話,液狀樹脂、蠟、雙面膠帶的膠劑等的一部分會附著殘存於電極,有降低從晶圓分割成個別後的裝置晶片的品質的問題。Furthermore, when the grinding is completed and the substrate is peeled from the surface of the wafer, a part of the liquid resin, wax, adhesive of the double-sided tape, etc. will adhere and remain on the electrode, which may reduce the separation of the wafer into individual device chips. Quality issues.
本發明係有鑑於前述事實所發明者,其主要的技術課題係提供即使藉由基材支持晶圓,對晶圓的背面進行加工,也不會降低裝置的品質之晶圓的加工方法。 [用以解決課題之手段]The present invention is the inventor in view of the foregoing facts, and its main technical subject is to provide a wafer processing method that does not reduce the quality of the device even if the wafer is supported by a substrate and the backside of the wafer is processed. [Means to solve the problem]
為了解決前述主要技術課題,依據本發明,提供一種晶圓的加工方法,係對複數裝置藉由預定分割線區劃且形成於表面之晶圓的背面進行加工之晶圓的加工方法,其特徵為至少由以下工程所構成:晶圓配設工程,係於與晶圓同徑以上之基材的上面配設比晶圓小徑的剝離層,並且將與晶圓同徑以上的聚烯系薄片或聚酯系薄片之任一薄片,隔著該剝離層鋪設於基材的上面,並將晶圓的表面定位且配設於該薄片的上面;薄片熱壓接合工程,係將隔著該薄片配設於該基材的晶圓,在密閉環境內減壓,對該薄片進行加熱,並且按壓晶圓,隔著該薄片將晶圓熱壓接合於該基材;加工工程,係對晶圓的背面施加加工;及剝離工程,係從該薄片剝離晶圓。In order to solve the aforementioned main technical problems, according to the present invention, a wafer processing method is provided, which is a wafer processing method in which a plurality of devices are divided by a predetermined dividing line and formed on the back surface of the wafer, which is characterized by Consists of at least the following processes: Wafer placement process, in which a release layer with a smaller diameter than the wafer is placed on a substrate with the same diameter or more as the wafer, and a polyolefin sheet with the same diameter or more as the wafer Or any one of the polyester-based sheets is laid on the top of the substrate through the release layer, and the surface of the wafer is positioned and arranged on the top of the sheet; the heat-compression bonding process of the sheet will be through the sheet The wafer arranged on the substrate is reduced in pressure in a closed environment, the sheet is heated, and the wafer is pressed, and the wafer is thermocompression bonded to the substrate through the sheet; the processing process is the wafer The back side of the substrate is processed; and the peeling process is to peel the wafer from the sheet.
該剝離層可包含紙、布、晶圓片、聚醯亞胺薄片的至少任一。又,在該加工工程中,可實施對晶圓的背面進行磨削的磨削加工。The release layer may include at least any one of paper, cloth, wafer, and polyimide sheet. In addition, in this processing process, a grinding process of grinding the back surface of the wafer can be performed.
聚烯系薄片,係藉由聚乙烯薄片、聚丙烯薄片、聚苯乙烯薄片的任一所構成為佳。於該薄片熱壓接合工程中,選擇該聚乙烯薄片時的加熱溫度為120~140℃,選擇該聚丙烯薄片時的加熱溫度為160~180℃,選擇該聚苯乙烯薄片時的加熱溫度為220~240℃為佳。The polyolefin sheet is preferably composed of any one of polyethylene sheet, polypropylene sheet, and polystyrene sheet. In the sheet thermocompression bonding process, the heating temperature when selecting the polyethylene sheet is 120-140°C, the heating temperature when selecting the polypropylene sheet is 160-180°C, and the heating temperature when selecting the polystyrene sheet is 220~240℃ is better.
該聚酯系薄片,係藉由聚對苯二甲酸乙二酯薄片、聚對萘二甲酸乙二酯薄片的任一所構成為佳。於該薄片熱壓接合工程中,選擇該聚對苯二甲酸乙二酯薄片時的加熱溫度為250~270℃,選擇該聚對萘二甲酸乙二酯薄片的加熱溫度為160~180℃為佳。The polyester-based sheet is preferably composed of either a polyethylene terephthalate sheet or a polyethylene naphthalate sheet. In the sheet thermocompression bonding process, the heating temperature when selecting the polyethylene terephthalate sheet is 250-270°C, and the heating temperature when selecting the polyethylene naphthalate sheet is 160-180°C. good.
於該薄片熱壓接合工程中,以該薄片圍繞晶圓***之方式按壓晶圓為佳。 [發明的效果]In the sheet thermal compression bonding process, it is better to press the wafer in such a way that the sheet is raised around the wafer. [Effects of the invention]
本發明的晶圓的加工方法,係對複數裝置藉由預定分割線區劃且形成於表面之晶圓的背面進行加工之晶圓的加工方法,至少由在與晶圓同徑以上之基材的上面配設比晶圓小徑的剝離層,並且將與晶圓同徑以上的聚烯系薄片或聚酯系薄片之任一薄片,隔著該剝離層鋪設於基材的上面,並將晶圓的表面定位且配設於該薄片的上面的晶圓配設工程、將隔著該薄片配設於該基材的晶圓,在密閉環境內減壓,對該薄片進行加熱,並且按壓晶圓,隔著該薄片將晶圓熱壓接合於該基材的薄片熱壓接合工程、對晶圓的背面施加加工的加工工程、及從該薄片剝離晶圓的剝離工程所構成。藉此,晶圓係能以對於基材充分的保持力保持,即使對晶圓的背面施加磨削加工,晶圓也不會破損。又,即使於裝置的表面形成複數個突起電極(凸塊)的狀況中,突起電極也可藉由薄片被確實地保持,磨削時的應力被分散而消除破損的問題。進而,不使用液狀樹脂、蠟、雙面膠帶等,隔著薄片藉由熱壓接合使基材支持晶圓,故液狀樹脂、蠟、雙面膠帶的膠劑等不會附著殘存於裝置,也不會發生裝置的品質降低的問題。進而,由於將比晶圓小徑的剝離層配設於薄片與基材之間,可容易從基材剝離薄片。The wafer processing method of the present invention is a wafer processing method in which a plurality of devices are divided by a predetermined dividing line and the back surface of the wafer formed on the surface is processed. A release layer with a smaller diameter than the wafer is arranged on the upper surface, and either a polyolefin-based sheet or a polyester-based sheet with the same diameter or larger as the wafer is laid on the substrate through the release layer, and the crystal In the wafer placement process where the round surface is positioned and placed on the upper surface of the sheet, the wafer placed on the substrate via the sheet is depressurized in a closed environment, the sheet is heated, and the wafer is pressed The circle is composed of a sheet thermocompression bonding process for thermocompression bonding of the wafer to the substrate via the sheet, a processing process for applying processing to the back surface of the wafer, and a peeling process for peeling the wafer from the sheet. Thereby, the wafer system can be held with sufficient holding force for the base material, and even if the back surface of the wafer is subjected to grinding processing, the wafer will not be damaged. In addition, even in a situation where a plurality of protruding electrodes (bumps) are formed on the surface of the device, the protruding electrodes can be reliably held by the sheet, and the stress during grinding is dispersed and the problem of breakage is eliminated. Furthermore, liquid resin, wax, double-sided tape, etc. are not used, and the substrate supports the wafer by thermocompression bonding through the sheet, so the liquid resin, wax, double-sided tape adhesive, etc. will not stick to the device. , The quality of the device will not be reduced. Furthermore, since the release layer having a smaller diameter than the wafer is arranged between the sheet and the base material, the sheet can be easily peeled from the base material.
以下,針對本發明之晶圓的加工方法的實施形態,參照添附圖面詳細進行說明。Hereinafter, the embodiment of the wafer processing method of the present invention will be described in detail with reference to the attached drawings.
於圖1(a),揭示複數裝置11藉由預定分割線12區劃,形成於表面10a的晶圓10。於本實施形態中,晶圓10係其背面10b被加工。In FIG. 1(a), it is disclosed that the plurality of
執行本實施形態之晶圓的加工方法時,首先,準備前述之晶圓10、薄片14、剝離層16、基材18。薄片14係與晶圓10同徑以上的薄片,選自聚烯系薄片、或聚酯系薄片中任一,在本實施形態中,選擇聚乙烯(PE)薄片。剝離層16係比晶圓10小徑之圓形狀的薄片,選擇不具有黏著性的薄膜的素材,例如紙。基材18係對於晶圓10呈同徑以上的圓形狀,例如選擇玻璃板。再者,剝離層16並不限定於紙,選自布、晶圓片、聚醯亞胺薄片亦可。又,基材18並不限定於玻璃,從於後述的熱壓接合工程中不受到熱影響且不軟化的合成樹脂,例如聚對苯二甲酸乙二脂(PET)形成亦可。When executing the wafer processing method of this embodiment, first, the
(晶圓配設工程)
實施晶圓配設工程時,首先,將基材18載置於成為實施後述之熱壓接合工程的熱壓接合裝置30(參照圖2)之保持手段的加熱台20的工作台表面22。工作台表面22係平坦面,於加熱台20的內部,內藏有未圖示的電熱器與溫度感測器。於載置於加熱台20的表面22的基材18上配設剝離層16。配設剝離層16時,使基材18的中心與剝離層16的中心一致為佳。如上所述,基材18係相對於晶圓10形成為同徑以上,由於剝離層16形成為比晶圓10小徑,於剝離層16的外側,成為基材18露出的狀態。(Wafer placement project)
When implementing the wafer placement process, first, the
於基材18上配設剝離層16的話,進而於其上,鋪設薄片14(聚乙烯薄片)。將薄片14鋪設於基材18上時也使雙方中心一致。如上所述,剝離層16形成為比晶圓10小徑,薄片14係以相對於晶圓10同徑以上的圓形狀形成。所以,於基材18上鋪設薄片14時,於其中心區域存在剝離層16,薄片14的外周成為直接接觸基材18的外周的狀態。然後,於薄片14的上面,定位晶圓10的表面10a以背面10b露出於上方之方式配設。藉由以上內容,完成晶圓配設工程。When the
(熱壓接合工程)
前述之晶圓配設工程完成的話,接下來實施熱壓接合工程。熱壓接合工程係將隔著薄片14配設於基材18的晶圓10,在密閉環境內減壓病並對薄片14進行加熱,並且按壓晶圓10,隔著薄片14將晶圓10熱壓接合於基材18的工程。一邊參照圖2,一邊針對實施該薄片熱壓接合工程的熱壓接合裝置30的功能、作用進行說明。(Thermocompression bonding process)
When the aforementioned wafer placement process is completed, the thermocompression bonding process will be implemented next. The thermocompression bonding process is to decompress and heat the
熱壓接合裝置30係具備內藏前述之電熱器、及溫度感測器(任一皆省略圖示)的加熱台20、載置固定加熱台20的支持基台32、形成於支持基台32的吸引孔34、用以使包含加熱台20之支持基台32上的空間S成為密閉空間的密閉護蓋構件36。再者,密閉護蓋構件36係覆蓋支持基台32之上面整體的箱型構件,在揭示熱壓接合裝置30的側視圖的圖2(a)中,為了便利說明內部的構造,僅密閉護蓋構件36揭示剖面。The thermocompression bonding device 30 is provided with a heating table 20 containing the aforementioned electric heater and a temperature sensor (any of which are not shown), a supporting
於密閉護蓋36的上壁36a的中央,貫通按壓構件38的支持軸38a,形成用以進退於箭頭Z所示上下方向的開口36b。於開口36b的周圍,為了一邊使支持軸38a往上下進退,一邊將密閉護蓋構件36的空間S與外部遮斷而作為密閉環境,形成密封構造36c。於支持軸38a的下端,配設按壓板38b。按壓板38b係形成為至少比晶圓10大徑的圓盤形狀,理想是以與加熱台20同徑程度的尺寸設定。於密閉護蓋構件36的下端面,涵蓋全周適當配設彈性密封構件為佳(省略圖示)。又,於按壓構件38的上方,配設用以使按壓構件38進退於上下方向之未圖示的驅動手段。At the center of the
藉由前述之晶圓配設工程,於包含載置晶圓10之加熱台20的支持基台32上,使密閉護蓋構件36下降,將空間S設為密閉環境。此時,按壓板38b係如圖2(a)所示,抬起至不接觸晶圓10的上面的上方位置。Through the aforementioned wafer placement process, the
形成於密閉護蓋構件36的內部的空間S成為密閉環境的話,未圖示的吸引手段動作,透過吸引孔34吸引空間S的空氣,將包含晶圓10的區域減壓至接近真空的狀態為止。同時,使內藏於加熱台20之未圖示的電熱器、及溫度感測器動作,控制加熱台20的上面22的溫度。具體來說,將構成薄片14的聚乙烯薄片以成為熔融溫度附近的120~140℃之方式進行加熱。進而,使未圖示的驅動手段動作,讓按壓板38b往箭頭Z所示方向下降,以均等的力按壓晶圓10的整個上面。收容晶圓10的空間S係被減壓至接近真空的狀態為止,從晶圓10、薄片14、剝離層16及基材18的各對合面適當吸引去除空氣。然後,薄片14係藉由加熱至上述之薄片14的熔融溫度附近(120~140℃)為止,一邊軟化一邊發揮黏著性,晶圓10、薄片14、剝離層16及基材18以圖2(b)的剖面圖所示的狀態進行熱壓接合。剝離層16係選擇即使加熱也不會發揮黏著性的素材(紙),剝離層16的配設位置成為大略真空狀態,薄片14與基材18係在外周區域熱壓接合。再者,此時,藉由利用按壓板38b按壓晶圓10,如圖2(b)所示,配設於晶圓10的正下方,軟化的薄片14的外周***,形成圍繞晶圓10的外周的***部14a,更強固地固定晶圓10。如此一來,完成熱壓接合工程,形成晶圓10、薄片14、剝離層16、基材18成為一體的一體化晶圓W。When the space S formed inside the
(加工工程)
前述之熱壓接合工程完成,形成一體化晶圓W的話,則實施對晶圓10的背面進行加工的加工工程。本實施形態的加工工程,係實施磨削背面10b的磨削加工者,一邊參照圖3、圖4一邊更具體進行說明。(Processing Engineering)
When the aforementioned thermocompression bonding process is completed and the integrated wafer W is formed, a processing process of processing the back surface of the
於圖3,揭示磨削裝置50(僅揭示一部分)的吸盤台52,吸盤台52的上面係以由具有通氣性之多孔陶瓷所成的吸附盤54構成。於該吸附盤54上,將一體化晶圓W的基材18側朝下載置。於吸附盤54上載置了一體化晶圓W的話,則使連接於吸盤台52之未圖示的吸引手段動作,吸引保持一體化晶圓W。In FIG. 3, the suction table 52 of the grinding device 50 (only a part is disclosed) is disclosed. The upper surface of the suction table 52 is composed of a
如圖4所示,磨削裝置50係具備用以磨削且薄化被吸引保持於吸盤台52上的晶圓10之背面10b的磨削手段60。磨削手段60係具備藉由未圖示的旋轉驅動裝置進行旋轉的旋轉主軸62、安裝於旋轉主軸62的下端的貼片機64、安裝於貼片機64的下面的磨削輪66,於磨削輪66的下面,複數磨削砥石68配設成環狀。As shown in FIG. 4, the grinding
將一體化晶圓W吸引保持於吸盤台52上的話,一邊使磨削手段60的旋轉主軸62往圖4中箭頭R1所示方向,例如以6000rpm旋轉,一邊使吸盤台52往圖4中箭頭R2所示方向,例如以300rpm旋轉。然後,藉由未圖示的磨削水供給手段,一邊將磨削水供給至露出於一體化晶圓W的上面的晶圓10,一邊使磨削砥石68接觸晶圓10的背面10b,將支持磨削砥石68的磨削輪66,例如以1μm/秒的磨削進送速度朝向下方進行磨削進送。此時,可一邊藉由未圖示的厚度檢測裝置測定晶圓10的厚度,一邊進行磨削,將晶圓10的背面10b磨削所定量,將晶圓10設為所定厚度(例如50μm),停止磨削手段60。如此一來,完成對晶圓10的背面10b進行磨削的加工工程。如上所述,在本實施形態中,將晶圓10隔著由聚乙烯薄片所成的薄片14,藉由熱壓接合讓基材18支持。藉此發揮充分的保持力,即使對於晶圓10的背面10b實施磨削加工,晶圓10也不會移動,故可防止破損的狀況。尤其,在本實施形態中,隔著薄片14將晶圓10熱壓接合於基材18時,於薄片14的外周形成圍繞晶圓10的***部14a,藉此,可更提升保持晶圓10的保持力。進而,由於將晶圓10對於基材18,隔著薄片14進行支持,即使於裝置11的表面形成複數個突起電極的狀況中,該突起電極也可藉由薄片14被確實地保持,磨削時的應力被分散而消除突起電極破損的問題。When the integrated wafer W is sucked and held on the chuck table 52, the
(剝離工程)
上述之對晶圓10的背面10b進行加工的加工工程完成的話,從磨削裝置50搬出一體化晶圓W,搬送至用以實施圖5(a)所示之剝離工程的保持手段70。保持手段70的上面係與前述之吸盤台52同樣地,連接藉由具有通氣性的吸附盤72形成,未圖示的吸引手段。(Peeling project)
When the above-mentioned processing process of processing the
搬送至保持手段70的一體化晶圓W係將晶圓10的背面10b側朝下,將基材18朝向上方,載置於吸附盤72上。於吸附盤72載置了一體化晶圓W的話,則使未圖示的吸引手段動作,吸引保持一體化晶圓W。The integrated wafer W transferred to the holding means 70 is placed on the
於保持手段70吸引保持一體化晶圓W的話,如圖5(b)所示,在將一體化晶圓W中晶圓10殘留於吸引手段70的狀態下,剝離基材18、剝離層16、薄片14。此時,對一體化晶圓W進行加熱或冷卻為佳。薄片14係如上所述利用加熱而軟化,故即使有黏著力也會成為易從晶圓10剝離的狀態。又,利用冷卻,薄片14硬化而黏著力降低,故即使藉由進行冷卻,也會成為容易剝離的狀態。關於實施剝離工程時,應實施加熱、冷卻中任一,可考慮構成薄片14的素材及薄片14的黏著力等來選擇。再者,在圖5(b)中,揭示一體化晶圓W中,基材18、剝離層16、薄片14成為一體的狀態下剝離之狀態,但是,並不一定限定於一體性剝離,首先,僅剝離基材18,之後,將剝離層16與薄片14一起從晶圓10的表面10a剝離亦可。藉由以上內容,完成剝離工程。When the integrated wafer W is sucked and held by the holding means 70, as shown in FIG. 5(b), the
於本實施形態中,不使用液狀樹脂、蠟、雙面膠帶,透過藉由加熱以發揮黏著力的薄片14來使基材18支持晶圓10。藉此,即使從晶圓10剝離薄片14,也不會發生液狀樹脂、蠟、雙面膠帶的膠劑等附著殘存於構成突起電極的凸塊周邊的問題,不會造成裝置的品質降低。進而,在薄片14與基材18之間,由於使比晶圓10小徑的剝離層16在真空狀態下存在且僅外周進行熱壓接合,從基材18剝離薄片14的過程中空氣進入剝離層16的區域,可容易剝離被熱壓接合的薄片14,提升作業性。In this embodiment, liquid resin, wax, or double-sided tape are not used, and the
再者,在前述的實施形態中,藉由聚乙烯薄片構成薄片14,但本發明並不限定於此。作為不使用液狀樹脂、雙面膠帶、蠟等而可將晶圓10支持於基材18的薄片14,可從聚烯系薄片、聚酯系薄片中適當選擇。作為聚烯系薄片,除了前述的聚乙烯薄片之外,例如可選擇聚丙烯(PP)薄片、聚苯乙烯(PS)薄片。又,作為聚酯系薄片,例如可選擇聚對苯二甲酸乙二脂(PET)薄片、聚萘二酸乙二醇酯(PEN)薄片。In addition, in the foregoing embodiment, the
在前述的實施形態中,將熱壓接合工程中對薄片14進行加熱時的溫度,設定為聚乙烯薄片的熔點附近的溫度(120~140℃),但是,如上所述,作為薄片14選擇其他薄片所構成的狀況中,以成為所選擇之薄片的素材之熔點附近的溫度之方式進行加熱為佳。例如,以聚丙烯薄片構成薄片14時,將加熱時的溫度設定設為160~180℃,以聚苯乙烯薄片構成薄片14時,將加熱時的溫度設為220~240℃為佳。又,以聚對苯二甲酸乙二酯薄片構成薄片14時,將加熱時的溫度設定設為250~270℃,以聚對萘二甲酸乙二酯薄片構成薄片14時,將加熱時的溫度設為160~180℃為佳。再者,如上所述,以合成樹脂構成基材18時,則要求熱壓接合時不受到熱影響。因此,以聚對苯二甲酸乙二酯薄片構成薄片14時,以玻璃構成基材18為佳。In the foregoing embodiment, the temperature when the
在前述的實施形態中,以圓形狀形成剝離層16,但不一定需要作為圓形,只要比晶圓10小徑,薄片14與基材18可在外周區域接著的形狀的話,該形狀並未特別限定。In the foregoing embodiment, the
在前述的實施形態中,已針對作為對晶圓10的背面10b進行加工的加工工程,實施對晶圓10的背面10b進行磨削的磨削加工之狀況進行說明,但本發明並不限定於此,適用於實施對晶圓10的背面10b進行研磨的研磨工程者、從晶圓10的背面10b藉由切削刀實施切削加工者、實施從晶圓10的背面10b照射雷射光線的雷射加工者等。In the foregoing embodiment, the situation where the grinding process of grinding the
又,在前述的實施形態中,藉由圖2(a)所示的裝置實施熱壓接合,但本發明並不限定於此,也可實施使用具備未圖示之加熱手段的輥,一邊按壓晶圓10側的全面,一邊將薄片14加熱至所希望的溫度,隔著薄片14,熱壓接合晶圓10、及基材18的薄片熱壓接合工程。In addition, in the foregoing embodiment, the thermocompression bonding was performed by the apparatus shown in FIG. 2(a), but the present invention is not limited to this, and it may be implemented using a roller provided with a heating means not shown while pressing The entire surface of the
10:晶圓
10a:表面
10b:背面
11:裝置
12:預定分割線
14:薄片
14a:***部
16:剝離層
18:基材
20:加熱台
30:熱壓接合裝置
32:支持基台
34:吸引孔
36:密閉護蓋構件
36a:上壁
36b:開口
36c:密封構造
38:按壓構件
38a:支持軸
38b:按壓板
50:磨削裝置
52:吸盤台
54:吸附盤
60:磨削手段
62:旋轉主軸
64:貼片機
66:磨削輪
68:磨削砥石
70:保持手段10:
[圖1] 揭示晶圓配設工程之實施樣態的立體圖。 [圖2] (a)實施薄片熱壓接合工程的熱壓接合裝置的側視圖,(b)藉由薄片熱壓接合工程所形成之一體化晶圓的剖面圖。 [圖3] 揭示將一體化晶圓載置於實施加工工程之磨削裝置的吸盤台之樣態的立體圖。 [圖4] 揭示使用磨削裝置的磨削加工之實施樣態的立體圖。 [圖5] (a)揭示將一體化晶圓載置於剝離用的保持手段之樣態的立體圖,(b)揭示從晶圓剝離基材的剝離工程之實施樣態的立體圖。[Figure 1] A three-dimensional view showing the implementation of the wafer placement process. [Figure 2] (a) A side view of the thermocompression bonding device that performs the sheet thermocompression bonding process, and (b) a cross-sectional view of the integrated wafer formed by the sheet thermocompression bonding process. [Fig. 3] A perspective view showing the state where the integrated wafer is placed on the suction table of the grinding device for processing. [Fig. 4] A perspective view showing the implementation of the grinding process using the grinding device. [FIG. 5] (a) A perspective view showing an aspect of mounting the integrated wafer on a holding means for peeling, and (b) a perspective view showing an implementation aspect of the peeling process for peeling the substrate from the wafer.
10:晶圓 10: Wafer
10b:背面 10b: back
14:薄片 14: flakes
14a:***部 14a: Uplift
16:剝離層 16: peel off layer
18:基材 18: Substrate
20:加熱台 20: heating table
32:支持基台 32: Support abutment
34:吸引孔 34: Attraction hole
36:密閉護蓋構件 36: Airtight cover member
36a:上壁 36a: upper wall
36b:開口 36b: opening
36c:密封構造 36c: Sealing structure
38:按壓構件 38: pressing member
38a:支持軸 38a: Support axis
38b:按壓板 38b: Press plate
Claims (8)
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JP2018194921A JP7317482B2 (en) | 2018-10-16 | 2018-10-16 | Wafer processing method |
JP2018-194921 | 2018-10-16 |
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JP2004296839A (en) | 2003-03-27 | 2004-10-21 | Kansai Paint Co Ltd | Method for manufacturing semiconductor chip |
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JP2011029450A (en) * | 2009-07-27 | 2011-02-10 | Disco Abrasive Syst Ltd | Method of processing wafer |
US8852391B2 (en) * | 2010-06-21 | 2014-10-07 | Brewer Science Inc. | Method and apparatus for removing a reversibly mounted device wafer from a carrier substrate |
JP5762213B2 (en) * | 2011-08-15 | 2015-08-12 | 株式会社ディスコ | Grinding method for plate |
EP2657963B1 (en) * | 2012-04-24 | 2017-09-06 | Shin-Etsu Chemical Co., Ltd. | Wafer-trilayer adhesive layer-support composite, wafer support with trilayer adhesive layer for use in wafer processing, trilayer adhesive layer for use in wafer processing, method of manufacturing said composite and method of manufacturing a thin wafer using said composite |
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JP7317482B2 (en) | 2023-07-31 |
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