TW202027223A - 半導體裝置的形成方法 - Google Patents

半導體裝置的形成方法 Download PDF

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TW202027223A
TW202027223A TW108138960A TW108138960A TW202027223A TW 202027223 A TW202027223 A TW 202027223A TW 108138960 A TW108138960 A TW 108138960A TW 108138960 A TW108138960 A TW 108138960A TW 202027223 A TW202027223 A TW 202027223A
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Taiwan
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layer
contact
air gap
source
cavity
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TW108138960A
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English (en)
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世海 楊
李凱璿
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台灣積體電路製造股份有限公司
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Abstract

裝置的形成方法包括：提供第一電晶體，其包含第一閘極結構以及與第一閘極結構相鄰的源極/汲極結構。沿著位於源極/汲極結構上的接點開口的側壁表面形成空洞。在形成空洞之後，沉積犧牲層於空洞中包含的接點開口之側壁表面與下表面上，其中犧牲層填入空洞。沿著接點開口的下表面移除犧牲層的第一部份，以露出源極/汲極結構的一部份。形成金屬插塞於露出的源極/汲極結構的部份上。移除犧牲層的保留部份，以形成氣隙於金屬插塞與第一閘極結構之間。之後沉積密封層於氣隙上，以形成氣隙間隔物。

Description

半導體裝置的形成方法
本發明實施例一般關於半導體裝置與其製作方法，更特別關於形成氣隙於源極/汲極接點結構與周圍的金屬閘極之間。
電子產業已經歷對更小且更快的半導體裝置的需求持續增加，且半導體裝置支援的大量複雜功能同時增加。綜上所述，半導體產業的持續趨勢為形成低成本、高效能、與低能耗的積體電路。這些目標的主要達成方法為縮小半導體積體電路的尺寸(比如最小結構尺寸)，進而改善產能並降低相關成本。然而尺寸縮小亦增加半導體形成製程的複雜度。為了實現半導體積體電路與裝置中的持續進展，半導體的形成製程與技術亦需類似進展。
舉例來說，隨著裝置尺寸縮小，內連線如源極/汲極接點插塞與附近的閘極之間的耦合電容增加。耦合電容增加會劣化裝置效能。為了降低耦合電容，可在源極/汲極結構與附近的閘極之間採用較低介電常數的絕緣材料如低介電常數的介電層與氣隙。然而這些材料經證明為難以製作。在一些例子中，低介電常數的介電材料硬脆、不穩定、且難以沉積，其對蝕刻、退火、與研磨等製程敏感，且難以控制氣隙形成。
因此現有技術仍未完全符合所有方面的需求。
本發明一實施例提供之半導體裝置的形成方法，包括：提供第一電晶體，其包含第一閘極結構以及與第一閘極結構相鄰的源極/汲極結構；沿著位於源極/汲極結構上的接點開口的側壁表面形成空洞；在形成空洞之後，沉積犧牲層於空洞中包含的接點開口之側壁表面與下表面上，其中犧牲層填入空洞；沿著接點開口的下表面移除犧牲層的第一部份，以露出源極/汲極結構的一部份；形成接點結構於露出的源極/汲極結構的部份上；移除犧牲層的保留部份，以形成氣隙於接點結構與第一閘極結構之間；以及沉積密封層於氣隙上，以形成氣隙間隔物。
本發明一實施例提供之半導體裝置的形成方法，包括：提供第一電晶體，其包括第一閘極結構；第二電晶體，其包括第二閘極結構；源極/汲極結構，位於第一閘極結構與第二閘極結構之間並與第一閘極結構與第二閘極結構的每一者相鄰；以及接點開口，位於源極/汲極結構上；形成第一空洞於接點開口的第一側壁表面上，以及第二開口於接點開口的第二側壁表面上；沿著第一空洞與第二空洞中包含的第一側壁表面與第二側壁表面沉積犧牲層；形成接點結構於源極/汲極結構上，其中接點結構位於沿著第一側壁表面的犧牲層與沿著第二側壁表面的犧牲層之間；在形成接點結構之後，自第一側壁表面與第二側壁表面移除犧牲層，以形成位於接點結構與第一閘極結構之間的第一氣隙與位於接點結構與第二閘極結構之間的第二氣隙；以及沉積密封層於第一氣隙與第二氣隙上，以形成與接點結構相鄰的多個氣隙間隔物。
本發明一實施例提供之半導體裝置，包括：閘極結構，以及與閘極結構相鄰的源極/汲極結構；接點結構，位於源極/汲極結構上並與閘極結構相鄰；以及氣隙間隔物，包括密封層形成於空洞上，其中氣隙間隔物位於接點結構與閘極結構之間，且其中空洞包括弧形側壁輪廓。
下述內容提供的不同實施例或實例可實施本發明的不同結構。下述特定構件、與配置的實施例係用以簡化本發明內容而非侷限本發明。舉例來說，形成第一構件於第二構件上的敘述包含兩者直接接觸的實施例，或兩者之間隔有其他額外構件而非直接接觸的實施例。另一方面，本發明之多個實例可重複採用相同標號以求簡潔，但多種實施例及/或設置中具有相同標號的元件並不必然具有相同的對應關係。此外，可由不同比例任意繪示多種結構，使圖式簡化與清楚。
此外，空間性的相對用語如「下方」、「其下」、「較下方」、「上方」、「較上方」、或類似用語可用於簡化說明某一元件與另一元件在圖示中的相對關係。空間性的相對用語可延伸至以其他方向使用之元件，而非侷限於圖示方向。舉例來說，若圖式中的裝置翻轉，則位於其他元件下方或之下的元件，將轉為位於其他元件上方或之上。因此例示性的用語「下方」可包含上方與下方的方向。元件亦可轉動90°或其他角度，因此方向性用語僅用以說明圖示中的方向。
本發明實施例一般關於半導體裝置與其製作方法，更特別關於形成氣隙於源極/汲極接點結構與周圍的金屬閘極之間。在一些例子中，源極/汲極接點結構的上視形狀為圓形、卵形、或矩形。為了說明，源極/汲極接點結構可視作接點結構、接點插塞、金屬插塞、通孔、通孔插塞、或金屬接點。隨著鰭狀場效電晶體技術朝向更小的技術節點，鰭狀物間距減少對金屬閘極與連接至源極/汲極結構(如磊晶的源極/汲極結構)的相鄰接點插塞之間所用的材料造成明顯限制。為了使金屬閘極與接點插塞之間的耦合電容最小化，氣隙有助於降低耦合電容，因為空氣的介電常數(等於1)小於其他介電材料的介電常數。然而在形成接點插塞之前即形成氣隙的話，後續形成接點插塞的方法易於損傷氣隙。舉例來說，在形成接點插塞時若未完全對準圖案化接點插塞所用的遮罩與下方的層狀物構件，則可能發生層疊偏移。層疊偏移可能使接點孔的位置非常靠近(若未接觸)相鄰的金屬閘極。在此例中，蝕刻接點孔或露出已密封的氣隙，而露出的氣隙會部份或完全填有氮化物襯墊層，其形成於蝕刻接點孔之後。氣隙因此喪失其降低耦合電容的目的。
本發明實施例比習知技術提供更多優點，但應理解其他實施例可提供不同優點，此處不必說明所有優點，且所有實施例不需具有特定優點。舉例來說，此處所述的實施例可在形成接點插塞之後形成氣隙(而非在形成接點插塞之前或同時形成氣隙)，以緩解現有方法的多種缺點。舉例來說，可選擇性移除虛置結構以形成氣隙，且虛置結構與接點插塞相鄰。藉由虛置結構材料與直接接觸虛置結構的其他材料之間的蝕刻選擇性，可實施選擇性移除虛置結構。此外，此處接露在接點插塞後形成氣隙的方法提供自對準的氣隙，因為氣隙位置取決於虛置結構的位置。在至少一些之前的實施方式中，與接點插塞相鄰的氣隙在不縮小接點金屬尺寸(如鈷 接點金屬尺寸）的情況下，提供***額外犧牲層所用的有限空間。在此例中，可減少裝置的有效電容，但會增加有效電阻。在本發明一些實施例中，可採用聚合物蓋乾蝕刻方法(與源極/汲極乾蝕刻促使近接法類似)形成大幅促進的接點氣隙間隔物，以形成較大的氣隙間隔物(比如較大體積的氣隙)並增加接點金屬的關鍵尺寸(比如鈷接點金屬的關鍵尺寸)，即同時改善電容與電阻。如此一來，可有效降低金屬堆疊與接點插塞之間的耦合電容。一般而言，此處提供的多種實施例改善有效電容與有效電阻，移除金屬閘極至源極/汲極接點的金屬短路風險、並提供可控制的氣隙體積及改良的氣隙密封。本發明實施例的額外細節將提供如下，且本技術領域中具有通常知識者由本發明實施例可輕易思及額外優點及/或其他優點。
圖1係一些實施例中，形成含有接點氣隙的裝置200所用的方法100之流程圖。方法100將搭配圖2至14詳述於下，其顯示製作的多種階段之裝置200的剖視圖。應理解的是在方法100之前、之中、與之後可實施額外步驟，且方法100的多種實施例可置換或省略一些所述的製程步驟。可以理解的式，方法100的部份可為已知的互補式金氧半技術製程流程，而此處僅簡述一些製程。
在一些實施例中，裝置200可為或包含鰭狀場效電晶體裝置，其可包含於微處理器、記憶體單元、及/或其他積體電路裝置中。裝置200可為製作下述晶片時的中間裝置：積體電路晶片、單晶片系統、或其他種類的晶片或其部份，其可包含多種被動與主動的半導體裝置如電阻、電容、電感、二極體、p型電晶體、n型電晶體、金氧半電晶體、互補式金氧半電晶體、雙極電晶體、高電壓或低電壓電晶體、高頻電晶體、應變的半導體裝置、絕緣層上矽裝置、部份空乏的絕緣層上矽裝置、完全空乏的絕緣層上矽裝置、其他合適裝置或構件、或上述之組合。本技術領域中具有通常知識者應理解半導體裝置或構件的其他實施例可得利於本發明實施例。此外，在後段製程時形成的內連線可連接多個半導體電路及/或裝置。亦應注意的是，已簡化圖2至14使圖式清楚，以利理解本發明實施例的發明概念。可添加額外結構至裝置200，且裝置200的其他實施例可置換、調整、或省略一些所述結構。
方法100一開始的步驟1020提供裝置200，其包括閘極堆疊與源極/汲極結構。如圖2所示的一實施例中，步驟1020提供裝置200，其中裝置200包括基板102、源極/汲極結構106、層間介電層110、閘極間隔物112、閘極堆疊116a與116b、接點蝕刻停止層118、與硬遮罩層120。
基板102可包含半導體基板如矽基板。基板102可包含多種層狀物，包含導電或絕緣層形成於半導體基板上。基板102可包含多種摻雜設置，端視本技術領域已知的設計需求而定。基板102亦可包含其他半導體如鍺、碳化矽、矽鍺、或鑽石。在其他實施例中，基板102可包含半導體化合物及/或半導體合金。此外，一些實施例中的基板102可包含磊晶層，可具有應力以增進效能、可包含絕緣層上矽結構、及/或可具有其他合適的增進結構。
在裝置200包含鰭狀場效電晶體裝置的例子中，基板102可包含一或多個自基板102延伸的鰭狀物單元。一或多個鰭狀物單元與基板102類似，可包含矽或另一半導體元素如鍺；半導體化合物如碳化矽、砷化鎵、磷化鎵、磷化銦、砷化銦、及/或銻化銦；半導體合金如矽鍺、磷砷化鎵、砷化鋁銦、砷化鋁鎵、砷化鎵銦、磷化鎵銦、磷砷化鎵銦、或上述之組合。
在多種實施例中，源極/汲極結構106位於基板102中，且可包含n型摻雜係以用於n型場效電晶體、p型摻雜的矽鍺以用於p型場效電晶體、或其他合適材料。源極/汲極結構106的形成方法可為蝕刻開口在與閘極間隔物112相鄰的主動區中，接著磊晶成長半導體材料於開口中。可原位摻雜或異位摻雜磊晶成長的半導體材料。源極/汲極結構106可具有任何合適形狀，且可完全或部份埋置於基板102中。舉例來說，磊晶的源極/汲極結構106可高於、等高、或低於基板102的上表面，端視磊晶成長量而定。在裝置200含有鰭狀場效電晶體裝置的實施例中，源極/汲極結構106可***高於鰭狀物的上表面、與鰭狀物的上表面等高、或維持低於鰭狀物的上表面，端視磊晶成長的量而定。
閘極堆疊116a與116b可各自包含閘極介電層，以及形成於閘極介電層上的金屬層。在一些實施例中，閘極介電層可包含界面層形成於裝置200之閘極堆疊116a與116b之下的通道區上，以及高介電常數的介電層形成於界面層上。界面層可包含介電材料如氧化矽或氮氧化矽。高介電常數的介電層可包含氧化鉿、氧化鈦、氧化鉿鋯、氧化鉭、氧化鉿矽、氧化鋯、氧化鋯矽、上述之組合、或其他合適材料。在其他實施例中，閘極介電層可包含氧化矽或另一合適介電層。閘極介電層的形成方法可為化學氧化、熱氧化、原子層沉積、物理氣相沉積、化學氣相沉積、及/或其他合適方法。金屬層形成於閘極介電層上，且金屬層可包含導電層如鎢、氮化鈦、氮化鉭、氮化鎢、錸、銥、釕、鉬、鋁、銅、鈷、鎳、上述之組合、及/或其他合適組成。在一些實施例中，金屬層可包含第一組金屬材料以用於n型裝置(如n型鰭狀場效電晶體)與第二阻金屬材料以用於p型裝置(如p型鰭狀場效電晶體)。因此裝置200可包含雙功函數金屬閘極的設置。在一些實施例中，金屬層可改為包含多晶矽。金屬層的形成方法可採用物理氣相沉積、化學氣相沉積、電子束蒸鍍、及/或其他合適製程。
閘極堆疊116a與116b的形成方法可為任何合適製程，比如閘極優先製程或閘極後製製程。在閘極優先製程的例子中，形成源極/汲極結構106之前可先沉積並圖案化多種材料層，以形成閘極堆疊116a與116b。在閘極後製製程(又稱做閘極置換製程)的例子中，先形成暫時的閘極結構(有時稱做虛置閘極)。在形成源極/汲極結構106之後，接著移除暫時的閘極結構並置換為閘極堆疊116a與116b。
在多種例子中，硬遮罩層120可形成於閘極堆疊116a與116b上。在一些實施例中，硬遮罩層120可包含氧化物層(如氧化矽)與形成於氧化物層上的氮化物層(如氮化矽)。在一些例子中，氧化物層可包含熱成長氧化物、化學氣相沉積的氧化物、及/或原子層沉積的氧化物，且氮化物可包含化學氣相沉積或其他合適技術所沉積的氮化物層。
在一些實施例中，閘極間隔物112形成於硬遮罩層120與閘極堆疊116a與116b的側壁上。閘極間隔物112可包括界電材料如氧化矽、氮化矽、碳化矽、氮氧化矽、或上述之組合。此外，閘極間隔物112可包括單層或多層結構。在多種實施例中，閘極間隔物112的形成方法為沉積(如化學氣相沉積或物理氣相沉積)與蝕刻製程。
接點蝕刻停止層118位於與閘極間隔物112相鄰處。在一些例子中，接點蝕刻停止層118位於源極/汲極結構106上。在一些實施例中，接點蝕刻停止層118可包含氮化矽、氧化矽、氮氧化矽、及/或其他材料。接點蝕刻停止層118的形成方法可為一或多種方法如電漿輔助化學氣相沉積、原子層沉積、及/或其他合適方法。在一些實施例中，層間介電層110形成於接點蝕刻停止層118上，且可包含材料如四乙氧矽烷的氧化物、未摻雜的矽酸鹽玻璃、或摻雜的氧化矽如硼磷矽酸鹽玻璃、摻雜氟的矽酸鹽玻璃、磷矽酸鹽玻璃、硼矽酸鹽玻璃、低介電常數的介電材料、及/或其他合適的介電材料。在多種實施例中，層間介電層110的形成方法可為可流動的化學氣相沉積、電漿輔助化學氣相沉積、或其他合適方法。
方法100的步驟1040進行接點光微影與蝕刻製程，以形成接點開口並露出源極/汲極結構。如圖2與3所示的一些實施例中，步驟1040進行的接點光微影步驟可包括形成光阻層於裝置200 (圖2)上、曝光光阻至一圖案(比如採用接點開口光罩)、浸型曝光後烘烤製程、與顯影光阻以形成圖案化的光阻層於裝置200上。在一些實施例中，形成圖案化的光阻層之後可進行接點蝕刻製程，以形成接點開口302 (圖3)並露出源極/汲極結構106的部份L1。在一些例子中，接點蝕刻製程可包含濕蝕刻、乾蝕刻、或上述之組合。在一些實施例中，形成接點開口302之後可移除圖案化的光阻層，且移除方法可採用溶劑、光阻剝除、灰化、或其他合適技術。值得注意的是，形成接點開口302的方法如接點蝕刻製程，可能會蝕刻層間介電層110與接點蝕刻停止層118。
接著進行方法100的步驟1060以形成聚合物層於閘極堆疊上。如圖3與4所示的一實施例中，步驟1060可形成聚合物層402於閘極堆疊116a與116b上。具體而言，如圖4所示，聚合物層402可形成於硬遮罩層120上、閘極間隔物112上、以及與閘極間隔物112相鄰並接觸閘極間隔物112的接點蝕刻停止層118的一部份上，使聚合物層402懸吊於閘極堆疊116a與116b (比如懸吊於閘極間隔物112與接點蝕刻停止層118)以形成懸吊區404。在所述例子中，聚合物層402的懸吊物，造成接點開口302之側壁表面的至少一部份上的聚合物層402。在一些實施例中，懸吊區404可包含距離D1，即聚合物層402在接點開口302之頂部延伸至接點開口302中的距離。在一些例子中，懸吊區404的尺寸可包含距離D2，其定義聚合物層402覆蓋的接點開口302之側壁表面的部份。在一些實施例中，聚合物層402的厚度為約5nm至20nm，其中聚合物層402的厚度至少取決於懸吊區404的尺寸(比如距離D1及/或距離D2)。在多種例子中，聚合物層402可包含碳氟化合物為主的聚合物、聚甲基丙烯酸甲酯、或氟聚合物如全氟化烷氧基烷。聚合物層402亦可包含單一聚合物、多種聚合物的混摻物、或單體與聚合物的混摻物。此外，一些例子的聚合物層402可包含多種官能基如螯合官能基或其他合適的官能基。在一些實施例中，聚合物層402的形成製程可採用多種方法如旋轉塗佈製程、氣相沉積製程、或其他合適製程。在一些實施例中，可進行烘烤製程以自聚合物層402移除溶劑。可在後續階段移除聚合物層402如下述，且移除方法可採用合適溶劑、濕蝕刻、灰化製程、或上述之組合。
方法100的步驟1080進行蝕刻製程，以形成空洞於接點開口的側壁表面中。如圖4與5所示的一實施例中，步驟1080可進行蝕刻製程502以形成空洞504於接點開口302的側壁表面中。在一些實施例中，蝕刻製程502可包含乾蝕刻製程如反應性離子蝕刻製程或其他合適的蝕刻製程。蝕刻製程可採用多種化學物種如氟、氯、氧、或其他合適物種。在一些例子中，可最佳化蝕刻至成以蝕刻接點蝕刻停止層118與閘極間隔物112的一或兩者。此外，可由傾斜角度ϴ進行蝕刻製程502，其為相對於垂直於裝置200的表面所量測的角度。在一些實施例中，傾斜角度ϴ小於約45度。在一些例子中，傾斜角度ϴ為約30度至45度。在多種實施例中，空洞504的輪廓取決於懸吊區404的尺寸(如上述)與蝕刻製程502的傾斜角度ϴ。此外，可調整空洞504的輪廓以控制後續形成的氣隙間隔物的尺寸。此外，多種實施例的空洞504的輪廓可包含弧形的側壁輪廓。在一些例子中，由於空洞504的弧形側壁輪廓，之後形成的氣隙間隔物寬度(比如沿著圖5的X方向)，可隨著深度(比如圖5的Y方向)變化。舉例來說，氣隙間隔物之中間部份的寬度，可大於氣隙間隔物之頂部與底部部份的寬度。
此外，多種實施例的空洞504之後可用於形成較大的氣隙間隔物(比如較大體積的氣隙)，如下詳述。形成空洞504的步驟亦可露出源極/汲極結構106的部份L2，且部份L2大於形成接點開口302 (見圖3)時原本露出的源極/汲極結構106的部份L1。如此一來，形成空洞504的步驟亦增加接點金屬的關鍵尺寸(如鈷接點金屬的關鍵尺寸)。因此形成空洞504可同時改善裝置200的電容與電阻。
在形成空洞504之後，方法100的步驟1100移除聚合物層。如圖5與6所示的一實施例中，步驟1100可採用合適的溶劑、濕蝕刻、灰化製程、或上述之組合移除聚合物層402。
接著進行方法100的步驟1120，以沉積犧牲層與阻擋層。如圖6至8所示的一實施例中，步驟1120沉積犧牲層702 (見圖7)於裝置200上。具體而言，犧牲層702沉積於裝置的上表面上(比如硬遮罩層120、閘極間隔物112、與接點蝕刻停止層118上)，以及接點開口302的下表面與側壁表面上，包含沉積於空洞504中以使空洞504實質上填有犧牲層702。在一些例子中，犧牲層702包括矽、鍺、矽鍺、低密度的氮化矽、低密度的氧化矽、及/或其他合適材料。由於之後選擇性地蝕刻犧牲層702以形成氣隙(如步驟1200)，需調整或最佳化犧牲層702的組成已用於選擇性蝕刻製程。在多種例子中，犧牲層702的形成製程可為一或多種方法如電漿輔助化學氣相沉積、原子層沉積、及/或其他合適的沉積或氧化製程。
在多種實施例中，可調整犧牲層702的厚度與空洞504 (如上述)的輪廓，以控制後續形成的氣隙間隔物的尺寸。在圖7所示的一些例子中，犧牲層702具有厚度T1 (沿著硬遮罩層120、閘極間隔物112、與接點蝕刻停止層118的上表面，並沿著聚合物層402之懸吊區404之前覆蓋的接點開口302之側壁表面的一部份，如圖4所示)。在一些實施例中，厚度T1可為約1nm至6nm，以確保犧牲層702連續並提供後續形成的結構(比如下述的金屬插塞1102A)所用的足夠製程容許範圍。犧牲層702亦具有沿著空洞504的厚度T2。舉例來說，沿著接點開口302之側壁的不同位置所量測的厚度T2可能不同。然而由於空洞504，厚度T2一般大於厚度T1。在一些實施例中，厚度T2可為約2nm至10nm，可比至少一些現存技術提供體積更大的氣隙間隔物，並維持接點金屬的關鍵尺寸。
在現有的實施方式中(比如無空洞504)，犧牲層702的厚度足以提供充足的氣隙間隔物，但薄到提供足夠體積以形成可信的金屬接點結構於接點開口中。如此一來，至少一些現有方法提供有限空間以***額外犧牲層或增加現有犧牲層的厚度，而不會縮小接點金屬的尺寸。與此相較，本發明實施例提供空洞504，可有效增加犧牲層702的厚度(比如沿著含空洞504的接點開口302之側壁的一部份)，因此可加大氣隙間隔物的體積(如下述)，並維持接點金屬增加的關鍵尺寸。
在步驟1120的其他實施例中，阻擋層802 (見圖8)沉積於犧牲層702上。在一些實施例中，阻擋層802包括含氮化物的層狀物，比如摻雜碳的氮化矽、高密度的氮化矽、及/或其他合適材料。在多種例子中，阻擋層802的厚度可介於約1nm至6nm之間。在一些例子中，阻擋層802的形成製程可為一或多種方法如電漿輔助化學氣相沉積、原子層沉積、及/或其他合適製程。在一些實施例中，阻擋層802包含在整個裝置200上通常具有順應性厚度的薄層。具體而言，阻擋層802沿著接點開口302的側壁之順應性品質，有助於避免後續形成的接點插塞(形成於步驟1180)至閘極堆疊116a與116b的漏電流路徑，反之亦然。
接著進行方法100的步驟1140，進行蝕刻製程以露出源極/汲極結構。如圖8與9所示的一實施例中，步驟1140進行蝕刻製程，以自閘極結構的上表面(如硬遮罩層120、閘極間隔物112、與接點蝕刻停止層的上表面)實質上移除阻擋層802與犧牲層702，亦自源極/汲極結構106的至少一部份移除阻擋層802與犧牲層702，以形成空洞902並露出源極/汲極結構106。上述蝕刻可包含濕蝕刻、乾蝕刻、或上述之組合。在一些實施例中，蝕刻製程在形成空洞902時，亦可蝕刻源極/汲極結構106的一部份。值得注意的是，在步驟1140的蝕刻製程之後，可實質上保留阻擋層802與犧牲層702於接點開口302的側壁上(包括空洞504中)。
接著進行方法100的步驟1160，形成矽化物層以接觸露出的源極/汲極結構。如圖9與10所示的一實施例中，步驟1160形成金屬層1002於裝置200上(包括形成於空洞902中)，使金屬層1002接觸源極/汲極結構106。在多種實施例中，金屬層1002一般可覆蓋接點開口302的下表面與側壁表面，以及閘極結構的上表面(如硬遮罩層120、閘極間隔物112、與接點蝕刻停止層118的上表面)。在一些例子中，金屬層1002的沉積方法可採用原子層沉積、化學氣相沉積、物理氣相沉積、或其他合適製程。舉例來說，金屬層1002可包含多種材料如鎳、鈷、鎢、鉭、鈦、上述之組合、或其他合適材料。在形成金屬層1002之後，步驟1160的其他實施例可退火裝置200以升高金屬層1002的溫度，使金屬層1002與源極/汲極結構106中的半導體材料反應形成金屬矽化物1002A。在一些實施例中，可移除金屬層1002的未反應區(如沿著接點開口302的側壁表面及閘極結構的上表面上的金屬層1002)，可保留金屬矽化物1002A以接觸源極/汲極結構106，且移除方法可為濕或乾蝕刻製程。在多種實施例中，金屬矽化物1002A可包括鎳矽化物、鈷矽化物、鈦矽化物、或其他合適材料。
接著進行方法100的步驟1180以形成金屬接點層，並進行化學機械平坦化製程以提供金屬插塞。如圖11與12所示的一些實施例中，步驟1180形成金屬接點層1102於裝置200上。在一些實施例中，金屬接點層1102包含鋁、鎢、銅、鈷、鈦、鎳、釕、上述之組合、或其他合適材料。在一些例子中，金屬接點層1102亦可包括導電的氮化物如氮化鉭或氮化鈦所組成的阻障層。在多種例子中，金屬接點層1102的形成方法可為物理氣相沉積、化學氣相沉積、原子層沉積、電鍍、或其他合適方法。金屬接點層1102經由金屬矽化物1002A電性耦接至源極/汲極結構106。然而在其他實施例中，金屬接點層1102可直接連接至源極/汲極結構106，而不需中間的矽化物結構。在形成金屬接點層1102之後，步驟1180的其他實施例可進行化學機械平坦化製程，以移除金屬接點層1102的多餘部份並平坦化裝置200的上表面，即提供金屬插塞1102A。在多種例子中，金屬插塞1102A可視作接點插塞、通孔、通孔插塞、或金屬接點。亦應注意的是，步驟1180的化學機械平坦化製程設置已露出犧牲層702的上表面(用於後續形成氣隙)。此外，化學機械平坦化製程亦露出阻擋層802的上表面與閘極結構的上表面(如硬遮罩層120的上表面、閘極間隔物112的上表面、與接點蝕刻停止層118的上表面)。
接著進行方法100的步驟1200，移除犧牲層以形成氣隙。如圖12與13所示的一實施例中，步驟1200移除犧牲層702的保留部份(由步驟1180的化學機械所露出)，以形成氣隙1302。在一些實施例中，犧牲層702的移除方法採用選擇性蝕刻製程，包含乾蝕刻、濕蝕刻、反應性離子蝕刻、及/或其他合適製程。舉例來說，氣隙1302可形成於金屬插塞1102A與相鄰的閘極堆疊116a及116b之間，以降低金屬插塞與閘極堆疊之間的電容。由於氣體的介電常數為約1且低於其他介電材料的介電常數，因此可降低電容。此外，形成空洞504如上述，可使犧牲層702占有較大體積，使步驟1200形成的氣隙1302亦占有較大體積並進一步降低電容(與至少一些現存的實施方式相較)。在不存在層疊偏移的一些實施例中，金屬插塞1102A的每一側上的氣隙1302可具有實質上類似的尺寸，因此其個別電容可大致相同。然而若有層疊偏移，金屬插塞1102A之每一側上的氣隙1302可能具有不同尺寸，因此個別電容可能不同。然而氣隙1302的體積增加並降低相關電容，可大幅緩解金屬插塞1102A的每一側上的電容變異(比如層疊偏移)對裝置或電路效能的任何影響。此外，由於空洞504具有弧型側壁輪廓如上述，氣隙1302的寬度可隨著深度改變。舉例來說，氣隙1302的中間部份的寬度可大於氣隙1302的頂部或底部的寬度。
方法100的步驟1220接著形成密封層以覆蓋氣隙。如圖13與14所示的一實施例中，步驟1220形成密封層14|在本發明實施例的教示下，本技術領域中具有通常知識者可輕易思及其他實施例與優點。
本發明一實施例提供之半導體裝置的形成方法，包括：提供第一電晶體，其包含第一閘極結構以及與第一閘極結構相鄰的源極/汲極結構。在一些實施例中，沿著位於源極/汲極結構上的接點開口的側壁表面形成空洞。在形成空洞之後，沉積犧牲層於空洞中包含的接點開口之側壁表面與下表面上，其中犧牲層填入空洞。在一些例子中，沿著接點開口的下表面移除犧牲層的第一部份，以露出源極/汲極結構的一部份。形成接點結構於露出的源極/汲極結構的部份上。在一些實施例中，移除犧牲層的保留部份，以形成氣隙於接點結構與第一閘極結構之間。之後沉積密封層於氣隙上，以形成氣隙間隔物。
在一實施例中，犧牲層的保留部份之移除方法採用選擇性蝕刻製程。
在一實施例中，方法更包括：在形成空洞之前，形成聚合物層於第一閘極結構上，其中聚合物層懸吊於第一閘極結構並覆蓋接點開口之側壁表面的至少一部份。
在一實施例中，形成空洞的步驟包括以傾斜角度進行乾蝕刻製程。
在一實施例中，沿著含有空洞之接點開口的第一側壁表面的犧牲層具有第一厚度，且第一閘極結構上的犧牲層具有第二厚度，且第一厚度大於第二厚度。
在一實施例中，方法更包括：在移除犧牲層的第一部份之前，形成阻擋層於犧牲層上；以及沿著接點開口的下表面移除犧牲層的第一部份與阻擋層的第一部份，以露出源極/汲極結構的部份。
在一實施例中，方法更包括：在露出源極/汲極結構的部份之後與形成接點結構之前，形成矽化物層以接觸露出的源極/汲極結構的部份；以及形成接點結構於矽化物層上。
在一實施例中，沿著接點開口的側壁表面形成空洞的步驟，增加源極/汲極結構的露出區域尺寸。
在一實施例中，方法更包括：形成第二電晶體，其包括第二閘極結構，其中源極/汲極結構位於第一閘極結構與第二閘極結構之間，並與第一閘極結構及第二閘極結構的每一者相鄰。
在一實施例中，氣隙間隔物的中間部份的第一寬度，大於氣隙間隔物的頂部或底部部份的第二寬度。
另一實施例提供之半導體裝置的形成方法，包括提供第一電晶體，其包括第一閘極結構；第二電晶體，其包括第二閘極結構；源極/汲極結構，位於第一閘極結構與第二閘極結構的之間並與第一閘極結構與第二閘極結構的每一者相鄰；以及接點開口，位於源極/汲極結構上。在一些實施例中，形成第一空洞於接點開口的第一側壁表面上，以及第二開口於接點開口的第二側壁表面上。在一些例子中，沿著第一空洞與第二空洞中包含的第一側壁表面與第二側壁表面沉積犧牲層。在多種實施例中，形成接點結構於源極/汲極結構上。接點結構位於沿著第一側壁表面的犧牲層與沿著第二側壁表面的犧牲層之間。在形成接點結構之後，自第一側壁表面與第二側壁表面移除犧牲層，以形成位於接點結構與第一閘極結構之間的第一氣隙與位於接點結構與第二閘極結構之間的第二氣隙。在一些實施例中，沉積密封層於第一氣隙與第二氣隙上，以形成與接點結構相鄰的多個氣隙間隔物。
在一些實施例中，方法更包括在形成第一空洞與第二空洞之前，沉積第一聚合物層於第一閘極結構上並沉積第二聚合物層於第二閘極結構上，其中第一聚合物層懸吊於該第一閘極結構並覆蓋接點開口之第一側壁表面的至少第一部份，且其中第二聚合物層懸吊於該第二閘極結構並覆蓋接點開口之第二側壁表面的至少第二部份。
在一些實施例中，形成第一空洞與第二空洞的步驟更包括蝕刻接點開口的第一側壁表面的第三部份以形成第一空洞，並蝕刻接點開口的第二側壁表面的第四部份以形成第二空洞。
在一些實施例中，方法更包括：在形成第一空洞與第二空洞之後，且在形成接點結構之前，沉積犧牲層於第一空洞與第二空洞中包含的接點開口之第一側壁表面、第二側壁表面、與下表面上；以及移除犧牲層沿著接點開口之下表面的第一部份，以露出源極/汲極結構的一部份。
在一些實施例中，方法更包括：在露出源極/汲極結構的部份之後且在形成接點結構之前，形成矽化物層以接觸源極/汲極結構的露出部份；以及形成接點結構於矽化物層上。
在一些實施例中，方法更包括：在形成接點結構之前，形成阻擋層於沿著第一側壁表面與第二側壁表面的犧牲層上；以及形成接點結構於源極/汲極結構上，其中接點結構位於沿著第一側壁表面的犧牲層上的阻擋層與位於沿著第二側壁表面的犧牲層上的阻擋層之間。
在一些實施例中，犧牲層在第一側壁表面與第二側壁表面的上側區域中具有第一厚度，其中犧牲層在第一側壁表面與第二側壁表面的下側區域中具有第二厚度，其中第一側壁表面的下側區域包括第一空洞而第二側壁表面的下側區域包括第二空洞，且其中第一厚度小於第二厚度。
本發明又一實施例提供之半導體裝置，包括閘極結構，以及與閘極結構相鄰的源極/汲極結構。半導體裝置亦包括接點結構，位於源極/汲極結構上並該閘極結構相鄰。在一些例子中，半導體裝置亦包括氣隙間隔物，包括密封層形成於空洞上，其中氣隙間隔物位於接點結構與閘極結構之間，且其中空洞包括弧形側壁輪廓。
在一些實施例中，半導體裝置更包括：阻擋層，位於接點結構的側壁上，其中阻擋層位於接點結構與氣隙間隔物之間。
在一些實施例中，半導體裝置更包括：矽化物層，接觸源極/汲極結構，其中接點結構位於矽化物層上。
上述內容已說明幾個實施例的特徵，以利本技術領域中具有通常知識者理解詳細說明。 本技術領域中具有通常知識者應理解，本發明實施例明顯可作為設計或調整其他製程和結構的基礎，以實現此處介紹的實施例之相同目的及/或相同優點。本技術領域中具有通常知識者亦應理解，這些等效構造並未脫離本發明實施例的精神與範疇，且在不脫離本發明實施例的精神與範疇的前提下，可進行多種改變、取代、或變更。
ϴ:傾斜角度 D1、D2:距離 L1、L2:部份 T1、T2:厚度 100:方法 102:基板 106:源極/汲極結構 110:層間介電層 112:閘極間隔物 116a、116b:閘極堆疊 118:接點蝕刻停止層 120:硬遮罩層 200:裝置 302:接點開口 402:聚合物層 404:懸吊區 502:蝕刻製程 504、902:空洞 702:犧牲層 802:阻擋層 1002:金屬層 1002A:金屬矽化物 1102:金屬接點層 1102A:金屬插塞 1020、1040、1060、1080、1100、1120、1140、1160、1180、1200、1220:步驟 1302:氣隙 1402:密封層 1404:單元
圖1係本發明多種實施例中，形成半導體裝置的方法之流程圖。 圖2、3、4、5、6、7、8、9、10、11、12、13、與14係本發明多種實施例中，製作半導體裝置的多種階段之剖視圖。
200:裝置
1302:氣隙
1402:密封層
1404:單元

Claims (1)

  1. 一種半導體裝置的形成方法，包括： 提供一第一電晶體，其包含一第一閘極結構以及與該第一閘極結構相鄰的一源極/汲極結構； 沿著位於該源極/汲極結構上的一接點開口的一側壁表面形成一空洞； 在形成該空洞之後，沉積一犧牲層於該空洞中包含的該接點開口之側壁表面與下表面上，其中該犧牲層填入該空洞； 沿著該接點開口的下表面移除該犧牲層的一第一部份，以露出該源極/汲極結構的一部份； 形成一接點結構於露出的該源極/汲極結構的部份上； 移除該犧牲層的保留部份，以形成一氣隙於該接點結構與該第一閘極結構之間；以及 沉積一密封層於該氣隙上，以形成一氣隙間隔物。
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