TW202017010A - 完全矽化閘控裝置及其形成方法 - Google Patents

完全矽化閘控裝置及其形成方法 Download PDF

Info

Publication number
TW202017010A
TW202017010A TW108102536A TW108102536A TW202017010A TW 202017010 A TW202017010 A TW 202017010A TW 108102536 A TW108102536 A TW 108102536A TW 108102536 A TW108102536 A TW 108102536A TW 202017010 A TW202017010 A TW 202017010A
Authority
TW
Taiwan
Prior art keywords
layer
forming
region
source
fully
Prior art date
Application number
TW108102536A
Other languages
English (en)
Other versions
TWI708282B (zh
Inventor
陳奕寰
周建志
林大為
段孝勤
亞歷山大 卡爾尼斯基
鄭光茗
吳佳泓
Original Assignee
台灣積體電路製造股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 台灣積體電路製造股份有限公司 filed Critical 台灣積體電路製造股份有限公司
Publication of TW202017010A publication Critical patent/TW202017010A/zh
Application granted granted Critical
Publication of TWI708282B publication Critical patent/TWI708282B/zh

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823828—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
    • H01L21/823835—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes silicided or salicided gate conductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
    • H01L21/28088—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being a composite, e.g. TiN
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/31051—Planarisation of the insulating layers
    • H01L21/31053—Planarisation of the insulating layers involving a dielectric removal step
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32139—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823437—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
    • H01L21/823443—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes silicided or salicided gate conductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823814—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823871—Complementary field-effect transistors, e.g. CMOS interconnection or wiring or contact manufacturing related aspects
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/0843—Source or drain regions of field-effect devices
    • H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/401—Multistep manufacturing processes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42372—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42372—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out
    • H01L29/42376—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out characterised by the length or the sectional shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/45—Ohmic electrodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/495—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a simple metal, e.g. W, Mo
    • H01L29/4958—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a simple metal, e.g. W, Mo with a multiple layer structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/4966—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a composite material, e.g. organic material, TiN, MoSi2
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/51—Insulating materials associated therewith
    • H01L29/511—Insulating materials associated therewith with a compositional variation, e.g. multilayer structures
    • H01L29/513—Insulating materials associated therewith with a compositional variation, e.g. multilayer structures the variation being perpendicular to the channel plane
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/665—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using self aligned silicidation, i.e. salicide
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66515—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using self aligned selective metal deposition simultaneously on the gate and on source or drain
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7838—Field effect transistors with field effect produced by an insulated gate without inversion channel, e.g. buried channel lateral MISFETs, normally-on lateral MISFETs, depletion-mode lateral MISFETs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42364—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/51—Insulating materials associated therewith
    • H01L29/517—Insulating materials associated therewith the insulating material comprising a metallic compound, e.g. metal oxide, metal silicate

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
  • Composite Materials (AREA)
  • Materials Engineering (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • General Chemical & Material Sciences (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

本揭露的各種實施例有關於一種形成完全矽化（fully silicided，FUSI）閘控裝置的方法，所述方法包括：在基底上方的閘極結構上形成罩幕層，閘極結構包括多晶矽層。在閘極結構的相對側上的基底內形成第一源極區及第一汲極區，閘極結構是在第一源極區及第一汲極區之前形成。執行第一移除製程，以移除罩幕層的一部分，並暴露出多晶矽層的上部表面。第一源極區及第一汲極區是在第一移除製程之前形成。形成與多晶矽層的上部表面直接接觸的導電層。導電層是在第一移除製程之後形成。將導電層和多晶矽層轉換成完全矽化層。完全矽化層較薄且厚度均勻。

Description

完全矽化閘控裝置的形成
許多現代電子裝置含有金屬氧化物半導體場效應電晶體（metal-oxide-semiconductor field-effect transistor；MOSFET）。MOSFET具有佈置於源極區與汲極區之間的基底上方的閘極結構。施加到閘極結構的閘極電極的電壓決定MOSFET的導電率。由於高介電常數（k）MOSFET裝置微型化的優點，具有完全矽化（fully silicided；FUSI）閘極電極的閘極結構是下一代MOSFET裝置的理想候選。
本揭露提供用於實施本揭露的不同特徵的許多不同實施例或實例。下文描述元件和配置的特定實例以簡化本揭露。當然，這些只是實例且並不意欲為限制性的。舉例來說，在以下描述中，第一特徵在第二特徵上方或第二特徵上的形成可包括第一特徵和第二特徵直接接觸地形成的實施例，並且還可包括額外特徵可在第一特徵與第二特徵之間形成使得第一特徵和第二特徵可不直接接觸的實施例。另外，本揭露可以在各種實例中重複附圖標號和/或字母。此重複是出於簡化和清楚的目的，且本身並不規定所論述的各種實施例和/或配置之間的關係。
此外，為易於描述附圖中所示的一個元件或特徵與另一元件或特徵的關係，本文中可使用例如“在...下面（beneath）”、“在...下方（below）”、“下部（lower）”、“在...上方（above）”、“上部（upper）”等空間相對用語。除附圖中所繪示的定向之外，所述空間相對術語意欲涵蓋裝置在使用或操作中的不同定向。設備可以其他方式定向（旋轉90度或處於其他定向），且本文中所使用的空間相對用語可同樣相應地進行解譯。
典型的金屬氧化物半導體場效應電晶體（MOSFET）包括位於基底內的井區上方的閘極結構。源極區和汲極區位於閘極結構下方的溝道區的相對側的基底中。閘極結構包括設置於閘極介電層上方的閘極電極。從閘極電極向源極區和汲極區施加電壓將改變MOSFET的電阻。增加電壓將增加溝道區中的電荷載體（例如，電子）的濃度，從而降低源極區與汲極區之間的電阻。
在過去二十年中，MOFSET電晶體通常使用的是包括多晶矽的閘極結構。近年來，高k金屬閘極（high k metal gate；HKMG）電晶體已開始廣泛使用，因為其能夠進一步實現調整並提高MOSFET裝置的性能。然而，使用HKMG替換閘極製程將低電壓裝置和高電壓裝置內嵌在一起具有挑戰性。HKMG的一種替代方案是使用完全矽化（FUSI）閘極。在製造具有FUSI閘極的MOSFET期間，多晶矽層形成於閘極介電層上方，且金屬層形成於多晶矽層上方。執行退火製程以將多晶矽層和金屬層轉換成閘極結構的完全矽化（FUSI）閘極電極。隨後，源極區和汲極區形成於閘極結構的相對側上。將導電接觸窗（conductive contact）設置於FUSI閘極電極以及源極區和汲極區上方。上方的金屬線隨後形成於導電接觸窗上方的層間介電（inter-level-dielectric；ILD）層內。
理想地，在FUSI製程期間使用相對較薄的多晶矽層。這是因為較厚的多晶矽層在退火製程期間將導致製程問題。舉例來說，如果多晶矽層太厚（例如大於大約600埃），且厚度不均勻，那麼退火製程將無法將整個多晶矽層轉換成FUSI閘極電極，使得FUSI閘極電極的一些部分（例如FUSI閘極電極的中心區內）為多晶矽而降低MOSFET裝置的性能。然而，已瞭解在閘極介電層上方形成較薄多晶矽層之後，將存在晶界（grain boundary），這將產生具有提升高度的凸起缺陷（hump defect）。凸起缺陷導致基底上的MOSFET裝置陣列上方的多晶矽層高度不均勻，這也將在退火製程期間導致製程問題。
本揭露一些實施例有關於一種形成MOSFET裝置的方法，所述方法包括在閘極介電層上方形成包括第一介電層（例如包括高k介電質的第一介電層）的閘極結構，在第一介電層上方形成金屬層（例如包括TiN的金屬層），以及在金屬層上方形成多晶矽層。多晶矽層均勻地且無缺陷地形成於金屬層上，由此消除任何潛在的凸起缺陷問題。形成源極區和汲極區於閘極結構的相對側上。形成第二介電層於閘極結構以及源極區和汲極區上方。執行平坦化製程和蝕刻製程以暴露多晶矽層的上部表面。形成導電層於多晶矽層的上部表面上方，並執行退火製程以將多晶矽層和導電層轉換成FUSI層。在金屬層上形成多晶矽層使得多晶矽層較薄（例如厚度約小於300埃）且大體上厚度均勻，確保退火製程使導電層正下方的整個厚度的多晶矽層矽化。
參考圖1，提供根據一些實施例的積體電路（IC）100的剖視圖。
IC 100包括基底101，其中第一MOSFET裝置122及第二MOSFET裝置124設置於基底101的上方及基底101內。在一些實施例中，MOSFET裝置又可被稱為閘控裝置（gated device）或閘控結構（gated structure）。蝕刻停止層110設置於基底101上方以及第一MOSFET裝置122及第二MOSFET裝置124的側壁周圍。第一層間介電（ILD）層128設置於第一MOSFET裝置122和第二MOSFET裝置124以及蝕刻停止層110上方。
第一MOSFET裝置122和第二MOSFET裝置124分別包括閘極結構121。閘極結構121包括閘極介電層112、第一介電層114、金屬層116以及完全矽化（FUSI）層118。閘極介電層112與基底101直接接觸。第一介電層114上覆於（overlie）閘極介電層112。金屬層116上覆於第一介電層114。FUSI層118上覆於金屬層116。在一些實施例中，FUSI層118相對較薄且厚度均勻，舉例來說，FUSI層118的每個點的頂部表面至FUSI層118的相應底部表面之間的厚度在約-15埃到+15埃的範圍內變化。在一些實施例中，FUSI層118被形成為厚度在約150埃到約300埃的範圍內。在其它實施例中，FUSI層118被形成為厚度在約225埃到約300埃的範圍內。在一些實施例中，FUSI層118被完全矽化，從而使得FUSI層118的頂部表面與底部表面之間不存在未矽化的多晶矽材料。在一些實施例中，金屬層116包括氮化鈦（TiN）。側壁間隙壁120環繞閘極結構121中的相應各層的側壁。第一導電接觸窗126分別上覆於第一MOSFET裝置122和第二MOSFET裝置124的FUSI層118。
第一源極/汲極區102和第二源極/汲極區104設置於第一MOSFET裝置122的閘極結構121的相對側上。第三源極/汲極區106和第四源極/汲極區108設置於第二MOSFET裝置124的閘極結構121的相對側上。第一源極/汲極區102、第二源極/汲極區104、第三源極/汲極區106以及第四源極/汲極區108設置於基底101內。第一源極/汲極區102和第二源極/汲極區104具有第一摻雜類型。第三源極/汲極區106和第四源極/汲極區108具有第二摻雜類型。在一些實施例中，第一摻雜類型和第二摻雜類型相同。在又一實施例中，第一摻雜類型為P+型且第二摻雜類型為N+型，或反之亦然。
在一些實施例中，第一MOSFET裝置122和第二MOSFET裝置124可包括高電壓裝置。高電壓技術已廣泛應用於功率管理（power management）、調節器（regulator）、電池保護器、直流電動機（DC motor）、自動化相關（automotive relative）、面板顯示驅動器（STN、TFT、OLED等）、彩色顯示器驅動器、電源供應器相關、電信等等。在一些實施例中，所揭露的MOFSET裝置可包括對稱和不對稱的橫向擴散的MOSFET（laterally diffused MOSFET；LDMOS）、雙擴散MOSFET（double-diffused MOSFET；DMOS）裝置或類似裝置。上覆於金屬層116的較薄且均勻的FUSI層118確保低電壓裝置和高電壓裝置可嵌入在一起。
使FUSI層118上覆於金屬層116使得FUSI層118具有相對較薄且均勻的厚度（例如厚度小於或等於約300埃或處於約150埃到300埃的範圍內）。此相對較薄且均勻的厚度確保整個厚度的FUSI層118完全矽化，並減少與FUSI層118的厚度相關的製程問題。具有金屬層116確保相反摻雜類型的MOSFET裝置可以最小缺陷（例如防止凸起缺陷）嵌入在FUSI層118內的同一平台（platform）上（例如具體地在電壓範圍為約6伏到32伏的高電壓應用中）。
圖2示出一些其它實施例的IC 200的剖視圖。
IC 200包括基底101，其中第一MOSFET裝置122設置於基底101上及基底101內。基底101可以是例如塊狀基底（例如，塊狀矽基底）、絕緣體上矽（silicon-on-insulator；SOI）基底、P摻雜矽或N摻雜矽。第二介電層212上覆於第一MOSFET裝置122。第一ILD層128設置於第二介電層212上方。
第一MOSFET裝置122包括閘極結構121。閘極結構121包括閘極介電層112、第一介電層114、金屬層116以及完全矽化（FUSI）層118。閘極介電層112與基底101直接接觸。在一些實施例中，舉例來說，閘極介電層112可為或可包括氧化物（例如氧化矽、氮氧化矽或其類似物）、高k介電質（例如氧化鉿、矽酸鋯或其類似物）或前述的任何組合，且被形成為厚度為約208埃或處於約50埃到約250埃的範圍內。第一介電層114上覆於閘極介電層112。在一些實施例中，舉例來說，第一介電層114可為或可包括高k介電質、氧化鉿（HfO2 ）、氧化鋯（ZrO2 ）或前述的任何組合，且被形成為厚度為約10埃、20埃或處於約5埃到約25埃的範圍內。在本文中，高k介電質可以是例如介電常數k大於約3.9、10或20的介電質。金屬層116上覆於第一介電層114。在一些實施例中，舉例來說，金屬層116可為或可包括氮化鈦（TiN）、鈦（Ti）、鉭（Ta）、氮化鉭（TaN）或前述的任何組合，且被形成為厚度為約10埃、30埃或處於約5埃到約40埃的範圍內。FUSI層118上覆於金屬層116。在一些實施例中，舉例來說，FUSI層118可為或可包括矽化鎳、矽化鈷、矽化鈦、矽化銅或前述的任何組合，且被形成為厚度為約150埃、169埃、200埃、250埃或處於約125埃到約325埃的範圍內。
閘極結構121被定義為位於中心區214a內。在一些實施例中，中心區214a居中於閘極結構121的中點（midpoint）（例如，FUSI層118的中點）或中線（midline）處。第一外部區214b和第二外部區214c被定義為位於中心區214a的相對側上。FUSI層118被定義為位於中心區214a內。整個厚度的FUSI層118完全矽化，從而使得FUSI層118的頂部表面與底部表面之間不存在未矽化的多晶矽材料。第一外部區214b和第二外部區214c分別包括上覆於金屬層116的多晶矽層204。在一些實施例中，舉例來說，多晶矽層204可為或可包括多晶矽，且被形成為厚度為約150埃、300埃或處於約125埃到約500埃的範圍內。在一些實施例中，多晶矽層204的底部層與FUSI層118的底部層對準，且多晶矽層204的厚度大於FUSI層118的厚度。在一些實施例中，多晶矽層204的厚度比FUSI層118的厚度厚約10%、25%、50%或75%。在一些實施例中，多晶矽層204的一部分藉由FUSI層118的導電材料而部分或完全矽化。
罩幕層210上覆於多晶矽層204。在一些實施例中（未繪示），罩幕層210可從多晶矽層204的正上方延伸到FUSI層118的正上方。在一些此類實施例中，FUSI層118可具有成角外側（angled outer side）（即，定義FUSI層118與多晶矽層204之間的成角界面），使得FUSI層118的寬度隨著距基底101的距離增加而增加。在一些實施例中，舉例來說，罩幕層210可為或可包括氮化矽（SiN）、碳化矽（SiC）、氧化矽（SiO2 ）或前述的任何組合，且被形成為厚度為約150埃、250埃或處於約100埃到約350埃的範圍內。第二介電層212上覆於罩幕層210。
第一外部區214b和第二外部區214c分別包括第一接觸區209a和第二接觸區209b。第一接觸區209a和第二接觸區209b分別包括被U型蝕刻停止層208包圍的第三介電層206。在一些實施例中，中心區214a和閘極結構121被定義為位於第一接觸區209a及第二接觸區209b的內側壁之間。第一源極/汲極區102和第二源極/汲極區104分別設置於第一接觸區209a和第二接觸區209b正下方的基底101內。第一矽化區102a和第二矽化區104a分別設置於第一源極/汲極區102和第二源極/汲極區104上方。在一些實施例中，第一源極/汲極區102和第二源極/汲極區104具有與基底101的摻雜類型相反的第一摻雜類型。隔離結構202延伸到基底101的上部表面或頂部表面中，以提供MOSFET裝置122與相鄰裝置之間的電隔離。隔離結構202包括分別位於MOSFET裝置122的相對側上的一對隔離部分。在一些實施例中，隔離結構202包括介電材料和/或為淺溝槽隔離（STI）結構、深溝槽隔離（deep trench isolation DTI）結構或其它適合的隔離結構。
參考圖3，提供一些實施例的包括第一MOSFET裝置122和第二MOSFET裝置124的IC 300的剖視圖。
IC 300包括基底101，其中第一MOSFET裝置122及第二MOSFET裝置124設置於基底101上方及基底101內。在一些實施例中，基底101摻雜有N型摻質或P型摻質。在基底101內，第一井區304和第二井區308分別上覆於第一深井區302和第二深井區306。第一源極/汲極擴展區303分別沿第一源極/汲極區102和第二源極/汲極區104的內側壁設置。第一源極/汲極擴展區303包括較低濃度的與第一源極/汲極區102和第二源極/汲極區104相同的摻質。第二源極/汲極擴展區305分別沿第三源極/汲極區106和第四源極/汲極區108的內側壁設置。第二源極/汲極擴展區305包括較低濃度的與第三源極/汲極區106和第四源極/汲極區108相同的摻質。
在一些實施例中，第一源極/汲極區102和第二源極/汲極區104分別包括第一摻質類型（例如P型或N型）。第一井區304和第一深井區302分別包括第二摻質。第一摻質與第二摻質相反。在一些實施例中，第三源極/汲極區106和第四源極/汲極區108分別包括第三摻質。第二井區308和第二深井區306分別包括第四摻質。第三摻質與第四摻質相反。在一些實施例中，第一摻質和第三摻質相同或相反，或者第一摻質和第四摻質相同或相反。因此，在一些實施例中，第一MOSFET裝置122為N型且第二MOSFET裝置124為P型，或反之亦然。在一些實施例中，第一MOSFET裝置122和第二MOSFET裝置124兩者都為N型或P型。
第一MOSFET裝置122和第二MOSFET裝置124分別包括閘極結構121。閘極結構121包括閘極介電層112、第一介電層114、金屬層116、FUSI層118以及第二側壁間隙壁310。閘極介電層112與基底101直接接觸。第一介電層114設置於閘極介電層112上方。金屬層116設置於第一介電層114上方。FUSI層118設置於金屬層116上方。第二側壁間隙壁310包括設置於金屬層116上方FUSI層118的相對側上的兩個部分。第二側壁間隙壁310的兩個部分包夾（sandwich）FUSI層118。在一些實施例中，第二側壁間隙壁310可例如為或包括SiN、SiC、SiO或前述的任何組合。第一ILD層128設置於第一MOSFET裝置122和第二MOSFET裝置124以及基底101上方。
第一導電接觸窗126分別上覆於第一MOSFET裝置122和第二MOSFET裝置124的FUSI層118和源極/汲極區（第一源極/汲極區102、第二源極/汲極區104、第三源極/汲極區106以及第四源極/汲極區108）。第一導電接觸窗126可例如為或包括鎢（W）、銅（Cu）、鋁（Al）、前述的組合或其類似物。第一導電線314分別上覆於第一導電接觸窗126且設置於第二ILD層312內。第一導電線314可例如為或包括Cu、Al、其組合或其類似物。第二導電通孔318分別上覆於第一導電線314且設置於第三ILD層316內。第二導電通孔318可例如為或包括Cu、Al、其組合或其類似物。第二導電線322分別上覆於第二導電通孔318且設置於第四ILD層320內。第二導電線322可例如為或包括Cu、Al、其組合或其類似物。
參考圖4，提供一些實施例的包括第一MOSFET裝置122和第二MOSFET裝置124的IC 400的剖視圖。第一MOSFET裝置122和第二MOSFET裝置124各自如圖2的MOSFET裝置122所示和所描述，其中第一MOSFET裝置122和第二MOSFET裝置124各自包括FUSI層118和金屬層116。另外，第一MOSFET裝置122和第二MOSFET裝置124分別包括如圖3中所描述的第一井區304和第二井區308。在一些實施例中，第一MOSFET裝置122和第二MOSFET裝置124分別包括設置於第一井區304和第二井區308下方的深井區。在一些實施例中，第一MOSFET裝置122為N型且第二MOSFET裝置124為P型，或反之亦然。在一些實施例中，第一MOSFET裝置122和第二MOSFET裝置124兩者均為N型或P型。
圖5、圖6、圖7A、圖8到圖16示出根據本揭露一些實施例的形成包括MOSFET裝置的IC的方法的剖視圖500、剖視圖600、剖視圖700a、剖視圖800到剖視圖1600，其中所述MOSFET裝置具有FUSI層和金屬層。雖然圖5、圖6、圖7A、圖8到圖16中繪示的剖視圖500、剖視圖600、剖視圖700a、剖視圖800到剖視圖1600參照一種方法描述，但是應瞭解，圖5、圖6、圖7A、圖8到圖16中繪示的結構不限於所述方法，而是可單獨作為與所述方法分開的結構。雖然圖5、圖6、圖7A、圖8到圖16被描述為一系列動作，但是應瞭解，這些動作不限於所述動作次序，可在其它實施例中更改這些動作的次序，且所揭露的方法還適用於其它結構。在其它實施例中，一些示出和/或描述的動作可完全或部分地省略。
如圖5的剖視圖500中所繪示，形成隔離結構202，隔離結構202延伸到基底101的上部表面或頂部表面中，以提供MOSFET裝置與相鄰裝置之間的電隔離。舉例來說，基底101可為塊狀單晶矽基底、其它適合的塊狀半導體基底、絕緣體上矽（SOI）基底或其它適合的半導體基底。隔離結構202包括一對隔離部分。在一些實施例中，隔離結構202包括介電材料和/或為淺溝槽隔離（STI）結構、深溝槽隔離（DTI）結構或其它適合的隔離結構。在一些實施例中，形成隔離結構202包括：圖案化基底101以形成溝槽，以及用介電材料填充溝槽。在一些實施例中，形成井區於隔離結構202的所述一對隔離部分之間的基底101內。在一些實施例中，形成深井區於井區下方。
如圖6的剖視圖600中所繪示，形成閘極介電層112於基底101上方。形成第一介電層114於閘極介電層112上方。形成金屬層116於第一介電層114上方。舉例來說，可藉由化學氣相沉積（chemical vapor deposition；CVD）、物理氣相沉積（physical vapor deposition；PVD）、其它適合的沉積製程或前述的任何組合來形成閘極介電層112、第一介電層114以及金屬層116。
如圖7A的剖視圖700a中所繪示，形成多晶矽層204於金屬層116上方。形成罩幕層210於多晶矽層204上方。罩幕層210包括定義第一開口702和第二開口704的一組兩個側壁。第一開口702和第二開口704暴露出多晶矽層204的上部表面。舉例來說，可藉由化學氣相沉積（CVD）、物理氣相沉積（PVD）、其它適合的沉積製程或前述的任何組合來形成多晶矽層204和罩幕層210。
在一些實施例中，金屬層116可例如為或包括氮化鈦（TiN）。多晶矽層204以均勻厚度形成於金屬層116上方，而減少多晶矽層204內的缺陷（例如，凸起缺陷）。在一些實施例中，此製程確保多個MOSFET裝置分別具有大體上均勻的高度。
圖7B示出一些其它實施例的IC 700b的俯視圖。
IC 700b包括矽晶片706沿圖7A的剖視圖700a的水平線（圖7A的A與A'之間）的俯視圖。所述水平線（圖7A的A與A'之間）與多晶矽層204的上部表面對準。多個凸起缺陷204a分佈在矽晶片706上。所述多個凸起缺陷204a凸出在多晶矽層204的上部表面上方。所述多個凸起缺陷204a與多晶矽層204的上部表面之間的高度差是歸因於在閘極介電層（圖7A的112）的上方形成多晶矽層204時的製程誤差（processing error）（例如晶界）導致產生多個凸起缺陷204a。在一些實施例中，所述多個凸起缺陷204a包括遍佈矽晶片706的10個或少於10個的凸起缺陷，相比之下，不具有金屬層（圖7A的116）的實施例包括遍佈矽晶片706的1000個或多於1000個凸起缺陷。在一些實施例中，不存在凸起缺陷及所述多個凸起缺陷204a，使得多晶矽層204包括大體上平坦且均勻的上部表面。在一些實施例中，多晶矽層204與水平線對準。因此，金屬層（圖7A的116）的存在克服多晶矽層204的製程誤差並使得跨越（across）矽晶片706的上部表面均勻且無凸起缺陷。
如圖8的剖視圖800中所繪示，執行圖案化製程，以移除位於第一開口和第二開口（圖7A的第一開口702、第二開口704）下方的部分閘極介電層112、第一介電層114、金屬層116以及多晶矽層204。圖案化製程分別定義第一孔802和第二孔804。在一些實施例中，可藉由將第一開口和第二開口（圖7A的第一開口702、第二開口704）下方的層暴露於蝕刻劑806來執行圖案化製程。舉例來說，可藉由微影/蝕刻製程和/或其它適合的圖案化製程來執行所述圖案化製程。
形成第一源極/汲極區102和第二源極/汲極區104於第一孔802和第二孔804正下方的基底101內。形成第一矽化區102a和第二矽化區104a於第一孔802和第二孔804正下方的基底101內。舉例來說，可藉由離子植入和/或將摻質植入到基底101中的其它適合的摻雜製程來形成第一源極/汲極區102和第二源極/汲極區104。
如圖9的剖視圖900中所繪示，形成蝕刻停止層208於罩幕層210上方並襯於第一孔802和第二孔804的內表面。蝕刻停止層208在第一孔802和第二孔804內具有U型。
如圖10的剖視圖1000中所繪示，形成第三介電層206於蝕刻停止層208上方。第三介電層206完全填滿第一孔802和第二孔804。沿水平線1002執行平坦化製程（產生圖11中所示出的結構）。平坦化製程移除部分的罩幕層210、蝕刻停止層208以及第三介電層206。舉例來說，可藉由化學機械平坦化（chemical mechanical planarization；CMP）製程和/或其它適合的平坦化製程來執行平坦化。
如圖11的剖視圖1100中所繪示，形成第二罩幕層1102於罩幕層210、蝕刻停止層208以及第三介電層206上方。第二罩幕層1102包括定義位於多晶矽層204正上方的第三開口1104的側壁。
如圖12的剖視圖1200中所繪示，執行圖案化製程，以移除部分的罩幕層210和多晶矽層204，並定義第三孔1204。在一些實施例中，圖案化製程移除約5埃到約150埃的多晶矽層204，產生比多晶矽層204的外部部分更薄的多晶矽層204的中心部分。在一些實施例中，可藉由將第三開口（圖11的1104）下方的多晶矽層204暴露於蝕刻劑1202來執行圖案化製程。舉例來說，可藉由微影/蝕刻製程和/或其它適合的圖案化製程來執行所述圖案化製程。
如圖13的剖視圖1300中所繪示，形成導電層1304於第三孔1204正下方的多晶矽層204上方。在一些實施例中，導電層1304形成於多晶矽層204的中心部分上方，且從多晶矽層204的最外側壁橫向後移非零間隙。在一些實施例中，導電層1304可例如為或包括鎳、鉑、鈀、鈷、鈦、矽化鎳（NiSi）、矽化鈷（CoSi）、矽化鈦（TiSi）、矽化銅（CuSi）或其類似物，且被形成為厚度約25埃、50埃、75埃或處於約5埃到約150埃的範圍內。
進行退火製程1306，以將多晶矽層204的中心部分和導電層1304轉換成FUSI層（圖14的118）。退火製程1306將整個厚度的多晶矽層204的中心部分轉換成FUSI層（圖14的118）。FUSI層（圖14的118）可例如為或包括NiSi、CoSi、TiSi、CuSi或其類似物的矽化物，且被形成為厚度約169埃、150埃、300埃或處於約125埃到約325埃的範圍內。在一些實施例中，位於所述中心部分以外的部分多晶矽層（例如圖14的FUSI層118的外側壁以外的部分多晶矽層204）被部分和/或完全矽化。
如圖14的剖視圖1400中所繪示，藉由蝕刻製程（未繪示）移除第二罩幕層（圖13的1102）。在一些實施例中，蝕刻製程可使用乾式蝕刻劑。在其它實施例中，蝕刻製程可使用濕式蝕刻劑（例如，丙酮、1-甲基-2-吡咯烷酮（NMP）或其類似物）。形成第二介電層212於FUSI層118和罩幕層210上方。
如圖15的剖視圖1500中所繪示，形成第一ILD層128於第二介電層212上方。分別形成第一導電接觸窗126於第一源極/汲極區102、第二源極/汲極區104以及FUSI層118上方。
如圖16的剖視圖1600中所繪示，形成互連結構1602於圖15的結構上方。互連結構1602包括ILD層1604、ILD層1606、多個導線1622、多個通孔1620以及多個接觸墊1624。可例如藉由CVD、PVD、其它適合的沉積製程或前述的任何組合來形成ILD層1604及ILD層1606。所述多個導線1622、多個通孔1620以及多個接觸墊1624可例如分別藉由以下方法來形成：利用通孔1620、導線1622或接觸墊1624的圖案將ILD層1604、ILD層1606圖案化，以形成通孔、導線或接觸墊開口；沉積導電層，以填充通孔、導線、接觸墊開口並上覆於ILD層1604、ILD層1606；以及對導電層執行平坦化直到到達ILD層1604或ILD層1606。可例如藉由微影/蝕刻製程和/或其它適合的圖案化製程來執行圖案化。可例如藉由CVD、PVD、無電鍍覆、電鍍、其它適合的沉積製程或前述的任何組合來進行沉積。可例如藉由CMP和/或其它適合的平坦化製程執行平坦化。所述多個導線1622、多個通孔1620以及多個接觸墊1624可例如分別為或包括Al、Cu或其類似物。為便於說明，僅標記所述多個導線1622、多個通孔1620以及多個接觸墊1624中的一些。
圖17示出根據一些實施例的形成記憶體裝置的方法1700。雖然方法1700被說明和/或描述為一系列動作或事件，但應瞭解，所述方法不限於所說明的次序或動作。因此，在一些實施例中，這些動作可以與所說明的不同次序進行，和/或可同時進行。此外，在一些實施例中，所說明的動作或事件可細分成多個動作或事件，所細分出的多個動作或事件可與其他動作或子動作在不同時間進行或同時進行。在一些實施例中，可省略一些所說明的動作或事件，且可包括其它未說明的動作或事件。
在動作1702處，形成第一介電層於基底上方，形成第二介電層於第一介電層上方，以及形成金屬層於第二介電層上方。圖6示出對應於動作1702的一些實施例的剖視圖600。
在動作1704處，形成多晶矽層於金屬層上方並形成第一罩幕層於多晶矽層上方，第一罩幕層定義開口。圖7A示出對應於動作1704的一些實施例的剖視圖700a。
在動作1706處，移除多晶矽層、金屬層、第二介電層以及第一介電層位於開口正下方的部分，以暴露出基底的上部表面。圖8示出對應於動作1706的一些實施例的剖視圖800。
在動作1708處，形成第一源極/汲極區和第二源極/汲極區於基底內。圖8示出對應於動作1708的一些實施例的剖視圖800。
在動作1710處，形成蝕刻停止層於第一罩幕層和基底上方。圖9示出對應於動作1710的一些實施例的剖視圖900。
在動作1712處，形成第三介電層於蝕刻停止層上，第三介電層填充開口。圖10示出對應於動作1712的一些實施例的剖視圖1000。
在動作1714處，執行平坦化製程以移除部分的第一罩幕層、第三介電層以及蝕刻停止層。圖10示出對應於動作1714的一些實施例的剖視圖1000。
在動作1716處，形成第二罩幕層於第一罩幕層上方，第二罩幕層覆蓋開口。圖11示出對應於動作1716的一些實施例的剖視圖1100。
在動作1718處，移除部分的第一罩幕層和多晶矽層。圖12示出對應於動作1718的一些實施例的剖視圖1200。
在動作1720處，形成導電層於多晶矽層上方。圖13示出對應於動作1720的一些實施例的剖視圖1300。
在動作1722處，將導電層和多晶矽層的中心區轉換成FUSI層。圖13示出對應於動作1722的一些實施例的剖視圖1300。
在動作1724處，形成ILD層於FUSI層和第一罩幕層上方。圖15示出對應於動作1724的一些實施例的剖視圖1500。
因此，在一些實施例中，本申請有關於一種MOSFET裝置，其包括具有形成於金屬層正上方的較薄FUSI層的閘極結構。
在一些實施例中，本申請提供一種用於形成完全矽化（FUSI）閘控裝置的方法，所述方法包括：在基底上方的閘極結構上形成罩幕層，閘極結構包括多晶矽層；在閘極結構的相對側上的基底內形成第一源極區和第一汲極區，其中閘極結構在第一源極區和第一汲極區之前形成；執行第一移除製程以移除罩幕層的一部分並暴露多晶矽層的上部表面，其中第一源極區和第一汲極區在第一移除製程之前形成；在第一移除製程之後形成與多晶矽層的上部表面直接接觸的導電層；以及將導電層和多晶矽層轉換成FUSI層。
在一些實施例中，本申請提供一種用於形成完全矽化（FUSI）閘控裝置的方法，所述方法包括：在包括多晶矽層的閘極結構上方形成第一罩幕層，其中第一罩幕層包括分別定義開口的兩組側壁；根據第一罩幕層選擇性地蝕刻多晶矽層，以移除位於開口正下方的部分閘極結構；在開口下方的基底內形成第一源極/汲極區和第二源極/汲極區；在罩幕層上方形成第一介電層，其中第一介電層填充開口；執行平坦化製程，以移除部分的第一罩幕層和第一介電層；執行第一蝕刻，以根據位於第一罩幕層上方且覆蓋開口的第二罩幕層選擇性地移除部分第一罩幕層和部分多晶矽層；在多晶矽層上方形成導電層；以及執行退火製程，以將導電層和多晶矽層轉換成矽化物層。
在一些實施例中，本申請提供一種完全矽化（FUSI）閘控裝置，包括：井區，設置於基底內；第一介電層，接觸基底；高介電常數介電層，上覆於第一介電層；金屬層，上覆於高介電常數介電層；FUSI層，上覆於金屬層；以及多晶矽層，沿FUSI層的相對側佈置，其中多晶矽層的底部表面與FUSI層的底部表面對準，其中多晶矽層與FUSI層相比具有較大厚度。
以上概述若干實施例的特徵，以使本領域的技術人員可更好地理解本揭露的各方面。本領域的技術人員應瞭解，其可輕易地使用本揭露作為設計或修改其它製程和結構的基礎，以實現本文所介紹的實施例的相同目的和/或達到相同優點。本領域的技術人員還應認識到，此類等效構造並不脫離本揭露的精神及範圍，且本領域的技術人員可在不脫離本揭露的精神和範圍的情況下對本文進行各種改變、置換以及變更。
100、200、300、400:積體電路 101:基底 102:第一源極/汲極區 102a、104a:矽化區 104:第二源極/汲極區 106:第三源極/汲極區 108:第四源極/汲極區 110、208:蝕刻停止層 112:閘極介電層 114:第一介電層 116:金屬層 118:完全矽化層 120:側壁間隙壁 121:閘極結構 122:第一金屬氧化物半導體場效電晶體裝置 124:第二金屬氧化物半導體場效電晶體裝置 126:導電接觸窗 128:第一層間介電層 202:隔離結構 204:多晶矽層 204a:凸起缺陷 206:第三介電層 209a:第一接觸區 209b:第二接觸區 210:罩幕層 212:第二介電層 214a:中心區 214b:第一外部區 214c:第二外部區 302:第一深井區 303:第一源極/汲極擴展區 304:第一井區 305:第二源極/汲極擴展區 306:第二深井區 308:第二井區 310:第二側壁間隙壁 312:第二層間介電層 314、322:導電線 316:第三層間介電層 318:導電通孔 320:第四層間介電層 500、600、700a、800、900、1000、1100、1200、1300、1400、1500、1600:剖視圖 702:第一開口 704:第二開口 802:第一孔 804:第二孔 806、1202:蝕刻劑 1002:水平線 1102:罩幕層 1104:第三開口 1204:第三孔 1304:導電層 1306:退火製程 1602:互連結構 1604、1606:層間介電層 1620:通孔 1622:導線 1624:接觸墊 1700:方法 1702、1704、1706、1708、1710、1712、1714、1716、1718、1720、1722、1724:動作 A、A':點
結合附圖閱讀以下詳細說明會最佳地理解本揭露的各方面。應注意，根據行業中的標準慣例，各種特徵未按比例繪製。實際上，為了論述清晰起見，可任意增大或減小各種特徵的尺寸。 圖1示出一些實施例的包括兩個MOSFET裝置的積體電路（integrated circuit；IC）的剖視圖，所述兩個MOSFET裝置分別包括位於金屬層上方的薄FUSI層。 圖2示出一些實施例的包括MOSFET裝置的IC的剖視圖，所述MOSFET裝置包括位於金屬層上方的薄FUSI層。 圖3和圖4示出一些實施例的包括一對MOSFET裝置的IC的剖視圖，所述一對MOSFET裝置分別包括位於金屬層上方的薄FUSI層。 圖5、圖6、圖7A、圖8到圖16示出根據本揭露一些實施例的形成包括MOSFET裝置的記憶體裝置的方法的剖視圖，所述MOSFET裝置包括位於金屬層上方的薄FUSI層。 圖7B示出一些實施例的在金屬層上方包括薄多晶矽層的圖7A的剖視圖的俯視圖。 圖17示出根據本揭露一些實施例的形成包括MOSFET裝置的記憶體裝置的方法的流程圖，所述MOSFET裝置在金屬層上方具有薄FUSI層的。
1700:方法
1702、1704、1706、1708、1710、1712、1714、1716、1718、1720、1722、1724:動作

Claims (20)

  1. 一種形成完全矽化閘控裝置的方法，所述方法包括： (i) 在基底上方的閘極結構上形成罩幕層，所述閘極結構包括多晶矽層； (ii) 在所述閘極結構的相對側上的所述基底內形成第一源極區以及第一汲極區； (iii) 執行第一移除製程，以移除所述罩幕層的一部分，並暴露出所述多晶矽層的上部表面； (iv) 形成導電層，所述導電層與所述多晶矽層的所述上部表面直接接觸；以及 (v) 將所述導電層及所述多晶矽層轉換成完全矽化層。
  2. 如申請專利範圍第1項所述的形成完全矽化閘控裝置的方法，其中所述閘極結構更包括與所述基底接觸的第一介電層、上覆於所述第一介電層的高介電常數介電層以及設置於所述多晶矽層與所述高介電常數介電層之間的金屬層。
  3. 如申請專利範圍第1項所述的形成完全矽化閘控裝置的方法， 其中在所述第一移除製程之後，所述多晶矽層包括中心區、第一外部區以及第二外部區，所述中心區被橫向包夾在所述第一外部區與所述第二外部區之間，且所述中心區的高度小於所述第一外部區的高度及所述第二外部區的高度； 其中在將所述導電層以及所述多晶矽層轉換成所述完全矽化層之前，所述罩幕層存在於所述第一外部區以及所述第二外部區上方且不存在於所述中心區上方；以及 其中在將所述導電層以及所述多晶矽層轉換成所述完全矽化層之後，所述中心區中整個厚度的所述多晶矽層被完全矽化且轉換為所述完全矽化層。
  4. 如申請專利範圍第1項所述的形成完全矽化閘控裝置的方法，其中所述完全矽化層的厚度範圍為150埃至300埃。
  5. 如申請專利範圍第1項所述的形成完全矽化閘控裝置的方法，更包括： 在形成所述閘極結構之前在所述基底內形成井區，所述閘極結構形成於所述井區正上方。
  6. 如申請專利範圍第5項所述的形成完全矽化閘控裝置的方法，其中在將所述罩幕層形成於所述閘極結構上方之前，在所述第一源極區以及所述第一汲極區內形成矽化物。
  7. 如申請專利範圍第6項所述的形成完全矽化閘控裝置的方法，更包括： 在所述第一移除製程之前，在所述罩幕層上方形成第二介電層，其中所述第二介電層完全覆蓋位於所述多晶矽層的上部表面正上方的所述罩幕層的上部表面。
  8. 如申請專利範圍第7項所述的形成完全矽化閘控裝置的方法，更包括： 在所述第一移除製程之前，執行第一平坦化製程，以移除部分的所述罩幕層以及所述第二介電層。
  9. 一種形成完全矽化閘控裝置的方法，所述方法包括： 在包括多晶矽層的閘極結構上方形成第一罩幕層，其中所述第一罩幕層包括分別定義開口的兩組側壁； 根據所述第一罩幕層選擇性地蝕刻所述多晶矽層，以移除位於所述開口正下方的部分所述閘極結構； 在所述開口下方的基底內形成第一源極/汲極區以及第二源極/汲極區； 在所述第一罩幕層上方形成介電層，其中所述介電層填充所述開口； 執行平坦化製程，以移除部分的所述第一罩幕層以及所述介電層； 執行第一蝕刻，以根據位於所述第一罩幕層上方且覆蓋所述開口的第二罩幕層來選擇性地移除部分的所述第一罩幕層以及所述多晶矽層； 在所述多晶矽層上方形成導電層；以及 執行退火製程，以將所述導電層以及所述多晶矽層轉換成矽化物層。
  10. 如申請專利範圍第9項所述的形成完全矽化閘控裝置的方法， 其中在所述第一蝕刻之後，所述多晶矽層包括中心區、第一外部區以及第二外部區，所述中心區被橫向包夾在所述第一外部區與所述第二外部區之間且居中於所述閘極結構的中線； 其中在所述退火製程之前，所述第一罩幕層存在於所述第一外部區以及所述第二外部區上方且不存在於所述中心區上方；以及 其中在所述退火製程之後，所述中心區中的整個厚度的所述多晶矽層被完全矽化且轉換為所述矽化物層。
  11. 如申請專利範圍第10項所述的形成完全矽化閘控裝置的方法，其中所述矽化物層的厚度範圍為150埃至300埃。
  12. 如申請專利範圍第10項所述的形成完全矽化閘控裝置的方法，其中在形成所述第一罩幕層之後形成所述第一源極/汲極區以及所述第二源極/汲極區，在形成所述第一源極/汲極區以及所述第二源極/汲極區之後執行所述第一蝕刻，在所述第一蝕刻之後形成所述導電層，以及在形成所述導電層之後立即執行所述退火製程。
  13. 如申請專利範圍第10項所述的形成完全矽化閘控裝置的方法， 其中所述閘極結構更包括與所述基底接觸的閘極介電層、上覆於所述閘極介電層的高介電常數介電層，以及設置於所述多晶矽層與所述高介電常數介電層之間的氮化鈦層；以及 其中所述第一源極/汲極區以及所述第二源極/汲極區包括P型摻質。
  14. 如申請專利範圍第13項所述的形成完全矽化閘控裝置的方法，更包括： 在形成所述閘極結構的同時形成第二閘極結構，其中所述第二閘極結構包括接觸所述基底的第二閘極介電層、上覆於所述第二閘極介電層的第二高介電常數介電層、設置於第二多晶矽層與所述第二高介電常數介電層之間的第二氮化鈦層； 形成包括N型摻質的第三源極/汲極區以及第四源極/汲極區； 其中所述第一蝕刻移除部分所述第一罩幕層以及部分所述第二多晶矽層；以及 其中所述退火製程將第二導電層及所述第二多晶矽層轉換成第二矽化物層。
  15. 如申請專利範圍第13項所述的形成完全矽化閘控裝置的方法，其中所述矽化物層具有直接接觸所述氮化鈦層的底部表面。
  16. 一種完全矽化閘控裝置，包括： 第一介電層，位於基底上方； 高介電常數介電層，上覆於所述第一介電層； 金屬層，上覆於所述高介電常數介電層； 完全矽化層，上覆於所述金屬層；以及 多晶矽層，與所述完全矽化層的相對側接觸，其中所述多晶矽層的底部表面以及所述完全矽化層的底部表面與所述金屬層接觸，以及其中所述多晶矽層的厚度大於所述完全矽化層的厚度。
  17. 如申請專利範圍第16項所述的完全矽化閘控裝置，其中所述完全矽化層沿成角界面接觸所述多晶矽層，使得所述完全矽化層的寬度隨著距所述基底的距離增加而增加。
  18. 如申請專利範圍第16項所述的完全矽化閘控裝置，其中所述第一介電層為閘極氧化物，以及所述金屬層包括氮化鈦，以及所述完全矽化層的厚度範圍為150埃至300埃。
  19. 如申請專利範圍第16項所述的完全矽化閘控裝置，更包括： 第一源極/汲極區以及第二源極/汲極區，設置於所述完全矽化層的相對側上，其中所述第一源極/汲極區以及所述第二源極/汲極區包括P型摻質。
  20. 如申請專利範圍第16項所述的完全矽化閘控裝置，其中所述多晶矽層的所述厚度比所述完全矽化層的所述厚度大至少10%。
TW108102536A 2018-10-22 2019-01-23 完全矽化閘控裝置及其形成方法 TWI708282B (zh)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US201862748709P 2018-10-22 2018-10-22
US62/748,709 2018-10-22
US16/169,220 2018-10-24
US16/169,220 US11133226B2 (en) 2018-10-22 2018-10-24 FUSI gated device formation

Publications (2)

Publication Number Publication Date
TW202017010A true TW202017010A (zh) 2020-05-01
TWI708282B TWI708282B (zh) 2020-10-21

Family

ID=70279739

Family Applications (1)

Application Number Title Priority Date Filing Date
TW108102536A TWI708282B (zh) 2018-10-22 2019-01-23 完全矽化閘控裝置及其形成方法

Country Status (3)

Country Link
US (3) US11133226B2 (zh)
CN (1) CN111081548B (zh)
TW (1) TWI708282B (zh)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11133226B2 (en) * 2018-10-22 2021-09-28 Taiwan Semiconductor Manufacturing Company, Ltd. FUSI gated device formation

Family Cites Families (105)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5358879A (en) * 1993-04-30 1994-10-25 Loral Federal Systems Company Method of making gate overlapped lightly doped drain for buried channel devices
JP2606143B2 (ja) * 1994-07-22 1997-04-30 日本電気株式会社 半導体装置及びその製造方法
US6111319A (en) * 1995-12-19 2000-08-29 Stmicroelectronics, Inc. Method of forming submicron contacts and vias in an integrated circuit
US5714414A (en) * 1996-08-19 1998-02-03 Micron Technology, Inc. Semiconductor processing method of forming field isolation oxide relative to a semiconductor substrate
US6063680A (en) * 1998-02-19 2000-05-16 Texas Instruments - Acer Incorporated MOSFETS with a recessed self-aligned silicide contact and an extended source/drain junction
US6165880A (en) * 1998-06-15 2000-12-26 Taiwan Semiconductor Manufacturing Company Double spacer technology for making self-aligned contacts (SAC) on semiconductor integrated circuits
US6051470A (en) * 1999-01-15 2000-04-18 Advanced Micro Devices, Inc. Dual-gate MOSFET with channel potential engineering
US6312995B1 (en) * 1999-03-08 2001-11-06 Advanced Micro Devices, Inc. MOS transistor with assisted-gates and ultra-shallow “Psuedo” source and drain extensions for ultra-large-scale integration
US6177317B1 (en) * 1999-04-14 2001-01-23 Macronix International Co., Ltd. Method of making nonvolatile memory devices having reduced resistance diffusion regions
US6069032A (en) * 1999-08-17 2000-05-30 United Silicon Incorporated Salicide process
US6544844B2 (en) * 1999-10-08 2003-04-08 Macronix International Co., Ltd. Method for forming a flash memory cell having contoured floating gate surface
US6774429B2 (en) * 2000-08-10 2004-08-10 Matsushita Electric Industrial Co., Ltd. Hybrid semiconductor device with a poly-metal gate structure
TW533539B (en) * 2002-06-13 2003-05-21 Intelligent Sources Dev Corp A scaled MOSFET device and its fabricating method
US6713393B2 (en) * 2002-06-20 2004-03-30 Intelligent Sources Development Corp. Method of forming a nanometer-gate MOSFET device
US6894353B2 (en) * 2002-07-31 2005-05-17 Freescale Semiconductor, Inc. Capped dual metal gate transistors for CMOS process and method for making the same
KR100456699B1 (ko) * 2002-10-04 2004-11-10 삼성전자주식회사 하부 막질에 대한 하부 전극의 접촉 구조 및 그 형성 방법
KR100480636B1 (ko) * 2002-11-22 2005-03-31 삼성전자주식회사 반도체 장치의 제조방법
TW573333B (en) * 2003-03-03 2004-01-21 Promos Technologies Inc Semiconductor device and manufacturing method thereof
US7067379B2 (en) * 2004-01-08 2006-06-27 Taiwan Semiconductor Manufacturing Company, Ltd. Silicide gate transistors and method of manufacture
US7285829B2 (en) * 2004-03-31 2007-10-23 Intel Corporation Semiconductor device having a laterally modulated gate workfunction and method of fabrication
US7279735B1 (en) * 2004-05-05 2007-10-09 Spansion Llc Flash memory device
US7498641B2 (en) * 2004-05-28 2009-03-03 Taiwan Semiconductor Manufacturing Company, Ltd. Partial replacement silicide gate
US7582931B2 (en) 2004-06-04 2009-09-01 Samsung Electronics Co., Ltd. Recessed gate electrodes having covered layer interfaces and methods of forming the same
US7018901B1 (en) * 2004-09-29 2006-03-28 Freescale Semiconductor, Inc. Method for forming a semiconductor device having a strained channel and a heterojunction source/drain
JP4440080B2 (ja) * 2004-11-12 2010-03-24 株式会社東芝 半導体装置およびその製造方法
US7195969B2 (en) 2004-12-31 2007-03-27 Taiwan Semiconductor Manufacturing Co., Ltd. Strained channel CMOS device with fully silicided gate electrode
US7538351B2 (en) * 2005-03-23 2009-05-26 Taiwan Semiconductor Manufacturing Co., Ltd. Method for forming an SOI structure with improved carrier mobility and ESD protection
KR100724563B1 (ko) * 2005-04-29 2007-06-04 삼성전자주식회사 다중 일함수 금속 질화물 게이트 전극을 갖는 모스트랜지스터들, 이를 채택하는 씨모스 집적회로 소자들 및그 제조방법들
US20060255405A1 (en) * 2005-05-12 2006-11-16 National Chiao Tung University Fully-depleted SOI MOSFET device and process for fabricating the same
US20060273410A1 (en) * 2005-06-07 2006-12-07 National University Of Singapore Thermally stable fully silicided Hf silicide metal gate electrode
JP2006344836A (ja) * 2005-06-09 2006-12-21 Matsushita Electric Ind Co Ltd 半導体装置及びその製造方法
JP2007059691A (ja) * 2005-08-25 2007-03-08 Matsushita Electric Ind Co Ltd 半導体装置の製造方法および半導体装置
EP1927135A2 (en) * 2005-09-15 2008-06-04 Nxp B.V. Method of manufacturing semiconductor device with different metallic gates
JP2007081249A (ja) * 2005-09-15 2007-03-29 Matsushita Electric Ind Co Ltd 半導体装置及びその製造方法
JP2007103694A (ja) * 2005-10-05 2007-04-19 Matsushita Electric Ind Co Ltd 半導体装置及びその製造方法
CN1945852A (zh) * 2005-10-06 2007-04-11 松下电器产业株式会社 半导体装置及其制造方法
JP4928890B2 (ja) * 2005-10-14 2012-05-09 株式会社東芝 不揮発性半導体記憶装置
JP2007123431A (ja) * 2005-10-26 2007-05-17 Matsushita Electric Ind Co Ltd 半導体装置及びその製造方法
JP2007123632A (ja) * 2005-10-28 2007-05-17 Matsushita Electric Ind Co Ltd 半導体装置及びその製造方法
JP5157450B2 (ja) * 2005-11-28 2013-03-06 日本電気株式会社 半導体装置およびその製造方法
JP2007158220A (ja) * 2005-12-08 2007-06-21 Matsushita Electric Ind Co Ltd 半導体装置の製造方法
JP2007242894A (ja) * 2006-03-08 2007-09-20 Toshiba Corp 半導体装置およびその製造方法
US8153832B2 (en) * 2006-04-03 2012-04-10 L'air Liquide Societe Anonyme Pour L'etude Et L'exploitation Des Procedes Georges Claude Pentakis(dimethylamino) disilane precursor comprising compound and method for the preparation thereof
JP2008028107A (ja) * 2006-07-20 2008-02-07 Matsushita Electric Ind Co Ltd 半導体装置及びその製造方法
EP1900681B1 (en) * 2006-09-15 2017-03-15 Imec Tunnel Field-Effect Transistors based on silicon nanowires
US7893476B2 (en) * 2006-09-15 2011-02-22 Imec Tunnel effect transistors based on silicon nanowires
US7374980B2 (en) * 2006-10-13 2008-05-20 International Business Machines Corporation Field effect transistor with thin gate electrode and method of fabricating same
JP2008140853A (ja) * 2006-11-30 2008-06-19 Matsushita Electric Ind Co Ltd 半導体装置及びその製造方法
JP2008159614A (ja) * 2006-12-20 2008-07-10 Toshiba Corp 不揮発性半導体メモリ
JP4861204B2 (ja) * 2007-01-22 2012-01-25 株式会社東芝 半導体装置およびその製造方法
US7439134B1 (en) * 2007-04-20 2008-10-21 Freescale Semiconductor, Inc. Method for process integration of non-volatile memory cell transistors with transistors of another type
JP2009004444A (ja) * 2007-06-19 2009-01-08 Panasonic Corp 半導体装置及びその製造方法
US20090007037A1 (en) * 2007-06-29 2009-01-01 International Business Machines Corporation Hybrid Fully-Silicided (FUSI)/Partially-Silicided (PASI) Structures
US20090001477A1 (en) * 2007-06-29 2009-01-01 Louis Lu-Chen Hsu Hybrid Fully-Silicided (FUSI)/Partially-Silicided (PASI) Structures
US8247861B2 (en) * 2007-07-18 2012-08-21 Infineon Technologies Ag Semiconductor device and method of making same
US20090053883A1 (en) 2007-08-24 2009-02-26 Texas Instruments Incorporated Method of setting a work function of a fully silicided semiconductor device, and related device
US7749822B2 (en) * 2007-10-09 2010-07-06 International Business Machines Corporation Method of forming a resistor and an FET from the metal portion of a MOSFET metal gate stack
JP2009130137A (ja) * 2007-11-22 2009-06-11 Toshiba Corp 半導体記憶装置及びその製造方法
EP2068351A1 (en) * 2007-12-03 2009-06-10 INTERUNIVERSITAIR MICROELEKTRONICA CENTRUM vzw (IMEC) Floating gate non-volatile memory device and method for manufacturing same
US8159038B2 (en) * 2008-02-29 2012-04-17 Infineon Technologies Ag Self aligned silicided contacts
US7943997B2 (en) * 2008-04-17 2011-05-17 International Business Machines Corporation Fully-depleted low-body doping field effect transistor (FET) with reverse short channel effects (SCE) induced by self-aligned edge back-gate(s)
WO2009133509A1 (en) * 2008-04-29 2009-11-05 Nxp B.V. Integrated circuit manufacturing method and integrated circuit
KR101079205B1 (ko) * 2008-08-22 2011-11-03 주식회사 하이닉스반도체 반도체 장치 및 그 제조 방법
US7943988B2 (en) * 2008-09-05 2011-05-17 Freescale Semiconductor, Inc. Power MOSFET with a gate structure of different material
JP2010080498A (ja) * 2008-09-24 2010-04-08 Toshiba Corp 不揮発性半導体記憶装置およびその製造方法
US8012817B2 (en) * 2008-09-26 2011-09-06 Taiwan Semiconductor Manufacturing Company, Ltd. Transistor performance improving method with metal gate
US8258587B2 (en) * 2008-10-06 2012-09-04 Taiwan Semiconductor Manufacturing Company, Ltd. Transistor performance with metal gate
KR101149044B1 (ko) * 2009-04-30 2012-05-24 에스케이하이닉스 주식회사 비휘발성 메모리 소자 및 그 제조 방법
US8193900B2 (en) * 2009-06-24 2012-06-05 United Microelectronics Corp. Method for fabricating metal gate and polysilicon resistor and related polysilicon resistor structure
US20110097867A1 (en) * 2009-10-22 2011-04-28 Taiwan Semiconductor Manufacturing Company, Ltd. Method of controlling gate thicknesses in forming fusi gates
US8530971B2 (en) * 2009-11-12 2013-09-10 International Business Machines Corporation Borderless contacts for semiconductor devices
JP5537130B2 (ja) * 2009-11-25 2014-07-02 株式会社東芝 半導体記憶装置
US20110248343A1 (en) * 2010-04-07 2011-10-13 International Business Machines Corporation Schottky FET With All Metal Gate
KR101676818B1 (ko) * 2010-05-19 2016-11-17 삼성전자주식회사 게이트 구조를 포함하는 반도체 소자들 및 그 제조 방법
US8349681B2 (en) * 2010-06-30 2013-01-08 Sandisk Technologies Inc. Ultrahigh density monolithic, three dimensional vertical NAND memory device
US8391068B2 (en) * 2010-12-20 2013-03-05 Texas Instruments Incorporated Adaptive programming for flash memories
US8697557B2 (en) * 2011-06-07 2014-04-15 Globalfoundries Inc. Method of removing gate cap materials while protecting active area
CN102227001B (zh) * 2011-06-23 2013-03-06 北京大学 一种锗基nmos器件及其制备方法
US9070784B2 (en) * 2011-07-22 2015-06-30 Taiwan Semiconductor Manufacturing Company, Ltd. Metal gate structure of a CMOS semiconductor device and method of forming the same
JP5667961B2 (ja) * 2011-11-04 2015-02-12 株式会社東芝 半導体装置の製造方法
US20130140442A1 (en) * 2011-12-02 2013-06-06 Sony Corporation Amplifying circuit and manufacturing method, solid-state imaging element, and electronic device
CN103165601B (zh) * 2011-12-12 2015-12-09 中芯国际集成电路制造(北京)有限公司 集成半导体器件及其制造方法
JP2013182949A (ja) * 2012-02-29 2013-09-12 Toshiba Corp 不揮発性半導体記憶装置およびその製造方法
US8569127B2 (en) * 2012-03-13 2013-10-29 United Microelectronics Corp. Semiconductor device and method for fabricating the same
US8753931B2 (en) * 2012-04-05 2014-06-17 Taiwan Semiconductor Manufacturing Company, Ltd. Cost-effective gate replacement process
US9159802B2 (en) * 2012-05-14 2015-10-13 Taiwan Semiconductor Manufacturing Company, Ltd. MOS devices with mask layers and methods for forming the same
JP2014011173A (ja) * 2012-06-27 2014-01-20 Toshiba Corp 半導体装置及びその製造方法
US9123577B2 (en) * 2012-12-12 2015-09-01 Sandisk Technologies Inc. Air gap isolation in non-volatile memory using sacrificial films
US8872285B2 (en) * 2013-03-01 2014-10-28 Globalfoundries Inc. Metal gate structure for semiconductor devices
US9236440B2 (en) * 2013-12-05 2016-01-12 Globalfoundries Inc. Sandwich silicidation for fully silicided gate formation
US9515155B2 (en) * 2013-12-20 2016-12-06 Globalfoundries Inc. E-fuse design for high-K metal-gate technology
US9349734B2 (en) * 2014-09-03 2016-05-24 Globalfoundries Inc. Selective FuSi gate formation in gate first CMOS technologies
US9666590B2 (en) * 2014-09-24 2017-05-30 Sandisk Technologies Llc High stack 3D memory and method of making
US9472642B2 (en) * 2014-12-09 2016-10-18 Globalfoundries Inc. Method of forming a semiconductor device structure and such a semiconductor device structure
US9954067B2 (en) * 2015-02-26 2018-04-24 Taiwan Semiconductor Manufacturing Company Ltd. Semiconductor device and manufacturing method thereof
US10134641B2 (en) * 2015-05-21 2018-11-20 CoolStar Technology, Inc. Enhanced integration of DMOS and CMOS semiconductor devices
US9570568B2 (en) * 2015-05-28 2017-02-14 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor component and method for fabricating the same
US9780193B2 (en) * 2015-10-27 2017-10-03 United Microelectronics Corporation Device with reinforced metal gate spacer and method of fabricating
US10825905B2 (en) * 2016-06-01 2020-11-03 Taiwan Semiconductor Manufacturing Co., Ltd. Thin poly field plate design
US10431670B2 (en) * 2016-12-15 2019-10-01 Taiwan Semiconductor Manufacturing Co., Ltd Source and drain formation technique for fin-like field effect transistor
US10056481B2 (en) * 2017-01-13 2018-08-21 Globalfoundries Inc. Semiconductor device structure
CN109494222B (zh) * 2017-09-13 2020-10-09 联华电子股份有限公司 半导体存储装置
US10340357B2 (en) * 2017-09-25 2019-07-02 Taiwan Semiconductor Manufacturing Co., Ltd. Dishing prevention dummy structures for semiconductor devices
US10510685B2 (en) * 2017-09-29 2019-12-17 Taiwan Semiconductor Manufacturing Co., Ltd. Dishing prevention columns for bipolar junction transistors
US11133226B2 (en) * 2018-10-22 2021-09-28 Taiwan Semiconductor Manufacturing Company, Ltd. FUSI gated device formation

Also Published As

Publication number Publication date
TWI708282B (zh) 2020-10-21
US20200126870A1 (en) 2020-04-23
CN111081548A (zh) 2020-04-28
US20210384082A1 (en) 2021-12-09
CN111081548B (zh) 2023-04-18
US20230377992A1 (en) 2023-11-23
US11133226B2 (en) 2021-09-28
US11823959B2 (en) 2023-11-21

Similar Documents

Publication Publication Date Title
TWI524397B (zh) 具有改善的閾値電壓表現的取代金屬閘極的積體電路及其製造方法
KR102254439B1 (ko) 반도체 장치
US11569363B2 (en) Dishing prevention dummy structures for semiconductor devices
US8420473B2 (en) Replacement gate devices with barrier metal for simultaneous processing
US8609484B2 (en) Method for forming high-K metal gate device
TWI669817B (zh) 積體晶片及其形成方法
TWI484567B (zh) 半導體結構與其製造方法
WO2019128500A1 (zh) 半导体器件及其制作方法
TWI748271B (zh) 積體晶片及其形成方法
TW201724219A (zh) 積體電路
US11688789B2 (en) Semiconductor device with reduced flicker noise
JP5752810B2 (ja) 半導体装置
US9299616B1 (en) Integrated circuits with separate workfunction material layers and methods for fabricating the same
KR20070015004A (ko) 실리사이드화된 게이트의 형성 방법
US20090224327A1 (en) Plane mos and the method for making the same
US20230377992A1 (en) Fusi gated device formation
KR20160082463A (ko) 반도체 소자 구조물 및 그 형성 방법
TW202005082A (zh) 用於減低半導體裝置中閘極導致的汲極洩漏的方法及相關設備
TWI836689B (zh) 半導體裝置及其形成方法
US20240071833A1 (en) Hybrid fin-dielectric semiconductor device
US11177212B2 (en) Contact formation method and related structure
JP2019046875A (ja) 半導体装置およびその製造方法
TWI723471B (zh) 半導體結構及半導體製造方法
US20240021475A1 (en) Semiconductor structure and methods for manufacturing the same
JP2006066757A (ja) 半導体装置