TW202015340A - Low power logic circuit - Google Patents

Low power logic circuit Download PDF

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TW202015340A
TW202015340A TW108121135A TW108121135A TW202015340A TW 202015340 A TW202015340 A TW 202015340A TW 108121135 A TW108121135 A TW 108121135A TW 108121135 A TW108121135 A TW 108121135A TW 202015340 A TW202015340 A TW 202015340A
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tft
logic circuit
logic
gate
transistor
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克里斯 曼尼
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比利時商愛美科公司
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/08—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices
    • H03K19/094—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors
    • H03K19/0944—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors using MOSFET or insulated gate field-effect transistors, i.e. IGFET
    • H03K19/09441—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors using MOSFET or insulated gate field-effect transistors, i.e. IGFET of the same canal type
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/08—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices
    • H03K19/094—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors
    • H03K19/0944—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors using MOSFET or insulated gate field-effect transistors, i.e. IGFET
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/01—Modifications for accelerating switching
    • H03K19/017—Modifications for accelerating switching in field-effect transistor circuits
    • H03K19/01707—Modifications for accelerating switching in field-effect transistor circuits in asynchronous circuits
    • H03K19/01721—Modifications for accelerating switching in field-effect transistor circuits in asynchronous circuits by means of a pull-up or down element

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  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Power Engineering (AREA)
  • Logic Circuits (AREA)

Abstract

The invention relates to a logic circuit. The logic circuit comprises a first thin film transistor, TFT, having a gate connected to an input of the logic circuit, and a drain connected to an output of the logic circuit. The logic circuit further comprises a second TFT having a source connected to the output of the logic circuit. The logic circuit further comprises a third TFT having a gate connected to the input of the logic circuit, a source connected to the source of the second TFT, and a drain connected to a gate of the second TFT. The logic circuit further comprises a fourth TFT having a gate connected to the output of the logic circuit, and a source connected to the gate of the second TFT and the drain of the third TFT.

Description

低功率邏輯電路Low power logic circuit

本發明大體上係關於邏輯電路，且更明確言之，係關於用於薄膜單極電路之一電路拓撲，其組合二極體負載邏輯之高速效能及操作期間零VGS邏輯之低功耗。The present invention relates generally to logic circuits, and more specifically, to a circuit topology for thin film unipolar circuits that combines the high-speed performance of diode load logic and the low power consumption of zero VGS logic during operation.

在過去幾年中，用薄膜電晶體(TFT)實施之電路越來越受歡迎。此主要歸因於由用TFT實施之電路所呈現之效能之增加及亦不斷增長之應用領域，諸如低成本RFID/NFC標籤、用於顯示器及生物醫學貼片之整合式掃描驅動器。許多薄膜電路(諸如標籤及掃描驅動器)嚴重依賴於數位電路方塊。Over the past few years, circuits implemented with thin-film transistors (TFTs) have become increasingly popular. This is mainly due to the increased performance presented by circuits implemented with TFTs and also growing applications, such as low-cost RFID/NFC tags, integrated scan drivers for displays and biomedical patches. Many thin-film circuits (such as tags and scan drivers) rely heavily on digital circuit blocks.

然而，由於某些薄膜電晶體技術(諸如金屬氧化物或有機物)之單極性質，現今設計中存在之數位方塊遭受大功率消耗。提供具有低功耗之電路將增強行動裝置及顯示器之電池壽命且能夠增加RFID標籤之複雜性等。However, due to the unipolar nature of certain thin film transistor technologies (such as metal oxides or organics), the digital blocks present in today's designs suffer from high power consumption. Providing circuits with low power consumption will enhance the battery life of mobile devices and displays and increase the complexity of RFID tags.

當前高功耗之一個原因係不存在互補薄膜裝置。產生互補裝置所需之額外層遮罩增加電路之製造成本。另外，一些技術缺乏匹配半導體之互補替代方案，其限制互補邏輯之實現。該領域中之主要重點係尋找基於單極技術之替代電路組態，主要關注與二極體負載或零VGS負載邏輯相比增強之穩健性及速度。One reason for current high power consumption is the absence of complementary thin film devices. The additional layer masks needed to create complementary devices increase the manufacturing cost of the circuit. In addition, some technologies lack complementary alternatives to match semiconductors, which limit the implementation of complementary logic. The main focus in this field is to find alternative circuit configurations based on unipolar technology, focusing on the enhanced robustness and speed compared to diode loads or zero VGS load logic.

T. C. Huang等人之「Pseudo-CMOS：A Design Style for Low-Cost and Robust Flexible Electronics」2011年1月之IEEE Transactions on Electron Devices，第58卷，第1號，第141-150頁揭示偽CMOS之使用。與一常規2-TFT反相器相比，此拓撲提供經改良穩健性及速度且使用四個TFT實施以實現一反相器。缺點仍係一高功耗及必須具有兩個供應電壓及一接地連接(VDD及VBIAS或VSS)。TC Huang et al. "Pseudo-CMOS: A Design Style for Low-Cost and Robust Flexible Electronics" IEEE Transactions on Electron Devices, Vol. 58, No. 1, pages 141-150, January 2011 use. Compared to a conventional 2-TFT inverter, this topology provides improved robustness and speed and is implemented using four TFTs to implement an inverter. The disadvantage is still a high power consumption and must have two supply voltages and a ground connection (VDD and VBIAS or VSS).

K. Myny等人之「Robust digital design in organic electronics by dual-gate technology」，2010年IEEE國際固態電路會議-(ISSCC)，加利福尼亞州舊金山，2010年，第140-141頁揭示藉由添加一背閘極來增加其穩健性之二極體負載邏輯。與偽CMOS邏輯相比，雙閘極二極體負載邏輯減少晶片面積，但當輸出一邏輯0時，歸因於負載電晶體之導通狀態，功耗仍係大的。K. Myny et al. "Robust digital design in organic electronics by dual-gate technology", 2010 IEEE International Conference on Solid-State Circuits (ISSCC), San Francisco, California, 2010, pages 140-141 revealed by adding a back Gate to increase the robustness of the diode load logic. Compared with pseudo-CMOS logic, dual-gate diode load logic reduces the chip area, but when a logic 0 is output, the power consumption is still large due to the on state of the load transistor.

J. S. Kim等人之「Dynamic Logic Circuits using a-IGZO TFTs」2017年10月之IEEE Transactions on Electron Devices，第64卷，第10號，第4123-4130頁揭示使用動態邏輯，其增加速度且減小尺寸，但代價係對臨限值電壓及時序之高靈敏度，且需要複雜時脈分佈系統。JS Kim et al. "Dynamic Logic Circuits using a-IGZO TFTs" October 2017 IEEE Transactions on Electron Devices, Volume 64, Number 10, pages 4123-4130 reveals the use of dynamic logic, which increases speed and decreases Size, but the cost is high sensitivity to threshold voltage and timing, and requires a complex clock distribution system.

M. Venturelli等人之「Unipolar Differential Logic for Large-Scale Integration of Flexible alGZO Circuits」，IEEE Transactions on Circuits and Systems II：Express Briefs，第64卷，第5號，第565-569頁，2017年5月揭示使用差分邏輯用於高靜態雜訊邊際，但代價係每個反相器不少於8個電晶體；及因而晶片面積。M. Venturelli et al. "Unipolar Differential Logic for Large-Scale Integration of Flexible alGZO Circuits", IEEE Transactions on Circuits and Systems II: Express Briefs, Volume 64, No. 5, pages 565-569, May 2017 Reveal the use of differential logic for high static noise margins, but at the cost of not less than 8 transistors per inverter; and thus the chip area.

N. P. Papadopoulos等人之「Low-Power Bootstrapped Rail-to-Rail Logic Gates for Thin-Film Applications」2016年12月之Journal of Display Technology，第12卷，第12號，第1539-1546頁揭示一種具有低功耗之自舉反相器，但此拓撲亦使用每個反相器之五個電晶體。NP Papadopoulos et al. "Low-Power Bootstrapped Rail-to-Rail Logic Gates for Thin-Film Applications" Journal of Display Technology, Volume 12, Number 12, No. 12, pages 1539-1546, December 2016 Power-consumption bootstrap inverters, but this topology also uses five transistors per inverter.

鑑於上文，本發明之一目的係提供一替代電路拓撲，其提供功耗之一降低同時仍提供一高操作速度。本發明之一進一步目的係提供一邏輯電路，其避免VDD與接地之間的多個電流分支。藉由提供具有獨立技術方案中界定之特徵之一邏輯電路來達成此等及其他目的。較佳實施例在附屬技術方案中界定。In view of the above, an object of the present invention is to provide an alternative circuit topology that provides a reduction in power consumption while still providing a high operating speed. A further object of the invention is to provide a logic circuit that avoids multiple current branches between VDD and ground. These and other objectives are achieved by providing a logic circuit with the features defined in the independent technical solution. The preferred embodiments are defined in the accompanying technical solutions.

根據本發明之一第一態樣，提供一種邏輯電路。該邏輯電路包括一第一薄膜電晶體TFT，其具有連接至該邏輯電路之一輸入的一閘極及連接至該邏輯電路之一輸出的一汲極。該邏輯電路進一步包括一第二TFT，其具有連接至該邏輯電路之該輸出的一源極。該邏輯電路進一步包括一第三TFT，其具有連接至該邏輯電路之該輸入的一閘極、連接至該第二TFT之該源極的一源極及連接至該第二TFT之一閘極的一汲極。該邏輯電路進一步包括一第四TFT，其具有連接至該邏輯電路之該輸出的一閘極及連接至該第二TFT之該閘極及該第三TFT之該汲極的一源極。According to a first aspect of the invention, a logic circuit is provided. The logic circuit includes a first thin film transistor TFT having a gate connected to an input of the logic circuit and a drain connected to an output of the logic circuit. The logic circuit further includes a second TFT having a source connected to the output of the logic circuit. The logic circuit further includes a third TFT having a gate connected to the input of the logic circuit, a source connected to the source of the second TFT, and a gate connected to the second TFT A Jiji. The logic circuit further includes a fourth TFT having a gate connected to the output of the logic circuit and a source connected to the gate of the second TFT and the drain of the third TFT.

本發明係基於如下想法：為數位方塊提供一替代拓撲(在下文中指稱交叉邏輯)，其與先前技術解決方案相比提供功耗之一顯著降低同時仍保持一相當高操作速度。由於速度在大多數系統中係重要的，因此交叉邏輯可與二極體負載邏輯或偽CMOS邏輯組合使用且尤其可用於速度不重要之區段，藉此降低一系統之總功耗而不犧牲運行速度。The present invention is based on the idea of providing an alternative topology for digital blocks (referred to below as crossover logic) that provides a significant reduction in power consumption compared to prior art solutions while still maintaining a fairly high operating speed. Since speed is important in most systems, cross logic can be used in combination with diode load logic or pseudo-CMOS logic and can be used especially in speed-unimportant sections, thereby reducing the total power consumption of a system without sacrificing Running speed.

因此，本發明之一優點係邏輯電路之拓撲在操作期間當輸入信號變化時藉由自二極體負載邏輯之高速操作交叉至零VGS邏輯之低功率操作來即時組合二極體負載邏輯及零VGS邏輯之優點。一進一步優點係，與先前技術相比，藉由較低複雜性之一邏輯電路達成低功耗及高速度之組合。Therefore, one of the advantages of the present invention is that the topology of the logic circuit is real-time combination of the diode load logic and zero by the low power operation from the high speed operation of the diode load logic to the zero VGS logic when the input signal changes during operation Advantages of VGS logic. A further advantage is that, compared to the prior art, a combination of low power consumption and high speed is achieved by a logic circuit of lower complexity.

本發明係關於一種邏輯電路。術語邏輯電路此處意謂實質上用於對一或多個輸入信號執行一邏輯運算之任何電子電路。邏輯電路可為一「AND」、「NOT」(反相器)、「NAND」、「OR」、「NOR」或互斥「OR」，其等亦可組合成更複雜電路。因此，邏輯電路可具有一或多個輸入及一或多個輸出，其取決於電路待執行之操作。The invention relates to a logic circuit. The term logic circuit here means essentially any electronic circuit used to perform a logical operation on one or more input signals. The logic circuit can be an "AND", "NOT" (inverter), "NAND", "OR", "NOR" or mutually exclusive "OR", which can also be combined into a more complex circuit. Therefore, a logic circuit may have one or more inputs and one or more outputs, depending on the operation to be performed by the circuit.

該邏輯電路包括薄膜電晶體，其等可使用任何薄膜技術實施，該薄膜技術具有可用之正臨限值電壓及負臨限值電壓兩者之裝置，例如，使用非晶矽、有機半導體、氧化物半導體或低溫多晶矽、LTPS實施之裝置。可藉由固有裝置性質(例如摻雜、半導體之選擇、通道之長度等)或藉由一第二閘極(背閘極)來控制臨限值電壓以控制通道性質。The logic circuit includes thin-film transistors, etc., which can be implemented using any thin-film technology with devices that have both positive threshold voltages and negative threshold voltages available, for example, using amorphous silicon, organic semiconductors, oxides The implementation of physical semiconductor or low temperature polysilicon, LTPS. The threshold voltage can be controlled by inherent device properties (such as doping, semiconductor selection, channel length, etc.) or by a second gate (back gate) to control channel properties.

在下文中，術語源極、汲極及閘極在技術領域中具有其等正常含義，即TFT之源極係載子通過其進入通道之端子，汲極係載子通過其離開通道之端子，且閘極係調變通道導電性之端子。In the following, the terms source, drain and gate have their normal meanings in the technical field, ie the source of the TFT is the terminal through which the carrier enters the channel and the drain is the terminal through which the carrier leaves the channel, and The gate is a terminal to modulate the conductivity of the channel.

根據本發明之一實施例，該第一TFT具有連接至一第一電源供應軌道之一源極。According to an embodiment of the invention, the first TFT has a source connected to a first power supply rail.

此實施例之一優點在於第一TFT之源極可充當供應軌道與邏輯電路之剩餘者之間的一連接點用於使得電流能夠流動通過邏輯電路。因此，可藉由控制第一TFT之狀態來控制在操作期間流動通過邏輯電路之電流，藉此降低邏輯電路之總功耗。One advantage of this embodiment is that the source of the first TFT can serve as a connection point between the supply rail and the rest of the logic circuit for enabling current to flow through the logic circuit. Therefore, the current flowing through the logic circuit during operation can be controlled by controlling the state of the first TFT, thereby reducing the total power consumption of the logic circuit.

術語「供應軌道」此處意謂任何電導體(諸如一電線、一電路板或晶片上之跡線或其類似者)，其能夠為邏輯電路提供一經界定正或負電位(諸如-12 V、-5 V、-3 V、0 V(接地)、3 V、5 V、12 V)以便為邏輯電路之操作提供電力。本技術領域中之供應軌道通常命名為VDD (正)、VSS (負)、GND、VCC (正)及VEE (負)。The term "supply rail" here means any electrical conductor (such as a wire, a trace on a circuit board or a wafer, or the like) that can provide a defined positive or negative potential (such as -12 V, -5 V, -3 V, 0 V (ground), 3 V, 5 V, 12 V) to provide power for the operation of logic circuits. The supply rails in this technical field are generally named VDD (positive), VSS (negative), GND, VCC (positive) and VEE (negative).

根據本發明之一實施例，該第二TFT及該第四TFT各具有連接至一第二電源供應軌道之一汲極。According to an embodiment of the invention, the second TFT and the fourth TFT each have a drain connected to a second power supply rail.

此實施例之一優點在於，當輸出係高時，第二TFT及第四TFT可提供一強上拉，此係歸因於第二TFT之閘極基本上經由第四TFT之通道連接至供應軌道，藉此致使邏輯電路作為高速二極體負載邏輯操作。One advantage of this embodiment is that when the output is high, the second TFT and the fourth TFT can provide a strong pull-up. This is due to the fact that the gate of the second TFT is basically connected to the supply through the channel of the fourth TFT Rail, thereby causing the logic circuit to operate as a high-speed diode load logic.

根據本發明之一實施例，該第一電源軌道係接地且該第二電源軌道係一正供應電壓。According to an embodiment of the invention, the first power rail is grounded and the second power rail is a positive supply voltage.

此實施例之一優點在於減輕與偽CMOS相關之問題，該偽CMOS除一接地連接外亦需要兩個供應電壓(VDD及VSS、VBIAS、VDD2等)。One advantage of this embodiment is to alleviate the problems associated with pseudo CMOS, which requires two supply voltages (VDD and VSS, VBIAS, VDD2, etc.) in addition to a ground connection.

根據本發明之一實施例，該第一TFT具有一臨限值電壓VT1 ，其高於該第二TFT之一臨限值電壓VT2 。According to an embodiment of the present invention, the first TFT has a threshold voltage V T1 that is higher than a threshold voltage V T2 of the second TFT.

此實施例之一優點在於，當輸入處之信號係低時，第一TFT之洩漏電流係低，且第二TFT可傳導足夠電流，使得當輸入處之信號自高轉變至低時促進在輸出處自低至高的一轉變。One advantage of this embodiment is that when the signal at the input is low, the leakage current of the first TFT is low, and the second TFT can conduct enough current so that the output at the input changes from high to low. A change from low to high.

術語「臨限值電壓」此處意謂在TFT之源極端子與汲極端子之間產生一導電路徑所需之閘極至源極電壓。The term "threshold voltage" here means the gate-to-source voltage required to create a conductive path between the source terminal and the drain terminal of the TFT.

在下文中，術語「高」及「低」信號在技術領域內具有其正常含義，即表示一二進制1及一二進制0之兩個邏輯狀態。高信號及低信號通常由兩個不同電壓(亦可為電流)表示。為了在一高信號與一低信號之間區分，指定高臨限值及低臨限值。當信號低於低臨限值時，信號為「低」，且當高於高臨限值時，信號為「高」。舉例而言，CMOS之二進制邏輯輸入位準通常針對「低」係0 V至1/3 VDD且針對「高」係2/3 VDD至VDD，其中VDD係供應電壓。TTL之對應典型位準對於「低」係0 V至0.8 V，且對於「高」係2 V，，其中VCC係5 V。單極性邏輯(諸如僅n型IGZO邏輯)通常產生不對稱傳遞曲線，導致典型位準之一不對稱劃分。In the following, the terms “high” and “low” signals have their normal meanings in the technical field, that is to say, two logic states of a binary 1 and a binary 0. The high signal and the low signal are usually represented by two different voltages (which can also be currents). In order to distinguish between a high signal and a low signal, a high threshold and a low threshold are specified. When the signal is below the low threshold, the signal is "low", and when above the high threshold, the signal is "high". For example, the binary logic input level of CMOS is usually for "low" from 0 V to 1/3 VDD and for "high" from 2/3 VDD to VDD, where VDD is the supply voltage. The corresponding typical level of TTL is 0 V to 0.8 V for the "low" system, and 2 V for the "high" system, where VCC is 5 V. Unipolar logic (such as n-type IGZO logic only) usually produces an asymmetric transfer curve, resulting in an asymmetric division of one of the typical levels.

根據本發明之一實施例，該第二TFT係一空乏模式電晶體。According to an embodiment of the invention, the second TFT is a depletion mode transistor.

術語「空乏模式電晶體」此處意謂當其閘極至源極電壓係0伏特時能夠傳導一電流之一電晶體。The term "depletion mode transistor" here means a transistor that can conduct a current when its gate-to-source voltage is 0 volts.

此實施例之一優點在於確保第二TFT能夠在其閘極至源極電壓為0時傳導一電流，使得當邏輯電路之輸入處之信號自高至低轉變時促進邏輯電路之輸出處之自低至高的一轉變。One of the advantages of this embodiment is to ensure that the second TFT can conduct a current when its gate-to-source voltage is 0, so that when the signal at the input of the logic circuit changes from high to low, it promotes the self-output at the output of the logic circuit. A transition from low to high.

根據本發明之一實施例，該第一TFT係一增強模式電晶體。According to an embodiment of the invention, the first TFT is an enhancement mode transistor.

術語「增強模式電晶體」此處意謂當其閘極至源極電壓為0時關閉(即，不傳導任何電流或一非常低洩漏電流)之一電晶體。The term "enhanced mode transistor" here means a transistor that is turned off (ie, does not conduct any current or a very low leakage current) when its gate-to-source voltage is zero.

此實施例之一優點在於確保當輸入處之信號為低時(僅可能存在一洩漏電流)在第一TFT之源極端子與汲極端子之間無實質傳導路徑。藉此大大降低邏輯電路之靜態功耗。One advantage of this embodiment is to ensure that when the signal at the input is low (only a leakage current may exist) there is no substantial conduction path between the source terminal and the drain terminal of the first TFT. This greatly reduces the static power consumption of the logic circuit.

根據本發明之一實施例，該第一TFT、該第二TFT、該第三TFT及該第四TFT之一或多者包括一背閘極。According to an embodiment of the invention, one or more of the first TFT, the second TFT, the third TFT, and the fourth TFT include a back gate.

此實施例之一優點在於可增加邏輯電路之穩健性，即提供足夠高之一雜訊邊際以確保穩定特性，因為TFT之任何者之臨限值電壓VT 可藉由施加一電壓至背閘極而調整。背閘極電壓可為一外部電壓或其可為一「內部」電壓，即背閘極可連接至邏輯電路之一內部節點，諸如(例如)邏輯電路之一輸出節點。One advantage of this embodiment is that it can increase the robustness of the logic circuit, that is, provide a sufficiently high noise margin to ensure stable characteristics, because the threshold voltage V T of any of the TFTs can be applied by applying a voltage to the back gate Extremely adjusted. The back gate voltage can be an external voltage or it can be an "internal" voltage, ie the back gate can be connected to an internal node of a logic circuit, such as, for example, an output node of a logic circuit.

術語「背閘極」此處意謂TFT之任何者提供有可影響TFT中之電場之一第四觸點。此可(例如)藉由沈積一額外絕緣層及一金屬層於TFT之頂部上來完成。根據裝置橫截面，一背閘極之函數有時指稱一頂閘極或底閘極。一TFT之臨限值電壓VT 由於相對於源極施加一電壓至背閘極而移位，即臨限值電壓VT 係源極-背閘極電壓之一線性函數。The term "back gate" here means that any of the TFTs is provided with a fourth contact that can affect the electric field in the TFT. This can be done, for example, by depositing an additional insulating layer and a metal layer on top of the TFT. Depending on the device cross-section, a function of a back gate is sometimes referred to as a top gate or bottom gate. The threshold voltage V T of a TFT is shifted by applying a voltage to the back gate relative to the source, that is, the threshold voltage V T is a linear function of the source-back gate voltage.

根據本發明之一實施例，該邏輯電路包括用於接收至該第一TFT之該背閘極的一調整信號之一第一調整輸入。According to an embodiment of the invention, the logic circuit includes a first adjustment input for receiving an adjustment signal to the back gate of the first TFT.

此實施例之一優點在於，在製造邏輯電路之後可容易地調整第一TFT之臨限值電壓，藉此促進確保第一TFT在增強模式中之操作，其繼而當輸入處之信號係低時提供通過TFT之低洩漏電流。One advantage of this embodiment is that the threshold voltage of the first TFT can be easily adjusted after the logic circuit is manufactured, thereby facilitating the operation of the first TFT in the enhancement mode, which in turn when the signal at the input is low Provides low leakage current through the TFT.

術語「調整輸入」此處意謂連接至TFT背閘極之任何電導體(諸如一電線、一電路板或晶片上之跡線或其類似者)。The term "adjust input" here means any electrical conductor connected to the back gate of the TFT (such as a wire, a circuit board or a trace on a chip or the like).

根據本發明之一實施例，該邏輯電路包括用於接收至該第二TFT之該背閘極的一調整信號之一第二調整輸入。According to an embodiment of the invention, the logic circuit includes a second adjustment input for receiving an adjustment signal to the back gate of the second TFT.

此實施例之一優點在於，在製造邏輯電路之後可容易地調整第二TFT之臨限值電壓，藉此控制第二TFT在空乏模式中之操作，使得第二TFT在其閘極至源極電壓為0時導通一電流。因此，藉由在其閘極至源極電壓為0時控制流動通過第二TFT之電流，當邏輯電路之輸入處之信號自高至低轉變時促進邏輯電路之輸出處的自低至高之一轉變。One of the advantages of this embodiment is that the threshold voltage of the second TFT can be easily adjusted after manufacturing the logic circuit, thereby controlling the operation of the second TFT in the depletion mode, so that the second TFT is at its gate to source Turn on a current when the voltage is 0. Therefore, by controlling the current flowing through the second TFT when its gate-to-source voltage is 0, when the signal at the input of the logic circuit transitions from high to low, it promotes one of the low to high at the output of the logic circuit change.

根據本發明之一實施例，該第一TFT經調適以回應於在其輸入處接收一邏輯高信號而導通且回應於在其輸入處接收一邏輯低信號而切斷。According to an embodiment of the invention, the first TFT is adapted to turn on in response to receiving a logic high signal at its input and to turn off in response to receiving a logic low signal at its input.

此實施例之一優點在於，第一TFT當輸入信號為高時將提供輸出之一強下拉且當輸入信號為低時將提供一非常低之靜態功耗。One advantage of this embodiment is that the first TFT will provide a strong pull-down of the output when the input signal is high and will provide a very low static power consumption when the input signal is low.

術語「導通」此處意謂TFT之閘極-源極電壓高於臨限值電壓，藉此在TFT之源極與汲極之間產生一導電通道(即TFT係作用中)且在源極與汲極之間傳導一電流。相反，術語「切斷」此處意謂TFT之閘極-源極電壓低於臨限值電壓，藉此阻礙在TFT之源極與汲極之間產生一導電通道(即TFT係非作用中)且除一可行小洩漏電流外，在源極與汲極之間不傳導一電流。The term "on" here means that the gate-source voltage of the TFT is higher than the threshold voltage, thereby creating a conductive channel between the source and drain of the TFT (that is, the TFT is active) and the source Conduct a current with the drain. Conversely, the term "cut-off" here means that the gate-source voltage of the TFT is lower than the threshold voltage, thereby preventing the creation of a conductive channel between the source and drain of the TFT (ie, the TFT is inactive ) In addition to a feasible small leakage current, a current is not conducted between the source and the drain.

根據本發明之一實施例，該第四TFT經調適以提供自該邏輯電路之該輸出至該第二TFT之該閘極的反饋。According to an embodiment of the invention, the fourth TFT is adapted to provide feedback from the output of the logic circuit to the gate of the second TFT.

此實施例之一優點在於，當輸出信號為高時，第二TFT及第四TFT提供一非常強上拉，藉此提供二極體負載邏輯之高速度。換言之，自邏輯電路之輸出至第四TFT及第二TFT之組合提供一正反饋，藉此確保當輸出為高時第二TFT完全傳導。One advantage of this embodiment is that when the output signal is high, the second TFT and the fourth TFT provide a very strong pull-up, thereby providing a high speed of diode load logic. In other words, the combination of the output from the logic circuit to the fourth TFT and the second TFT provides a positive feedback, thereby ensuring that the second TFT is fully conductive when the output is high.

根據本發明之一實施例，該第三TFT經調適以回應於在其輸入處接收一邏輯高輸入信號而切斷該第二TFT。According to an embodiment of the invention, the third TFT is adapted to turn off the second TFT in response to receiving a logic high input signal at its input.

此實施例之一優點在於，當輸入信號為高時，第三TFT致使邏輯電路作為一整體操作零VGS邏輯模式。第二TFT之切斷減小流動通過第二TFT之電流(僅存在一小零VGS電流)，其中邏輯電路之功耗大大降低。One advantage of this embodiment is that when the input signal is high, the third TFT causes the logic circuit to operate a zero VGS logic mode as a whole. The cutting off of the second TFT reduces the current flowing through the second TFT (only a small zero VGS current exists), in which the power consumption of the logic circuit is greatly reduced.

根據本發明之一實施例，該第一TFT經連接使得在使用時自該第二供應軌道至該第一供應軌道之流動通過該邏輯電路之所有電流流動通過該第一TFT。According to an embodiment of the invention, the first TFT is connected so that in use all current flowing through the logic circuit from the second supply rail to the first supply rail flows through the first TFT.

此實施例之一優點在於，總功耗降低，因為僅當第一TFT作用中時電流才自第二供應軌道流動至第一供應軌道。先前技術裝置包括在供應軌道之間的多個獨立電流路徑(例如，用於偏置目的)，藉此增加靜態功耗。One of the advantages of this embodiment is that the total power consumption is reduced because current flows from the second supply rail to the first supply rail only when the first TFT is active. Prior art devices include multiple independent current paths between supply rails (eg, for biasing purposes), thereby increasing static power consumption.

根據本發明之一第二態樣，提供一種邏輯電路，其包括一下拉電路，該下拉電路具有連接至該邏輯電路之一輸入的一輸入及連接至該邏輯電路之一輸出的一輸出。該下拉電路經調適以回應於在其輸入處接收一正高輸入信號而導通(即經啟動)且回應於在其輸入處接收一邏輯低信號而切斷(即經撤銷啟動)。該邏輯電路包括一上拉電路，其具有連接至該邏輯電路之該輸出的一輸出。該邏輯電路包括一反饋電路，其提供自該邏輯電路之該輸出至該上拉電路之一輸入的正反饋。該邏輯電路包括一輸入電路，其具有連接至該邏輯電路之該輸入的一輸入且經調適以回應於在其輸入處接收一邏輯高輸入信號而切斷(即經撤銷啟動)該上拉電路。According to a second aspect of the present invention, there is provided a logic circuit including a pull-down circuit having an input connected to an input of the logic circuit and an output connected to an output of the logic circuit. The pull-down circuit is adapted to turn on in response to receiving a positive high input signal at its input (that is, activated) and to turn off in response to receiving a logic low signal at its input (that is, deactivated). The logic circuit includes a pull-up circuit having an output connected to the output of the logic circuit. The logic circuit includes a feedback circuit that provides positive feedback from the output of the logic circuit to an input of the pull-up circuit. The logic circuit includes an input circuit having an input connected to the input of the logic circuit and adapted to cut off (ie, deactivated) the pull-up circuit in response to receiving a logic high input signal at its input .

將自以下[實施方式]、自隨附技術方案以及附圖明白本發明之其他目的、特徵及優點。Other objects, features, and advantages of the present invention will be understood from the following [embodiment], the accompanying technical solutions, and the drawings.

一般而言，技術方案中所使用之所有術語將根據其等在技術領域中之一般含義來解釋，除非本文另有明確定義。對「一/一個/該[元件、裝置、組件、構件、步驟等]」之所有引用將公開解釋為指代該元件、裝置、組件、構件、步驟等之至少一個例項，除非另有明確說明。本文中所揭示之任何方法之步驟不必以所揭示之確切順序執行，除非明確說明。In general, all the terms used in the technical solutions will be interpreted according to their general meanings in the technical field, unless explicitly defined otherwise herein. All references to "a/a/the [element, device, assembly, component, step, etc.]" will be publicly interpreted as referring to at least one instance of the element, device, assembly, component, step, etc., unless expressly stated otherwise Instructions. The steps of any method disclosed herein do not have to be performed in the exact order disclosed, unless explicitly stated.

圖1繪示根據本發明之一實施例之一邏輯電路100。邏輯電路100包括一第一薄膜電晶體TFT，110，其具有連接至邏輯電路之一輸入101的一閘極110a及連接至邏輯電路100之一輸出102的一汲極110b。第一TFT可指稱一驅動電晶體。邏輯電路100包括一第二TFT 120，其具有連接至邏輯電路100之輸出102的一源極120c。第二TFT可指稱一負載電晶體。該邏輯電路包括一第三TFT 130，其具有連接至邏輯電路100之輸入101的一閘極130a、連接至第二TFT 120之源極120c的一源極130c及連接至第二TFT 120之一閘極120a的一汲極130b。該邏輯電路包括一第四TFT 140，其具有連接至邏輯電路100之輸出102的一閘極140a及連接至第二TFT 120之閘極120a及第三TFT 130之汲極130b的一源極140c。FIG. 1 illustrates a logic circuit 100 according to an embodiment of the invention. The logic circuit 100 includes a first thin film transistor TFT, 110 having a gate 110a connected to an input 101 of the logic circuit and a drain 110b connected to an output 102 of the logic circuit 100. The first TFT may be referred to as a driving transistor. The logic circuit 100 includes a second TFT 120 having a source 120c connected to the output 102 of the logic circuit 100. The second TFT may be referred to as a load transistor. The logic circuit includes a third TFT 130 having a gate 130a connected to the input 101 of the logic circuit 100, a source 130c connected to the source 120c of the second TFT 120, and one of the second TFT 120 A drain 130b of the gate 120a. The logic circuit includes a fourth TFT 140 having a gate 140a connected to the output 102 of the logic circuit 100 and a source 140c connected to the gate 120a of the second TFT 120 and the drain 130b of the third TFT 130 .

第一TFT 110具有連接至一第一電源供應軌道之一源極110c，該第一供應軌道根據一較佳實施例係接地，即一零伏特電位(替代地，若邏輯電路100由p型TFT而非n型TFT實施，則第一TFT 110之源極連接至VDD，如圖1中所繪示)。第一TFT 110可進一步具有一背閘極110d，其連接至一背閘極電壓信號VBG 。第二TFT 120及第四TFT 140各具有一汲極120b、140b，其等連接至一第二電源供應軌道，根據一較佳實施例，該第二電源供應軌道係一正供應電壓VDD，諸如3 V、5 V或12 V以便為邏輯電路之操作提供電力。The first TFT 110 has a source 110c connected to a first power supply rail, which is grounded according to a preferred embodiment, ie a zero volt potential (alternatively, if the logic circuit 100 is composed of a p-type TFT Instead of an n-type TFT implementation, the source of the first TFT 110 is connected to VDD, as shown in FIG. 1). The first TFT 110 may further have a back gate 110d connected to a back gate voltage signal V BG . The second TFT 120 and the fourth TFT 140 each have a drain 120b, 140b connected to a second power supply rail. According to a preferred embodiment, the second power supply rail is a positive supply voltage VDD, such as 3 V, 5 V or 12 V to provide power for the operation of logic circuits.

本發明實施根據一發明性電路拓撲之邏輯電路，其可指稱交叉邏輯，因為其即時組合二極體負載邏輯及零VGS邏輯之優點。二極體負載邏輯使用一二極體連接電晶體作為驅動電晶體之負載。在二極體負載邏輯拓撲中，負載電晶體之閘極及汲極短接。若適當選擇負載及驅動電晶體之尺寸，則可達成具有小延遲及高速度之一邏輯電路。然而，歸因於流動通過負載電晶體之相對較高靜態電流，二極體負載邏輯之靜態功耗係高的。在零VGS負載邏輯中，負載電晶體之閘極及源極短接。因此，負載電晶體在零伏特之一恆定VGS電壓下充當一電流源。與二極體負載邏輯相比，流動通過負載電晶體之靜態電流小得多(典型地大於2個數量級)，其以一較慢操作速度為代價提供具有較低功耗之一邏輯電路。The present invention implements a logic circuit according to an inventive circuit topology, which can be referred to as cross logic, because of its immediate combination of the advantages of diode load logic and zero VGS logic. The diode load logic uses a diode connected to the transistor as the load to drive the transistor. In the diode load logic topology, the gate and drain of the load transistor are shorted. If the size of the load and the driving transistor are properly selected, a logic circuit with small delay and high speed can be achieved. However, due to the relatively high quiescent current flowing through the load transistor, the static power consumption of the diode load logic is high. In zero VGS load logic, the gate and source of the load transistor are shorted. Therefore, the load transistor acts as a current source at a constant VGS voltage of one of zero volts. Compared to diode load logic, the quiescent current flowing through the load transistor is much smaller (typically greater than 2 orders of magnitude), which provides a logic circuit with lower power consumption at the expense of a slower operating speed.

根據本發明之邏輯電路之操作機構回應於在其輸入處所接收之信號自二極體負載邏輯之高速操作跨越至零VGS負載邏輯之低功率操作。參考圖2a及圖2b，將分別針對一邏輯低輸入信號及一邏輯高輸入信號描述作為一反相器之邏輯電路之操作。The operating mechanism of the logic circuit according to the present invention is responsive to the signal received at its input from high-speed operation of diode load logic to low-power operation of zero VGS load logic. 2a and 2b, the operation of the logic circuit as an inverter will be described for a logic low input signal and a logic high input signal, respectively.

當輸入係一邏輯低信號(如Vin=0所指示)時，如圖2a中所見，邏輯電路200如二極體負載邏輯般操作。歸因於其等閘極210a、230a處之邏輯低輸入信號，第一電晶體210及第三電晶體230非作用中(如由圖2a中之交叉所指示)，節省一可行小洩漏電流，且輸出由第二電晶體220 (負載電晶體)拉高(如由Vout =1所指示)。靜態功耗由第一電晶體210之洩漏電流判定。因此，第一電晶體210較佳地設計有一高(正)臨限值電壓VT，其導致邏輯電路200之一非常小靜態功耗。由於輸出信號經由第四電晶體240反饋至第二電晶體220，所以上拉強且速度高，因為第二電晶體220之閘極220a經由作用中第四電晶體240之低阻抗通道連接至正電源供應。When the input is a logic low signal (as indicated by Vin=0), as seen in FIG. 2a, the logic circuit 200 operates as a diode load logic. Due to the logic low input signal at its equal gates 210a, 230a, the first transistor 210 and the third transistor 230 are inactive (as indicated by the cross in FIG. 2a), saving a feasible small leakage current, And the output is pulled high by the second transistor 220 (load transistor) (as indicated by V out =1). The static power consumption is determined by the leakage current of the first transistor 210. Therefore, the first transistor 210 is preferably designed with a high (positive) threshold voltage VT, which causes one of the logic circuits 200 to have very small static power consumption. Since the output signal is fed back to the second transistor 220 through the fourth transistor 240, the pull-up is strong and the speed is high because the gate 220a of the second transistor 220 is connected to the positive through the active low impedance channel of the fourth transistor 240 power supply.

當輸入係一邏輯高信號(如由Vin=1所指示)時，如圖2b中所見，邏輯電路200如零VGS邏輯般操作。第一電晶體210 (驅動電晶體)在其閘極210a處接收高輸入信號且因此作用中，其提供一強下拉，導致高速，藉此在邏輯電路200之輸出處產生一邏輯低信號(如由VOUT =0所指示)。邏輯高輸入信號亦經提供至第三電晶體230之閘極230a，其使得第三電晶體230作用中，藉此在其汲極230b與源極230c之間提供一低阻抗路徑。因此，第二電晶體220之閘極220a (充當負載)經由第三電晶體230連接至源極220c，其使得第二電晶體220在僅一小零VGS電流(其取決於臨限值電壓VT)流動通過電晶體之意義上非作用中(如由圖2b中之交叉所指示)。第二電晶體220充當第一電晶體210之供應軌道與汲極210b之間的一高阻抗方塊。第四電晶體240在其閘極240a處接收邏輯低輸出信號且因此非作用中(如由圖2b中之交叉所指示)。第四電晶體240充當第三電晶體230之供應軌道與汲極230b之間的一高阻抗方塊，藉此防止一電流自正軌道經由第四電晶體、第三電晶體及第一電晶體流動至接地。由於第一電晶體210之下拉非常強，因此功耗由第二電晶體220之小零VGS洩漏電流判定。因此，邏輯電路200之靜態功耗非常小。When the input is a logic high signal (as indicated by Vin=1), as seen in FIG. 2b, the logic circuit 200 operates as zero VGS logic. The first transistor 210 (driving transistor) receives a high input signal at its gate 210a and therefore, it provides a strong pull-down, resulting in high speed, thereby generating a logic low signal (such as (Indicated by V OUT =0). The logic high input signal is also provided to the gate 230a of the third transistor 230, which makes the third transistor 230 active, thereby providing a low impedance path between its drain 230b and source 230c. Therefore, the gate 220a (acting as a load) of the second transistor 220 is connected to the source 220c via the third transistor 230, which makes the second transistor 220 at only a small zero VGS current (which depends on the threshold voltage VT ) Flow through the transistor is inactive in the sense (as indicated by the cross in Figure 2b). The second transistor 220 serves as a high impedance block between the supply rail of the first transistor 210 and the drain 210b. The fourth transistor 240 receives a logic low output signal at its gate 240a and is therefore inactive (as indicated by the cross in Figure 2b). The fourth transistor 240 serves as a high impedance block between the supply rail of the third transistor 230 and the drain 230b, thereby preventing a current from flowing from the positive rail through the fourth transistor, the third transistor, and the first transistor To ground. Since the pull-down of the first transistor 210 is very strong, the power consumption is determined by the small zero VGS leakage current of the second transistor 220. Therefore, the static power consumption of the logic circuit 200 is very small.

如可自上文論述理解，交叉邏輯之一益處係流動通過邏輯電路之所有電流流動通過第一電晶體210。因此不存在允許電流自正供應軌道流動至接地之單獨分支(用於偏置目的)。此將有效地降低靜態功耗，因為當輸入接收使第一電晶體非作用中之一邏輯低信號時，通過電路之電流基本上經切斷(除一可行小洩漏電流流動通過第一電晶體210外)。同樣地，歸因於自輸出至第四電晶體240之反饋及第三電晶體230之連接，當輸入接收一邏輯高信號時，流動通過邏輯電路之電流基本上經切斷(除一小零VGS電流流動通過第二電晶體220外)。As can be understood from the above discussion, one of the benefits of cross logic is that all current flowing through the logic circuit flows through the first transistor 210. There is therefore no separate branch (for biasing purposes) that allows current to flow from the positive supply rail to ground. This will effectively reduce the static power consumption, because when the input receives a logic low signal in which the first transistor is inactive, the current through the circuit is basically cut off (except for a feasible small leakage current flowing through the first transistor 210 outside). Similarly, due to the feedback from the output to the fourth transistor 240 and the connection of the third transistor 230, when the input receives a logic high signal, the current flowing through the logic circuit is substantially cut off (except for a small zero VGS current flows through the second transistor 220).

二極體負載與零VGS負載之間的切換由第三電晶體230及第四電晶體240製成之一電阻分壓器完成。當輸入係一邏輯低信號時，如圖2a中所見，輸出係一邏輯高信號，且第四電晶體240經由自第四電晶體240之輸出至閘極240a的反饋而變為作用中。第三電晶體230在其閘極230a處接收邏輯低輸入信號且非作用中。視為一電阻分壓器，非作用中第三電晶體230在其汲極230b與源極230c之間呈現一阻抗，該阻抗遠高於在作用中第四電晶體240之汲極240b與源極240c之間所見之阻抗。因此，第二電晶體220之閘極220a虛擬地透過第四電晶體240連接至電源，而第三電晶體230非作用中且不下拉第二電晶體220處之閘極電位。The switching between the diode load and the zero VGS load is performed by a resistor divider made of the third transistor 230 and the fourth transistor 240. When the input is a logic low signal, as seen in FIG. 2a, the output is a logic high signal, and the fourth transistor 240 becomes active through feedback from the output of the fourth transistor 240 to the gate 240a. The third transistor 230 receives a logic low input signal at its gate 230a and is inactive. Considered as a resistor divider, the non-active third transistor 230 presents an impedance between its drain 230b and source 230c, which is much higher than the drain 240b and source of the fourth transistor 240 in action The impedance seen between pole 240c. Therefore, the gate 220a of the second transistor 220 is virtually connected to the power source through the fourth transistor 240, and the third transistor 230 is inactive and does not pull down the gate potential at the second transistor 220.

當輸入係一邏輯高信號時，如圖2b中所見，輸出係一邏輯低信號，且第四電晶體240經由自第四電晶體240之輸出至閘極240a的反饋而變為非作用中。第三電晶體230在其閘極230a處接收邏輯高輸入信號且作用中。視為一電阻分壓器，作用中第三電晶體230在其汲極230b與源極230c之間呈現一阻抗，該阻抗遠低於非作用中第四電晶體240之汲極240b與源極240c之間所見之阻抗。因此，第二電晶體220之閘極220a透過第三電晶體230虛擬地連接至第二電晶體之源極220c (及輸出)，實現零VGS操作，而第四電晶體240非作用中且不上拉第二電晶體220處之閘極電位。When the input is a logic high signal, as seen in FIG. 2b, the output is a logic low signal, and the fourth transistor 240 becomes inactive through feedback from the output of the fourth transistor 240 to the gate 240a. The third transistor 230 receives a logic high input signal at its gate 230a and is active. Considered as a resistive voltage divider, the active third transistor 230 presents an impedance between its drain 230b and source 230c, which is much lower than the drain 240b and source of the inactive fourth transistor 240 The impedance seen between 240c. Therefore, the gate electrode 220a of the second transistor 220 is virtually connected to the source electrode 220c (and output) of the second transistor 230 through the third transistor 230 to achieve zero VGS operation, while the fourth transistor 240 is inactive and does not Pull up the gate potential at the second transistor 220.

當輸入信號自一邏輯高信號變至一邏輯低信號(即1至0)時，輸出最初處於一邏輯低信號位準處，該信號位準經反饋至第四電晶體240之閘極240a，使其非作用中。此意謂第二電晶體220處於一高阻抗模式(零VGS模式)中，因為第四電晶體240不能增加第二電晶體220之閘極-源極電壓，VGS。為了邏輯電路200切換狀態，通過第二電晶體220之一洩漏電流必須對輸出再充電，直至反饋翻轉第二電晶體220之操作模式(即，自零VGS負載至二極體負載)為止。因此，在由第二電晶體220之洩漏電流設定之速度與功耗之間存在一折衷，其由其臨限值電壓VT 設定。一較高切斷電流可更快速地對輸出節點再充電，但當輸入為高時亦洩漏更多，藉此增加靜態功耗。When the input signal changes from a logic high signal to a logic low signal (ie 1 to 0), the output is initially at a logic low signal level, which is fed back to the gate 240a of the fourth transistor 240, Make it inactive. This means that the second transistor 220 is in a high impedance mode (zero VGS mode) because the fourth transistor 240 cannot increase the gate-source voltage of the second transistor 220, VGS. In order for the logic circuit 200 to switch states, the leakage current through one of the second transistors 220 must recharge the output until the operating mode of the second transistor 220 is reversed by feedback (ie, from a zero VGS load to a diode load). Therefore, there is a trade-off between the speed set by the leakage current of the second transistor 220 and the power consumption, which is set by its threshold voltage V T. A higher cutoff current can recharge the output node more quickly, but also leak more when the input is high, thereby increasing static power consumption.

第四電晶體240及第三電晶體230可經最小化以獲得面積，因為其等僅需對第二電晶體220之閘極電容充電。The fourth transistor 240 and the third transistor 230 can be minimized to obtain the area because they only need to charge the gate capacitance of the second transistor 220.

總之，已揭示用於具有低功耗、交叉邏輯之薄膜技術之一新拓撲。該拓撲使用來自二極體負載邏輯及零VGS邏輯之元件以將二極體負載邏輯之速度與零VGS邏輯之低靜態功率性質組合。舉例而言，對於具有背閘極之二極體負載邏輯，已量測靜態雜訊邊際自一5 V電源之0.475 V增加至1.572 V。另外，已量測功耗降低一因數5，而速度之降低限制於一因數2.1。新邏輯類型亦可與二極體負載邏輯完全相容。In summary, a new topology for thin film technology with low power consumption and cross logic has been revealed. This topology uses elements from diode load logic and zero VGS logic to combine the speed of the diode load logic with the low static power properties of zero VGS logic. For example, for a diode load logic with back gate, the measured static noise margin has increased from 0.475 V to 1.572 V from a 5 V power supply. In addition, it has been measured that the power consumption is reduced by a factor of 5, and the reduction in speed is limited to a factor of 2.1. The new logic type is also fully compatible with diode load logic.

以上主要參考幾個實施例描述本發明。然而，如熟習此項技術者容易瞭解，除上文所揭示之實施例外之其他實施例同樣可在由隨附專利申請專利範圍界定之本發明之範疇內。The invention has mainly been described above with reference to a few embodiments. However, as those skilled in the art can easily understand, other embodiments than the ones disclosed above can also fall within the scope of the present invention defined by the scope of the accompanying patent application.

100:邏輯電路 101:輸入 102:輸出 110:第一薄膜電晶體TFT 110a:閘極 110b:汲極 110c:源極 110d:背閘極 120:第二TFT 120a:閘極 120b:汲極 120c:源極 130:第三TFT 130a:閘極 130b:汲極 130c:源極 140:第四TFT 140a:閘極 140b:汲極 140c:源極 200:邏輯電路 210:第一電晶體 210a:閘極 220:第二電晶體 220a:閘極 220c:源極 230:第三電晶體 230a:閘極 230b:汲極 230c:源極 240:第四電晶體 240a:閘極 240b:汲極 240c:源極 VBG:背閘極電壓信號100: logic circuit 101: input 102: output 110: first thin film transistor TFT 110a: gate 110b: drain 110c: source 110d: back gate 120: second TFT 120a: gate 120b: drain 120c: Source 130: Third TFT 130a: Gate 130b: Drain 130c: Source 140: Fourth TFT 140a: Gate 140b: Drain 140c: Source 200: Logic circuit 210: First transistor 210a: Gate 220: second transistor 220a: gate 220c: source 230: third transistor 230a: gate 230b: drain 230c: source 240: fourth transistor 240a: gate 240b: drain 240c: source V BG : back gate voltage signal

將參考附圖(其中相同元件符號將用於類似元件)透過本發明之較佳實施例之以下闡釋性及非限制性詳細描述更佳地理解本發明之上述以及額外目的、特徵及優點，其中：The above and additional objects, features, and advantages of the present invention will be better understood through the following illustrative and non-limiting detailed description of preferred embodiments of the present invention with reference to the drawings in which the same element symbols will be used for similar elements. :

圖1示意性地繪示根據本發明之一較佳實施例之一邏輯電路。FIG. 1 schematically illustrates a logic circuit according to a preferred embodiment of the present invention.

圖2a示意性地繪示在二極體邏輯負載模式中操作之邏輯電路。Figure 2a schematically illustrates a logic circuit operating in a diode logic load mode.

圖2b示意性地繪示在零VGS模式中操作之邏輯電路。Figure 2b schematically illustrates a logic circuit operating in a zero VGS mode.

100:邏輯電路 100: logic circuit

101:輸入 101: input

102:輸出 102: output

110:第一薄膜電晶體TFT 110: The first thin film transistor TFT

110a:閘極 110a: gate

110b:汲極 110b: Drain

110c:源極 110c: source

110d:背閘極 110d: back gate

120:第二TFT 120: Second TFT

120a:閘極 120a: gate

120b:汲極 120b: Drain

120c:源極 120c: source

130:第三TFT 130: third TFT

130a:閘極 130a: gate

130b:汲極 130b: Drain

130c:源極 130c: source

140:第四TFT 140: Fourth TFT

140a:閘極 140a: gate

140b:汲極 140b: Drain

140c:源極 140c: source

VBG:背閘極電壓信號 V BG : back gate voltage signal

Claims (14)

一種邏輯電路(100、200)，其包括： 一第一薄膜電晶體(110、210)(TFT)，其具有連接至該邏輯電路(100、200)之一輸入(101)的一閘極(110a、210a)，及連接至該邏輯電路之一輸出的一汲極(110b、210b)， 一第二TFT (120、220)，其具有連接至該邏輯電路(100、200)之該輸出(102)的一源極(120c、220c)， 一第三TFT (130、230)，其具有連接至該邏輯電路(100、200)之該輸入(101)的一閘極(130a、230a)、連接至該第二TFT (120、220)之該源極(120c、220c)的一源極(130c，230c)及連接至該第二TFT (120、220)之一閘極(120a、220a)的一汲極(130b、230b)，及 一第四TFT (140、240)，其具有連接至該邏輯電路(100、200)之該輸出(102)的一閘極(140a、240a)，及連接至該第二TFT (120、220)之該閘極(120a、220a)及該第三TFT (130、230)之該汲極(130b、230b)的一源極(140c、240c)。A logic circuit (100, 200), including: A first thin film transistor (110, 210) (TFT) having a gate (110a, 210a) connected to an input (101) of the logic circuit (100, 200), and a gate connected to the logic circuit One drain (110b, 210b), A second TFT (120, 220) having a source (120c, 220c) connected to the output (102) of the logic circuit (100, 200), A third TFT (130, 230) having a gate (130a, 230a) connected to the input (101) of the logic circuit (100, 200), connected to the second TFT (120, 220) A source (130c, 230c) of the source (120c, 220c) and a drain (130b, 230b) connected to a gate (120a, 220a) of the second TFT (120, 220), and A fourth TFT (140, 240) having a gate (140a, 240a) connected to the output (102) of the logic circuit (100, 200), and connected to the second TFT (120, 220) A source electrode (140c, 240c) of the gate electrode (120a, 220a) and the drain electrode (130b, 230b) of the third TFT (130, 230). 如請求項1之邏輯電路(100、200)，其中該第一TFT (110、210)具有連接至一第一電源供應軌道之一源極(110c、210c)。The logic circuit (100, 200) of claim 1, wherein the first TFT (110, 210) has a source (110c, 210c) connected to a first power supply rail. 如請求項1之邏輯電路(100、200)，其中該第二TFT (120、220)具有連接至一第二電源供應軌道之一汲極(120b、220b)，且其中該第四TFT (140、240)具有連接至該第二電源供應軌道之一汲極(140b、240b)。The logic circuit (100, 200) of claim 1, wherein the second TFT (120, 220) has a drain (120b, 220b) connected to a second power supply rail, and wherein the fourth TFT (140 , 240) has a drain (140b, 240b) connected to the second power supply rail. 如請求項2之邏輯電路(100、200)，其中該第一電源軌道接地，且該第二電源軌道係一正供應電壓。The logic circuit (100, 200) of claim 2 wherein the first power rail is grounded and the second power rail is a positive supply voltage. 如請求項1之邏輯電路(100、200)，其中該第一TFT (110、210)具有一臨限值電壓VT1 ，其高於該第二TFT (120、220)之一臨限值電壓VT2 。The logic circuit (100, 200) of claim 1, wherein the first TFT (110, 210) has a threshold voltage V T1 which is higher than a threshold voltage of the second TFT (120, 220) V T2 . 如請求項1之邏輯電路(100、200)，其中該第二TFT (120、220)係一空乏模式電晶體。The logic circuit (100, 200) of claim 1, wherein the second TFT (120, 220) is a depletion mode transistor. 如請求項1之邏輯電路(100、200)，其中該第一TFT (110、210)係一增強模式電晶體。The logic circuit (100, 200) of claim 1, wherein the first TFT (110, 210) is an enhancement mode transistor. 如請求項1之邏輯電路(100、200)，其中該第一TFT、該第二TFT、該第三TFT及該第四TFT之一或多者包括一背閘極。The logic circuit (100, 200) of claim 1, wherein one or more of the first TFT, the second TFT, the third TFT, and the fourth TFT include a back gate. 如請求項8之邏輯電路(100、200)，其包括用於接收對該第一TFT (110、210)之該背閘極的一調整信號之一第一調整輸入。The logic circuit (100, 200) of claim 8 includes a first adjustment input for receiving an adjustment signal of the back gate of the first TFT (110, 210). 如請求項8之邏輯電路(100、200)，其包括用於接收對該第二TFT (120、220)之該背閘極的一調整信號之一第二調整輸入。The logic circuit (100, 200) of claim 8 includes a second adjustment input for receiving an adjustment signal of the back gate of the second TFT (120, 220). 如請求項1之邏輯電路(100、200)，其中該第一TFT (110、210)經調適以回應於在其輸入處接收一邏輯高信號而導通且回應於在其輸入處接收一邏輯低信號而切斷。The logic circuit (100, 200) of claim 1, wherein the first TFT (110, 210) is adapted to turn on in response to receiving a logic high signal at its input and respond to receiving a logic low at its input Signal to cut off. 如請求項1之邏輯電路(100、200)，其中該第四TFT (140、240)經調適以提供自該邏輯電路(100、200)之該輸出(102)的反饋至該第二TFT (120、220)之該閘極(120a、220a)。The logic circuit (100, 200) of claim 1, wherein the fourth TFT (140, 240) is adapted to provide feedback from the output (102) of the logic circuit (100, 200) to the second TFT ( 120, 220) of the gate (120a, 220a). 如請求項1之邏輯電路(100、200)，其中該第三TFT (130、230)經調適以回應於在其輸入處接收一邏輯高輸入信號而切斷該第二TFT (120、220)。The logic circuit (100, 200) of claim 1, wherein the third TFT (130, 230) is adapted to cut off the second TFT (120, 220) in response to receiving a logic high input signal at its input . 如請求項2之邏輯電路(100、200)，其中該第一TFT (110、210)經連接使得流動通過該邏輯電路(100、200)自該第二供應軌道至該第一供應軌道之所有電流當使用時流動通過該第一TFT (110、210)。The logic circuit (100, 200) of claim 2, wherein the first TFT (110, 210) is connected such that all the flow through the logic circuit (100, 200) from the second supply track to the first supply track Current flows through the first TFT (110, 210) when used.
TW108121135A 2018-06-28 2019-06-18 Low power logic circuit TW202015340A (en)

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US4999523A (en) * 1989-12-05 1991-03-12 Hewlett-Packard Company BICMOS logic gate with higher pull-up voltage
US8013633B2 (en) * 2007-06-20 2011-09-06 Hewlett-Packard Development Company, L.P. Thin film transistor logic
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