TW202010066A - 晶片封裝結構的形成方法 - Google Patents

晶片封裝結構的形成方法 Download PDF

Info

Publication number
TW202010066A
TW202010066A TW108129034A TW108129034A TW202010066A TW 202010066 A TW202010066 A TW 202010066A TW 108129034 A TW108129034 A TW 108129034A TW 108129034 A TW108129034 A TW 108129034A TW 202010066 A TW202010066 A TW 202010066A
Authority
TW
Taiwan
Prior art keywords
layer
conductive
substrate
forming
molding
Prior art date
Application number
TW108129034A
Other languages
English (en)
Other versions
TWI828739B (zh
Inventor
蔡柏豪
洪士庭
鄭心圃
翁得期
Original Assignee
台灣積體電路製造股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 台灣積體電路製造股份有限公司 filed Critical 台灣積體電路製造股份有限公司
Publication of TW202010066A publication Critical patent/TW202010066A/zh
Application granted granted Critical
Publication of TWI828739B publication Critical patent/TWI828739B/zh

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/50—Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/565—Moulds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/563—Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5383—Multilayer substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5385—Assembly of a plurality of insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5386—Geometry or layout of the interconnection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/07—Structure, shape, material or disposition of the bonding areas after the connecting process
    • H01L24/09—Structure, shape, material or disposition of the bonding areas after the connecting process of a plurality of bonding areas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/17—Structure, shape, material or disposition of the bump connectors after the connecting process of a plurality of bump connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0655—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00 the devices being arranged next to each other
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/18—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68345—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used as a support during the manufacture of self supporting substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0231—Manufacturing methods of the redistribution layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0237—Disposition of the redistribution layers
    • H01L2224/02373—Layout of the redistribution layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13101—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H01L2224/13111—Tin [Sn] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13139—Silver [Ag] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13144—Gold [Au] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16227—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/81001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector involving a temporary auxiliary member not forming part of the bonding apparatus
    • H01L2224/81005—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector involving a temporary auxiliary member not forming part of the bonding apparatus being a temporary or sacrificial substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/83001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector involving a temporary auxiliary member not forming part of the bonding apparatus
    • H01L2224/83005—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector involving a temporary auxiliary member not forming part of the bonding apparatus being a temporary or sacrificial substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/921—Connecting a surface with connectors of different types
    • H01L2224/9212—Sequential connecting processes
    • H01L2224/92122—Sequential connecting processes the first connecting process involving a bump connector
    • H01L2224/92125—Sequential connecting processes the first connecting process involving a bump connector the second connecting process involving a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L24/80 - H01L24/90
    • H01L24/92—Specific sequence of method steps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H01L2924/1815—Shape
    • H01L2924/1816—Exposing the passive side of the semiconductor or solid-state body
    • H01L2924/18161—Exposing the passive side of the semiconductor or solid-state body of a flip chip

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Geometry (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

本發明實施例提供一種晶片封裝結構的形成方法，包含：形成導電結構於基板之上；基板包含介電層和位於介電層中的佈線層，且導電結構電性連接至佈線層；形成第一模製層於基板之上並圍繞導電結構；形成重分佈結構於第一模製層和導電結構之上；以及將晶片結構接合至重分佈結構。

Description

晶片封裝結構的形成方法
本發明實施例係關於晶片封裝結構及其形成方法，且特別是有關於晶片封裝結構中的導電結構及其形成方法。
半導體裝置已運用在各種電子應用上，例如個人電腦、手機、數位相機以及其他的電子設備。半導體裝置的製造通常會依序將絕緣層或介電層、導電層及半導體層沉積在半導體基板之上，並且利用微影製程和蝕刻製程將各材料層圖案化以形成電路元件及其上的元件。
隨著半導體技術的發展，半導體晶片/晶粒變得越來越小。此時，需要將更多功能整合到半導體晶粒中。結果，半導體晶粒的封裝變得更困難。
根據本發明的一實施例，提供一種晶片封裝結構的形成方法，包含：形成導電結構於基板之上，其中基板包含介電層和位於介電層中的佈線層，且導電結構電性連接至佈線層；形成第一模製層於基板之上並圍繞導電結構和基板；形成重分佈結構於第一模製層和導電結構之上；以及將晶片結構接合至重分佈結構。
根據本發明的另一實施例，提供一種晶片封裝結構的形成方法，包含：形成導電結構於基板之上，其中基板包含介電層和位於介電層中的佈線層，且導電結構電性連接至佈線層；形成第一模製層於基板之上以圍繞導電結構；移除導電結構之上的第一模製層；形成重分佈結構於第一模製層和導電結構之上，其中重分佈結構直接接觸導電結構；以及將晶片結構接合至重分佈結構。
又根據本發明的另一實施例，提供一種晶片封裝結構，包含：基板，包含介電層和位於介電層中的佈線層，其中基板具有第一表面和側壁，且側壁鄰接第一表面；導電結構，位於第一表面之上並電性連接至佈線層；第一模製層，位於第一表面和側壁之上以圍繞導電結構和基板；重分佈結構，位於第一模製層和導電結構之上；以及晶片結構，位於重分佈結構之上。
以下內容提供了許多不同的實施例或範例，用於實施所提供之標的之不同部件。組件和配置的具體範例描述如下，以簡化本發明實施例。當然，這些僅僅是範例，並非用以限定本發明實施例。舉例來說，敘述中若提及第一部件形成於第二部件上方，可能包含形成第一和第二部件直接接觸的實施例，也可能包含額外的部件形成於第一和第二部件之間，使得第一和第二部件不直接接觸的實施例。此外，本發明實施例在不同範例中可重複使用參考數字及/或字母，此重複是為了簡化和清楚之目的，並非代表所討論的不同實施例及/或組態之間有特定的關係。
此外，其中可能用到與空間相對用語，例如「在……之下」、「在……下方」、「下方的」、「在……上方」、「上方的」及類似的用詞，這些空間相對用語係為了便於描述如圖所示之一個（些）元件或部件與另一個（些）元件或部件之間的關係。這些空間相對用語包含使用中或步驟中的裝置之不同方位，以及圖式中所描述的方位。當裝置被轉向不同方位時（旋轉90度或其他方位），則其中所使用的空間相對形容詞也將依轉向後的方位來解釋。應理解的是，可在此方法之前、期間及之後提供額外的步驟，且在此方法的其他實施例中，可置換或刪除所述的一些操作。
第1A～1I圖根據一些實施例繪示形成晶片封裝結構的製程之各個階段的剖面圖。根據一些實施例，如第1A圖所示，提供載體基板110。根據一些實施例，載體基板110被配置以在後續製程步驟期間提供暫時性的機械和結構支撐。根據一些實施例，載體基板110包含玻璃、矽、氧化矽、氧化鋁、金屬、前述之組合及/或類似的材料。根據一些實施例，載體基板110包含金屬框架。
根據一些實施例，如第1A圖所示，形成黏著層120於載體基板110之上。根據一些實施例，黏著層120直接接觸載體基板110。根據一些實施例，黏著層120順應性地（conformally）形成於載體基板110上。根據一些實施例，黏著層120是由例如聚合物材料的絕緣材料所組成。利用塗佈製程或其他合適的製程來形成黏著層120。
根據一些實施例，如第1A圖所示，基板130設置在黏著層120之上。根據一些實施例，基板130具有表面131a和131b以及側壁131c。根據一些實施例，表面131a背向載體基板110。根據一些實施例，表面131a相反於表面131b。根據一些實施例，側壁131c位於表面131a和131b之間。根據一些實施例，側壁131c鄰接表面131a和131b。
根據一些實施例，基板130包含介電層132、佈線層（wiring layers）134、導孔（conductive vias）136以及導電墊138和139。根據一些實施例，佈線層134、導孔136以及導電墊138和139位於介電層132中。根據一些實施例，一些導孔136在佈線層134之間電性連接。根據一些實施例，其他導孔136在佈線層134和導電墊138之間電性連接。
根據一些實施例，佈線層134、導孔136以及導電墊138和139彼此電性連接。介電層132是由聚合物材料或其他合適的材料所組成。舉例而言，介電層132包含例如玻璃纖維材料的纖維材料、例如聚合物材料的預浸材料（prepreg material）、Ajinomoto積層膜（ABF；Ajinomoto Build-up Film）、阻焊材料或前述之組合。根據一些實施例，佈線層134、導孔136以及導電墊138和139是由例如銅、鋁或鎢的導電材料所組成。
根據一些實施例，如第1A圖所示，形成種子層142於基板130之上。根據一些實施例，種子層142形成於導電墊138和介電層132之上。根據一些實施例，種子層142直接接觸導電墊138及介電層132。根據一些實施例，種子層142是由鈦、銅及/或其他合適的導電材料所組成。根據一些實施例，利用例如物理氣相沉積製程的沉積製程來形成種子層142。
根據一些實施例，如第1A圖所示，遮罩層144形成於種子層142之上。根據一些實施例，遮罩層144具有開口144a。根據一些實施例，開口144a露出種子層142的一部分。根據一些實施例，遮罩層144是由例如光阻材料的聚合物材料所組成。根據一些實施例，利用塗佈製程和微影製程來形成遮罩層144。
根據一些實施例，如第1A圖所示，形成導電層146於開口144a中。根據一些實施例，導電層146是由例如銅、鋁或鎢的導電材料所組成。根據一些實施例，利用電鍍製程（plating process）或其他合適的製程來形成導電層146，所述電鍍製程例如為電鍍製程（electro-plating process）或無電電鍍製程（electroless plating process）。
根據一些實施例，如第1B圖所示，移除遮罩層144。根據一些實施例，如第1B圖所示，移除原本位於遮罩層144之下的種子層142。根據一些實施例，如第1B圖所示，導電層146和位於導電層146之下的種子層142一起形成導電結構147。在一些其他實施例中，在將基板130設置於黏著層120之上之前，形成導電結構147於基板130之上。
根據一些實施例，導電結構147包含導電柱及/或導電跡線（traces）（或導線）。根據一些實施例，每一個導電結構147電性連接至其下的導電墊138。根據一些實施例，每一個導電結構147直接接觸其下的導電墊138。在一些實施例中，導電結構147是導電跡線，並且導電跡線與隨後形成的佈線層的佈線（routing）匹配。
根據一些實施例，如第1B圖所示，形成模製層（molding layer）150於載體基板110之上以覆蓋基板130和導電結構147。根據一些實施例，模製層150覆蓋基板130的表面131a和側壁131c。根據一些實施例，模製層150直接接觸基板130及導電結構147。根據一些實施例，模製層150包含聚合物材料。根據一些實施例，利用模製製程來形成模製層150。
根據一些實施例，模製層150包含聚合物材料。根據一些實施例，用語「聚合物」可代表熱固性聚合物、熱塑性聚合物或前述之任何混合物。舉例而言，聚合物材料可包含塑膠材料、環氧樹脂，聚醯亞胺（polyimide）、聚對苯二甲酸乙二酯（polyethylene terephthalate；PET）、聚氯乙烯（polyvinyl chloride；PVC）、聚甲基丙烯酸甲酯（polymethylmethacrylate；PMMA）、摻雜有特定填料（fillers）的聚合物成分，填料包含纖維、黏土、陶瓷、無機粒子或前述之任何組合。在其他實施例中，根據一些實施例，模製層150可由例如環氧甲酚酚醛清漆（epoxy cresol novolac；ECN）、聯苯環氧樹脂（biphenyl epoxy resin）、多功能液態環氧樹脂或前述之任何組合的環氧樹脂所組成。又在其他實施例中，模製層150可由可選擇性地（optionally）包含一或多種填料的環氧樹脂所組成，以提供組合物任何各種所需的性質。根據一些實施例，填料的例子可為鋁、二氧化鈦、碳黑、碳酸鈣、二氧化矽或前述之任何組合。
根據一些實施例，如第1C圖所示，移除模製層150的上部以露出導電結構147。根據一些實施例，移除製程包含平坦化製程，例如化學機械研磨製程（chemical mechanical polishing process；CMP製程）。因此，在移除製程之後，每一個導電結構147的頂表面147a與模製層150的頂表面152共平面。
根據一些實施例，模製層150連續地圍繞導電結構147和整個基板130。根據一些實施例，導電結構147在基板130之上穿過模製層150。在一些實施例中，導電結構147的厚度T1介於約2 µm至約50 µm的範圍。在一些實施例中，導電結構147的厚度T1介於約20 µm至約50 µm的範圍。在一些實施例中，模製層150在基板130之上的厚度T2介於約2 µm至約50 µm的範圍。在一些實施例中，模製層150在基板130之上的厚度T2介於約20 µm至約50 µm的範圍。
根據一些實施例，導電結構147的厚度T1大致上等於模製層150在基板130之上的厚度T2。根據一些實施例，本案中的用語「大致上等於」意味著「在10%以內」。舉例而言，根據一些實施例，用語「大致上等於」意味著厚度T1和T2之間的差異在導電結構147和位於基板130之上的模製層150之間的平均厚度的10%之內。此差異可能是由於生產製程所導致。在一些實施例中，導電結構147的寬度W1介於約5 µm至約200 µm的範圍。在一些實施例中，導電結構147的寬度W1介於約15 µm至約30 µm的範圍。在一些實施例中，導電結構147之間的距離D1介於約10 µm至約400 µm的範圍。在一些實施例中，導電結構147之間的距離D1介於約10 µm至約20 µm的範圍。
根據一些實施例，如第1D圖所示，形成重分佈結構（redistribution structure）160於模製層150和導電結構147之上。根據一些實施例，重分佈結構160直接接觸導電結構147及模製層150。
重分佈結構160的形成包含：形成介電層161於模製層150和導電結構147之上，其中介電層161具有分別露出其下方的導電結構147的開口161a；形成佈線層162於介電層161之上和開口161a中，以電性連接至導電結構147；形成介電層163於介電層161和佈線層162之上，其中介電層163具有部分地露出佈線層162的開口163a；形成佈線層164於介電層163之上和開口163a中，以電性連接至佈線層162；形成介電層165於介電層163和佈線層164之上，其中介電層165具有部分地露出佈線層164的開口165a；形成導電墊166於開口165a中。
根據一些實施例，每一個介電層161、163和165的形成包含沉積製程（例如化學氣相沉積製程或物理氣相沉積製程）、微影製程和蝕刻製程。根據一些實施例，每一個佈線層162和164以及導電墊166的形成包含微影製程、電鍍製程和蝕刻製程。
根據一些實施例，介電層161順應性地形成於模製層150和導電結構147上。在一些實施例中，導電墊166的寬度W2沿著方向V1縮小，其中方向V1從重分佈結構160的頂表面167到重分佈結構160的底表面168。根據一些實施例，導電墊166的寬度W2小於開口163a的寬度。根據一些實施例，開口163a的寬度小於開口161a的寬度。
根據一些實施例，介電層161、163和165是由例如聚合物材料（例如聚苯並噁唑、聚醯亞胺或光敏材料）、氮化物（例如氮化矽）、氧化物（例如氧化矽）、氮氧化矽或類似的材料的絕緣材料所組成。根據一些實施例，佈線層162和164以及導電墊166是由例如金屬（例如銅、鋁或鎢）的導電材料所組成。
根據一些實施例，如第1E圖所示，晶片結構170透過導電凸塊182、184和186接合至重分佈結構160。根據一些實施例，晶片結構170包含晶片172和174以及晶片封裝176。
根據一些實施例，晶片172和174以及晶片封裝176透過導電凸塊182、184和186電性連接至重分佈結構160的導電墊166。根據一些實施例，晶片172和174以及晶片封裝176透過重分佈結構160和導電結構147電性連接至基板130。
晶片172和174包含晶片上系統（system-on-chip；SoC）、記憶體晶片（例如動態隨機存取記憶體晶片）、射頻（radio frequency；RF）晶片或其他合適的晶片。晶片172和174以及晶片封裝176可具有相同或不同的寬度。晶片172和174以及晶片封裝176可具有相同或不同的高度。
根據一些實施例，晶片172具有基板172a、裝置層172b和內連線層（interconnect layer）172c。在一些實施例中，基板172a是由包含單晶、多晶或非晶結構的矽或鍺的元素半導體材料所組成。在一些其他實施例中，基板172a是由例如碳化矽、砷化鎵、磷化鎵、磷化銦、砷化銦、合金半導體（例如SiGe或GaAsP）或前述之組合的化合物半導體所組成。
基板172a也可包含多層半導體、絕緣體上覆半導體（semiconductor on insulator；SOI）（例如絕緣體上覆矽或絕緣體上覆鍺）或前述之組合。根據一些實施例，基板172a具有面向重分佈結構160的底表面B1。
根據一些實施例，裝置層172b位於底表面B1之上。根據一些實施例，裝置層172b包含電子元件（未繪示）、介電層DI1和導電墊P1。
在一些實施例中，電子元件形成於基板172a上或基板172a中。根據一些實施例，電子元件包含主動元件（例如電晶體、二極體或類似的元件）及/或被動元件（例如電阻器、電容器、電感器或類似的元件）。根據一些實施例，介電層DI1形成於底表面B1之上並覆蓋電子元件。
根據一些實施例，導電墊P1內埋於（embedded）介電層DI1中並且電性連接至電子元件。根據一些實施例，導電墊P1是由例如金屬（例如銅、鋁、鎳或前述之組合）的導電材料所組成。
根據一些實施例，內連線層172c形成於裝置層172b之上。根據一些實施例，內連線層172c包含內連線結構（未繪示）和介電層（未繪示）。根據一些實施例，內連線結構位於介電層中並且電性連接至導電墊P1。
根據一些實施例，導電凸塊182位於導電墊166和內連線層172c之間，以透過內連線層172c的內連線結構將導電墊166電性連接至導電墊P1。
根據一些實施例，晶片174具有基板174a、裝置層174b和內連線層174c。在一些實施例中，基板174a是由包含單晶、多晶或非晶結構的矽或鍺的元素半導體材料所組成。在一些其他實施例中，基板174a是由例如碳化矽、砷化鎵、磷化鎵、磷化銦、砷化銦、合金半導體（例如SiGe或GaAsP）或前述之組合的化合物半導體所組成。
基板174a也可包含多層半導體、絕緣體上覆半導體（例如絕緣體上覆矽或絕緣體上覆鍺）或前述之組合。根據一些實施例，基板174a具有面向重分佈結構160的底表面B2。根據一些實施例，裝置層174b位於底表面B2之上。根據一些實施例，裝置層174b包含電子元件（未繪示）、介電層DI2和導電墊P2。
在一些實施例中，電子元件形成於基板174a上或基板174a中。根據一些實施例，電子元件包含主動元件（例如電晶體、二極體或類似的元件）及/或被動元件（例如電阻器、電容器、電感器或類似的元件）。根據一些實施例，介電層DI2形成於底表面B2之上並覆蓋電子元件。
根據一些實施例，導電墊P2內埋於介電層DI2中並且電性連接至電子元件。根據一些實施例，導電墊P2是由例如金屬（例如銅、鋁、鎳或前述之組合）的導電材料所組成。
根據一些實施例，內連線層174c形成於裝置層174b之上。根據一些實施例，內連線層174c包含內連線結構（未繪示）和介電層（未繪示）。根據一些實施例，內連線結構位於介電層中並且電性連接至導電墊P2。
根據一些實施例，導電凸塊184位於導電墊166和內連線層174c之間，以透過內連線層174c的內連線結構將導電墊166電性連接至導電墊P2。
在一些實施例中，根據一些實施例，晶片封裝176包含重分佈結構（或基板）176a、晶片176b、導電凸塊176c和模製層176d。根據一些實施例，重分佈結構176a包含介電層（未繪示）和佈線層（未繪示）。根據一些實施例，佈線層位於介電層中。
根據一些實施例，晶片176b透過導電凸塊176c接合至重分佈結構176a。晶片176b包含動態隨機存取記憶體（dynamic random access memory；DRAM）晶片、高帶寬記憶體（high bandwidth memory；HBM）晶片或其他合適的晶片。
根據一些實施例，導電凸塊176c將晶片176b電性連接至重分佈結構176a的佈線層。根據一些實施例，導電凸塊176c是由例如錫和銀或其他合適的導電材料（例如金）的焊料材料所組成。
根據一些實施例，模製層176d形成於重分佈結構176a之上以圍繞晶片176b和導電凸塊176c。模製層176d是由聚合物材料或其他合適的絕緣材料所組成。
根據一些實施例，導電凸塊186位於導電墊166和重分佈結構176a之間，以透過重分佈結構176a的佈線層和導電凸塊176c將導電墊166電性連接至晶片176b。
根據一些實施例，導電凸塊186比導電凸塊182或184寬。根據一些實施例，導電凸塊182或184也稱為微凸塊。根據一些實施例，導電凸塊186也稱為C4凸塊。
在一些實施例中，導電凸塊182的寬度W3介於約10 µm至約150 µm的範圍。在一些實施例中，導電凸塊182的寬度W3介於約40 µm至約50 µm的範圍。在一些實施例中，導電凸塊184的寬度W4介於約10 µm至約150 µm的範圍。在一些實施例中，導電凸塊184的寬度W4介於約40 µm至約50 µm的範圍。在一些實施例中，導電凸塊186的寬度W5介於約50 µm至約250 µm的範圍。在一些實施例中，導電凸塊186的寬度W5介於約100 µm至約150 µm的範圍。
根據一些實施例，導電凸塊182、184和186是由例如錫和銀或其他合適的導電材料（例如金）的焊料材料所組成。根據一些實施例，導電凸塊182、184和186是焊球。
根據一些實施例，如第1E圖所示，形成底部充填層190於晶片172和174、晶片封裝176和重分佈結構160之間。根據一些實施例，底部充填層190圍繞晶片172和174、晶片封裝176以及導電凸塊182、184和186。根據一些實施例，底部充填層190是由絕緣材料所組成，所述絕緣材料例如為聚合物材料或由環氧樹脂和充填材料組成的模製化合物材料。
根據一些實施例，在基板130的熱膨脹係數（coefficient of thermal expansion；CTE）、模製層150的熱膨脹係數和載體基板110的熱膨脹係數之間實現了熱膨脹係數平衡。因此，根據一些實施例，降低了基板130的翹曲（warpage）。從而，改善了隨後形成於表面131b之上的導電凸塊的共面性（coplanarity）。
由於導電結構147、模製層150和重分佈結構160以良好的共面性依序形成於基板130之上，導電結構147、模製層150和重分佈結構160具有良好的共面性，這改善了導電凸塊182、184和186與重分佈結構160之間的黏結性（bondability）。
根據一些實施例，如第1F圖所示，形成模製層210於重分佈結構160、底部充填層190、晶片172和174以及晶片封裝176之上。根據一些實施例，模製層210包含聚合物材料。根據一些實施例，利用模製製程來形成模製層210。
根據一些實施例，如第1G圖所示，移除模製層210的上部以露出晶片174的頂表面174d。因此，根據一些實施例，晶片174的散熱效率得到改善。
根據一些實施例，移除製程包含平坦化製程，例如化學機械研磨製程（化學機械研磨製程）。因此，根據一些實施例，在移除製程之後，頂表面174d與模製層210的頂表面212共平面。在一些其他實施例（未繪示）中，頂表面174d和212以及晶片172和晶片封裝176的頂表面與彼此共平面。
根據一些實施例，模製層210圍繞晶片172和174以及晶片封裝176、導電凸塊182、184和186以及底部充填層190。根據一些實施例，模製層210直接接觸晶片172和174以及晶片封裝176和底部充填層190。
根據一些實施例，如第1H圖所示，將基板130上下翻轉。根據一些實施例，如第1H圖所示，移除載體基板110。根據一些實施例，如第1H圖所示，移除黏著層120。
根據一些實施例，如第1I所示，移除介電層132的一部分以於介電層132中形成開口132a。根據一些實施例，開口132a露出其下的導電墊139。
根據一些實施例，如第1I圖所示，導電凸塊220分別形成於由開口132a露出的導電墊139之上。根據一些實施例，導電凸塊220是由例如錫和銀或其他合適的導電材料的焊料材料所組成。
根據一些實施例，如第1I圖所示，在模製層150、重分佈結構160和模製層210上進行切割製程（或鋸切（sawing）製程）以切穿模製層150和210以及重分佈結構160，以形成晶片封裝結構100。為了簡單起見，根據一些實施例，第1I圖僅繪示出其中一個晶片封裝結構100。
在一些實施例中，在切割製程之後，模製層150的側壁154、重分佈結構160的側壁169和模製層210的側壁214與彼此共平面。在一些實施例中，基板130的表面130a與模製層150的表面156共平面。根據一些實施例，導電結構147的厚度T1小於重分佈結構160的厚度T3、基板130的厚度T4和晶片172的厚度T5中的任一個。
根據一些實施例，由於重分佈結構160透過導電結構147（其由電鍍製程形成）電性連接至基板130而非焊球，因此不需要進行退火製程來將焊球接合至基板130。因此，根據一些實施例，降低了基板130的翹曲。
此外，導電結構147是透過電鍍製程形成於基板130之上，因此導電結構147的形成不會受到基板130翹曲的影響。因此，根據一些實施例，導電結構147和基板130之間的黏結性得到改善。
由於導電結構147是透過在遮罩層144的開口144a中形成導電層146而形成，因此可利用微影製程來調整遮罩層144的開口144a（如第1A圖和第1B圖所示）以調節導電結構147的尺寸和兩個相鄰導電結構147之間的距離。因此，導電結構147的尺寸和兩個相鄰導電結構147之間的距離可小於焊球的尺寸/焊球之間的距離及/或比焊球的尺寸/焊球之間的距離更為均勻。結果，改善了導電結構147的密度。
根據一些實施例，提供晶片封裝結構及其形成方法。此方法（用於形成晶片封裝結構）包含利用電鍍製程形成導電結構於基板和重分佈結構之間。因此，導電結構和基板之間的黏結性不會受到基板翹曲的影響。結果，基板和重分佈結構之間的電性連接性質得到改善。
根據一些實施例，提供一種晶片封裝結構的形成方法。所述方法包含形成導電結構於基板之上。基板包含介電層和位於介電層中的佈線層，且導電結構電性連接至佈線層。所述方法包含形成第一模製層於基板之上並圍繞導電結構。所述方法包含形成重分佈結構於第一模製層和導電結構之上。所述方法包含將晶片結構接合至重分佈結構。
在一些實施例中，第一模製層連續地覆蓋基板的表面和側壁，所述表面面向重分佈結構，且所述側壁鄰接並圍繞所述表面。在一些實施例中，所述晶片封裝結構的形成方法更包含：在將晶片結構接合至重分佈結構之後，形成導電凸塊於基板之上，其中基板位於導電凸塊和重分佈結構之間。在一些實施例中，所述晶片封裝結構的形成方法更包含：在形成導電凸塊於基板之上之後，切穿第一模製層和重分佈結構。在一些實施例中，在切穿第一模製層和重分佈結構之後，第一模製層的第一側壁與重分佈結構的第二側壁共平面。在一些實施例中，導電結構穿過第一模製層。在一些實施例中，重分佈結構直接接觸導電結構及第一模製層。在一些實施例中，晶片結構透過重分佈結構和導電結構電性連接至基板。在一些實施例中，所述晶片封裝結構的形成方法更包含：形成第二模製層於重分佈結構之上並圍繞晶片結構。在一些實施例中，所述晶片封裝結構的形成方法更包含：在形成第二模製層於重分佈結構之上之前，形成底部充填層於晶片結構和重分佈結構之間，其中第二模製層更圍繞底部充填層。
根據一些實施例，提供一種晶片封裝結構的形成方法。所述方法包含形成導電結構於基板之上。基板包含介電層和位於介電層中的佈線層，且導電結構電性連接至佈線層。所述方法包含形成第一模製層於基板之上以圍繞導電結構。所述方法包含移除導電結構之上的第一模製層。所述方法包含形成重分佈結構於第一模製層和導電結構之上。重分佈結構直接接觸導電結構。所述方法包含將晶片結構接合至重分佈結構。
在一些實施例中，導電結構的形成包含：形成種子層於基板之上；形成遮罩層於種子層之上，其中遮罩層具有開口，所述開口部分地露出種子層；形成導電層於開口中；以及移除遮罩層和位於遮罩層之下的種子層，其中導電層和位於導電層之下的種子層一起形成導電結構。在一些實施例中，導電層的形成包含電鍍製程或無電電鍍製程。在一些實施例中，在移除導電結構之上的第一模製層之後，第一模製層的第一頂表面與導電結構的第二頂表面共平面。在一些實施例中，形成重分佈結構於第一模製層和導電結構之上包含：形成介電層於第一模製層和導電結構之上，其中介電層具有開口，所述開口露出導電結構；以及形成佈線層於介電層之上和開口中以連接至導電結構，其中晶片結構電性連接至佈線層。
根據一些實施例，提供一種晶片封裝結構。所述晶片封裝結構包含基板，其包含介電層和位於介電層中的佈線層。基板具有第一表面和側壁，且所述側壁鄰接所述第一表面。所述晶片封裝結構包含導電結構，其位於第一表面之上並電性連接至佈線層。所述晶片封裝結構包含第一模製層，其位於第一表面和側壁之上以圍繞導電結構和基板。所述晶片封裝結構包含重分佈結構，其位於第一模製層和導電結構之上。所述晶片封裝結構包含晶片結構，其位於重分佈結構之上。
在一些實施例中，第一模製層的第一側壁與重分佈結構的第二側壁共平面。在一些實施例中，所述晶片封裝結構更包含第二模製層，其位於重分佈結構之上並圍繞晶片結構，其中第二模製層的第三側壁與第一模製層的第一側壁及重分佈結構的第二側壁共平面。在一些實施例中，第一模製層的第一頂表面與導電結構的第二頂表面共平面。在一些實施例中，基板具有相對於第一表面的第二表面，且第二表面與第一模製層的第三表面共平面。
前述內文概述了許多實施例的部件，以使本技術領域中具有通常知識者可以從各個方面更佳地了解本發明實施例。本技術領域中具有通常知識者應可理解，且可輕易地以本發明實施例為基礎來設計或修飾其他製程及結構，並以此達到相同的目的及/或達到與在此介紹的實施例等相同之優點。本技術領域中具有通常知識者也應了解這些相等的結構並未背離本發明的精神與範圍。在不背離本發明的精神與範圍之前提下，可對本發明實施例進行各種改變、置換或修改。
100‧‧‧晶片封裝結構 110‧‧‧載體基板 120‧‧‧黏著層 130、172a、174a‧‧‧基板 130a、131a、131b、156‧‧‧表面 131c、154、169、214‧‧‧側壁 132、161、163、165、DI1、DI2‧‧‧介電層 132a、144a、161a、163a、165a‧‧‧開口 134、162、164‧‧‧佈線層 136‧‧‧導孔 138、139、166、P1、P2‧‧‧導電墊 142‧‧‧種子層 144‧‧‧遮罩層 146‧‧‧導電層 147‧‧‧導電結構 147a、152、167、174d、212‧‧‧頂表面 150、176d、210‧‧‧模製層 160、176a‧‧‧重分佈結構 168、B1、B2‧‧‧底表面 170‧‧‧晶片結構 172、174、176b‧‧‧晶片 172b、174b‧‧‧裝置層 172c、174c‧‧‧內連線層 176‧‧‧晶片封裝 176c、182、184、186、220‧‧‧導電凸塊 190‧‧‧底部充填層 D1‧‧‧距離 T1、T2、T3、T4、T5‧‧‧厚度 V1‧‧‧方向 W1、W2、W3、W4、W5‧‧‧寬度
藉由以下的詳細描述配合所附圖式，可以更加理解本發明實施例的內容。需強調的是，根據產業上的標準慣例，許多部件（feature）並未按照比例繪製。事實上，為了能清楚地討論，各種部件的尺寸可能被任意地增加或減少。 第1A～1I圖根據一些實施例繪示形成晶片封裝結構的製程之各個階段的剖面示意圖。
100‧‧‧晶片封裝結構
130‧‧‧基板
130a、156‧‧‧表面
132‧‧‧介電層
132a‧‧‧開口
139‧‧‧導電墊
147‧‧‧導電結構
150、210‧‧‧模製層
154、169、214‧‧‧側壁
160‧‧‧重分佈結構
172、174‧‧‧晶片
176‧‧‧晶片封裝
190‧‧‧底部充填層
220‧‧‧導電凸塊
T1、T3、T4、T5‧‧‧厚度

Claims (1)

  1. 一種晶片封裝結構的形成方法，包括： 形成一導電結構於一基板之上，其中該基板包含一介電層和位於該介電層中的一佈線層，且該導電結構電性連接至該佈線層； 形成一第一模製層於該基板之上並圍繞該導電結構和該基板； 形成一重分佈結構於該第一模製層和該導電結構之上；以及 將一晶片結構接合至該重分佈結構。
TW108129034A 2018-08-30 2019-08-15 封裝結構、晶片封裝結構及其形成方法 TWI828739B (zh)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US201862724838P 2018-08-30 2018-08-30
US62/724,838 2018-08-30
US16/242,311 2019-01-08
US16/242,311 US11114311B2 (en) 2018-08-30 2019-01-08 Chip package structure and method for forming the same

Publications (2)

Publication Number Publication Date
TW202010066A true TW202010066A (zh) 2020-03-01
TWI828739B TWI828739B (zh) 2024-01-11

Family

ID=69641563

Family Applications (1)

Application Number Title Priority Date Filing Date
TW108129034A TWI828739B (zh) 2018-08-30 2019-08-15 封裝結構、晶片封裝結構及其形成方法

Country Status (3)

Country Link
US (1) US11114311B2 (zh)
CN (1) CN110875194A (zh)
TW (1) TWI828739B (zh)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11410897B2 (en) * 2019-06-27 2022-08-09 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor structure having a dielectric layer edge covering circuit carrier
US11605600B2 (en) * 2020-08-06 2023-03-14 Taiwan Semiconductor Manufacturing Company, Ltd. Package structure with reinforced element and formation method thereof
US20220270909A1 (en) * 2021-02-25 2022-08-25 Marvell Asia Pte Ltd Glass carrier stacked package assembly method

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8354297B2 (en) * 2010-09-03 2013-01-15 Stats Chippac, Ltd. Semiconductor device and method of forming different height conductive pillars to electrically interconnect stacked laterally offset semiconductor die
US9041212B2 (en) * 2013-03-06 2015-05-26 Qualcomm Incorporated Thermal design and electrical routing for multiple stacked packages using through via insert (TVI)
US20150228594A1 (en) * 2014-02-13 2015-08-13 Qualcomm Incorporated Via under the interconnect structures for semiconductor devices
US9735131B2 (en) * 2015-11-10 2017-08-15 Taiwan Semiconductor Manufacturing Company, Ltd. Multi-stack package-on-package structures
CN108307661B (zh) * 2015-11-20 2022-07-08 美国德卡科技公司 全模制的微型化半导体模块
US10050013B2 (en) * 2015-12-29 2018-08-14 Taiwan Semiconductor Manufacturing Company, Ltd. Packaged semiconductor devices and packaging methods
US9865566B1 (en) * 2016-06-15 2018-01-09 Taiwan Semiconductor Manufacturing Company Ltd. Semiconductor structure and manufacturing method thereof
US10141198B2 (en) * 2016-07-08 2018-11-27 Dyi-chung Hu Electronic package and manufacturing method thereof
KR101939046B1 (ko) * 2017-10-31 2019-01-16 삼성전기 주식회사 팬-아웃 반도체 패키지
US10522508B2 (en) * 2018-05-01 2019-12-31 Advanced Semiconductor Engineering, Inc. Semiconductor device package and a method of manufacturing the same
US11469206B2 (en) * 2018-06-14 2022-10-11 Intel Corporation Microelectronic assemblies

Also Published As

Publication number Publication date
US11114311B2 (en) 2021-09-07
US20200075350A1 (en) 2020-03-05
CN110875194A (zh) 2020-03-10
TWI828739B (zh) 2024-01-11

Similar Documents

Publication Publication Date Title
US11482788B2 (en) Antenna device and method for manufacturing antenna device
US11670577B2 (en) Chip package with redistribution structure having multiple chips
TWI669785B (zh) 半導體封裝體及其形成方法
US20220059515A1 (en) Method of forming package structure
TWI710072B (zh) 半導體裝置封裝體及其製造方法
US10157808B2 (en) Package structure and method of forming package structure
US8803306B1 (en) Fan-out package structure and methods for forming the same
US9502386B2 (en) Fan-out package structure and methods for forming the same
US20190131241A1 (en) Package with fan-out structures
US11508671B2 (en) Semiconductor package and manufacturing method thereof
TW202038348A (zh) 天線整合式封裝結構及其製造方法
KR102079790B1 (ko) 팬 아웃 구조물을 갖는 패키지
US10163854B2 (en) Package structure and method for manufacturing thereof
US9831215B1 (en) Semiconductor package and forming method thereof
US10211139B2 (en) Chip package structure
US11430739B2 (en) Structure and formation method of package structure with fan-out structure
TWI828739B (zh) 封裝結構、晶片封裝結構及其形成方法
TWI750069B (zh) 具有在凸塊墊下方之緩衝件的半導體結構與其製備方法
TWI773400B (zh) 半導體元件及其製造方法
TWI726306B (zh) 封裝結構