TW201946239A - 具有最佳化場板設計的功率半導體裝置 - Google Patents
具有最佳化場板設計的功率半導體裝置 Download PDFInfo
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- TW201946239A TW201946239A TW108106811A TW108106811A TW201946239A TW 201946239 A TW201946239 A TW 201946239A TW 108106811 A TW108106811 A TW 108106811A TW 108106811 A TW108106811 A TW 108106811A TW 201946239 A TW201946239 A TW 201946239A
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Abstract
本發明揭示一種功率半導體裝置及用於製造功率半導體裝置的方法。該種裝置包括:源極接合墊與汲極接合墊、包括其連接到汲極接合墊的汲極場板之汲極金屬化結構、及包含連接到源極接合墊的源極場板之源極金屬化結構。該等接合墊之至少一者的至少一部分係直接位在主動區域之上。該等場板之至少一者的尺度係取決於相鄰該場板之結構而變化。
Description
本發明係關於具有在主動區域上的接合墊(BPOA, bonding pad over active area)佈局以及最佳化場板設計之一種功率半導體裝置,諸如例如:一種異質結構AlGaN/GaN高電子移動率的電晶體或整流器。
相關申請案之交互參照
相關申請案之交互參照
本申請案主張於2018年2月27日提出的美國非臨時申請案第15/906,698號之權益,其內容係以參照方式而納入本文。
功率半導體裝置係例如使用為在功率電子器件中的一個開關或整流器之一種半導體裝置,例如:用於馬達控制之直流至交流(DC to AC)變流器或用於切換模式的電源供應器之直流至直流(DC to DC)轉換器。一種功率半導體裝置係通常使用於“換向(commutation)模式”,即:其為接通(on)或斷開(off),且因此具有針對於該種使用為最佳化的設計。
矽雙極接面電晶體(BJT, bipolar junction transistor)、金屬氧化物半導體場效電晶體(MOSFET, Metal-Oxide-Semiconductor field effect transistor)、與絕緣閘雙極電晶體(IGBT, insulated gate bipolar transistor)係常見型式的功率半導體切換裝置。其應用領域係範圍為不限於從可攜式消費電子產品、家用電器、電動車、馬達控制與電源供應器到射頻(RF)與微波電路以及電信系統。
在過去十年來,氮化鎵(GaN)係已經逐漸被視為用在功率裝置之領域的一種極為前景看好的材料,其具有潛力以導致提高的功率密度、降低的接通電阻、與高頻響應。該種材料的寬帶間隙Eg
=3.39eV係造成高的臨界電場EC
=3.3MV/cm,其可導致具有較短的漂移區域之裝置設計,且因此較低的接通狀態電阻,若相較於一種具有相同的擊穿電壓之矽基裝置[參閱:U. K. Mishra等人, GaN基RF功率裝置與放大器, IEEE期刊, 第96冊, 第2號, 第287-305頁, 西元2008年]。一種AlGaN/GaN異質結構之使用係亦允許一種二維的電子氣體(2DEG, two-dimensional electron gas)之形成在其載體可達到極高的移動率μ=2000 cm2
/Vs值的異介面處[參閱:U. K. Mishra等人, GaN基RF功率裝置與放大器, IEEE期刊, 第96冊, 第2號, 第287-305頁, 西元2008年]。此外,存在於AlGaN/GaN異質結構之壓電極化電荷係造成在2DEG層的高電子密度,例如:1x1013
cm-2
。此些性質係可導致高電子移動率的電晶體(HEMT, High Electron Mobility Transistor)與蕭特基(Shottky)障壁二極體之產生為具有極為競爭性的性能參數[參閱:M. H. Kwan等人, 用於高電壓功率應用之CMOS相容的GaN-on-Si場效電晶體, IEDM, 舊金山, 西元2014年12月, 第17.6.1-17.6.4頁;S. Lenci等人, 具有閘控邊緣終端之無Au的AlGaN/GaN功率二極體8英寸矽基板, 電子裝置期刊(Elec. Dev. Lett.), 第34冊, 第8號, 第1035頁, 西元2013年]。大量研究係已經針對於使用AlGaN/GaN異質結構的功率裝置之開發。
如在圖1、2、3A、4A與5A所示,在主動區域上的接合墊(BPOA, bonding pad over active area)佈局係已經提議為可改善在側向AlGaN/GaN異質結構裝置中的電流密度之一種設計特徵,且其顯示針對於該等結構之競爭性的on狀態與off狀態特性之研究係可見於文獻中。
舉例來說,圖1係示意顯示其具有交叉式指部幾何形狀之一種說明性的BPOA佈局之三維的立體圖。在圖1所顯示的方位,x名稱係顯示寬度,y名稱係顯示高度,且x名稱係顯示深度。圖1係一種說明性的設計,其顯示如為AlGaN 1之III-V半導體的表面、一個源極接合墊SBP之源極墊金屬2、標示為FS之一個源極場板、源極場板FS之源極/閘極指部金屬化3 (亦稱為“源極金屬化”)、一個汲極接合墊DBP之汲極墊金屬4、標示為FD之一個汲極場板、汲極場板FD之汲極指部金屬化5 (亦稱為“汲極金屬化”)以及SiO2
鈍化或金屬化間的介電質6。
用於源極墊金屬2之可接受的材料係包括而不限於鋁(Al)。用於汲極墊金屬4之可接受的材料係包括而不限於鋁(Al)。用於源極場板FS與源極金屬化3之可接受的材料係包括而不限於氮化鈦(TiN)與鋁(Al)。用於汲極場板FD與汲極金屬化5之可接受的材料係包括而不限於氮化鈦(TiN)與鋁(Al)。
圖2係示意顯示其具有交叉式指部幾何形狀之一種半導體裝置100的BPOA佈局的俯視圖。亦在圖2所標出者係在圖3A、4A、5A與6所示的橫截面,其進一步描述於下文。各個源極指部金屬化3係包括以下的區段:定位在主動區域上的源極墊(SPOA, source pad over active area)之區段,其具有標示為ss1
的一個尺度;定位在主動區域上的無墊(NPOA, no pad over active area)之區段,其具有標示為ns1
的一個尺度;及,定位在主動區域上的汲極墊(DPOA, drain pad over active area)之區段,其具有標示為ds1
的一個尺度。
檢視BPOA佈局的性能,且尤其是BPOA設計的可靠度,所揭露的是應針對於當該裝置為偏壓於斷開狀態時而在金屬化間的介電質(例如:SiO2
)所觀察到的電場峰值。該等場峰值係當設計其對於時間相依的介電崩潰(TDDB, time dependent dielectric breakdown)為彈性之裝置時是有相關的,由於在此些介電層中的高電場係可導致TDDB之提高的機率。此係特別是在該裝置為同時暴露於高溫與高電場之情形。TDDB係指數式相依於溫度與電場峰值。已觀察到的是,GaN基的裝置係意謂著操作在較高的接面溫度,且不同於其他的寬帶隙材料,諸如:鑽石或碳化矽,GaN的熱導率係較低而造成更顯著的自我發熱。此係特別是在該等GaN異質結構為成長在基板上且諸如氮化鋁(AlN)之一個熱阻性的晶核生成層與一個緩衝層為形成在基板的頂部上且在主動層之下方以考慮到在GaN外延堆疊和基板之間的晶格不匹配。該種組態係可造成附加的自我發熱,其可使得TDDB效應為更加嚴厲。
如作為舉例在圖2、3、4、與5所看出,在一個半導體裝置的不同區段之間的區別係可作成。此些者係如下:
圖3A–在主動區域上的無墊(NPOA);
圖4A–在主動區域上的源極墊(SPOA);
圖5A–在主動區域上的汲極墊(DPOA)。
圖3A、4A、與5A係顯示如從圖2的頂部所顯示在指出的所在處與位置之一種說明性的現有技術的裝置之指定的橫截面。針對於此三個截面的各者,在一種介電質中的電場係以其施加到該裝置的汲極端子之斷開狀態的偏壓而模擬,如下文所述。
圖3A、4A、與5A係概括顯示一種現有技術的BPOA半導體裝置的配置,該種BPOA半導體裝置係具有一個基板9、在基板9之上的一個緩衝層8、在緩衝層8之上的一個GaN層7、與在GaN層7之上的一個AlGaN層1。一個閘極端子10係設置為包含一個高度p摻雜的GaN蓋11,其定位在AlGaN層1之上。一個表面鈍化介電質15係覆蓋閘極10且為定位在一個源極端子13與一個汲極端子14之間,源極端子13係延伸自其定位在源極金屬化3之下方的第一通孔12,汲極端子14係延伸自其定位在汲極金屬化5之下方的第二通孔12。諸如SiO2
層之一個金屬化間的介電質或鈍化介電層6係定位在表面鈍化介電質15之上且位在該等通孔12之間。如由箭頭所示,一個閘極汲極偏移長度LGD
係從閘極10而達到汲極端子14。一個選用式的基板端子16係可設置在裝置的下部,但此係並非必要條件。
用於金屬化間的介電質或鈍化介電層6之可接受的材料係包括而不限於二氧化矽(SiO2
)。用於緩衝層8之可接受的材料係包括而不限於AlN與AlGaN層。用於基板9之可接受的材料係包括而不限於矽(Si)。用於閘極端子10之可接受的材料係包括而不限於氮化鈦(TiN)。用於高度p摻雜的GaN蓋11之可接受的摻雜劑係包括而不限於鎂(Mg)。用於通孔12之可接受的材料係包括而不限於鎢(W)。用於源極端子13之可接受的材料係包括而不限於氮化鈦(TiN)。用於汲極端子14之可接受的材料係包括而不限於氮化鈦(TiN)。用於表面鈍化介電質15之可接受的材料係包括而不限於氮化矽(SiN)。用於基板端子16之可接受的材料係包括而不限於矽(Si)。
圖3A係示意顯示在一種現有技術的說明性的裝置之在主動區域上的無墊(NPOA)區段中且從圖2所指出的區域而取得的橫截面。圖3A係顯示其具有標示為ns1’
(其為在圖2所示之ns1
的一個部分)的尺度之源極金屬化3的一個部分與其具有標示為nd1’
(其為在圖2所示之nd1
的一個部分)的尺度之汲極金屬化5的一個部分。尺度ns1’
係對應於在圖2之半導體裝置的NPOA部分中之源極金屬化3的一個部分的一個區域。尺度nd1’
係對應於在圖2之半導體裝置的NPOA部分中之汲極金屬化5的一個部分的一個區域。諸如SiO2
與GaN之在圖3A、4A、與5A所示的特定材料係並非視作為限制性。熟習相關技藝人士係將理解材料可被使用在其具有BPOA佈局之一種功率半導體裝置的配置中。
圖4A係示意顯示在一種現有技術的裝置之在主動區域上的源極墊(SPOA)區段中且從圖2所指出的區域而取得的橫截面。圖4A係顯示其具有標示為ss1’
(其為在圖2所示之ss1
的一個部分)的尺度之源極金屬化3的一個部分與其具有標示為sd1’
(其為在圖2所示之sd1
的一個部分)的尺度之汲極金屬化5的一個部分。尺度ss1’
係對應於在圖2之半導體裝置的SPOA部分中之源極金屬化3的一個部分的一個區域。尺度sd1’
係對應於在圖2之半導體裝置的SPOA部分中之汲極金屬化5的一個部分的一個區域。圖4A係亦顯示在該裝置的頂部之源極墊金屬2。
圖5A係示意顯示在一種現有技術的裝置之在主動區域上的汲極墊(DPOA)區段中且從圖2所指出的區域而取得的橫截面。圖4A係顯示其具有標示為ds1’
(其為在圖2所示之ds1
的一個部分)的尺度之源極金屬化3的一個部分與其具有標示為dd1’
(其為在圖2所示之dd1
的一個部分)的尺度之汲極金屬化5的一個部分。尺度ds1’
係對應於在圖2之半導體裝置的SPOA部分中之源極金屬化3的一個部分的一個區域。尺度dd1’
係對應於在圖2之半導體裝置的SPOA部分中之汲極金屬化5的一個部分的一個區域。圖5A係亦顯示在該裝置的頂部之汲極墊金屬4。
如在圖2、3A、4A、與5A所示,源極金屬化指部3的各者與汲極金屬化指部5的各者係具有沿著其整個長度之實質相同的寬度,不論其是否在NPOA區域(對應於尺度ns1
與nd1
)、SPOA區域(對應於尺度ss1
與sd1
)、或DPOA區域(對應於尺度ds1
與dd1
)。注意到的是,在諸如圖2、3A、4A、與5A所示之習知的組態中,以下的尺度條件係適用:
ns1=ss1=ds1
nd1=sd1=dd1
檢視圖2、3A、4A、與5A的設計,顯明的是,電位之分佈係在主動區域為由接合墊所覆蓋處的區域中而顯著改變。此係具有在電場峰值出現在結構中之處的影響。觀察到的電場峰值之變化係主要有關於在裝置中的介電層(諸如:在圖3A、4A、與5A的層6)而非半導體層之一個因素,雖然同樣存有在該半導體層的表面之場分佈的小影響。
絕對電場輪廓線係針對於在結構中所關注的不同位置(NPOA、SPOA、與DPOA)的橫截面而描繪。以下係說明性的實例。
圖3A與3B係顯示個別的說明性的設計與針對於在圖示結構的NPOA區域之SiO2
的電場峰值之對應描繪的電場測量。在圖3A,於該種結構中的四個點係標示為P1、P2、P3、與P4以指出在絕對電場中的局部峰值的位置。針對於此些點的各者,對應的電場峰值之大小係顯示於圖3B。
圖4A與4B係顯示個別的說明性的設計與針對於在圖示結構的SPOA區域之SiO2
的電場峰值之對應描繪的電場測量。在圖4A,於該種結構中的四個點係標示為P1、P2、P3、與P4以指出在絕對電場中的局部峰值的位置。針對於此些點的各者,對應的電場峰值之大小係顯示於圖4B。
圖5A與5B係顯示個別的說明性的設計與針對於在圖示結構的DPOA區域之SiO2
的電場峰值之對應描繪的電場測量。在圖5A,於該種結構中的四個點係標示為P1、P2、P3、與P4以指出在絕對電場中的局部峰值的位置。針對於此些點的各者,對應的電場峰值之大小係顯示於圖5B。
關注的主要區域係可識別在此些繪圖中,如在圖3A與3B所見者係相關於NPOA區段,圖4A與4B係相關於SPOA區段,且圖5A與5B係相關於DPOA區段。在源極墊(SPOA)與汲極墊(DPOA)覆蓋區域所產生的峰值係比在其具有無墊覆蓋(NPOA)的區域中所觀察到的彼等者為較高許多。相較於在NPOA區段所觀察到之5.7 MV/cm的最大值,7.0 MV/cm的一個最大值係在DPOA區段所觀察到且6.1 MV/cm的一個最大值係在SPOA區段所觀察到。
因此已經觀察的是,在介電層與半導體表面所觀察的最大電場峰值係可取決於受到研究之裝置的區段而變化。
甚者,已經得知的是,一個高電場係可能存在於z維度,歸因於在該裝置的主動區域上之諸墊的放置。此些位置係無法藉著標準2D橫截面模擬模型之使用而模型化,且因此3D TCAD模擬係用以識別臨界區域。圖6係示意顯示針對於圖2之說明性的現有技術的裝置而沿著指部金屬化方向的橫截面。識別為關於一種BPOA結構之可能關注的一個點係在源極接觸墊的邊緣,參閱在圖6之中的P5。一個類似的峰值係可在汲極接觸墊邊緣所觀察到。
BPOA佈局係可能導致可靠度的問題,其中,時間相依的介電崩潰(TDDB)係尤其在長期操作、高電場操作、與高溫操作期間為重大的關注。
此關注係隨著在主動區域上的接合墊改變當偏壓時的電位所分佈在結構中之方式而產生,相較於不具有在主動區域上的墊之一種習用的指部結構交叉結構。高電場係不會僅有害於半導體而且有害於所使用之金屬化間的介電層,且可能導致諸如TDDB之可靠度的議題。
為了降低針對於TDDB的風險,在介電層中的電場峰值係必須透過在本文所揭示之智慧的場板設計而為最小化。
本發明係針對於替代的結構與方法,其係針對於使在介電質內與在半導體裝置的表面之電場峰值變小。
在另一個觀點,電場峰值係朝該半導體裝置的第三維(z方向)而在介電層內為最小化。
本發明的數個觀點係基於重新最佳化且因此改變場板的尺度,諸如:朝x或z方向,根據是否有直接放置在其上方的無墊、或是否一個低電壓的源極墊為放置在其上方、或一個高電壓的汲極墊為放置在其上方。
一種功率半導體裝置及用於製造功率半導體裝置的方法係揭示。該種裝置係包括:一個源極接合墊與一個汲極接合墊、包括其連接到該汲極接合墊的一個汲極場板之一個汲極金屬化結構、及包含其連接到該源極接合墊的一個源極場板之一個源極金屬化結構。該等接合墊之至少一者的至少一部分係直接位在一個主動區域之上。該等場板之至少一者的一個尺度係取決於相鄰該場板之一個結構而變化。相鄰該場板之結構係可為在一個特定位置而定位在該場板之上的一個接合墊。
在本發明的又一個觀點,一種半導體裝置係包含:一個源極接合墊;一個汲極接合墊;一個汲極金屬化結構,其包含一個汲極場板;及,一個源極金屬化結構,其包含一個源極場板。該等接合墊之至少一者的至少一部分係直接位在該裝置的一個主動區域之上。該等場板之至少一者的一個尺度係取決於相鄰結構而變化。
在本發明的再一個觀點,一種半導體裝置係提供。該半導體裝置的第一部分係包含在主動區域上的一個源極墊且包括一個源極墊金屬。該半導體裝置的第二部分係包含在主動區域上的無墊。該半導體裝置的第三部分係包含在主動區域上的一個汲極墊且包括一個汲極墊金屬。一個源極金屬化場板係具有定位在該半導體裝置的第一、第二與第三部分中之部分。該源極金屬化場板係具有定位在半導體裝置的該等部分之至少一者中的一個尺度,其為不同於定位在該半導體裝置的其他部分之至少一者中的一個尺度。一個汲極金屬化場板係具有定位在該半導體裝置的第一、第二與第三部分中之部分。該汲極金屬化場板係具有定位在半導體裝置的該等部分之至少一者中的一個尺度,其為不同於定位在該半導體裝置的其他部分之至少一者中的一個尺度。
在本發明的另一個觀點,一種具有BPOA佈局的半導體裝置係提供包含:一個源極接合墊與一個汲極接合墊、包含其連接到該汲極接合墊的一個汲極場板之一個汲極金屬化結構、及包含其連接到該源極接合墊的一個源極場板之一個源極金屬化結構。該等接合墊之至少一者的至少一部分係直接位在該裝置的一個主動區域之上。該等場板之至少一者的一個尺度係取決於相鄰該場板之結構而變化。
在本發明的另一個觀點,一種具有BPOA佈局的半導體裝置係提供,其中,一個場板係設置具有金屬化指部。該等金屬化指部的尺度係具有其相關於彼等部分是否為在該裝置之在主動區域上的無墊(NPOA)、在主動區域上的源極墊(SPOA)、或在主動區域上的汲極墊(DPOA)之區域中而具有變化的尺度之部分。
根據本發明的另一個觀點,諸如III氮化物基的裝置之一種異質結構III-V半導體基的裝置係提供有在至少一個主動區域之上的至少一個接合墊。諸如其包含金屬化的指部結構之場板的部分,在主動區域中之場板的部分係在該至少一個接合墊之下方的一個區域中而具有不同的尺度,相較於其在該區域之上為不存有任何墊的一個區域,俾使至少一個電場峰值係在該等介電層為降低,相較於在一種相同的場板設計係無關於在主動區域中的交叉指狀結構之上的一個接合墊之存在與否而運用之情形中的彼等者。
在本發明的再一個觀點,一種用於降低在半導體裝置內的電場強度之方法係提出。該種方法係包含:製造金屬場板,各個金屬場板係具有至少一個尺度,其基於該等金屬場板在該裝置內的一個位置以及在一個特定位置為相鄰於該等金屬場板之該裝置的一個對應結構而變化。
在本發明的又一個觀點,一種具有BPOA佈局的半導體裝置係提供,其包括在該等接合墊的內緣之上且延伸超過該等接合墊的內緣之場板。
在本發明的再一個觀點,一種半導體裝置係提供包括一個汲極墊金屬、與其直接定位在該汲極墊金屬之上的一個汲極墊場板。該汲極墊場板係具有延伸超過該汲極墊金屬的一個內緣之一個延伸部分。一個源極墊金屬係提供。一個源極墊場板係直接定位在該源極墊金屬之上。該源極墊場板係具有延伸超過該源極墊金屬的一個內緣之一個延伸部分。
本文所提出的說明係致使熟習此技藝人士能夠作成且利用陳述的說明實施例。然而,種種的修改、等效者、變化、組合、與替代者係將仍然對於熟習此技藝人士而言為容易明瞭。任何與所有該等修改、變化、等效者、組合、與替代者係意圖為歸屬於由申請專利範圍所界定之本發明的精神與範疇之內。
某些術語係僅為了方便而使用於以下說明且非限制性。字詞“右”、“左”、“頂”、與“底”係標出在圖式中所作參考的方向。如在申請專利範圍與在說明書的對應部分所使用,字詞“一個”係定義為包括一個或多個所提及的項目,除非是另為指明。此術語係包括以上明確敘述的字詞、其衍生字詞、與類似含義的字詞。跟隨諸如“A、B、或C”之一系列的二個或多個項目之片語“至少一者”係意指A、B、或C之任何個別者以及其任何組合。
本文所揭示者係具有在主動區域上的接合墊(BPOA)佈局之功率半導體裝置的實施例。一個場板組態係提供,其構成以降低電場峰值,藉以當一個裝置係操作在off狀態時、在高電場之下而保護金屬化間的介電質或鈍化介電質與一個半導體表面。在一個實施例中,一種功率半導體裝置係具有一個可變的最佳化場板結構在上方且一個主動區域在下方。在另一個實施例中,場板係附加在上方且延伸超過接合墊邊緣的內部部分,用以降低在彼等位置所觀察到的電場。
圖7係示意顯示本發明之一個實施例的俯視圖,顯示其具有一種BPOA佈局之一種功率半導體裝置200。一個源極場板FS’係製造為具有源極指部金屬化3’,且一個汲極場板FD’係製造為具有汲極指部金屬化5’。
源極指部金屬化3’係具有在一個源極接合墊SBP’的源極墊金屬2’ (一個SPOA區段)之下的第一部分101、在其上不具有墊(即:並非在源極墊金屬2’或一個汲極接合墊DBP’的汲極墊金屬4’ (一個NPOA區段)之下)的第二部分102、與在汲極墊金屬4’ (一個DPOA區段)之下的第三部分103。汲極指部金屬化5’係具有在汲極墊金屬4’ (一個DPOA區域或區段)之下的第一部分201、在其上不具有墊(即:並非在汲極墊金屬4’或源極墊金屬2’ (一個NPOA區域或區段)之下)的第二部分202、與在源極墊金屬2’ (一個SPOA區域或區段)之下的第三部分203。
視相較於裝置的相鄰結構之該部分的位置而定,指部金屬化之不同部分的尺度係可沿著各個該種指部金屬化的長度而變化。一個指部金屬化之一個部分或區段的尺度係可考慮為面積、長度、寬度、厚度或高度、體積、或彼等參數的任一者之任何組合。
如在圖7所示,一個場板之指部金屬化的一個尺度(在此實例中為朝x方向的寬度)係當直接在場板之上的結構為某種型式者而為固定。同時,指部金屬化的尺度係當不同結構(例如:不同的墊結構,諸如在SPOA區域之源極墊金屬、或在DPOA區域之汲極墊金屬)為在一個特定場板結構之上或不在其之上(如同在NPOA區域)而為不同或變化。
在圖7所示的實例中,一個源極金屬場板FS’之源極指部金屬化3’的一個尺度係具有當該場板在一個源極接合墊之下的一個尺度值(例如:一個特定寬度)、當在無接合墊之下的一個較小尺度值(例如:一個較小相對寬度)、以及當在一個汲極接合墊之下的一個更小尺度值(例如:一個最小相對寬度)。同理,在圖7所示的實例中,一個汲極金屬場板FD’之汲極指部金屬化5’的一個尺度係具有當該場板在一個汲極接合墊之下的一個尺度值(例如:一個特定寬度)、當在無接合墊之下的一個較小值(例如:一個較小相對寬度)、以及當在一個源極接合墊之下的一個更小值(例如:一個最小相對寬度)。圖7係亦顯示針對於在其進一步論述於下文之圖8A、9A、與10A所示的視圖之橫截面切割線。
如在圖7所示,源極指部金屬化3’的第一部分101係具有一個尺度(ss1i
),其為大於第二部分102的尺度(ns1i
)。源極指部金屬化3’的第一部分101係亦具有一個尺度(ss1i
),其為大於第三部分103的尺度(ds1i
)。第二部分102係具有一個尺度(ns1i
) ,其為大於第三部分103的尺度(ds1i
)。因此,第一部分101的尺度>第二部分102的尺度>第三部分103的尺度。是以,在圖示的實例中,ss1i
>ns1i
>ds1i
。
在圖7所示的實施例中,汲極指部金屬化5’的第一部分201係具有一個尺度(dd1i
),其為大於第二部分202的尺度(nd1i
)。汲極指部金屬化5’的第一部分201係具有一個尺度(dd1i
),其亦為大於第三部分203的尺度(sd1i
)。第二部分202係具有一個尺度(nd1i
) ,其為大於第三部分203的尺度(sd1i
)。因此,第一部分201的尺度>第二部分202的尺度>第三部分203的尺度。是以,在圖示的實例中,dd1i
>nd1i
>dd1i
。
應指明的是,尺度ss1i
、ns1i
、與ds1i
係可用不同方式而變化,俾使ss1i
≠ns1i
≠ds1i
,且尺度dd1i
、nd1i
、與dd1i
係可用不同方式而變化,俾使dd1i
≠nd1i
≠dd1i
。
圖8A、9A、與10A係概括顯示根據本發明的揭示內容之一種BPOA半導體裝置的配置,其具有一個基板9’、在基板9’之上的一個緩衝層8’、在緩衝層8’之上的一個GaN層7’、與在GaN層7’之上的一個AlGaN層1’。一個閘極端子10’係設置為包含一個高度p摻雜的GaN蓋11’,其定位在AlGaN層1’之上。一個表面鈍化介電質15’係覆蓋閘極10’且為定位在一個源極端子13’與一個汲極端子14’之間,源極端子13’係延伸自其定位在源極金屬化3’之下方的第一通孔12’,汲極端子14’係延伸自其定位在汲極金屬化5’之下方的第二通孔12’。諸如SiO2
層之一個金屬化間的介電質或鈍化介電層6’係定位在表面鈍化介電質15’之上且位在該等通孔12’之間。如由箭頭所示,一個閘極汲極偏移長度LGD
係從閘極10’的一側而達到汲極端子14’。一個選用式的基板端子16’係可設置在該裝置的下部,但此係並非必要條件。形成圖7之所示的元件、構件、與諸層之種種材料係可為類似於相關於圖2、3A、4A、5A與6所述的彼等者。
圖8A與8B、圖9A與9B、以及圖10A與10B係顯示在源極與汲極金屬化場板結構為根據本文揭示內容而最佳化之後的設計與個別結果。比較係和其為由上文所分析及論述之說明性的現有技術的裝置所得到之在圖3A與3B、圖4A與4B、以及圖5A與5B之中的結果而作成。
圖8A係顯示如圖7所示之具有一種BPOA佈局的功率半導體裝置之NPOA區域的橫截面圖,其沿著圖7的指示橫截面區域而取得。NPOA區段係對應於源極指部金屬化3’的第二部分102與汲極指部金屬化5’的第二部分202。在此NPOA區域橫截面,源極場板FS係具有在源極指部金屬化3’的尺度為ns1i’
(其對應於在圖7所示之ns1i
的一部分),且汲極場板係具有在汲極指部金屬化5的尺度為nd1i’
(其對應於在圖7所示之nd1i
的一部分)。
如在圖8A所示,在結構中的種種點係識別為P1、P2、P3、與P4。圖8B係顯示在圖8A所示的裝置之該結構的一個NPOA區段中的點P1、P2、P3、與P4之在SiO2
的對應的電場峰值。
圖9A係顯示如圖7所示之裝置的一個實施例,其包括SPOA區域的一個橫截面。如在圖9A所示,一個上方的源極墊金屬2’係定位在其包括源極金屬化3’的一個源極場板FS’之上,且一個通孔12’係設置在源極墊金屬2’與源極金屬化3’之間。一個源極場板FS’係製造為具有源極指部金屬化3’,且一個汲極場板FD’係製造為具有汲極指部金屬化5’。SPOA區段係對應於源極指部金屬化3’的第一部分101與汲極指部金屬化5’的第三部分203。在此SPOA區域橫截面,源極場板FS’係具有在源極指部金屬化3’的尺度為ss1i’
(其對應於在圖7所示之ss1i
的一部分),且汲極場板係具有在汲極指部金屬化5’的尺度為sd1i’
(其對應於在圖7所示之sd1i
的一部分)。
尺度ss1i
係可為不同於尺度ns1i
,且尺度sd1i
係可為不同於尺度nd1i
。舉例來說,在一個SPOA區段之圖示的實例中,至少該源極指部金屬化3’的區段101的寬度係大於源極指部金屬化3’的區段102的寬度。在該例中,尺度ss1i
>尺度ns1i
。在一個SPOA區段之圖示的實例中,至少該汲極指部金屬化5’的區段202的寬度係大於汲極指部金屬化5’的區段203的寬度。在該例中,尺度nd1i
>尺度sd1i
。
如在圖9A所示,在結構中的種種點係識別為P1、P2、P3、與P4。圖9B係顯示針對於圖9A的裝置之在該結構的一個SPOA區段中的點P1、P2、P3、與P4之在SiO2
的對應的電場峰值。
圖10A係顯示根據圖7之裝置的一個實施例,其包括DPOA區域的一個橫截面。如在圖10A所示,一個上方的汲極墊金屬4’係定位在汲極金屬化5’之上,且一個通孔12’係設置在汲極墊金屬4’與汲極金屬化5’之間。一個場板FS’係製造為具有源極指部金屬化3’,且另一個場板FD’係製造為具有汲極指部金屬化5’。DPOA區段係對應於源極指部金屬化3’的第三部分103與汲極指部金屬化5’的第一部分201。在此SPOA區域橫截面,源極場板係具有在源極指部金屬化3’的尺度為ds1i’
(其對應於在圖7所示之ds1i
的一部分)且汲極場板係具有在汲極指部金屬化5’的尺度為dd1i’
(其對應於在圖7所示之dd1i
的一部分)。
尺度ds1i
係可為不同於尺度ns1i
及/或ss1i
。舉例來說,在一個DPOA區段之圖示的實例中,至少該源極指部金屬化3’的區段103的寬度係小於源極指部金屬化3’的區段102的寬度,且小於源極指部金屬化3’的區段101的寬度。在該例中,尺度ss1i
>尺度ns1i
>尺度ds1i
。
尺度dd1i
係可為不同於尺度nd1i
及/或sd1i
。舉例來說,在一個DPOA區段之圖示的實例中,至少該汲極指部金屬化5’的區段201的寬度係大於汲極指部金屬化5’的區段202的寬度,且大於汲極指部金屬化5’的區段203的寬度。在該例中,尺度dd1i
>尺度nd1i
>尺度sd1i
。
如在圖10A所示,在結構中的種種點係識別為P1、P2、P3、與P4。圖10B係顯示針對於其運用本文所述的場板結構的一種裝置之在該結構的一個DPOA區段中的點P1、P2、P3、與P4之在SiO2
的對應的電場峰值。
假設高電壓墊汲極與低電壓墊源極係均放置在主動區域之上,在如先前所識別之一種功率半導體裝置的所有三個不同區段(NPOA、SPOA、DPOA)的金屬化間介電質所觀察到的電場峰值之降低係可根據在本文所揭示的配置而達成。
舉例來說,比較如圖3A所示的一種現有技術的NPOA區段之測量電場峰值和如圖8A所示之根據本發明揭示內容的一種裝置之電場峰值係顯示在電場峰值的降低。如在圖3B與8B的描繪的測量所示,關於點P2之描繪的測量係顯示在電場峰值的降低為從5.6 MV/cm到3.5 MV/cm。點P3之描繪的測量係顯示在電場峰值的降低為從5.7 MV/cm到4.1 MV/cm。點P4之描繪的測量係顯示在電場峰值的降低為從2.7 MV/cm到2.4 MV/cm。
比較如圖4A所示的一種現有技術的SPOA區段之測量電場峰值和如圖9A所示之根據本發明揭示內容的一種裝置之電場峰值係顯示在電場峰值的降低。如在圖4B與9B的描繪的測量所示,關於點P2之描繪的測量係顯示在電場峰值的降低為從6.0 MV/cm到4.0 MV/cm。點P3之描繪的測量係顯示在電場峰值的降低為從5.0 MV/cm到3.2 MV/cm。
比較如圖5A所示的一種現有技術的DPOA區段之測量電場峰值和如圖10A所示之根據本發明揭示內容的一種裝置之電場峰值係顯示在電場峰值的降低。如在圖5B與10B的描繪的測量所示,關於點P2之描繪的測量係顯示在電場峰值的降低為從5.2 MV/cm到3.2 MV/cm。點P3之描繪的測量係顯示在電場峰值的降低為從6.4 MV/cm到5.1 MV/cm。
圖11係示意顯示根據一種半導體裝置300的另一個實施例之一種BPOA佈局的俯視圖。圖11係類似於圖7,除了在圖11的實施例中,例如該等場板之指部金屬化的寬度之一個尺度係連續變化,俾使該等指部金屬化的側邊係從在一個源極接合墊的個別源極金屬或一個汲極接合墊的汲極金屬之下的一個較大尺度部分301而漸縮、傾向、或傾斜到在源極金屬與汲極金屬墊NPOA區段之間的一個中間尺度部分302、到在相對的個別源極金屬或汲極金屬墊之下的一個較小尺度部分303,如同此情形可能為者。如所顯示,該等場板係從區段301而漸縮,持續為漸縮通過區段302,且持續為漸縮通過區段303,俾使寬度(且因此為一個尺度)係取決於一個場板是否在一個源極接合墊、一個汲極接合墊、或無接合墊之下而為不同。
圖12與13係顯示半導體裝置400的一個實施例,其具有一個場板為延伸超過一個內部接合墊邊緣,其中,場板係位在該等接合墊之上方。如在圖12所示,在裝置的不同區域中之指部金屬化的尺度係無須變化。圖13係示意顯示沿著在圖12所示之裝置的指定區域而取得的橫截面。根據此實施例,一個源極場板17”與一個汲極場板18”係位在接合墊2”、4”之上方。源極場板17”與汲極場板18”的內部部分30、31係亦延伸超過接合墊2”、4”的內部邊緣部分40、41,如在圖13所示。如在圖12與13所示之源極場板17”與汲極場板18”的延伸與定位係降低在汲極墊邊緣的電場峰值,諸如:在圖13所指出的P5。
圖14A、14B、與14C係顯示圖12與13的實施例之電腦模型化,其說明一種BPOA結構,具有一個場板為定位在該等接合墊之上、且朝內延伸為超過該等接合墊。在圖14A所示的圖例係顯示該源極場板17”與汲極場板18”為定位之處的開放區域,在接合墊2”、4”之上。此種配置係進而降低在汲極墊邊緣的電場峰值,諸如:在圖14A所指出的位置P6。圖14B係顯示在定位的源極場板17”與汲極場板18”以及接合墊2”、4”。
圖14C係顯示此場板為如何降低在墊邊緣所達到的最大電場,當該場板結構係如在例如圖12與13所示而使用時。描繪的資料係比較一種現有技術的BPOA裝置和如同在圖12與13之根據本發明的一種BPOA裝置。透過一個墊邊緣場板之使用,在汲極墊與源極墊二者的邊緣所觀察到的電場峰值之降低係達成,如同例如在圖14C所示。在類似於圖13的P5之位置所分析之說明性的裝置中係觀察到4 MV/cm的最大絕對電場位準。如在圖14C所示,藉著如本文所提出而最佳化的場板,35%的電場峰值之降低係在圖13的位置P5為達成。
一種製造功率半導體的方法係亦提出,顯示在圖15的流程圖。概括而言,如在本發明的一種BPOA半導體裝置係藉由一種金屬有機化學氣相沉積(MOCVD, metal-organic chemical vapor deposition)方法之製造方法而形成,用於形成在基板9之上的緩衝層8、GaN層7、AlGaN層1、與pGaN層11。pGaN區域係藉由平版印刷術與蝕刻方法而形成。鈍化介電質15係藉由化學氣相沉積(CVD)而形成。論述的金屬層係藉由平版印刷術、金屬/介電質沉積與一種蝕刻程序而形成。理解的是,前述的形成方法係可於製造方法期間以任何可接受的順序而發生,且為不受限於特定的順序。
雖然本發明的特徵與元件係以特定組合而描述於實例的實施例中,各個特徵係可在沒有該等實例的實施例之其他特徵與元件的情況下而單獨使用或是以有無本發明的其他特徵與元件之種種組合而使用。在構件或零件的形式與比例以及在等效者的替代之變化係思及,由於環境係可在未脫離本發明的精神或範疇之情況下而建議或提供權宜之計。
前述的說明係已經為了說明描述目的而提出。該等說明係無意為窮舉性質或將本發明限制於所揭露的精確形式,且諸多的修改與變化係鑑於上述的揭示內容而為可能。本發明係將根據申請專利範圍與其等效者而理解。
1、1’‧‧‧AlGaN層
2、2’‧‧‧源極墊金屬
2”、4”‧‧‧接合墊
3、3’‧‧‧源極金屬化
4、4’‧‧‧汲極墊金屬
5、5’‧‧‧汲極金屬化
6、6’‧‧‧介電質或鈍化介電層
7、7’‧‧‧GaN層
8、8’‧‧‧緩衝層
9、9’‧‧‧基板
10、10’‧‧‧閘極端子
11、11’‧‧‧GaN蓋
12、12’‧‧‧通孔
13、13’‧‧‧源極端子
14、14’‧‧‧汲極端子
15、15’‧‧‧表面鈍化介電質
16、16’‧‧‧基板端子
17”‧‧‧源極場板
18”‧‧‧汲極場板
30、31‧‧‧內部部分
40、41‧‧‧內部邊緣部分
100‧‧‧半導體裝置
101‧‧‧源極指部金屬化的第一部分
102‧‧‧源極指部金屬化的第二部分
103‧‧‧源極指部金屬化的第三部分
200‧‧‧功率半導體裝置
201‧‧‧汲極指部金屬化的第一部分
202‧‧‧汲極指部金屬化的第二部分
203‧‧‧汲極指部金屬化的第三部分
300‧‧‧半導體裝置
301‧‧‧較大尺度部分
302‧‧‧中間尺度部分
303‧‧‧較小尺度部分
400‧‧‧半導體裝置
本發明的實施例係作為舉例且非作為限制而說明於伴隨圖式,其中,同樣的參考標號係指出類似的元件。
圖1係顯示一種現有技術的半導體裝置的立體圖。
圖2係顯示其具有BPOA佈局之一種現有技術的半導體裝置的俯視圖。
圖3A係顯示其沿著圖2的指定區域所取得之圖2的裝置的橫截面。
圖3B係顯示在圖3A的結構內之絕對電場的標繪圖。
圖4A係顯示其沿著圖2的指定區域所取得之圖2的裝置的橫截面。
圖4B係顯示在圖4A的結構內之絕對電場的標繪圖。
圖5A係顯示其沿著圖2的指定區域所取得之圖2的裝置的橫截面。
圖5B係顯示在圖5A的結構內之絕對電場的標繪圖。
圖6係顯示其沿著圖2的指定區域所取得之圖2的裝置的橫截面。
圖7係顯示其具有BPOA佈局之根據本發明的一種半導體裝置之一個實施例的俯視圖。
圖8A係顯示其沿著圖7的指定區域所取得之圖7的實施例的橫截面。
圖8B係顯示在圖8A的結構內之絕對電場的標繪圖。
圖9A係顯示圖7的實施例的第二橫截面,具有關於標示的測量之特定點。
圖9B係顯示在圖9A的結構內之絕對電場的標繪圖。
圖10A係顯示圖7之一種半導體裝置的實施例的第三橫截面,具有關於標示的測量之特定點。
圖10B係顯示在圖10A的結構內之絕對電場的標繪圖。
圖11係顯示一種半導體裝置之一個實施例的俯視圖,該半導體裝置係具有傾斜的側邊與變化的尺度之源極指部金屬化與汲極指部金屬化。
圖12係顯示一種半導體裝置之一個實施例的俯視圖,該半導體裝置係具有在接合墊邊緣的一個場板。
圖13係顯示圖12的實施例的橫截面。
圖14A係顯示其關於在圖12所示的實施例之電腦模型化的立體圖與橫截面圖。
圖14B係顯示在圖12所示之電腦模型化的附加的視圖。
圖14C係顯示在圖12的結構內之絕對電場的標繪圖。
圖15係根據本發明之一種用於形成半導體裝置的說明性的製造方法之流程圖。
Claims (16)
- 一種半導體裝置,其包含: 源極接合墊; 汲極接合墊; 汲極金屬化結構,其包含汲極場板;及 源極金屬化結構,其包含源極場板; 其中該源極接合墊或該汲極接合墊之至少一者的至少一部分係直接位在該裝置的主動區域之上;且 其中該汲極場板或該源極場板之至少一者的尺度係取決於相鄰結構而變化。
- 如請求項1所述之半導體裝置,其中該相鄰結構的至少一部分係直接位在該汲極場板或該源極場板的至少一者之上或之下。
- 如請求項1所述之半導體裝置,其中該汲極場板或該源極場板之至少一者的尺度係取決於該相鄰結構是否包括源極接合墊、汲極接合墊或無接合墊而變化。
- 如請求項1所述之半導體裝置,其中該汲極場板或該源極場板之至少一者的尺度係連續變化。
- 如請求項1所述之半導體裝置,其中該汲極場板或該源極場板之至少一者係具有當直接在該汲極場板或該源極場板之上的結構為第一結構時的第一尺度、以及當直接在該汲極場板或該源極場板之上的結構為不同於該第一結構的第二結構時的第二尺度,該第二尺度係不同於該第一尺度。
- 一種半導體裝置,其包含: 第一部分,其包含在主動區域上的源極墊且包括源極墊金屬; 第二部分,其包含在主動區域上的無墊; 第三部分,其包含在主動區域上的汲極墊且包括汲極墊金屬; 源極金屬化場板,其具有定位在該第一、第二與第三部分中的部分,該源極金屬化場板係具有定位在該部分之至少一者中的尺度,其為不同於定位在其他部分之至少一者中的尺度; 汲極金屬化場板,其具有定位在該第一、第二與第三部分中的部分,該源極金屬化場板係具有定位在該部分之至少一者中的尺度,其為不同於定位在其他部分之至少一者中的尺度。
- 如請求項6所述之半導體裝置,其中該源極金屬化場板係具有在該第一、第二與第三部分之各者中的不同尺度。
- 如請求項7所述之半導體裝置,其中該汲極金屬化場板係具有在該第一、第二與第三部分之各者中的不同尺度。
- 如請求項6所述之半導體裝置,其中該源極金屬化場板的尺度係連續變化。
- 如請求項9所述之半導體裝置,其中該汲極金屬化場板的尺度係連續變化。
- 一種半導體裝置,其包含: 汲極墊金屬; 汲極墊場板,其直接定位在該汲極墊金屬之上,該汲極墊場板係具有延伸超過該汲極墊金屬的內緣之延伸部分; 源極墊金屬; 源極墊場板,其直接定位在該源極墊金屬之上,該源極墊場板係具有延伸超過該源極墊金屬的內緣之延伸部分。
- 一種用於降低在半導體裝置內的電場強度之方法,該種方法係包含:製造金屬場板,各個金屬場板係具有至少一個尺度,其基於該金屬場板在該裝置內的位置以及在特定位置為相鄰於該金屬場板之該裝置的對應結構而變化。
- 如請求項12所述之方法,其包含:製造相鄰於該至少一個場板之結構的至少一部分為直接位在該場板之上或之下。
- 如請求項12所述之方法,其包含:取決於直接在該場板之上的該結構是否包括源極接合墊、汲極接合墊或無接合墊而改變該金屬場板的尺度。
- 如請求項12所述之方法,其中該場板係具有當直接在該場板之上的結構為第一結構時的第一尺度、以及當直接在該場板之上的結構為不同於該第一結構之第二結構時的第二尺度,該第二尺度係不同於該第一尺度。
- 如請求項12所述之方法,其包含:製造該至少一個場板,俾使該至少一個場板的尺度係連續變化。
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US9722063B1 (en) | 2016-04-11 | 2017-08-01 | Power Integrations, Inc. | Protective insulator for HFET devices |
US10529802B2 (en) * | 2017-09-14 | 2020-01-07 | Gan Systems Inc. | Scalable circuit-under-pad device topologies for lateral GaN power transistors |
JP6967024B2 (ja) * | 2019-02-04 | 2021-11-17 | 株式会社東芝 | 半導体装置及びその製造方法 |
DE112021003325T5 (de) * | 2020-06-19 | 2023-04-27 | Finwave Semiconductor, Inc. (nd.Ges.des Staates Delaware) | III-Nitrid-Diode mit modifiziertem Zugangsbereich |
JPWO2023042617A1 (zh) * | 2021-09-14 | 2023-03-23 | ||
DE112022004823T5 (de) * | 2021-11-09 | 2024-07-18 | Rohm Co., Ltd. | Halbleiterbauteil |
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JP2010219117A (ja) * | 2009-03-13 | 2010-09-30 | Toshiba Corp | 半導体装置 |
CN102013437B (zh) | 2009-09-07 | 2014-11-05 | 苏州捷芯威半导体有限公司 | 半导体器件及其制造方法 |
US9093432B2 (en) | 2011-09-23 | 2015-07-28 | Sanken Electric Co., Ltd. | Semiconductor device |
US9087718B2 (en) * | 2013-03-13 | 2015-07-21 | Transphorm Inc. | Enhancement-mode III-nitride devices |
JP6186832B2 (ja) | 2013-04-18 | 2017-08-30 | 富士通株式会社 | 化合物半導体装置及びその製造方法 |
US10566429B2 (en) * | 2013-08-01 | 2020-02-18 | Dynax Semiconductor, Inc. | Semiconductor device and method of manufacturing the same |
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US9590053B2 (en) * | 2014-11-25 | 2017-03-07 | Taiwan Semiconductor Manufacturing Co., Ltd. | Methodology and structure for field plate design |
SG10201503305PA (en) * | 2015-04-27 | 2016-11-29 | Globalfoundries Sg Pte Ltd | Lateral high voltage transistor |
US9755027B2 (en) * | 2015-09-15 | 2017-09-05 | Electronics And Telecommunications Research Institute | Electronical device |
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US9722063B1 (en) * | 2016-04-11 | 2017-08-01 | Power Integrations, Inc. | Protective insulator for HFET devices |
US10217827B2 (en) | 2016-05-11 | 2019-02-26 | Rfhic Corporation | High electron mobility transistor (HEMT) |
US10224401B2 (en) * | 2016-05-31 | 2019-03-05 | Transphorm Inc. | III-nitride devices including a graded depleting layer |
US20180076310A1 (en) * | 2016-08-23 | 2018-03-15 | David Sheridan | Asymmetrical blocking bidirectional gallium nitride switch |
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