TW201942989A - 球焊用貴金屬被覆銀線及其製造方法、及使用球焊用貴金屬被覆銀線的半導體裝置及其製造方法 - Google Patents
球焊用貴金屬被覆銀線及其製造方法、及使用球焊用貴金屬被覆銀線的半導體裝置及其製造方法 Download PDFInfo
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Abstract
[課題]本發明之目的在於提供一種貴金屬被覆銀接合線,其在以接合線將半導體晶片的電極與引線框架等的電極連接的半導體裝置中,即使在汽車等嚴苛的高溫高濕條件下亦可抑制接合界面的腐蝕,而避免發生導電不良。 [解決手段]本發明的球焊用之貴金屬被覆銀線,係在由純銀或銀合金所構成的芯材上具備貴金屬被覆層的貴金屬被覆銀線,其特徵為:線材包含至少1種硫族元素,貴金屬被覆層的至少1層為鈀層,鈀相對於線材整體的含量總計為0.01質量%以上5.0質量%以下,且硫族元素相對於線材整體的含量總計為0.1質量ppm以上100質量ppm以下。
Description
本發明係關於一種在以接合線將半導體裝置內之半導體晶片的電極與引線框架等的電極連接的半導體裝置中,較佳的球焊用貴金屬被覆銀線及其製造方法、及使用該線材的半導體裝置及其製造方法。
以往,作為將半導體裝置內之半導體晶片的電極與外部引線等連接的球焊線材,係使用金線、銅線、被覆銅線、及銀線。藉由放電使球焊線材其線材的一端熔融,並利用表面張力變成球形而凝固。凝固之球體稱為焊球(FAB;free air ball),藉由超音波併用熱壓接合法與半導體晶片的電極連接,另一端則與印刷基板或引線框架等的電極連接。接著,連接之接合線被樹脂密封而成為半導體裝置。
以往的接合線之金線的材料成本高,銅線或被覆銅線則具有材料堅硬而對半導體晶片造成損傷的課題。又,銀線雖成本低且柔軟而適合作為接合線,但純銀線在大氣中長期放置則表面硫化,銀合金線因於純銀中使鈀或金合金化而會發生電阻率變高這樣的問題。
於是,為了解決上述課題,考量在銀線的表面被覆鈀等鉑族金屬的被覆銀接合線。然而,被覆銀接合線雖解決接合線表面硫化的問題,但要在汽車等高溫高濕的嚴苛環境下使用,相較於金線仍無法滿足接合可靠度。
例如,日本特開2013-033811號公報(下述專利文獻1)中提出一種鈀被覆銀接合線。該公報的第四圖(a)及(b)的顯微鏡影像顯示了FAB表面無鈀層溶解殘留部分的正球狀焊球。該公報的申請專利範圍第1項中記載了「一種球焊線材,其係用以藉由球焊法將半導體元件的電極(a)與電路配線基板的導體配線(c)連接的接合線(W),其特徵為:在由Ag所構成之芯材(1)外周面形成Pt或Pd的被覆層(2),並使該被覆層(2)之剖面積(At)與該線材(W)之剖面積(A)的比值(At/A×100)為0.1~0.6%」。
再者,該公報的第0021段中記載了「製作FAB時,在線材前端部與放電棒g之間放電以使線材前端熔融時,熔點高於Ag的Au、Pt或Pd堆積於FAB表面,故FAB(焊球b)表面形成Au、Pt或Pd的高濃度層,在該圖(b)中接下來的第一次(1st)接合時,有助於與電極a之接合界面的高可靠度化」。然而,Pt或Pd的被覆層會熔入FAB內部,因此即使添加至芯材的Au、Pt或Pd堆積於FAB表面而形成高濃度層,該高濃度層亦無法確保高溫高濕下接合界面的長期可靠度。
於是,有人提出日本特開2016-115875號公報(下述專利文獻2)。該公報的申請專利範圍第4項中揭示了「一種半導體裝置用接合線,其特徵為:該被覆層的最表面具有包含15~50at.%之Au的含Au區域,該含Au區域的厚度為0.001~0.050μm」…(中略)…「其特徵為包含芯材與形成於該芯材表面的被覆層;該芯材包含總計0.1~3.0at.%的Ga、In及Sn之1種以上,剩餘部分由Ag及不可避免的雜質所構成;該被覆層包含Pd及Pt之1種以上、或Pd及Pt之1種以上與Ag,剩餘部分由不可避免的雜質所構成;該被覆層的厚度為0.005~0.070μm」。然而,若於芯材中添加Ga、In及Sn,則發生接合線本身的電阻率上升的問題,而無法滿足作為鈀被覆銀接合線。 [先前技術文獻] [專利文獻]
[專利文獻1]日本特開2013-033811號公報 [專利文獻2]日本特開2016-115875號公報
[發明所欲解決之課題]
在以接合線將半導體晶片的電極與引線框架等的電極連接的半導體裝置中,若將球焊用貴金屬被覆銀線與半導體晶片之電極的鋁墊進行球焊,則在接合界面形成容易被腐蝕之銀與鋁的金屬間化合物。該金屬間化合物容易被腐蝕,故隨著時間腐蝕至接合界面的內部,最終在鋁墊與接合線之間生成腐蝕層而導致導電不良。於是,本發明之目的在於提供一種即使在汽車等嚴苛的高溫高濕條件下亦可抑制接合界面的腐蝕,而避免發生導電不良的貴金屬被覆銀接合線。 [解決課題之手段]
本發明的球焊用貴金屬被覆銀線,係在由純銀或銀合金所構成的芯材上具備貴金屬被覆層的貴金屬被覆銀線,其特徵為:線材包含至少1種硫族元素,貴金屬被覆層的至少1層為鈀層,鈀相對於線材整體的含量總計為0.01質量%以上5.0質量%以下,且硫族元素相對於線材整體的含量總計為0.1質量ppm以上100質量ppm以下。
本發明的球焊用貴金屬被覆銀線的製造方法,係製造在由純銀或銀合金所構成的芯材上具備貴金屬被覆層之貴金屬被覆銀線的方法,其特徵為:線材包含至少1種硫族元素,貴金屬被覆層的至少1層為鈀層,鈀相對於線材整體的含量總計為0.01質量%以上5.0質量%以下,且硫族元素相對於線材整體的含量總計為0.1質量ppm以上100質量ppm以下。
本發明的使用球焊用貴金屬被覆銀線的半導體裝置,係以球焊用之貴金屬被覆銀線將半導體裝置內之半導體晶片的電極與引線框架的電極、或半導體晶片的電極與基板的電極、或複數半導體晶片的電極之間連接的半導體裝置,其特徵為:球焊用之貴金屬被覆銀線在由純銀或銀合金所構成的芯材上具備貴金屬被覆層,線材包含至少1種硫族元素,貴金屬被覆層的至少1層為鈀層,鈀相對於線材整體的含量,總計為0.01質量%以上5.0質量%以下,且硫族元素相對於線材整體的含量,總計為0.1質量ppm以上100質量ppm以下。
本發明的使用球焊用貴金屬被覆銀線的半導體裝置之製造方法,係以球焊用之貴金屬被覆銀線將半導體裝置內之半導體晶片的電極與引線框架等的電極連接的半導體裝置之製造方法,其特徵為:球焊用貴金屬被覆銀線在由純銀或銀合金所構成的芯材上具備貴金屬被覆層,線材包含至少1種硫族元素,貴金屬被覆層的至少1層為鈀層,鈀相對於線材整體的含量總計為0.01質量%以上5.0質量%以下,且硫族元素相對於線材整體的含量總計為0.1質量ppm以上100質量ppm以下。 [發明之效果]
本發明可提供一種貴金屬被覆銀接合線,其在以接合線將半導體晶片的電極與引線框架等的電極連接的半導體裝置中,即使在汽車等嚴苛的高溫高濕條件下亦可抑制接合界面的腐蝕,而避免發生導電不良。再者,本發明之貴金屬被覆銀接合線亦可解決材料堅硬而對半導體晶片造成損傷這種以往的銅接合線或被覆銅接合線的課題,故可提供一種貴金屬被覆銀線不僅作為銀接合線或被覆銀接合線、甚至是以往的銅接合線或被覆銅接合線的代替品。
對本發明之實施形態進行說明。以下所示的實施形態,係用於將本發明之技術思想具體化,本發明並不限定於以下的例示。
本發明的基本概念是:藉由使貴金屬被覆層中含有熔點低於貴金屬被覆層的鈀、且與銀的反應性高的硫族元素,在球焊時可使鈀分布層穩定殘留於FAB表面。亦即,在FAB與鋁墊的接合界面中存在鈀分布層,藉此可抑制長期在水分或鹵素離子的影響下發生的腐蝕所導致的電阻上升,亦即導電不良。此外,硫族元素係指硫(S)、硒(Se)及碲(Te)。
硫族元素的熔點分別為:硫(S)113℃、硒(Se)220℃及碲(Te)450℃,比銀的熔點962℃更低。又,硫族元素的熔點,比貴金屬被覆層的鈀的熔點1,552℃及金的熔點1,064℃更低。
本發明之特徵的機制雖未完全明朗,但推測其特徵係在於熔融焊球的形成過程,因此順著時序說明形成FAB的製程。最初,隨著將接合線加熱,熔點最低的貴金屬被覆層內之硫族元素變成熔融狀態。硫族元素容易與芯材的銀反應,故熔融狀態的硫族元素被銀吸引。接著,熔點低的芯材之銀熔融,從小焊球成長成大焊球。此時,在芯材的銀與貴金屬被覆層的鈀的界面中,芯材最表層面的銀與硫族元素反應而形成硫族化銀(例如硫化銀等),該等硫族化銀覆蓋芯材的銀之最表層面的周圍。該等硫族化銀在芯材的銀與貴金屬被覆層的鈀之間發揮屏障效果,即使加熱溫度上升至鈀的熔點,亦可抑制貴金屬被覆層的鈀熔入芯材的銀。因貴金屬被覆層的鈀之一部分與芯材表面的銀合金化,雖未完全分離,但在FAB表面形成鈀或鈀-銀合金、或是鈀與鈀-銀合金兩者,並覆蓋在FAB表面上。將該層稱為鈀分布層。將形成有鈀分布層的FAB之剖面進行面分析的結果顯示於第一圖。
藉由以例如電子微探儀(EPMA;electron probe micro analyzer)對於將FAB中心部從線材頸部往焊球前端部裁切的面進行面分析,可確認FAB表面的鈀分布層。面分析係量測樣品在一定範圍內之元素分布的方法,係可視覺上了解各元素分布的分析方法。第一圖係藉由EPMA對FAB剖面的鈀分布進行面分析的結果。看起來白色的部分顯示鈀的分布,可知FAB表面形成有鈀分布層。又,EPMA難以量測的薄鈀分布層,雖無法進行視覺上的面分析,但可藉由以歐傑電子光譜法(AES;auger electron spectroscopy)從FAB表面往芯材進行深度分析而確認形成有鈀分布層。另外亦可藉由穿透式電子顯微鏡(TEM;transmission electron microscope)附屬的能量色散型X射線分析(EDX;energy dispersive x-ray spectrometry)等確認鈀分布層。如上述,將FAB表面分布有鈀定義為鈀分布層。
鈀分布層完全覆蓋FAB表面係解決本課題的最佳條件,但在接合時,只要以至少在與鋁墊的接合界面存在鈀的程度,使鈀分布層覆蓋FAB表面,即可充分解決本課題。亦即,藉由至少在與鋁墊的接合界面存在鈀分布層,可抑制因接合界面的腐蝕引起的電阻上升,亦即導電不良。第二圖中鈀熔入芯材的銀,係FAB表面未形成鈀分布層的狀態。第二圖的狀態無法解決本發明的課題。
又,在本發明的球焊用之貴金屬被覆銀線中,若在貴金屬被覆層(特別是被覆有堅硬之鈀層的情況等)的最外層被覆金層,因金的高延展性,而可防止拉線加工中線材表面的破裂或斷線。又,鑽石拉線模的磨耗減少,故可實現拉線模的長壽命化,亦有助於減少加工費用。此處所說的金層的被覆,可連成層狀,但亦可不必連成層狀。因為金即使散布成島狀,亦具有充分提高拉線加工性的效果。
此外,再次確認本發明之貴金屬被覆層中鈀層及金層的定義。各層係從線材整體的含量在計算上所要求的層,方便上使用「層」這樣的表達,但實際上含量較少的情況下,亦具有未連成層狀而散布成島狀的情況,故未形成層狀的島狀之狀態亦包含於「層」。因為島狀而未形成層狀的情況亦可充分解決本發明之課題。
再者,在本發明的球焊用貴金屬被覆銀接合線中,若芯材使用純度99.9質量%以上的銀,則可減少線材的電阻率,故為較佳,但銀與貴金屬被覆層的材料強度、展延性及伸長率有很大的差距,而成為在拉線加工中貴金屬被覆層從芯材的銀剝離,或發生斷線等的原因。因此可知,為了順利地進行拉線加工,若使芯材的銀含有微量的銅以提高芯材的強度,則貴金屬被覆層與芯材的材料強度及伸長率的差距變小,拉線時的加工性變得良好。此外,藉由將金、鉑或鈀等添加至芯材中,亦可得到相同的效果。
在本發明的球焊用貴金屬被覆銀接合線中,使鈀相對於線材整體的含量為0.01質量%以上5.0質量%以下的理由如下。亦即,使鈀的下限值為0.01質量%以上,係因為小於0.01質量%則無法以鈀分布層覆蓋FAB表面,而無法在FAB與鋁墊的接合界面抑制腐蝕。又,使鈀的上限值為5.0質量%以下,係因為若超過5.0質量%,則無法使FAB的真圓度穩定。
在本發明的球焊用貴金屬被覆銀接合線中,使貴金屬被覆層含有硫族元素係因為可知,若因應貴金屬被覆層的成分組成適當存在至少1種由硫(S)、硒(Se)及碲(Te)所構成之硫族元素,則可以鈀分布層覆蓋FAB表面。此外,雖藉由於貴金屬被覆層含有硫族元素可解決本發明之課題,但貴金屬被覆層係非常薄的層體,含量少的情況下亦可能並非層狀而形成島狀,故難以分析貴金屬被覆層中是否含有硫族元素,甚至是分析貴金屬被覆層內硫族元素的含量亦非常困難,故在申請專利範圍中,定義在線材整體中硫族元素的含量。
使硫族元素的下限值為0.1質量ppm以上,係因為小於0.1質量ppm則鈀分布層無法殘留於FAB的表面。又,使硫族元素的上限值為100質量ppm以下,係因為若超過100質量ppm,則無法使球焊時焊球的真圓度穩定。
在本發明的球焊用之貴金屬被覆銀接合線中,貴金屬被覆層較佳為進一步至少1層為金層。特佳係在上述鈀層的外周面形成金層。因為若在鈀層上設置金層並進行連續拉線,則可減少拉線模的磨耗。又,較佳係在上述鈀層的芯材面形成金層。因為金中間層變成緩衝墊而緩和連續拉線加工中芯材與鈀層之伸長率的差異,進而減少貴金屬被覆層的拉線加工不良。
使金相對於線材整體的含量的下限值為0.01質量%以上,係因為小於0.01質量%則無法抑制拉線加工不良。又,使金相對於線材整體的含量的上限值小於1.0質量%,係因為即使超過1.0質量%,拉線加工不良的抑制亦不會變化。少量的金即可充分發揮效果,且其價格昂貴,故較佳為盡量減少添加量。
上述芯材的銀合金較佳為含有0.005質量%以上2.0質量%以下的銅。使銅相對於線材整體的含量的下限值為0.005質量%以上,係因為小於0.005質量%則無法抑制拉線加工不良。又,使銅相對於線材整體的含量的上限值小於2.0質量%,係因為若超過2.0質量%,則電阻率上升,而且線材強度提高,拉線加工變得困難。此外,藉由使芯材的銀合金含有總計0.005質量%以上2.0質量%以下的金、鉑或鈀之至少1種亦可得到相同的效果。
此外,本發明的球焊用貴金屬被覆銀接合線中各元素的含量,係使用感應耦合電漿原子發射光譜法(ICP-AES;inductively coupled plasma atomic emission spectroscopy)或感應耦合電漿質譜法(ICP-MS;inductively coupled plasma mass spectrometry)或輝光放電質譜法(GDMS;glow discharge mass spectrometry)、二次離子質譜法(TOF-SIMS;time-of-flight secondary ion mass spectrometry)等進行測量。
又,針對本發明的球焊用貴金屬被覆銀接合線中積層於芯材之貴金屬被覆層的結構,可藉由以AES從接合線的表層往芯材在深度方向上進行分析而確認積層的順序。又,以機械研磨或聚焦離子束裝置(FIB;focused ion beam system)裁切出接合線的剖面,再以掃描式電子顯微鏡(SEM;scanning electron microscope)附屬的EDX、EPMA或TEM附屬的EDX進行表面部分之元素的線分析或多處的點分析亦可確認各元素的積層或配置。
此處,本發明中貴金屬被覆層的貴金屬元素、鈀中間層的鈀元素、金表皮層及金中間層的金元素,在各層中亦可無100質量%之部分且其係被合金化的情況,貴金屬被覆層、鈀中間層、金表皮層及金中間層被定義包含這種情況。 (製造方法)
接著,說明本發明的球焊用貴金屬被覆銀接合線的製造方法。此外,實施形態中球焊用貴金屬被覆銀接合線的製造方法並無特別限定於以下所述。 (芯材)
用於接合線之芯材的純銀或銀合金,可藉由將原料同時溶解而製造。溶解可使用電弧加熱爐、高頻加熱爐、電阻加熱爐等,較佳為使用連續鑄造爐。其順序如下。於碳坩堝中裝載預先秤量的原料,在真空或是氮氣或氬氣等不活潑氣體環境下使其加熱溶解後進行冷卻。藉由將所得到之純銀或銀合金的鑄錠重複進行輥軋加工或使用拉線模的拉拔加工、連續拉線加工,以使其細線化至最終線徑。 (貴金屬被覆層)
形成貴金屬被覆層的方法具有:於最終線徑的銀線上形成貴金屬被覆層的方法;或是於連續鑄造而成的銀線或中間線徑的銀線上形成貴金屬被覆層後,重複連續拉線以加工成最終線徑的方法。
於芯材的銀線表面上形成貴金屬被覆層的方法,可使用濕式鍍覆、乾式鍍覆法、熔融法等。濕式鍍覆法可以電鍍法、無電鍍敷法等進行製造。亦可組合被稱為擊噴鍍(strike plating)、閃鍍的電鍍法。亦可使用用於無電鍍敷的溶液為取代型、還原型、自溶型之任一種的方法。形成厚貴金屬被覆層的情況下,亦可在取代型鍍覆後併用自溶型鍍覆。乾式鍍覆法可使用:濺射法、離子鍍法、真空蒸鍍等的物理吸附法;或電漿化學氣相沉積(CVD;chemical vapour deposition)等的化學吸附。該等皆為乾式,故無需像濕式鍍覆法般在形成貴金屬被覆層後進行清洗,而沒有清洗時的表面汙染等的疑慮。
對形成上述銀線的方法進行具體說明。對於藉由溶解鑄造所得到的直徑3mm以上10mm以下的圓柱狀銀合金,進行拉拔加工以拉線至直徑1.2mm以上2.0mm以下。之後,使用拉線模連續進行拉線加工,藉此製作直徑300μm以上600μm以下的線材。亦可藉由連續鑄造進行該等步驟。
對上述在銀線上形成貴金屬被覆層的方法進行具體說明。可藉由濕式鍍覆形成貴金屬被覆層。於鈀層的鈀電鍍浴中添加作為結晶調整劑的硫(S)化合物、硒(Se)化合物或碲(Te)化合物進行調整。又,設置金層的情況下,係使用金電鍍浴。之後,重複進行拉線加工以拉線至最終線徑的直徑12μm以上60μm以下、較佳為直徑15μm以上35μm以下,並進行最終熱處理。
若最終熱處理於最終線徑的貴金屬被覆銀線連續拉線時一併進行,則可得到高生產性,故為有效。具體而言,具有下述方法:使最終線徑的貴金屬被覆銀線連續通過設定在適當溫度之電爐中的方法,或在將最終線徑的貴金屬被覆銀線捲繞成捲線等的狀態下,放置於設定適當溫度之烘箱中一定時間的方法。
若使用以本發明之實施形態所記載的製造方法製造的球焊用貴金屬被覆銀接合線進行球焊,則可發揮在FAB表面形成鈀的分布層,而可抑制因在鋁墊與接合線之間生成的金屬間化合物之腐蝕而發生的導電不良這樣優異的特性。再者,藉由使用本發明的球焊用貴金屬被覆銀接合線,可實現比以往的半導體裝置更高壽命的半導體裝置。
針對本發明之一實施形態的半導體裝置及其製造方法,參照第三圖說明其代表例。 以貴金屬被覆銀接合線4將半導體晶片2與引線框架3接合後,為了保護貴金屬被覆銀接合線4及接合部,以陶瓷或模製樹脂等進行密封。之後,使外部引線形成既定的形狀。最後經由電特性檢査及外觀檢査等的產品檢査、以及環境試驗及壽命試驗等的可靠度檢査形成半導體裝置1。
接著參照第四圖對本發明之另一實施形態的半導體裝置之內部的結構進行說明。 於基板5配置複數的半導體晶片2,以貴金屬被覆銀線4將基板5的電極6與半導體晶片2的電極(圖中未顯示)、半導體晶片2的電極(圖中未顯示)與半導體晶片2的電極(圖中未顯示)進行電性接合。此外,以貴金屬被覆銀線4進行電接合的半導體晶片2之電極,亦包含預先與在半導體晶片2上之電極接合的凸塊(圖中未顯示)。半導體裝置,具體而言係具有:邏輯IC、類比IC、離散半導體、記憶體、光學半導體等。
以下顯示實施例及比較例進一步說明本發明,但本發明只要不脫離其主旨即可,並不限定於以下實施例。 [實施例]
首先,對實施例進行說明。芯材使用純度為99.9質量%以上的銀,貴金屬被覆層使用金及鈀。所使用的方法是在將貴金屬被覆層積層至中間線徑的銀線上後,進行連續拉線以加工至最終線徑。於芯材的表面形成貴金屬被覆層的方法,係使用連續地運送線材同時浸漬於鍍覆浴的電鍍法。之後,對加工至最終線徑的接合線進行最終熱處理,製作從實施例1至實施例20的接合線。
接著,使用市售的接合裝置(K&S ICONN),吹出氮氣同時將製作之接合線形成FAB,藉由以超音波併用熱壓接方式所進行的球焊法,與加熱至200℃之評估用Si晶片上的鋁合金墊片進行第一次接合,在由42合金所構成之引線框架(200pin)上經實施鍍銀的引線之間,藉由以超音波併用熱壓接方式所進行的釘合式接合法進行第二次接合,將共計200條的線材接線。之後,觀察該壓接焊球的形狀。 (真圓度的評估)
壓接焊球的真圓度,係將接合線接合裝置的壓接焊球徑的縱向(施加超音波的方向)作為Y,將横向(與施加超音波正交的方向)作為X,以其比值,亦即Y/X進行評估。設定評估基準係:「○」(合格)為0.8~1.2、「×」(不合格)為0.79以下及1.21以上。然而,即使真圓度為「○」(合格),但關於具有偏芯現象的線材,真圓度的評估仍為「×」(不合格)。偏芯現象,係指壓接焊球形狀形成相對於線材軸不對稱的現象,偏芯越大,越容易因與鄰接之焊球接觸引起短路不良。又,偏芯亦可能引起接合強度不足。此外,經接合的實施例之線材的壓接焊球形狀,真圓度的評估如表1所示皆為「○」(合格)。表1顯示貴金屬被覆銀線的實施評估。
之後,以市售的環氧系樹脂將與鋁合金墊片接合的球焊線材密封,並測量電阻。電阻係使用KEITHLEY公司製的「Source Meter(型號2004)」,以專用的IC插槽及專門建置的自動測量系統進行測量,從探針往鄰接之外部引線之間(選擇半導體晶片上的墊片短路的成對引線)流通固定電流,使用測量探針之間電壓的直流四端子法進行測量。 (HAST可靠度評估)
接著,進行高加速壽命試驗(HAST;highly accelerated temperature and humidity stress test)。將上述所製作之線材放入HAST裝置內,在溫度130℃、相對濕度85%、2氣壓的氣體環境下放置192小時的方法,進行HAST可靠度評估。之後進行電阻測量,以與試驗前之電阻的上升率進行評估。選擇此評估方法的理由如下:因在線材的鋁接合界面所生成的銀與鋁之金屬間化合物的腐蝕,而發生在接合界面生成腐蝕層的狀況,因此接合面積變小,而導電性變差,進而導致電阻上升。因此,測量在HAST前後線材的電阻上升率,適合作為用以解決課題的評估方法。
結果顯示於表1中,將在HAST前後鄰接的100對外部引線之間的電阻上升率之平均值為20%以下的線材視為「○」(合格),將超過20%的線材視為「×」(不合格)。此外,實施例之線材在HAST後的電阻相較於HAST前的電阻,上升率的平均值皆在20%以下。
之後,以SEM附屬的EDX對評估用晶片上的鋁合金墊片與線材之接合界面的剖面進行分析,結果在接合界面檢測出鈀。該檢測出的鈀,係源自第一圖所示的形成於FAB表面的鈀分布層。亦即,係因為藉由覆蓋在FAB表面的鈀分布層與鋁合金墊片接合,抑制銀-鋁金屬間化合物的生成,以及鈀分布層抑制水分或氯對金屬間化合物的腐蝕,而有助於抑制電阻上升。 [比較例]
以與實施例相同的方法製作比較例的貴金屬被覆銀線。比較例的接合線與實施例相同,吹出氮氣同時形成FAB,結果在比較例23、24、26及27中,形成扭曲的偏芯焊球,真圓度的評估為「×」(不合格)。由該結果可知,真圓度係歸因於鈀的含量(質量%)及硫族元素的含量(質量%)。此外,在真圓度評估中「×」(不合格)的接合線,不實施HAST可靠度評估,故在表1為「-」(未實施)。
比較例21、22、25及28雖通過真圓度的評估,但HAST後電阻的上升率比HAST前超過20%,故為「×」(不合格)。以SEM附屬的EDX分析評估用晶片上的鋁合金墊片與接合線之接合界面的剖面,結果接合界面未檢測出鈀。由該結果可知,為了在接合界面檢測出鈀,亦即以鈀分布層覆蓋FAB表面,係受鈀的含量(質量%)及硫族元素的添加量所影響。又可知,在接合界面有無鈀,係解決本發明之課題的關鍵。
[表1]
由上述實施例及比較例的結果可知,評估用晶片上的鋁合金墊片與接合線的接合界面是否存在鈀,大幅影響接合線的導電性,亦即接合壽命。該接合界面的鈀,係來自第一圖所示的形成於FAB表面的鈀分布層。
如上所述,藉由使鈀分布層穩定殘留於FAB表面,可提供一種貴金屬被覆銀接合線,其即使在汽車等嚴苛的高溫高濕的條件下亦可抑制接合界面產生的腐蝕所導致的電阻上升,亦即導電不良。
又,本發明的球焊用之貴金屬被覆銀線,可發揮抑制因在鋁墊與接合線之間生成的金屬間化合物之腐蝕而發生的導電不良這樣優異的特性,故藉由將本發明的球焊用之貴金屬被覆銀接合線用於半導體裝置,可提供比以往的半導體裝置更高壽命的半導體裝置。 [產業上的可利用性]
本發明的球焊用之貴金屬被覆銀線,即使在高濕高溫的條件下亦可抑制電阻上升,除了邏輯IC、類比IC、離散半導體、記憶體以外,亦具有光學半導體等的各種用途。
1‧‧‧半導體裝置
2‧‧‧半導體晶片
3‧‧‧引線框架
4‧‧‧貴金屬被覆銀線
5‧‧‧基板
6‧‧‧電極
第一圖係形成鈀分布層之FAB的剖面圖。 第二圖係未形成鈀分布層之FAB的剖面圖。 第三圖係本發明之一實施形態的半導體裝置的結構圖。 第四圖係本發明之另一實施形態的半導體裝置之內部的結構圖。
Claims (20)
- 一種球焊用貴金屬被覆銀線,其係在由純銀或銀合金所構成的芯材上具備貴金屬被覆層的貴金屬被覆銀線,其特徵為:線材包含至少1種硫族元素,貴金屬被覆層的至少1層為鈀層,鈀相對於線材整體的含量總計為0.01質量%以上5.0質量%以下,且硫族元素相對於線材整體的含量總計為0.1質量ppm以上100質量ppm以下。
- 如申請專利範圍第1項之球焊用貴金屬被覆銀線,其中該貴金屬被覆層進一步至少1層為金層,且金相對於線材整體的含量為0.01質量%以上且小於1.0質量%。
- 如申請專利範圍第1項之球焊用貴金屬被覆銀線,其中該鈀層的外周面具備金層。
- 如申請專利範圍第1項之球焊用貴金屬被覆銀線,其中該鈀層的外周面及芯材面分別具備金層。
- 如申請專利範圍第1項之球焊用貴金屬被覆銀線,其中該芯材包含銅,且銅相對於線材整體的含量為0.005質量%以上2.0質量%以下。
- 一種球焊用貴金屬被覆銀線的製造方法,其係製造在由純銀或銀合金所構成的芯材上具備貴金屬被覆層之貴金屬被覆銀線的方法,其特徵為:線材包含至少1種硫族元素,貴金屬被覆層的至少1層為鈀層,鈀相對於線材整體的含量總計為0.01質量%以上5.0質量%以下,且硫族元素相對於線材整體的含量總計為0.1質量ppm以上100質量ppm以下。
- 如申請專利範圍第6項之球焊用貴金屬被覆銀線的製造方法,其中該貴金屬被覆層進一步至少1層為金層,且金相對於線材整體的含量為0.01質量%以上且小於1.0質量%。
- 如申請專利範圍第6項之球焊用貴金屬被覆銀線的製造方法,其中該鈀層的外周面具備金層。
- 如申請專利範圍第6項之球焊用貴金屬被覆銀線的製造方法,其中該鈀層的外周面及芯材面分別具備金層。
- 如申請專利範圍第6項之球焊用貴金屬被覆銀線的製造方法,其中該芯材包含銅,且銅相對於線材整體的含量為0.005質量%以上2.0質量%以下。
- 一種半導體裝置,其係具備至少1個半導體晶片、引線框架或基板,且以球焊用貴金屬被覆銀線將半導體晶片的電極與引線框架的電極、或半導體晶片的電極與基板的電極、或複數的半導體晶片的電極之間連接的半導體裝置,其特徵為:球焊用貴金屬被覆銀線在由純銀或銀合金所構成的芯材上具備貴金屬被覆層,線材包含至少1種硫族元素,貴金屬被覆層的至少1層為鈀層,鈀相對於線材整體的含量總計為0.01質量%以上5.0質量%以下,且硫族元素相對於線材整體的含量總計為0.1質量ppm以上100質量ppm以下。
- 如申請專利範圍第11項之半導體裝置,其具有該貴金屬被覆層進一步至少1層為金層、且金相對於線材整體的含量為0.01質量%以上且小於1.0質量%的球焊用之貴金屬被覆銀線。
- 如申請專利範圍第11項之半導體裝置,其具有該鈀層的外周面具備金層的球焊用之貴金屬被覆銀線。
- 如申請專利範圍第11項之半導體裝置,其具有該鈀層的外周面及芯材面分別具備金層的球焊用之貴金屬被覆銀線。
- 如申請專利範圍第11項之半導體裝置,其中該芯材包含銅,且銅相對於線材整體的含量為0.005質量%以上2.0質量%以下。
- 一種半導體裝置之製造方法,其係具備至少1個半導體晶片、引線框架或基板,且以球焊用貴金屬被覆銀線將半導體晶片的電極與引線框架的電極、或半導體晶片的電極與基板的電極、或複數半導體晶片的電極之間連接的半導體裝置之製造方法,其特徵為:球焊用貴金屬被覆銀線在由純銀或銀合金所構成的芯材上具備貴金屬被覆層,線材包含至少1種硫族元素,貴金屬被覆層的至少1層為鈀層,鈀相對於線材整體的含量總計為0.01質量%以上5.0質量%以下,且硫族元素相對於線材整體的含量總計為0.1質量ppm以上100質量ppm以下。
- 如申請專利範圍第16項之半導體裝置之製造方法,其具有該貴金屬被覆層進一步至少1層為金層、且金相對於線材整體的含量為0.01質量%以上且小於1.0質量%的球焊用之貴金屬被覆銀線。
- 如申請專利範圍第16項之半導體裝置之製造方法,其具有該鈀層的外周面具備金層的球焊用之貴金屬被覆銀線。
- 如申請專利範圍第16項之半導體裝置之製造方法,其具有該鈀層的外周面及芯材面分別具備金層的球焊用之貴金屬被覆銀線。
- 如申請專利範圍第16項之半導體裝置之製造方法,其具有該芯材包含銅、且銅相對於線材整體的含量為0.005質量%以上2.0質量%以下的球焊用之貴金屬被覆銀線。
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JP2013033811A (ja) | 2011-08-01 | 2013-02-14 | Tatsuta Electric Wire & Cable Co Ltd | ボールボンディングワイヤ |
US20150322586A1 (en) * | 2011-11-26 | 2015-11-12 | Microbonds Inc. | Bonding wire and process for manufacturing a bonding wire |
TW201336599A (zh) * | 2012-03-12 | 2013-09-16 | Wire technology co ltd | 銀-鈀合金表面鍍金屬薄膜之複合線材及其製造方法 |
KR101902611B1 (ko) * | 2012-03-23 | 2018-09-28 | 스미또모 베이크라이트 가부시키가이샤 | 반도체 장치 |
JP5213146B1 (ja) * | 2012-10-03 | 2013-06-19 | 田中電子工業株式会社 | 半導体装置接続用銅ロジウム合金細線 |
TWI525726B (zh) * | 2013-11-25 | 2016-03-11 | Preparation method of package wire with skin layer and its finished product | |
WO2015115241A1 (ja) * | 2014-01-31 | 2015-08-06 | タツタ電線株式会社 | ワイヤボンディング及びその製造方法 |
MY162021A (en) * | 2014-03-31 | 2017-05-31 | Nippon Micrometal Corp | Bonding wire for semiconductor device use and method of production of same |
TWI555155B (zh) * | 2014-04-17 | 2016-10-21 | 光洋應用材料科技股份有限公司 | 銀合金線材 |
JP6516465B2 (ja) * | 2014-12-17 | 2019-05-22 | 日鉄ケミカル&マテリアル株式会社 | 半導体装置用ボンディングワイヤ |
JP6002300B1 (ja) * | 2015-09-02 | 2016-10-05 | 田中電子工業株式会社 | ボールボンディング用パラジウム(Pd)被覆銅ワイヤ |
JP6047214B1 (ja) * | 2015-11-02 | 2016-12-21 | 田中電子工業株式会社 | ボールボンディング用貴金属被覆銅ワイヤ |
JP6507329B1 (ja) * | 2019-02-08 | 2019-04-24 | 田中電子工業株式会社 | パラジウム被覆銅ボンディングワイヤ、ワイヤ接合構造、半導体装置及び半導体装置の製造方法 |
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2018
- 2018-04-02 JP JP2018070813A patent/JP6869920B2/ja active Active
- 2018-04-19 CN CN201880072388.2A patent/CN111344846A/zh active Pending
- 2018-04-19 MY MYPI2020003455A patent/MY195984A/en unknown
- 2018-04-19 US US16/975,218 patent/US11251153B2/en active Active
- 2018-04-19 WO PCT/JP2018/016201 patent/WO2019193771A1/ja active Application Filing
- 2018-04-19 KR KR1020207016070A patent/KR102425336B1/ko active IP Right Grant
- 2018-04-19 SG SG11202009825RA patent/SG11202009825RA/en unknown
- 2018-04-20 TW TW107113549A patent/TWI740031B/zh active
Also Published As
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TWI740031B (zh) | 2021-09-21 |
MY195984A (en) | 2023-02-27 |
US20200395330A1 (en) | 2020-12-17 |
JP2019186248A (ja) | 2019-10-24 |
US11251153B2 (en) | 2022-02-15 |
CN111344846A (zh) | 2020-06-26 |
KR20200086310A (ko) | 2020-07-16 |
KR102425336B1 (ko) | 2022-07-26 |
SG11202009825RA (en) | 2020-11-27 |
WO2019193771A1 (ja) | 2019-10-10 |
JP6869920B2 (ja) | 2021-05-12 |
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