TW201941433A

TW201941433A - Semiconductor structrue, method of manufacturing the semiconductor structrue and semiconductor device

Info

Publication number: TW201941433A
Application number: TW107109696A
Authority: TW
Inventors: 張翼; 林岳欽; 許嘉傑; 李景華; 江繼群
Original assignee: 漢民科技股份有限公司
Priority date: 2018-03-21
Filing date: 2018-03-21
Publication date: 2019-10-16
Also published as: TWI652820B

Abstract

A semiconductor structure includes a substrate, a semiconductor layer, a lanthanum silicate layer and a gate electrode layer. The semiconductor layer is disposed on the substrate. The lanthanum silicate layer is disposed on the semiconductor layer, and the lanthanum silicate layer includes La2O3/SiO2 composite oxide. The gate electrode layer is disposed on the lanthanum silicate layer.

Description

半導體結構、半導體結構的製造方法及半導體裝置 Semiconductor structure, manufacturer of semiconductor structure Method and semiconductor device

本發明是有關於一種半導體結構及其製造方法，以及一種半導體裝置。 The invention relates to a semiconductor structure and a manufacturing method thereof, and a semiconductor device.

在半導體技術中，III-V族半導體化合物可用於形成各種積體電路裝置，例如高功率場效電晶體、高頻電晶體或高電子遷移率電晶體(High electron mobility transistor,HEMT)，此III-V族半導體化合物電晶體具有取代傳統矽電晶體之潛力。 In semiconductor technology, III-V semiconductor compounds can be used to form various integrated circuit devices, such as high-power field-effect transistors, high-frequency transistors, or high electron mobility transistors (HEMT). This III -V semiconductor compound transistors have the potential to replace traditional silicon transistors.

傳統矽電晶體是利用二氧化矽作為閘極介電層。二氧化矽之於矽具有晶格匹配及介面品質優良的優點，能使矽電晶體獲得較大的電容值。然而，III-V族半導體電晶體缺乏如同二氧化矽之於矽的原生氧化物作為閘極介電層。因此隨著積體電路裝置對於單位電容量的需求提升，需要研發具有更高介電系數的介電材料作為III-V族半導體電晶體的閘極介電層。 Traditional silicon transistors use silicon dioxide as the gate dielectric. Silicon dioxide has the advantages of lattice matching and excellent interface quality to silicon, which enables silicon transistors to obtain larger capacitance values. However, III-V semiconductor transistors lack a native oxide of silicon like silicon dioxide as the gate dielectric layer. Therefore, as the demand for integrated capacitance of integrated circuit devices increases, it is necessary to develop a dielectric material having a higher dielectric constant as a gate dielectric layer of a III-V semiconductor transistor.

根據本發明之各種實施方式，提供一種半導體結構，包含基板、設置於基板上的半導體層、設置於半導體層上的矽酸鑭層，以及設置於矽酸鑭層上的閘極電極層。矽酸鑭層包含氧化鑭/二氧化矽(La₂O₃/SiO₂)複合氧化物。 According to various embodiments of the present invention, there is provided a semiconductor structure including a substrate, a semiconductor layer provided on the substrate, a lanthanum silicate layer provided on the semiconductor layer, and a gate electrode layer provided on the lanthanum silicate layer. The lanthanum silicate layer includes a lanthanum oxide / silicon dioxide (La ₂ O ₃ / SiO ₂ ) composite oxide.

根據本發明之某些實施方式，矽酸鑭層是由二氧化矽及氧化鑭經固態反應所形成。 According to some embodiments of the present invention, the lanthanum silicate layer is formed by a solid state reaction between silicon dioxide and lanthanum oxide.

根據本發明之某些實施方式，氧化鑭/二氧化矽(La₂O₃/SiO₂)複合氧化物包含化學式為LaSiO_x之複合氧化物，其中x為介於3至4之間的數值。 According to some embodiments of the present invention, the lanthanum oxide / silicon dioxide (La ₂ O ₃ / SiO ₂ ) composite oxide includes a composite oxide having a chemical formula LaSiO _x , where x is a value between 3 and 4.

根據本發明之某些實施方式，矽酸鑭層具有厚度為約2奈米至約50奈米。 According to some embodiments of the invention, the lanthanum silicate layer has a thickness of about 2 nm to about 50 nm.

根據本發明之某些實施方式，矽酸鑭層具有介電常數為約12至約22。 According to some embodiments of the present invention, the lanthanum silicate layer has a dielectric constant of about 12 to about 22.

根據本發明之某些實施方式，半導體層包含III-V族半導體。 According to some embodiments of the present invention, the semiconductor layer includes a III-V semiconductor.

根據本發明之某些實施方式，半導體層包含砷化銦鎵(InGaAs)、砷化銦(InAs)、砷化銦鋁(InAlAs)、磷化銦(InP)、砷化鎵(GaAs)、銻化銦(InSb)、銻化銦鎵(InGaSb)、氮化鎵(GaN)或砷化鋁鎵(AlGaAs)。 According to some embodiments of the present invention, the semiconductor layer includes indium gallium arsenide (InGaAs), indium arsenide (InAs), indium aluminum arsenide (InAlAs), indium phosphide (InP), gallium arsenide (GaAs), antimony Indium (InSb), InGaSb, GaN, or AlGaAs.

根據本發明之各種實施方式，提供一種半導體結構的製造方法，包含形成半導體層於基板上；交錯地形成複數個二氧化矽層及複數個氧化鑭層於半導體層上；快速退火二氧化矽層及氧化鑭層，以形成矽酸鑭層；以及形成閘極電極層於矽酸鑭層上。 According to various embodiments of the present invention, a method for manufacturing a semiconductor structure is provided. The method includes forming a semiconductor layer on a substrate; staggeringly forming a plurality of silicon dioxide layers and a plurality of lanthanum oxide layers on the semiconductor layer; and rapidly annealing the silicon dioxide layer. And a lanthanum oxide layer to form a lanthanum silicate layer; and a gate electrode The electrode layer is on the lanthanum silicate layer.

根據本發明之某些實施方式，氧化鑭層具有厚度為約0.3奈米至約2奈米。 According to some embodiments of the invention, the lanthanum oxide layer has a thickness of about 0.3 nm to about 2 nm.

根據本發明之某些實施方式，二氧化矽層具有厚度為約0.3奈米至約2奈米。 According to some embodiments of the present invention, the silicon dioxide layer has a thickness of about 0.3 nm to about 2 nm.

根據本發明之某些實施方式，快速退火步驟是在約400℃至約800℃下執行。 According to some embodiments of the present invention, the rapid annealing step is performed at about 400 ° C to about 800 ° C.

根據本發明之某些實施方式，形成氧化鑭層及二氧化矽層包含原子層沉積或分子束沉積。 According to some embodiments of the present invention, forming the lanthanum oxide layer and the silicon dioxide layer includes atomic layer deposition or molecular beam deposition.

根據本發明之各種實施方式，提供一種半導體裝置，包含基板；通道層設置於基板上；阻障層設置於通道層上，阻障層具有凹槽，且凹槽具有第一側壁及與第一側壁相對的第二側壁；源極及汲極設置於阻障層上，且源極位於接近凹槽之第一側壁的一端，汲極位於接近凹槽之第二側壁的另一端；閘極介電層設置於阻障層上並覆蓋凹槽，其中閘極介電層包含矽酸鑭；以及閘極設置於閘極介電層上，且閘極填入凹槽中，其中閘極具有第一表面、與第一表面相對的第二表面及位於第一表面與第二表面之間的底面。 According to various embodiments of the present invention, there is provided a semiconductor device including a substrate; a channel layer is disposed on the substrate; a barrier layer is disposed on the channel layer, the barrier layer has a groove, and the groove has a first sidewall and a first A second side wall opposite to the side wall; the source electrode and the drain electrode are disposed on the barrier layer, and the source electrode is located at one end of the first side wall close to the groove, and the drain electrode is located at the other end close to the second side wall of the groove; The electrical layer is disposed on the barrier layer and covers the groove, wherein the gate dielectric layer includes lanthanum silicate; and the gate is disposed on the gate dielectric layer and the gate is filled in the groove, wherein the gate has a first A surface, a second surface opposite to the first surface, and a bottom surface located between the first surface and the second surface.

根據本發明之某些實施方式，閘極介電層具有厚度為約2奈米至約50奈米。 According to some embodiments of the present invention, the gate dielectric layer has a thickness of about 2 nm to about 50 nm.

根據本發明之某些實施方式，閘極的底表面具有寬度為約80奈米至約3微米。 According to some embodiments of the invention, the bottom surface of the gate has a width of about 80 nanometers to about 3 microns.

根據本發明之某些實施方式，閘極的第一表面與源極之間具有間距為約1微米至約5微米。 According to some embodiments of the present invention, a gap between the first surface of the gate and the source is about 1 micrometer to about 5 micrometers.

根據本發明之某些實施方式，閘極的第二表面與汲極之間具有間距為約2微米至約50微米。 According to some embodiments of the present invention, a gap between the second surface of the gate electrode and the drain electrode is about 2 micrometers to about 50 micrometers.

根據本發明之某些實施方式，還包括保護層設置在閘極介電層上。 According to some embodiments of the present invention, a protection layer is further provided on the gate dielectric layer.

根據本發明之某些實施方式，通道層與阻障層包含III-V族半導體。 According to some embodiments of the present invention, the channel layer and the barrier layer include a III-V semiconductor.

10‧‧‧方法 10‧‧‧Method

12、14、16、18‧‧‧操作 12, 14, 16, 18 ‧‧‧ operation

100‧‧‧半導體結構 100‧‧‧Semiconductor Structure

110‧‧‧基板 110‧‧‧ substrate

120‧‧‧半導體層 120‧‧‧Semiconductor layer

130‧‧‧矽酸鑭層 130‧‧‧lanthanum silicate layer

132、132a、132b、132c‧‧‧二氧化矽層 132, 132a, 132b, 132c‧‧‧ Silicon dioxide layer

134、134a、134b、134c‧‧‧氧化鑭層 134, 134a, 134b, 134c

140‧‧‧閘極電極層 140‧‧‧Gate electrode layer

200‧‧‧半導體裝置 200‧‧‧ semiconductor device

210‧‧‧基板 210‧‧‧ substrate

220‧‧‧通道層 220‧‧‧Channel layer

230‧‧‧阻障層 230‧‧‧ barrier layer

232‧‧‧凹槽 232‧‧‧Groove

234‧‧‧缺口 234‧‧‧ gap

236、237‧‧‧側面 236, 237‧‧‧ side

238‧‧‧下表面 238‧‧‧lower surface

240‧‧‧源極 240‧‧‧Source

250‧‧‧汲極 250‧‧‧ Drain

260‧‧‧閘極介電層 260‧‧‧Gate dielectric layer

262‧‧‧第一表面 262‧‧‧first surface

264‧‧‧第二表面 264‧‧‧Second Surface

266‧‧‧底面 266‧‧‧ Underside

270‧‧‧閘極 270‧‧‧Gate

T₁、T₂、T₃、T₄‧‧‧厚度 T ₁ , T ₂ , T ₃ , T ₄ ‧‧‧ thickness

D₁、D₂‧‧‧距離 D ₁ , D ₂ ‧‧‧ distance

S₁、S₂‧‧‧間距 S ₁ , S ₂ ‧‧‧ pitch

W₁‧‧‧寬度 W ₁ ‧‧‧Width

第1圖為根據本發明之某些實施方式繪示的半導體結構的製造方法流程圖。 FIG. 1 is a flowchart of a method for manufacturing a semiconductor structure according to some embodiments of the present invention.

第2A-2D圖為根據本發明之某些實施方式繪示的半導體結構的製程各步驟剖面圖。 Figures 2A-2D are cross-sectional views of steps in a manufacturing process of a semiconductor structure according to some embodiments of the present invention.

第3A-3E圖為根據本發明之某些實施方式繪示的半導體裝置的製程各步驟剖面圖。 3A-3E are cross-sectional views of steps of a semiconductor device manufacturing process according to some embodiments of the present invention.

第4圖為根據本發明之某些實施方式製造的半導體結構之矽酸鑭層的電子顯微鏡相片。 FIG. 4 is an electron micrograph of a lanthanum silicate layer of a semiconductor structure manufactured according to some embodiments of the present invention.

第5圖為根據本發明之某些實施方式之半導體裝置的I_D-V_GS特性曲線。 FIG. 5 is an I _D -V _GS characteristic curve of a semiconductor device according to some embodiments of the present invention.

第6圖為根據本發明之某些實施方式之閘極介電層之閘極電壓對電容值之折線圖。 FIG. 6 is a line graph of gate voltage versus capacitance of a gate dielectric layer according to some embodiments of the present invention.

以下將以圖式揭露本發明之複數個實施方式，為明確說明起見，許多實務上的細節將在以下敘述中一併說明。然而，應瞭解到，這些實務上的細節不應用以限制本發明。也就是說，在本發明部分實施方式中，這些實務上的細節是非必要的。此外，為簡化圖示起見，一些習知慣用的結構與元件在圖示中將以簡單示意的方式繪示之。 In the following, a plurality of embodiments of the present invention will be disclosed graphically. For the sake of clarity, many practical details will be explained in the following description. It should be understood, however, that these practical details should not be used to limit the invention. That is, in some embodiments of the present invention, these practical details are unnecessary. In addition, in order to simplify the illustration, some conventional structures and components will be shown in a simple and schematic manner in the illustration.

在本文中使用空間相對用語，例如「下方」、「之下」、「上方」、「之上」等，這是為了便於敘述一元件或特徵與另一元件或特徵之間的相對關係，如圖中所繪示。這些空間上的相對用語的真實意義包含其他的方位。例如，當圖示上下翻轉180度時，一元件與另一元件之間的關係，可能從「下方」、「之下」變成「上方」、「之上」。此外，本文中所使用的空間上的相對敘述也應作同樣的解釋。 In this article, spatial relative terms such as "below", "below", "above", "above", etc. are used to facilitate the description of the relative relationship between one element or feature and another element or feature, such as Shown in the figure. The true meaning of these spatial relative terms includes other directions. For example, when the icon is flipped 180 degrees up and down, the relationship between one component and another component may change from "below" and "below" to "above" and "above". In addition, the spatially relative descriptions used in this article should be interpreted the same.

第1圖繪示本發明各種實施方式之半導體結構的製造方法10的流程圖。如第1圖所示，方法10包含操作12、操作14、操作16及操作18。第2A-2D圖繪示根據第1圖所示之方法10製造之半導體結構100在各製程階段的剖面圖。 FIG. 1 is a flowchart of a method 10 for manufacturing a semiconductor structure according to various embodiments of the present invention. As shown in FIG. 1, the method 10 includes an operation 12, an operation 14, an operation 16, and an operation 18. 2A-2D are cross-sectional views of the semiconductor structure 100 manufactured according to the method 10 shown in FIG. 1 at each process stage.

請參照第1圖及第2A圖，在方法10的操作12中，形成半導體層120於基板110上。根據本發明某些實施方式，半導體層120包含III-V族半導體。在某些實施方式中，半導體層120包含砷化銦鎵(InGaAs)、砷化銦(InAs)、砷化銦鋁(InAlAs)、磷化銦(InP)、砷化鎵(GaAs)、銻化銦(InSb)、銻化銦鎵(InGaSb)、氮化鎵(GaN)或砷化鋁鎵 (AlGaAs)，但不限於此。在某些實施方式中，基板110可以為矽基板、碳化矽(SiC)基板、藍寶石(sapphire)基板、氮化鎵(GaN)基板、氮化鋁鎵(AlGaN)基板、氮化鋁(AlN)基板、磷化鎵(GaP)基板、砷化鎵(GaAs)基板或砷化鋁鎵(AlGaAs)基板，但不限於此。 Referring to FIG. 1 and FIG. 2A, in operation 12 of method 10, a semiconductor layer 120 is formed on a substrate 110. According to some embodiments of the present invention, the semiconductor layer 120 includes a III-V semiconductor. In some embodiments, the semiconductor layer 120 includes indium gallium arsenide (InGaAs), indium arsenide (InAs), indium aluminum arsenide (InAlAs), indium phosphide (InP), gallium arsenide (GaAs), antimonide Indium (InSb), indium gallium antimonide (InGaSb), gallium nitride (GaN), or aluminum gallium arsenide (AlGaAs), but is not limited to this. In some embodiments, the substrate 110 may be a silicon substrate, a silicon carbide (SiC) substrate, a sapphire substrate, a gallium nitride (GaN) substrate, an aluminum gallium nitride (AlGaN) substrate, or aluminum nitride (AlN). A substrate, a gallium phosphide (GaP) substrate, a gallium arsenide (GaAs) substrate, or an aluminum gallium arsenide (AlGaAs) substrate, but is not limited thereto.

參照第1圖及第2B圖，方法10繼續進行至操作14，交錯地形成複數個二氧化矽(SiO₂)層132及複數個氧化鑭(La₂O₃)層134於半導體層120上。根據本發明某些實施方式，形成二氧化矽層132及氧化鑭層134的方法包含原子層沉積(Atomic layer deposition；ALD)或分子束沉積(Molecular beam deposition；MBD)，但不限於此。可以用任何合適的沉積方法在半導體層120上形成二氧化矽層132及氧化鑭層134。在某些實施方式中，如第2B圖所示，可以先形成一層二氧化矽層132a於半導體層120上，再形成一層氧化鑭層134a於二氧化矽層132a上。之後，繼續交錯地形成二氧化矽層132b及氧化鑭層134b於氧化鑭層134a之上。在其他實施方式中，也可以先形成一層氧化鑭層134a於半導體層120上，再形成一層二氧化矽層132a於上述氧化鑭層134a上。之後，繼續交錯地形成氧化鑭層134b及二氧化矽層132b於二氧化矽層132a上。在某些實施方式中，可以在半導體層120上形成相同數量的氧化鑭層134及二氧化矽層132。例如，在第2B圖中，在半導體層120上交錯地形成三層二氧化矽層132a、132b、132c及三層氧化鑭層134a、134b、134c。應了解到，第2B圖所示的半導體結構100僅為本發明的其中一示例，實際上可以於半導體層120上交錯地形成任意數量的二氧化矽層132及任意數量的氧化鑭層134。例如，可以於半導體層120上形成交錯地十層二氧化矽層及十層氧化鑭層。 Referring to FIG. 1 and FIG. 2B, the method 10 continues to operation 14, stably forming a plurality of silicon dioxide (SiO ₂ ) layers 132 and a plurality of lanthanum oxide (La ₂ O ₃ ) layers 134 on the semiconductor layer 120. According to some embodiments of the present invention, the method for forming the silicon dioxide layer 132 and the lanthanum oxide layer 134 includes, but is not limited to, atomic layer deposition (ALD) or molecular beam deposition (MBD). The silicon dioxide layer 132 and the lanthanum oxide layer 134 can be formed on the semiconductor layer 120 by any suitable deposition method. In some embodiments, as shown in FIG. 2B, a silicon dioxide layer 132a may be formed on the semiconductor layer 120, and then a lanthanum oxide layer 134a may be formed on the silicon dioxide layer 132a. After that, the silicon dioxide layer 132b and the lanthanum oxide layer 134b are continuously formed on the lanthanum oxide layer 134a. In other embodiments, a lanthanum oxide layer 134a may be formed on the semiconductor layer 120, and then a silicon dioxide layer 132a may be formed on the lanthanum oxide layer 134a. After that, the lanthanum oxide layer 134b and the silicon dioxide layer 132b are continuously formed on the silicon dioxide layer 132a in a staggered manner. In some embodiments, the same number of lanthanum oxide layers 134 and silicon dioxide layers 132 can be formed on the semiconductor layer 120. For example, in FIG. 2B, three silicon dioxide layers 132a, 132b, and 132c and three lanthanum oxide layers 134a, 134b, and 134c are alternately formed on the semiconductor layer 120. It should be understood that the semiconductor structure 100 shown in FIG. 2B is only one example of the present invention. Actually, any number of silicon dioxide layers 132 and any number of lanthanum oxide layers 134 can be staggered on the semiconductor layer 120. For example, ten silicon dioxide layers and ten lanthanum oxide layers may be formed on the semiconductor layer 120 in a staggered manner.

根據本發明某些實施方式，上述二氧化矽層132中的每一層(例如132a、132b、132c)的厚度為約0.3奈米至約2奈米，例如為約0.4、0.5、0.7、1、1.5或1.7奈米。根據本發明某些實施方式，上述氧化鑭層134中的每一層(例如134a、134b、134c)的厚度為約0.3奈米至約2奈米，例如為約0.4、0.5、0.7、1、1.5或1.7奈米。在某些實施方式中，二氧化矽層132中任一層的厚度與氧化鑭層134中任一層的厚度相同。例如，二氧化矽層132a的厚度T₁及氧化鑭層134a的厚度T₂皆為0.5奈米。在某些實施方式中，二氧化矽層132中的每一層具有相同的厚度，並且氧化鑭層134中的每一層具有相同的厚度。例如，二氧化矽層132a、132b及132c的厚度相同，氧化鑭層134a、134b及134c的厚度相同。 According to some embodiments of the present invention, the thickness of each of the silicon dioxide layers 132 (eg, 132a, 132b, 132c) is about 0.3 nm to about 2 nm, such as about 0.4, 0.5, 0.7, 1, 1.5 or 1.7 nm. According to some embodiments of the present invention, each of the lanthanum oxide layers 134 (eg, 134a, 134b, 134c) has a thickness of about 0.3 nm to about 2 nm, such as about 0.4, 0.5, 0.7, 1, 1.5. Or 1.7 nm. In some embodiments, the thickness of any one of the silicon dioxide layers 132 is the same as the thickness of any one of the lanthanum oxide layers 134. For example, the thickness T ₁ of the silicon dioxide layer 132 a and the thickness T _{2 of the} lanthanum oxide layer 134 a are both 0.5 nm. In some embodiments, each of the silicon dioxide layers 132 has the same thickness, and each of the lanthanum oxide layers 134 has the same thickness. For example, the thicknesses of the silicon dioxide layers 132a, 132b, and 132c are the same, and the thicknesses of the lanthanum oxide layers 134a, 134b, and 134c are the same.

參照第1圖及第2C圖，方法10繼續進行至操作16，快速退火二氧化矽層132及氧化鑭層134，以形成矽酸鑭(Lanthanum silicate)層130。根據本發明某些實施方式，可以在約400℃至約800℃下執行快速退火。例如，在約450、500、550、600、650、700或750℃下執行快速退火。快速退火溫度將會影響後續形成之矽酸鑭層130的介電常數。可以依據二氧化矽層132及氧化鑭層134的厚度以及矽酸鑭層130所需之介電常數選擇適當的退火溫度。根據本發明某些實施方式，矽酸鑭層包含氧化鑭/二氧化矽(La₂O₃/SiO₂)複合氧化物。在某些實施方式中，氧化鑭/二氧化矽(La₂O₃/SiO₂)複合氧化物包含化學式為LaSiO_x之複合氧化物，其中x為介於3至4之間的數值。例如，x可以為約3.3、3.4、3.5、3.6或3.7。在某些實施方式中，矽酸鑭層130的厚度T₃為約2奈米至約50奈米。例如為約3、5、6、8、10、12、15、20、25、30、35、40或45奈米。此厚度範圍內的矽酸鑭層130可以維持低漏電流以及較薄的等效氧化物厚度(EOT)。在某些實施方式中，矽酸鑭層130的介電常數為約12至約22。第4圖為本發明之一實施例之根據第1圖所示方法10製造之矽酸鑭層130的電子顯微鏡相片。由第4圖可知，二氧化矽層132及氧化鑭層134在快速退火後形成之矽酸鑭層130為一層均勻混合的非結晶態矽酸鑭層。 Referring to FIG. 1 and FIG. 2C, the method 10 continues to operation 16 to rapidly anneal the silicon dioxide layer 132 and the lanthanum oxide layer 134 to form a Lanthanum silicate layer 130. According to some embodiments of the present invention, rapid annealing may be performed at about 400 ° C to about 800 ° C. For example, rapid annealing is performed at about 450, 500, 550, 600, 650, 700, or 750 ° C. The rapid annealing temperature will affect the dielectric constant of the subsequently formed lanthanum silicate layer 130. An appropriate annealing temperature may be selected according to the thickness of the silicon dioxide layer 132 and the lanthanum oxide layer 134 and the dielectric constant required for the lanthanum silicate layer 130. According to some embodiments of the present invention, the lanthanum silicate layer includes a lanthanum oxide / silicon dioxide (La ₂ O ₃ / SiO ₂ ) composite oxide. In some embodiments, the lanthanum oxide / silicon dioxide (La ₂ O ₃ / SiO ₂ ) composite oxide comprises a composite oxide of the formula LaSiO _x , where x is a value between 3 and 4. For example, x may be about 3.3, 3.4, 3.5, 3.6, or 3.7. In some embodiments, the thickness T ₃ of the lanthanum silicate layer 130 is about 2 nm to about 50 nm. For example, it is about 3, 5, 6, 8, 10, 12, 15, 20, 25, 30, 35, 40, or 45 nanometers. The lanthanum silicate layer 130 in this thickness range can maintain a low leakage current and a thin equivalent oxide thickness (EOT). In some embodiments, the dielectric constant of the lanthanum silicate layer 130 is about 12 to about 22. FIG. 4 is an electron microscope photograph of a lanthanum silicate layer 130 manufactured according to the method 10 shown in FIG. 1 according to an embodiment of the present invention. It can be seen from FIG. 4 that the lanthanum silicate layer 130 formed by the rapid anneal of the silicon dioxide layer 132 and the lanthanum oxide layer 134 is a uniformly mixed amorphous lanthanum silicate layer.

參照第1圖及第2D圖，方法10繼續進行至操作18，形成閘極電極層140於矽酸鑭層130上。根據本發明某些實施方式，閘極電極層140包含鎳(Ni)、金(Au)、鈦(Ti)、鉑(Pt)、銅(Cu)、鋁(Al)、氧化鉭(TaN)或其組合，但不限於此。如第2D圖所示，半導體結構100包含基板110、半導體層120、矽酸鑭層130以及閘極電極層140。半導體層120設置於基板110上。矽酸鑭層130設置於半導體層120上，矽酸鑭層130設置於半導體層120上，且矽酸鑭層包含氧化鑭/二氧化矽(La₂O₃/SiO₂)複合氧化物，其中x為介於3至4 之間的數值。閘極電極層140設置於矽酸鑭層130上。 Referring to FIG. 1 and FIG. 2D, the method 10 continues to operation 18 to form a gate electrode layer 140 on the lanthanum silicate layer 130. According to some embodiments of the present invention, the gate electrode layer 140 includes nickel (Ni), gold (Au), titanium (Ti), platinum (Pt), copper (Cu), aluminum (Al), tantalum oxide (TaN), or The combination is not limited to this. As shown in FIG. 2D, the semiconductor structure 100 includes a substrate 110, a semiconductor layer 120, a lanthanum silicate layer 130, and a gate electrode layer 140. The semiconductor layer 120 is disposed on the substrate 110. The lanthanum silicate layer 130 is disposed on the semiconductor layer 120, the lanthanum silicate layer 130 is disposed on the semiconductor layer 120, and the lanthanum silicate layer includes a lanthanum oxide / silicon dioxide (La ₂ O ₃ / SiO ₂ ) composite oxide, wherein x is a number between 3 and 4. The gate electrode layer 140 is disposed on the lanthanum silicate layer 130.

第3A-3E圖為根據本發明之某些實施方式繪示的製造半導體裝置的製程各步驟剖面圖。 3A-3E are cross-sectional views of steps in a manufacturing process of a semiconductor device according to some embodiments of the present invention.

首先請參考第3A圖，通道層220及阻障層230依序形成於基板210上。根據本發明某些實施方式，通道層220及阻障層230包含III-V族半導體。在某些實施方式中，通道層220可以包含氮化鎵(GaN)、氮化鋁鎵(AlGaN)、氮化銦鎵(InGaN)、氮化鋁銦鎵(AlInGaN)或其他合適的III-V族半導體，但不限於此。在某些實施方式中，阻障層230可以包含氮化鋁鎵(AlGaN)、氮化鋁(AlN)、氮化鋁銦(AlInN)、氮化鎵(GaN)、氮化銦鎵(InGaN)、氮化鋁銦鎵(AlInGaN)或其他合適的III-V族半導體，但不限於此。在某些實施方式中，通道層220的材料可以與阻障層230不同。例如，阻障層230可以為氮化鎵(GaN)，通道層220可以為氮化鋁鎵(AlGaN)。在某些實施方式中，基板210可以為矽基板、碳化矽(SiC)基板、藍寶石(sapphire)基板、氮化鎵(GaN)基板、氮化鋁鎵(AlGaN)基板、氮化鋁(AlN)基板、磷化鎵(GaP)基板、砷化鎵(GaAs)基板或砷化鋁鎵(AlGaAs)基板，但不限於此。通道層220的能隙小於阻障層230的能隙，且通道層220和阻障層230的組合和厚度必須能夠產生二維電子氣。 First, referring to FIG. 3A, the channel layer 220 and the barrier layer 230 are sequentially formed on the substrate 210. According to some embodiments of the present invention, the channel layer 220 and the barrier layer 230 include a III-V semiconductor. In some embodiments, the channel layer 220 may include gallium nitride (GaN), aluminum gallium nitride (AlGaN), indium gallium nitride (InGaN), aluminum indium gallium nitride (AlInGaN), or other suitable III-V Family semiconductors, but not limited to this. In some embodiments, the barrier layer 230 may include aluminum gallium nitride (AlGaN), aluminum nitride (AlN), indium aluminum nitride (AlInN), gallium nitride (GaN), indium gallium nitride (InGaN) , AlInGaN, or other suitable III-V semiconductors, but not limited thereto. In some embodiments, the material of the channel layer 220 may be different from the barrier layer 230. For example, the barrier layer 230 may be gallium nitride (GaN), and the channel layer 220 may be aluminum gallium nitride (AlGaN). In some embodiments, the substrate 210 may be a silicon substrate, a silicon carbide (SiC) substrate, a sapphire substrate, a gallium nitride (GaN) substrate, an aluminum gallium nitride (AlGaN) substrate, or aluminum nitride (AlN). A substrate, a gallium phosphide (GaP) substrate, a gallium arsenide (GaAs) substrate, or an aluminum gallium arsenide (AlGaAs) substrate, but is not limited thereto. The energy gap of the channel layer 220 is smaller than the energy gap of the barrier layer 230, and the combination and thickness of the channel layer 220 and the barrier layer 230 must be capable of generating two-dimensional electron gas.

接著請參照第3B圖，形成源極240與汲極250於阻障層230上。源極240與汲極250包含鎳(Ni)、銀(Ag)、鈦(Ti)、鋁(Al)、銅(Cu)、鎢(W)、鉭(Ta)、釕(Ru)、鈀 (Pd)、鉑(Pt)、錳(Mn)、氮化鎢(WN)、氮化鈦(TiN)、氮化鉭(TaN)、氮化鋁(AlN)、矽化鎢(WSi)、氮化鉬(MoN)、鋁化鈦(TiAl)、氮化鋯(ZrN)、碳化鉭(TaC)、碳氮化鉭(TaCN)、氮化鉭矽(TaSiN)、氮化鈦鋁(TiAlN)、矽化物或其任意之組合，但不限於此。形成源極240和汲極250的方法可包含濺鍍或任何習知之製程。 Referring to FIG. 3B, a source 240 and a drain 250 are formed on the barrier layer 230. Source 240 and drain 250 include nickel (Ni), silver (Ag), titanium (Ti), aluminum (Al), copper (Cu), tungsten (W), tantalum (Ta), ruthenium (Ru), and palladium (Pd), platinum (Pt), manganese (Mn), tungsten nitride (WN), titanium nitride (TiN), tantalum nitride (TaN), aluminum nitride (AlN), tungsten silicide (WSi), nitride Molybdenum (MoN), titanium aluminide (TiAl), zirconium nitride (ZrN), tantalum carbide (TaC), tantalum carbonitride (TaCN), tantalum silicon nitride (TaSiN), titanium aluminum nitride (TiAlN), silicidation Or any combination thereof, but is not limited thereto. The method of forming the source 240 and the drain 250 may include sputtering or any conventional process.

接著請參照第3C圖，進行平台隔離(mesa isolation)，之後在阻障層230中形成凹槽234。在某些實施方式中，平台隔離包含形成遮罩層(未示出)於阻障層230上，再利用蝕刻製程移除半導體裝置200兩側的一部分通道層220及一部分阻障層230以形成缺口232，定義出半導體裝置200的主動區。上述蝕刻製程包含乾式蝕刻，例如可以為感應耦合電漿(Inductively Coupled Plasma；ICP)蝕刻，但不限於此。在某些實施方式中，可藉由圖案化製程在阻障層230中形成凹槽234。圖案化製程包含在阻障層230上形成遮罩層(未示出)，並在遮罩層上形成圖案，再利用蝕刻製程將圖案轉移至阻障層230而形成凹槽234。在某些實施方式中，蝕刻製程可為反應式離子蝕刻、電漿乾式蝕刻或其他非等向性蝕刻方式，蝕刻氣體可以使用六氟化硫、四氯化矽、八氟環丁烷、甲烷、氫氣、氬或其他已知蝕刻氣體或其組合。如第3C圖所示，凹槽234位於源極240和汲極250之間，並且未貫穿阻障層230。凹槽234未貫穿阻障層230目的在於削弱阻障層230之極化現象並消除二維電子氣通道之載子，使其臨界電壓大於0V。因較薄的阻障層230會提升導帶能階，故減少閘極270區域底下之阻障層230厚度可驅趕(deplete)二維電子氣。 Referring to FIG. 3C, mesa isolation is performed, and then a groove 234 is formed in the barrier layer 230. In some embodiments, the platform isolation includes forming a mask layer (not shown) on the barrier layer 230, and then using an etching process to remove a portion of the channel layer 220 and a portion of the barrier layer 230 on both sides of the semiconductor device 200 to form The notch 232 defines an active area of the semiconductor device 200. The above-mentioned etching process includes dry etching, for example, inductively coupled plasma (ICP) etching, but is not limited thereto. In some embodiments, the grooves 234 can be formed in the barrier layer 230 by a patterning process. The patterning process includes forming a masking layer (not shown) on the barrier layer 230, forming a pattern on the masking layer, and then transferring the pattern to the barrier layer 230 by using an etching process to form a groove 234. In some embodiments, the etching process may be reactive ion etching, plasma dry etching, or other anisotropic etching methods. The etching gas may use sulfur hexafluoride, silicon tetrachloride, octafluorocyclobutane, and methane. , Hydrogen, argon, or other known etching gases, or a combination thereof. As shown in FIG. 3C, the groove 234 is located between the source 240 and the drain 250 and does not penetrate the barrier layer 230. The purpose of the recess 234 not penetrating the barrier layer 230 is to weaken the polarization phenomenon of the barrier layer 230 and eliminate the carriers of the two-dimensional electron gas channel, so that the threshold voltage thereof is greater than 0V. Because the thinner barrier layer 230 will increase The energy level of the conduction band is raised, so reducing the thickness of the barrier layer 230 under the gate 270 region can deplete two-dimensional electron gas.

在某些實施方式中，源極240至凹槽234之側面236的距離D₁與汲極250至凹槽234之側面237的距離D₂不相等，也就是說，凹槽234並不是位於源極240與汲極250的正中央。在某些實施方式中，凹槽234側面237與汲極250的距離D₂大於凹槽234側面236與源極240的距離D₁。在某些實施方式中，在阻障層230中形成凹槽234之後，可以對阻障層230的上表面進行表面處理，以利後續閘極介電層260的沉積。例如，可以利用包含NH₄OH的溶液清洗阻障層230的上表面。 In some embodiments, the distance D ₁ between the source 240 and the side 236 of the groove 234 is not equal to the distance D ₂ between the drain 250 and the side 237 of the groove 234, that is, the groove 234 is not located at the source. The center of pole 240 and drain 250. In some embodiments, the distance D ₂ between the side 237 of the groove 234 and the drain 250 is greater than the distance D ₁ between the side 236 of the groove 234 and the source 240. In some embodiments, after the grooves 234 are formed in the barrier layer 230, a surface treatment may be performed on the upper surface of the barrier layer 230 to facilitate subsequent deposition of the gate dielectric layer 260. For example, the upper surface of the barrier layer 230 may be cleaned with a solution containing NH ₄ OH.

請參照第3D圖，形成閘極介電層260於阻障層230上並覆蓋凹槽234，且閘極介電層260包含矽酸鑭。在某些實施方式中，閘極介電層260包含氧化鑭/二氧化矽(La₂O₃/SiO₂)複合氧化物。在某些實施方式中，氧化鑭/二氧化矽(La₂O₃/SiO₂)複合氧化物包含化學式為LaSiO_x之矽酸鑭，其中，x為介於3至4之間的數值。包含矽酸鑭之閘極介電層260的形成方法與前述半導體結構100中的矽酸鑭層130的形成方法相同，故不再重複敘述。如第3D圖所示，閘極介電層260共形地覆蓋在阻障層230上，並覆蓋凹槽234的側面236、237及下表面238。在某些實施方式中，閘極介電層260的厚度T₄為約2奈米至約50奈米。例如為約5、9、10、12、15、20、25、30、35、40或45奈米。閘極介電層260的厚度T₄越小則半導體裝置的電流越大且穩定性較差。反之，當閘極介電層260的厚度T₄越大則半導體裝置的電流越小且穩定性較佳。可以根據所需的半導體裝置性質選擇適當厚度的閘極介電層260。 Referring to FIG. 3D, a gate dielectric layer 260 is formed on the barrier layer 230 and covers the groove 234, and the gate dielectric layer 260 includes lanthanum silicate. In some embodiments, the gate dielectric layer 260 includes a lanthanum oxide / silicon dioxide (La ₂ O ₃ / SiO ₂ ) composite oxide. In some embodiments, the lanthanum oxide / silicon dioxide (La ₂ O ₃ / SiO ₂ ) composite oxide comprises lanthanum silicate having a chemical formula LaSiO _x , where x is a value between 3 and 4. The method for forming the gate dielectric layer 260 including lanthanum silicate is the same as the method for forming the lanthanum silicate layer 130 in the semiconductor structure 100 described above, so the description will not be repeated. As shown in FIG. 3D, the gate dielectric layer 260 conformally covers the barrier layer 230 and covers the side surfaces 236 and 237 and the lower surface 238 of the groove 234. In some embodiments, the thickness T ₄ of the gate dielectric layer 260 is about 2 nm to about 50 nm. For example, it is about 5, 9, 10, 12, 15, 20, 25, 30, 35, 40, or 45 nanometers. The smaller the thickness T _{4 of the} gate dielectric layer 260 is, the larger the current of the semiconductor device is and the worse the stability is. Conversely, as the thickness T _{4 of} the gate dielectric layer 260 is larger, the current of the semiconductor device is smaller and the stability is better. The gate dielectric layer 260 may be selected to have an appropriate thickness according to the required properties of the semiconductor device.

請參照第3E圖，形成閘極270於閘極介電層260上，且閘極270填滿凹槽234。如第3E圖所示，半導體裝置200包含基板210、通道層220、阻障層230、源極240、汲極250、閘極介電層260及閘極270。通道層220設置於基板210上。阻障層230設置於通道層220上且具有凹槽234。源極240與汲極250設置於阻障層230上，分別位於凹槽234的兩端。閘極介電層260設置於阻障層230上並覆蓋凹槽234。閘極270設置於閘極介電層260上，且閘極270的一部分填入凹槽234中，未填入凹槽234的另一部分閘極270突出於阻障層230的上表面。閘極270具有第一表面262、與第一表面262相對的第二表面264，以及位於第一表面262及第二表面264之間的底面266。根據本發明某些實施方式，閘極270底面266的寬度W₁為約80奈米至3微米。例如可以為約100、180、200、230、250、270、300、350、400、450、500、600、700、800、900奈米、1微米或2微米奈米。根據本發明某些實施方式，閘極270的第一表面262與源極240之間的間距S₁為約1微米至5微米。例如為約2、3、3.5或4微米。根據本發明某些實施方式，閘極270的第二表面264與汲極250之間的間距S₂為約2微米至約50微米。例如為約5、6、8、10、12、15、18、20、25、30、35、40或45微米。閘極270的第二表面264與汲極250之間的間距S₂將影響半導體裝置之電流與崩潰電壓。在某些實施方式中，間距S₂大於間距S₁。間距S₂大於間距S₁的目的在於，汲極250的偏壓較大，當閘極270與汲極250之間距S₂較大時，可以承受較大的電壓。在某些實施方式中，還可以在閘極介電層260上形成保護層(未示出)覆蓋部分閘極介電層260。在某些實施方式中，保護層包含Si₃N₄。 Referring to FIG. 3E, a gate 270 is formed on the gate dielectric layer 260, and the gate 270 fills the groove 234. As shown in FIG. 3E, the semiconductor device 200 includes a substrate 210, a channel layer 220, a barrier layer 230, a source 240, a drain 250, a gate dielectric layer 260, and a gate 270. The channel layer 220 is disposed on the substrate 210. The barrier layer 230 is disposed on the channel layer 220 and has a groove 234. The source 240 and the drain 250 are disposed on the barrier layer 230 and are respectively located at two ends of the groove 234. The gate dielectric layer 260 is disposed on the barrier layer 230 and covers the groove 234. The gate 270 is disposed on the gate dielectric layer 260, and a part of the gate 270 is filled in the groove 234, and another part of the gate 270 that is not filled in the groove 234 protrudes from the upper surface of the barrier layer 230. The gate electrode 270 has a first surface 262, a second surface 264 opposite to the first surface 262, and a bottom surface 266 located between the first surface 262 and the second surface 264. According to some embodiments of the present invention, the width W ₁ of the bottom surface 266 of the gate electrode 270 is about 80 nanometers to 3 micrometers. For example, it can be about 100, 180, 200, 230, 250, 270, 300, 350, 400, 450, 500, 600, 700, 800, 900 nanometers, 1 micrometer or 2 micrometer nanometers. According to some embodiments of the present invention, a distance S ₁ between the first surface 262 of the gate electrode 270 and the source electrode 240 is about 1 micrometer to 5 micrometers. For example, it is about 2, 3, 3.5, or 4 microns. According to some embodiments of the present invention, a distance S ₂ between the second surface 264 of the gate electrode 270 and the drain electrode 250 is about 2 micrometers to about 50 micrometers. For example, it is about 5, 6, 8, 10, 12, 15, 18, 20, 25, 30, 35, 40, or 45 microns. The distance S ₂ between the second surface 264 of the gate 270 and the drain 250 will affect the current and the breakdown voltage of the semiconductor device. In some embodiments, the spacing S _{2 is} greater than the spacing S ₁ . The reason why the distance S _{2 is} greater than the distance S ₁ is that the bias voltage of the drain 250 is large. When the distance S ₂ between the gate 270 and the drain 250 is large, it can withstand a larger voltage. In some embodiments, a protective layer (not shown) may be formed on the gate dielectric layer 260 to cover a portion of the gate dielectric layer 260. In some embodiments, the protective layer includes Si ₃ N ₄ .

第5圖為根據本發明之某些實施方式之半導體裝置的I_D-V_GS特性曲線。由第5圖可以看出，本發明包含矽酸鑭的閘極介電層可以減少因閘極介電層與其下的通道層介面不佳所造成之遲滯效應(Hysteresis)。 FIG. 5 is an I _D -V _GS characteristic curve of a semiconductor device according to some embodiments of the present invention. It can be seen from FIG. 5 that the gate dielectric layer containing lanthanum silicate of the present invention can reduce the hysteresis caused by the poor interface between the gate dielectric layer and the channel layer below it.

第6圖為根據本發明之某些實施方式之閘極介電層之閘極電壓對電容值之折線圖。由第6圖可知，根據本發明某些實施方式之包含矽酸鑭的閘極介電層具有較高的電容值，表示其介電係數較高，並且在製作半導體元件時，元件可以具有較多的載子。 FIG. 6 is a line graph of gate voltage versus capacitance of a gate dielectric layer according to some embodiments of the present invention. It can be seen from FIG. 6 that according to some embodiments of the present invention, the gate dielectric layer containing lanthanum silicate has a higher capacitance value, which indicates that its dielectric constant is higher, and when manufacturing a semiconductor device, the device may have Many carriers.

如上所述，根據本發明的實施方式，藉由快速退火交錯堆疊於半導體層上的複數個二氧化矽層及複數個氧化鑭層，形成矽酸鑭層。本發明之矽酸鑭層包含均勻混合的非結晶態矽酸鑭，其厚度可以藉由交錯堆疊的二氧化矽層及氧化鑭層的數量控制，並且具有高介電係數與較高之能間隙。因此和僅使用具有較低能間隙的單一氧化鑭(La₂O₃)層相比，可避免氧化鑭擴散至半導體層。此外，本發明的矽酸鑭層可以降低半導體元件的漏電流，亦可以與III-V族半導體形成良好的介面，具有較低的介面缺陷密度(Interface trap density；Dit)。 As described above, according to the embodiment of the present invention, the lanthanum silicate layer is formed by rapid annealing of a plurality of silicon dioxide layers and a plurality of lanthanum oxide layers that are staggered on the semiconductor layer. The lanthanum silicate layer of the present invention comprises a uniformly mixed amorphous lanthanum silicate, the thickness of which can be controlled by the number of staggered silicon dioxide layers and lanthanum oxide layers, and has a high dielectric constant and a high energy gap . Therefore, compared to using only a single lanthanum oxide (La ₂ O ₃ ) layer with a lower energy gap, the lanthanum oxide can be prevented from diffusing into the semiconductor layer. In addition, the lanthanum silicate layer of the present invention can reduce the leakage current of the semiconductor device, and can also form a good interface with the III-V semiconductor, and has a lower interface trap density (Dit).

以下結合各種實施例對本發明做更詳細的說明，但本發明並不限於以下實施例。 The following describes the present invention in more detail with reference to various embodiments, but the present invention is not limited to the following embodiments.

實施例1：形成矽酸鑭(Lanthanum silicate)層 Example 1: Formation of Lanthanum silicate layer

依照二氧化矽層、氧化鑭層、二氧化矽層的順序交錯地形成10層二氧化矽層及10層氧化鑭層於氮化鎵(GaN)半導體層上，每一層二氧化矽層及每一層氧化鑭層的厚度皆為約0.5奈米。之後，在約600℃下快速退火上述二氧化矽層及氧化鑭層的疊層，以形成矽酸鑭層。上述矽酸鑭層具有介電係數為約17.6及介面缺陷密度(Dit)小於約5×10¹¹cm^-2eV^-1。 According to the order of the silicon dioxide layer, the lanthanum oxide layer, and the silicon dioxide layer, ten silicon dioxide layers and ten lanthanum oxide layers are formed on the gallium nitride (GaN) semiconductor layer. Each silicon dioxide layer and each The thickness of one lanthanum oxide layer is about 0.5 nm. After that, the stack of the silicon dioxide layer and the lanthanum oxide layer is rapidly annealed at about 600 ° C. to form a lanthanum silicate layer. The lanthanum silicate layer has a dielectric constant of about 17.6 and an interface defect density (Dit) of less than about 5 × 10 ¹¹ cm ^-2 eV ^-1 .

雖然本發明已以實施方式揭露如上，然其並非用以限定本發明，任何熟習此技藝者，在不脫離本發明之精神和範圍內，當可作各種之更動與潤飾，因此本發明之保護範圍當視後附之申請專利範圍所界定者為準。 Although the present invention has been disclosed in the above embodiments, it is not intended to limit the present invention. Any person skilled in the art can make various modifications and retouches without departing from the spirit and scope of the present invention. Therefore, the protection of the present invention The scope shall be determined by the scope of the attached patent application.

Claims

一種半導體結構，包含：一基板；一半導體層，設置於該基板上；一矽酸鑭層，設置於該半導體層上，該矽酸鑭層包含一氧化鑭/二氧化矽(La₂O₃/SiO₂)複合氧化物；以及一閘極電極層，設置於該矽酸鑭層上。 A semiconductor structure includes: a substrate; a semiconductor layer disposed on the substrate; a lanthanum silicate layer disposed on the semiconductor layer; the lanthanum silicate layer comprising lanthanum monoxide / silicon dioxide (La ₂ O ₃ / SiO ₂ ) composite oxide; and a gate electrode layer disposed on the lanthanum silicate layer.

如請求項1所述之半導體結構，其中該矽酸鑭層係由二氧化矽及氧化鑭經固態反應所形成。 The semiconductor structure according to claim 1, wherein the lanthanum silicate layer is formed by a solid state reaction between silicon dioxide and lanthanum oxide.

如請求項1所述之半導體結構，其中該氧化鑭/二氧化矽(La₂O₃/SiO₂)複合氧化物包含化學式為LaSiO_x之複合氧化物，其中x為介於3至4之間的數值。 The semiconductor structure according to claim 1, wherein the lanthanum oxide / silicon dioxide (La ₂ O ₃ / SiO ₂ ) composite oxide comprises a composite oxide having a chemical formula LaSiO _x , where x is between 3 and 4. Value.

如請求項1所述之半導體結構，其中該矽酸鑭層具有一厚度為約2奈米至約50奈米。 The semiconductor structure according to claim 1, wherein the lanthanum silicate layer has a thickness of about 2 nm to about 50 nm.

如請求項1所述之半導體結構，其中該矽酸鑭層具有一介電常數為約12至約22。 The semiconductor structure according to claim 1, wherein the lanthanum silicate layer has a dielectric constant of about 12 to about 22.

如請求項1所述之半導體結構，其中該半導體層包含III-V族半導體。 The semiconductor structure according to claim 1, wherein the semiconductor layer comprises a III-V semiconductor.

如請求項6所述之半導體結構，其中該半導體層包含砷化銦鎵(InGaAs)、砷化銦(InAs)、砷化銦鋁(InAlAs)、磷化銦(InP)、砷化鎵(GaAs)、銻化銦(InSb)、銻化銦鎵(InGaSb)、氮化鎵(GaN)或砷化鋁鎵(AlGaAs)。 The semiconductor structure according to claim 6, wherein the half The conductor layer contains InGaAs, InAs, InAlAs, InP, GaAs, InSb, InSb Gallium (InGaSb), gallium nitride (GaN), or aluminum gallium arsenide (AlGaAs).

一種半導體結構的製造方法，包含：形成一半導體層於一基板上；交錯地形成複數個二氧化矽層及複數個氧化鑭層於該半導體層上；快速退火該些二氧化矽層及該些氧化鑭層，以形成一矽酸鑭層；以及形成一閘極電極層於該矽酸鑭層上。 A method for manufacturing a semiconductor structure includes: forming a semiconductor layer on a substrate; staggeringly forming a plurality of silicon dioxide layers and a plurality of lanthanum oxide layers on the semiconductor layer; rapidly annealing the silicon dioxide layers and the Oxidizing the lanthanum layer to form a lanthanum silicate layer; and forming a gate electrode layer on the lanthanum silicate layer.

如請求項8所述之半導體結構的製造方法，其中各該氧化鑭層具有一厚度為約0.3奈米至約2奈米。 The method for manufacturing a semiconductor structure according to claim 8, wherein each of the lanthanum oxide layers has a thickness of about 0.3 nm to about 2 nm.

如請求項8所述之半導體結構的製造方法，其中各該二氧化矽層具有一厚度為約0.3奈米至約2奈米。 The method for manufacturing a semiconductor structure according to claim 8, wherein each of the silicon dioxide layers has a thickness of about 0.3 nm to about 2 nm.

如請求項8所述之半導體結構的製造方法，其中該快速退火步驟是在約400℃至約800℃下執行。 The method for manufacturing a semiconductor structure according to claim 8, wherein the rapid annealing step is performed at about 400 ° C to about 800 ° C.

如請求項8所述之半導體結構的製造方法，其中形成該些氧化鑭層及該些二氧化矽層包含原子層沉積或分子束沉積。 Manufacturer of a semiconductor structure as described in claim 8 Method, wherein the lanthanum oxide layers and the silicon dioxide layers are formed by atomic layer deposition or molecular beam deposition.

一種半導體裝置，包含：一基板；一通道層，設置於該基板上；一阻障層，設置於該通道層上，且該阻障層具有一凹槽，其中該凹槽具有一第一側壁及與該第一側壁相對的一第二側壁；一源極及一汲極，設置於該阻障層上，其中該源極位於接近該凹槽之該第一側壁的一端，該汲極位於接近該凹槽之該第二側壁的另一端；一閘極介電層，設置於該阻障層上並覆蓋該凹槽，其中該閘極介電層包含矽酸鑭；以及一閘極，設置於該閘極介電層上，且該閘極填入該凹槽中，其中該閘極具有一第一表面、與該第一表面相對的一第二表面及位於該第一表面與該第二表面之間的一底面。 A semiconductor device includes: a substrate; a channel layer disposed on the substrate; a barrier layer disposed on the channel layer; and the barrier layer has a groove, wherein the groove has a first side wall And a second side wall opposite to the first side wall; a source electrode and a drain electrode disposed on the barrier layer, wherein the source electrode is located at one end of the first side wall close to the groove, and the drain electrode is located at Near the other end of the second side wall of the groove; a gate dielectric layer disposed on the barrier layer and covering the groove, wherein the gate dielectric layer includes lanthanum silicate; and a gate, Disposed on the gate dielectric layer, and the gate is filled in the groove, wherein the gate has a first surface, a second surface opposite to the first surface, and the first surface and the second surface A bottom surface between the second surfaces.

如請求項13所述之半導體裝置，其中該閘極介電層具有一厚度為約2奈米至約50奈米。 The semiconductor device according to claim 13, wherein the gate dielectric layer has a thickness of about 2 nm to about 50 nm.

如請求項13所述之半導體裝置，其中該閘極的該底表面具有一寬度為約80奈米至約3微米。 The semiconductor device according to claim 13, wherein the bottom surface of the gate has a width of about 80 nm to about 3 microns.

如請求項13所述之半導體裝置，其中該閘極的該第一表面與該源極之間具有一間距為約1微米至約5微米。 The semiconductor device according to claim 13, wherein a gap between the first surface of the gate electrode and the source electrode is about 1 micrometer to about 5 micrometers.

如請求項13所述之半導體裝置，其中該閘極的該第二表面與該汲極之間具有一間距為約2微米至約50微米。 The semiconductor device according to claim 13, wherein a gap between the second surface of the gate electrode and the drain electrode is about 2 μm to about 50 μm.

如請求項13所述之半導體裝置，其中還包括一保護層設置在該閘極介電層上。 The semiconductor device according to claim 13, further comprising a protection layer disposed on the gate dielectric layer.

如請求項13所述之半導體裝置，其中該通道層與該阻障層包含III-V族半導體。 The semiconductor device according to claim 13, wherein the channel layer and the barrier layer comprise a III-V semiconductor.