CN110581068A - Method for realizing low-on-resistance enhanced gallium nitride transistor by using gate dielectric - Google Patents
Method for realizing low-on-resistance enhanced gallium nitride transistor by using gate dielectric Download PDFInfo
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- CN110581068A CN110581068A CN201910836162.1A CN201910836162A CN110581068A CN 110581068 A CN110581068 A CN 110581068A CN 201910836162 A CN201910836162 A CN 201910836162A CN 110581068 A CN110581068 A CN 110581068A
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- 238000000034 method Methods 0.000 title claims abstract description 43
- 229910002601 GaN Inorganic materials 0.000 title abstract description 32
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 title abstract description 14
- 229910002704 AlGaN Inorganic materials 0.000 claims abstract description 47
- XOLBLPGZBRYERU-UHFFFAOYSA-N tin dioxide Chemical compound O=[Sn]=O XOLBLPGZBRYERU-UHFFFAOYSA-N 0.000 claims abstract description 41
- 229910001887 tin oxide Inorganic materials 0.000 claims abstract description 41
- 230000004888 barrier function Effects 0.000 claims abstract description 39
- 238000005530 etching Methods 0.000 claims abstract description 32
- 238000002161 passivation Methods 0.000 claims abstract description 21
- 229910052751 metal Inorganic materials 0.000 claims abstract description 13
- 239000002184 metal Substances 0.000 claims abstract description 13
- 239000000758 substrate Substances 0.000 claims abstract description 11
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 7
- 239000010703 silicon Substances 0.000 claims abstract description 7
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 4
- 238000000151 deposition Methods 0.000 claims description 16
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 15
- 239000001301 oxygen Substances 0.000 claims description 15
- 229910052760 oxygen Inorganic materials 0.000 claims description 15
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 claims description 14
- 238000000137 annealing Methods 0.000 claims description 14
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 claims description 13
- 230000008021 deposition Effects 0.000 claims description 11
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 10
- 239000012299 nitrogen atmosphere Substances 0.000 claims description 10
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 9
- 238000004518 low pressure chemical vapour deposition Methods 0.000 claims description 9
- 239000002243 precursor Substances 0.000 claims description 9
- 229910052782 aluminium Inorganic materials 0.000 claims description 8
- 238000001259 photo etching Methods 0.000 claims description 8
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 claims description 7
- 229910015844 BCl3 Inorganic materials 0.000 claims description 6
- 239000000956 alloy Substances 0.000 claims description 6
- 229910045601 alloy Inorganic materials 0.000 claims description 6
- 239000000463 material Substances 0.000 claims description 6
- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 claims description 6
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 5
- 238000001312 dry etching Methods 0.000 claims description 5
- 238000005566 electron beam evaporation Methods 0.000 claims description 5
- 239000007789 gas Substances 0.000 claims description 5
- 230000003647 oxidation Effects 0.000 claims description 5
- 238000007254 oxidation reaction Methods 0.000 claims description 5
- 239000000377 silicon dioxide Substances 0.000 claims description 5
- 239000010936 titanium Substances 0.000 claims description 5
- 238000001039 wet etching Methods 0.000 claims description 5
- MHAJPDPJQMAIIY-UHFFFAOYSA-N Hydrogen peroxide Chemical compound OO MHAJPDPJQMAIIY-UHFFFAOYSA-N 0.000 claims description 4
- 239000007772 electrode material Substances 0.000 claims description 4
- 239000010931 gold Substances 0.000 claims description 4
- 229910052737 gold Inorganic materials 0.000 claims description 4
- 229910052759 nickel Inorganic materials 0.000 claims description 4
- 229910052697 platinum Inorganic materials 0.000 claims description 4
- 235000012239 silicon dioxide Nutrition 0.000 claims description 4
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 4
- -1 silicon-aluminum-nitrogen Chemical compound 0.000 claims description 4
- 229910052719 titanium Inorganic materials 0.000 claims description 4
- 229910052721 tungsten Inorganic materials 0.000 claims description 4
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 claims description 4
- BUGBHKTXTAQXES-UHFFFAOYSA-N Selenium Chemical compound [Se] BUGBHKTXTAQXES-UHFFFAOYSA-N 0.000 claims description 3
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims description 3
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 claims description 3
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims description 3
- 229910052594 sapphire Inorganic materials 0.000 claims description 3
- 239000010980 sapphire Substances 0.000 claims description 3
- 229910052711 selenium Inorganic materials 0.000 claims description 3
- 239000011669 selenium Substances 0.000 claims description 3
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 claims description 3
- 229910010271 silicon carbide Inorganic materials 0.000 claims description 3
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims description 3
- 239000010937 tungsten Substances 0.000 claims description 3
- CBENFWSGALASAD-UHFFFAOYSA-N Ozone Chemical compound [O-][O+]=O CBENFWSGALASAD-UHFFFAOYSA-N 0.000 claims description 2
- KEJQTHYHDVZLMT-UHFFFAOYSA-N bis(2-methylpropyl)tin Chemical compound CC(C)C[Sn]CC(C)C KEJQTHYHDVZLMT-UHFFFAOYSA-N 0.000 claims description 2
- 238000003475 lamination Methods 0.000 claims description 2
- 239000000203 mixture Substances 0.000 claims description 2
- CPRPKIMXLHBUGA-UHFFFAOYSA-N triethyltin Chemical compound CC[Sn](CC)CC CPRPKIMXLHBUGA-UHFFFAOYSA-N 0.000 claims description 2
- LYRCQNDYYRPFMF-UHFFFAOYSA-N trimethyltin Chemical compound C[Sn](C)C LYRCQNDYYRPFMF-UHFFFAOYSA-N 0.000 claims description 2
- WGTYBPLFGIVFAS-UHFFFAOYSA-M tetramethylammonium hydroxide Chemical compound [OH-].C[N+](C)(C)C WGTYBPLFGIVFAS-UHFFFAOYSA-M 0.000 claims 2
- AJNVQOSZGJRYEI-UHFFFAOYSA-N digallium;oxygen(2-) Chemical compound [O-2].[O-2].[O-2].[Ga+3].[Ga+3] AJNVQOSZGJRYEI-UHFFFAOYSA-N 0.000 claims 1
- 229910001195 gallium oxide Inorganic materials 0.000 claims 1
- 229910000449 hafnium oxide Inorganic materials 0.000 claims 1
- WIHZLLGSGQNAGK-UHFFFAOYSA-N hafnium(4+);oxygen(2-) Chemical compound [O-2].[O-2].[Hf+4] WIHZLLGSGQNAGK-UHFFFAOYSA-N 0.000 claims 1
- RVTZCBVAJQQJTK-UHFFFAOYSA-N oxygen(2-);zirconium(4+) Chemical compound [O-2].[O-2].[Zr+4] RVTZCBVAJQQJTK-UHFFFAOYSA-N 0.000 claims 1
- 229910001928 zirconium oxide Inorganic materials 0.000 claims 1
- 230000005533 two-dimensional electron gas Effects 0.000 abstract description 12
- 239000004065 semiconductor Substances 0.000 abstract description 9
- 230000015556 catabolic process Effects 0.000 abstract description 2
- 230000005669 field effect Effects 0.000 abstract description 2
- 239000012212 insulator Substances 0.000 abstract description 2
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 abstract 2
- RNQKDQAVIXDKAG-UHFFFAOYSA-N aluminum gallium Chemical compound [Al].[Ga] RNQKDQAVIXDKAG-UHFFFAOYSA-N 0.000 abstract 1
- 229910052757 nitrogen Inorganic materials 0.000 abstract 1
- 229910052718 tin Inorganic materials 0.000 description 12
- 239000011135 tin Substances 0.000 description 12
- 238000009616 inductively coupled plasma Methods 0.000 description 11
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 8
- 238000000231 atomic layer deposition Methods 0.000 description 8
- 238000004151 rapid thermal annealing Methods 0.000 description 6
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 3
- 238000010894 electron beam technology Methods 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 3
- 238000002488 metal-organic chemical vapour deposition Methods 0.000 description 3
- 230000008569 process Effects 0.000 description 3
- 238000006243 chemical reaction Methods 0.000 description 2
- 239000008367 deionised water Substances 0.000 description 2
- 229910021641 deionized water Inorganic materials 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 230000005684 electric field Effects 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 230000010287 polarization Effects 0.000 description 2
- 239000004411 aluminium Substances 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 229910052681 coesite Inorganic materials 0.000 description 1
- 229910052906 cristobalite Inorganic materials 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 238000002156 mixing Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- WHXTVQNIFGXMSB-UHFFFAOYSA-N n-methyl-n-[tris(dimethylamino)stannyl]methanamine Chemical compound CN(C)[Sn](N(C)C)(N(C)C)N(C)C WHXTVQNIFGXMSB-UHFFFAOYSA-N 0.000 description 1
- 229920006395 saturated elastomer Polymers 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 230000002269 spontaneous effect Effects 0.000 description 1
- 229910052682 stishovite Inorganic materials 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 229910052905 tridymite Inorganic materials 0.000 description 1
- JLTRXTDYQLMHGR-UHFFFAOYSA-N trimethylaluminium Chemical compound C[Al](C)C JLTRXTDYQLMHGR-UHFFFAOYSA-N 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66446—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET]
- H01L29/66462—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET] with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
- H01L29/7786—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Junction Field-Effect Transistors (AREA)
Abstract
The invention discloses a method for realizing an enhanced gallium nitride transistor with low on-resistance by using a gate dielectric, wherein the gallium nitride transistor comprises a silicon substrate; a gallium nitride channel layer and an aluminum gallium nitrogen barrier layer which are arranged on the substrate in sequence; a source and a drain in contact with the AlGaN barrier layer; the passivation layer is arranged on the AlGaN barrier layer except for the source electrode and the drain electrode; and etching the passivation layer below the gate and part of the AlGaN barrier layer below the gate to form the gate with a groove structure. The first layer of the grid electrode is p-type tin oxide, the second layer is an insulating layer, and the third layer is a metal layer. The p-type tin oxide is used as a gate dielectric, so that two-dimensional electron gas below a gate is exhausted in zero gate voltage, an enhanced metal insulator semiconductor field effect transistor structure is realized, meanwhile, an insulating layer can block gate leakage possibly generated by the p-type tin oxide, and the gallium nitride transistor with the structure has low leakage and high breakdown voltage.
Description
Technical Field
The invention belongs to the field of semiconductor manufacturing, relates to a method for realizing a transistor with low on-resistance by using a gate dielectric and a semiconductor device manufactured by the method, and particularly relates to a method for realizing an enhanced gallium nitride transistor with low on-resistance by using p-type tin oxide and a manufactured enhanced metal insulator semiconductor field effect transistor.
Background
The gallium nitride semiconductor material has the advantages of large band gap width and high voltage endurance capability, has attracted the great interest of researchers, and can be widely applied to high-temperature, high-frequency and high-power electronic devices. The forbidden band width is 3.4eV at normal temperature, the bonding force between atoms is strong, the chemical property is stable, the critical breakdown electric field is large, the saturated electron mobility is high, the temperature resistance is good, and the high-frequency high-power semiconductor device is widely applied as a high-frequency high-power device. The working principle of the gallium nitride high electron mobility transistor (GaN HEMT) is that a high-concentration two-dimensional electron gas is generated on an AlGaN/GaN interface to form a conducting channel by means of a built-in polarization electric field generated by two effects, namely piezoelectric effect and spontaneous polarization, which are specific to AlGaN/GaN heterojunction. The most common method for realizing the enhancement-type gallium nitride HEMT is to use a groove enhancement-type structure, and the structure is formed by etching a gate region to thin an AlGaN barrier layer above two-dimensional electron gas. However, in this method, the threshold voltage is too low (generally not more than 1V), and a dielectric layer is further added to increase the threshold voltage. The selection of the dielectric layer is also very important, for example, the interface between the dielectric layer and the AlGaN barrier layer has a high-density interface state, and the on-resistance is high, so that the instability of the threshold of the device can be increased, and the switching efficiency of the device is greatly influenced.
Therefore, in view of the above technical problems, it is desirable to provide an enhanced gan semiconductor device using a gate dielectric to achieve low on-resistance, so as to overcome the above drawbacks.
Disclosure of Invention
Tin oxide is a special oxide that changes its electrical properties at different ratios of tin to oxygen. And the P-type tin oxide medium pulls the Fermi level in the two-dimensional electron gas channel below the grid to exhaust the two-dimensional electron gas concentration below the grid, so that the normally-off device under zero grid voltage is realized.
the invention provides a method for realizing an enhanced gallium nitride transistor with low on-resistance by utilizing P-type tin oxide, which comprises the following steps:
(1) A GaN channel layer and an AlGaN barrier layer are grown on a substrate in sequence by using MOCVD.
(2) And forming an active region table top on the sample of the AlGaN/GaN structure by photoetching and an ICP etching technology.
(3) And (3) performing rapid thermal annealing on the material of the electron beam evaporation source and the drain electrode on the table top of the active region in a nitrogen atmosphere to form ohmic contact, and preparing the alloy electrode of the source and the drain.
(4) and (3) using PECVD (plasma enhanced chemical vapor deposition), ICPCVD (Integrated plasma enhanced chemical vapor deposition) or LPCVD (Low pressure chemical vapor deposition) on the sample, and completely etching the passivation layer below the gate by utilizing a photoetching and etching method.
(5) Etching the AlGaN barrier layer under part of the gate by utilizing an ICP (inductively coupled plasma) etching or oxidation and wet etching circulating method to form a groove structure.
(6) The sample is placed in an ALD or PEALD apparatus and tin oxide is deposited as the gate dielectric using an oxygen source and a tin precursor source.
(7) And after the deposition is finished, putting the sample into an annealing furnace, and annealing in a nitrogen atmosphere to enable the intrinsic tin oxide medium to react to form a P-type tin oxide medium.
(8) The sample is placed in an ALD or PEALD apparatus, and aluminum oxide is deposited as a gate dielectric insulating layer using an oxygen source and an aluminum precursor source.
(9) The metal electrode of the gate region is evaporated by an electron beam.
Preferably, in step (1), the substrate may be silicon or sapphire or silicon carbide.
Preferably, in step (1), the thickness of the GaN channel layer is 0 ~ 6000 nm.
Preferably, in step (1), the AlGaN barrier layer has a thickness of 0 ~ 50 nm.
Preferably, in step (1), the composition of Al in the AlGaN barrier layer is 0 ~ 1.
Preferably, in step (2), the gases used for ICP etching are: cl2Or BCl3or Cl2/BCl3and (4) mixing the gases.
Preferably, the ICP etching depth in step (2) is 0 ~ 1000 nm.
Preferably, in step (3), the source and drain ohmic contact electrode materials are: one or more combinations of titanium, aluminum, nickel, gold, titanium nitride, platinum, tungsten, silicon, selenium, and the like.
Preferably, in step (3), the rapid thermal annealing temperature is 700 ℃ ~ 900 ℃ and the rapid thermal annealing time is 30s ~ 60 s.
Preferably, in the step (4), the passivation layer may be SiO2、SiON、Si3N4One or more combinations of;
Preferably, the thickness of the passivation layer in step (4) is 1nm ~ 1000 nm.
Preferably, in step (5), the etching technique may be to use Cl2,BCl3Or Cl2/BCl3Dry etching techniques using mixed gases, or wet etching techniques using oxygen oxidation, HCl or KOH solution etching.
Preferably, the etching depth in step (5) is 0 ~ 50 nm.
preferably, in step (6), the temperature of the reaction chamber of the ALD or PEALD apparatus is 25 deg.C ~ 400 deg.C, preferably 200 deg.C ~ 300 deg.C, and the vacuum range is 1Pa ~ 500 Pa;
Preferably, the tin oxide is deposited in step (6) to a thickness of 1nm ~ 500nm, preferably 3nm ~ 50 nm.
Preferably, the thermal annealing temperature in step (7) is 25 ℃ ~ 600 ℃ and the rapid thermal annealing time is 1s ~ 5000 s.
Preferably, the temperature of the reaction chamber of the ALD or PEALD apparatus in step (8) is 25 deg.C ~ 400 deg.C, preferably 200 deg.C ~ 300 deg.C, and the vacuum range is 1Pa ~ 500 Pa;
Preferably, the alumina is deposited in step (8) to a thickness of 1nm ~ 500nm, preferably 10nm ~ 50 nm.
Preferably, in step (9), the gate electrode material is one or more of Ti, Al, Ni, Au, TiN, Pt, W, Si, Se, etc., preferably Ni/TiN, Ni thickness is 50nm ~ 100nm, and metal TiN thickness is 40nm ~ 120 nm.
the invention has the advantages that: the p-type semiconductor tin oxide can pull the Fermi level in the two-dimensional electron gas channel below the p-type semiconductor tin oxide, deplete the two-dimensional electron gas below the grid or greatly reduce the concentration of the two-dimensional electron gas. A normally-off device under zero gate voltage is realized; by forming the grid groove structure, the AlGaN barrier layer can be thinned, the concentration of two-dimensional electron gas formed at the interface of the AlGaN barrier layer and the GaN channel layer is reduced, the threshold voltage of the device is improved, and the device is transferred to the positive direction, so that the enhanced device with higher threshold voltage and convenient practical application is realized. Meanwhile, the grid dielectric insulating layer can block grid electrode electric leakage possibly generated by p-type tin oxide, and the high-voltage characteristic of the device is improved.
Drawings
The invention is further described with reference to the following figures and examples:
FIG. 1 is a cross-sectional view of an AlGaN/GaN heterojunction structure substrate;
FIG. 2 is a cross-sectional view of the device after formation of source and drain ohmic contact electrodes;
FIG. 3 is a cross-sectional view of the device after the passivation layer under the gate has been completely etched;
FIG. 4 is a cross-sectional view of the device after partial etching of the barrier layer under the gate;
FIG. 5 is a cross-sectional view of the device after forming a P-type tin oxide gate dielectric;
FIG. 6 is a cross-sectional view of the device after forming P-type tin oxide and an insulating layer gate dielectric;
Fig. 7 is a cross-sectional view of the device after fabrication is complete.
Detailed Description
Example 1
The method for realizing the enhancement type gallium nitride transistor with low on-resistance by utilizing the p-type tin oxide comprises the following steps:
Firstly, growing a GaN channel layer and an AlGaN barrier layer on a substrate in sequence to form a sample of an AlGaN/GaN structure.
Secondly, forming an active region table surface on a sample of the AlGaN/GaN structure, preparing alloy electrodes of a source region and a drain region on the active region table surface through electron beam evaporation, and performing rapid annealing on the source electrode and the drain electrode in a nitrogen atmosphere at 700 ℃ and ~ 900 ℃ for 30s and ~ 60s to form ohmic contact.
Thirdly, depositing a passivation layer formed by one or a combination of silicon nitride, silicon dioxide and silicon-aluminum-nitrogen on the AlGaN barrier layer between the source electrode and the drain electrode by PECVD (plasma enhanced chemical vapor deposition) or ICPCVD (Integrated plasma enhanced chemical vapor deposition) or LPCVD (low pressure chemical vapor deposition) equipment, wherein the lamination thickness of the passivation layer and the AlGaN barrier layer does not exceed the thickness of the alloy electrode.
And fourthly, etching off the passivation layer below the gate electrode by using a photoetching and dry etching method, etching and extending the passivation layer to the AlGaN barrier layer to form a groove structure, and reserving the AlGaN barrier layer at the bottom of the groove.
Fifthly, using water, hydrogen peroxide, oxygen and ozone as oxygen sources, trimethyl tin, triethyl tin and diisobutyl tin as precursor sources, depositing tin oxide in an etching area under the conditions of 25 ℃ of ~ ℃ and 0.1Pa of ~ Pa, and annealing the tin oxide in nitrogen atmosphere at 25 ℃ of ~ ℃ for 1s ~ 4000s to enable the intrinsic tin oxide medium to react to form the P-type tin oxide medium.
And sixthly, forming an insulating layer which does not exceed the grid electrode region on the P-type tin oxide medium.
And seventhly, forming a metal gate on the insulating layer.
Based on the steps of the method, the specific values of the related process parameters are shown in the following table:
| Sequence of steps Number (C) | Source and drain electrodes Fast heating annealing temperature degree (. degree. C.) | Source and drain electrodes during rapid thermal annealing Workshop(s) | Tin oxide deposition Temperature (. degree.C.) | Tin oxide deposition pressure (Pa) | P-type tin oxide dielectric Mass annealing temperature （℃） | P-type tin oxide dielectric Annealing time （s） | alumina insulation Temperature of layer deposition （℃） | Alumina insulating layer Pressure (Pa) |
| 1 | 870 | 45 | 200 | 14 | 300 | 600 | 200 | 14 |
| 2 | 870 | 45 | 200 | 14 | 400 | 600 | 200 | 14 |
| 3 | 870 | 45 | 300 | 14 | 400 | 1200 | 200 | 14 |
| 4 | 870 | 45 | 300 | 14 | 500 | 1200 | 200 | 14 |
example 2:
The method for realizing the enhancement type gallium nitride transistor with low on-resistance by utilizing the P-type tin oxide comprises the following steps:
1. And sequentially growing a GaN channel layer and an AlGaN barrier layer on a silicon or sapphire or silicon carbide substrate by using MOCVD, wherein the thickness of the GaN channel layer is 0 ~ 6000nm, and the thickness of the AlGaN barrier layer is 0 ~ 50 nm.
2. On a sample of the AlGaN/GaN structure, an active region mesa is formed by photoetching and an ICP etching technology, and the ICP etching depth is 0 ~ 1000 nm.
3. and (3) performing rapid thermal annealing on the material of the electron beam evaporation source and the drain electrode on the table top of the active region in a nitrogen atmosphere to form ohmic contact, and preparing the alloy electrode of the source and the drain.
4. And (3) completely etching the passivation layer under the gate by using PECVD (plasma enhanced chemical vapor deposition) or ICPCVD (Integrated plasma enhanced chemical vapor deposition) or LPCVD (low pressure chemical vapor deposition) on the sample by using a photoetching and etching method, wherein the thickness of the passivation layer is 1nm ~ 1000 nm.
5. Etching the AlGaN barrier layer under partial gate by using an ICP (inductively coupled plasma) etching or oxidation and wet etching circulating method to form a groove structure, wherein the depth of the groove is 0 ~ 50nm, and the AlGaN barrier layer with the thickness of 1 ~ 25nm is reserved.
6. The sample is placed in an ALD or PEALD apparatus, and tin oxide is deposited as a gate dielectric using an oxygen source and a tin precursor source, wherein the thickness of the deposited tin oxide is 1nm ~ 500nm, preferably 3nm ~ 50 nm.
7. and after the deposition is finished, putting the sample into an annealing furnace, and annealing in a nitrogen atmosphere to enable the intrinsic tin oxide medium to react to form a P-type tin oxide medium.
8. The sample is placed into an ALD or PEALD device, and aluminum oxide is deposited as a gate dielectric insulating layer by using an oxygen source and an aluminum precursor source, wherein the thickness of the aluminum oxide is 1nm ~ 500nm, and is preferably 10nm ~ 50 nm.
9. The metal electrode, preferably a combination of Ni/TiN as the gate electrode material, evaporated out of the gate region by electron beam, was 50nm ~ 100nm in Ni thickness and 40nm ~ 120nm in metal TiN thickness.
Based on the steps of the method, the specific values of the related thickness parameters of each layer are shown in the following table:
| Sequence of steps Number (C) | GaN channel layer Thickness (nm) | AlGaN barrier layer thickness （nm） | Active region mesa ICP etching depth Degree (nm) | Thickness of passivation layer Degree (nm) | AlGaN barrier depth of groove on layer Degree (nm) | Oxygen deposition Thickness of tin （nm） | Oxygen deposition thickness of aluminium （nm） | Metal grid thickness of medium Ni （nm） | TiN in metal grid thickness (nm) |
| 1 | 4200 | 25 | 500 | 100 | 23 | 5 | 15 | 50 | 80 |
| 2 | 4200 | 25 | 500 | 100 | 23 | 10 | 15 | 50 | 80 |
| 3 | 4200 | 25 | 500 | 100 | 23 | 25 | 15 | 50 | 80 |
| 4 | 4200 | 25 | 500 | 100 | 23 | 20 | 15 | 50 | 80 |
Example 3:
As shown in fig. 1-7, a method for implementing a low on-resistance enhancement mode gan transistor using a gate dielectric includes the steps of:
1. On a Si substrate, a 420 μm GaN channel layer was first grown by MOCVD, and a 25nm AlGaN barrier layer was grown thereon, the cross-sectional view of which is shown in fig. 1.
2. And forming an active region mesa on the gallium nitride heterojunction substrate with the structure by photoetching and ICP etching technology. Four materials of Ti/Al/Ni/TiN (30 nm/120nm/60nm/60 nm) are evaporated by electron beams, and the metal electrodes of the source region and the drain region are prepared by adopting a stripping process. And a rapid annealing was performed in a nitrogen atmosphere at 860 c for 40 seconds to form an ohmic contact, a cross-sectional view of which is shown in fig. 2.
3. After ohmic contacts are formed on the source electrode and the drain electrode, one or a combination of several of 200nm silicon nitride, silicon dioxide and silicon-aluminum-nitrogen is grown on a sample wafer by PECVD, ICPCVD or LPCVD as a passivation layer, and the passivation layer under the gate electrode area is completely etched by photoetching and dry etching methods, wherein the structure is shown in FIG. 3.
4. On the basis of the structure, the AlGaN barrier layer under a part of gate electrode area can be etched slowly and uniformly by using a method of oxidation and wet etching circulation to form a groove structure. An approximately 5nm undergate AlGaN barrier layer was left above the GaN channel layer. The concentration of two-dimensional electron gas below the grid electrode can be greatly reduced by etching part of the AlGaN barrier layer, and the AlGaN barrier layer below the rest 5nm grid can keep an AlGaN/GaN heterojunction channel structure and keep the characteristic of high mobility of a device channel. The structure is shown in fig. 4.
5. On the basis of the structure, a sample is placed in atomic layer deposition equipment, deionized water is used as an oxygen source, tetra (dimethylamino) tin is used as a precursor source, the temperature of a cavity is 210 ℃, the pressure of the cavity is about 14Pa, and tin oxide with the thickness of 9nm is deposited in an etched area and used as a gate medium.
6. after the deposition of the tin oxide is finished, the sample is placed into an annealing furnace and annealed for 1 hour in a nitrogen atmosphere at 250 ℃ so that the intrinsic tin oxide medium reacts to form a P-type tin oxide medium. On the basis of partially etching off the AlGaN barrier layer, the Fermi level in a two-dimensional electron gas channel below the grid is pulled by the P-type tin oxide medium, the two-dimensional electron gas concentration below the grid is exhausted, and a normally-off device under zero grid voltage is realized.
7. on the basis of the structure, a sample is placed in atomic layer deposition equipment, deionized water is used as an oxygen source, trimethylaluminum is used as a precursor source, the temperature of a cavity is 230 ℃, the pressure of the cavity is about 14Pa, and 20 nm-thick aluminum oxide is deposited to be used as a gate dielectric insulating layer.
The metal electrode of the gate region is prepared by electron beam evaporation of two materials of Ni/TiN (50 nm/100 nm) and a stripping process. The structure is shown in fig. 6.
The foregoing embodiments are merely illustrative of the principles and utilities of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or change the above-mentioned embodiments without departing from the spirit and scope of the present invention. Accordingly, it is intended that all equivalent modifications or changes which can be made by those skilled in the art without departing from the spirit and technical concepts disclosed herein be covered by the appended claims.
Claims (9)
1. A method for using a gate dielectric to realize a low on-resistance enhancement mode GaN transistor is characterized in that: the method comprises the following steps:
firstly, growing a GaN channel layer and an AlGaN barrier layer on a substrate in sequence to form an AlGaN/GaN structural sample;
Secondly, forming an active region table top on a sample of the AlGaN/GaN structure, preparing alloy electrodes of a source region and a drain region on the active region table top through electron beam evaporation, and performing rapid annealing on the source electrode and the drain electrode in a nitrogen atmosphere at 700 ℃ and ~ 900 ℃ for 30s and ~ 60s to form ohmic contact;
Thirdly, depositing a passivation layer formed by combining one or more of silicon nitride, silicon dioxide and silicon-aluminum-nitrogen on the AlGaN barrier layer between the source electrode and the drain electrode by PECVD (plasma enhanced chemical vapor deposition) or ICPCVD (Integrated plasma enhanced chemical vapor deposition) or LPCVD (low pressure chemical vapor deposition) equipment, wherein the lamination thickness of the passivation layer and the AlGaN barrier layer is not more than the thickness of the alloy electrode;
Etching the passivation layer below the gate electrode by using a photoetching and dry etching method, etching and extending the passivation layer to the AlGaN barrier layer to form a groove structure, and reserving the AlGaN barrier layer at the bottom of the groove;
Fifthly, taking water, hydrogen peroxide, oxygen and ozone as oxygen sources, taking trimethyl tin, triethyl tin and diisobutyl tin as precursor sources, depositing tin oxide in an etching area under the conditions of the temperature of 25 ℃ of ~ 400 ℃ and the pressure of 0.1Pa of ~ 500Pa, annealing the tin oxide in nitrogen atmosphere at the temperature of 25 ℃ of ~ 600 ℃ for 1s of ~ 4000s, and enabling the intrinsic tin oxide medium to react to form a P-type tin oxide medium;
Sixthly, depositing aluminum oxide on the P-type tin oxide medium as an insulating layer by using an oxygen source and an aluminum precursor source, wherein the deposition temperature is 25 ℃, the deposition temperature is ~ 400 ℃, and the deposition pressure is 0.1Pa, ~ 500 Pa;
Seventh, a metal gate is formed over the insulating layer using one or a combination of titanium, aluminum, nickel, gold, titanium nitride, platinum, tungsten, silicon, selenium, or the like as a gate electrode material.
2. the method of claim 1, wherein the gate dielectric is used to realize a low on-resistance enhancement mode GaN transistor, the method comprising: the etching method of the active area table top is selected from the following steps: cl2or BCl3Or Cl2/BCl3Dry etching of the mixed gas; or is selected from O2Gas oxidation, wet etching with HCl or KOH or TMAH solution etching.
3. The method of claim 1, wherein the gate dielectric is used to realize a low on-resistance enhancement mode GaN transistor, the method comprising: the source electrode and the drain electrode are made of the following materials: one or more combinations of titanium, aluminum, nickel, gold, titanium nitride, platinum, tungsten, silicon, selenium, and the like.
4. The method of claim 1, wherein the gate dielectric is used to realize a low on-resistance enhancement mode GaN transistor, the method comprising: the insulating layer is: one or more of silicon nitride, silicon dioxide, silicon aluminum nitrogen, aluminum oxide, hafnium oxide, zirconium oxide and gallium oxide.
5. The method of claim 1, wherein the gate dielectric is used to realize a low on-resistance enhancement mode GaN transistor, the method comprising: the substrate may be silicon or sapphire or silicon carbide.
6. the method of claim 1, wherein said AlGaN barrier layer has an Al composition of 0 ~ 1.
7. The method of claim 1, wherein in the first step, the thickness of the GaN channel layer is 0 ~ 6000nm and the thickness of the AlGaN barrier layer is 0 ~ 50 nm.
8. The method of claim 1, wherein in the third step, the passivation layer has a thickness of 0nm ~ 1000 nm.
9. The method of claim 8, wherein in the fourth step, the passivation layer is etched through, the etched region extends to the AlGaN barrier layer and forms a recess with an etching depth of 0 ~ 50nm, and the thickness of the AlGaN barrier layer is 1 ~ 25 nm.
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