TW201937730A - 半導體裝置 - Google Patents

半導體裝置 Download PDF

Info

Publication number
TW201937730A
TW201937730A TW107114999A TW107114999A TW201937730A TW 201937730 A TW201937730 A TW 201937730A TW 107114999 A TW107114999 A TW 107114999A TW 107114999 A TW107114999 A TW 107114999A TW 201937730 A TW201937730 A TW 201937730A
Authority
TW
Taiwan
Prior art keywords
layer
nitride semiconductor
semiconductor layer
semiconductor device
source electrode
Prior art date
Application number
TW107114999A
Other languages
English (en)
Inventor
松下景一
Original Assignee
日商東芝股份有限公司
日商東芝基礎設施系統股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 日商東芝股份有限公司, 日商東芝基礎設施系統股份有限公司 filed Critical 日商東芝股份有限公司
Publication of TW201937730A publication Critical patent/TW201937730A/zh

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/778Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
    • H01L29/7786Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT
    • H01L29/7787Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT with wide bandgap charge-carrier supplying layer, e.g. direct single heterostructure MODFET
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02107Forming insulating materials on a substrate
    • H01L21/02109Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/0217Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02107Forming insulating materials on a substrate
    • H01L21/02225Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02263Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
    • H01L21/02271Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
    • H01L21/02274Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition in the presence of a plasma [PECVD]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/24Alloying of impurity materials, e.g. doping materials, electrode materials, with a semiconductor body
    • H01L21/244Alloying of electrode materials
    • H01L21/246Alloying of electrode materials with AIIIBV compounds
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/30604Chemical etching
    • H01L21/30612Etching of AIIIBV compounds
    • H01L21/30621Vapour phase etching
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/432Heterojunction gate for field effect devices
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007Multistep manufacturing processes
    • H01L29/66075Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409Unipolar field-effect transistors
    • H01L29/66446Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET]
    • H01L29/66462Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET] with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/778Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
    • H01L29/7786Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02436Intermediate layers between substrates and deposited layers
    • H01L21/02439Materials
    • H01L21/02455Group 13/15 materials
    • H01L21/02458Nitrides
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02518Deposited layers
    • H01L21/02521Materials
    • H01L21/02538Group 13/15 materials
    • H01L21/0254Nitrides
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02612Formation types
    • H01L21/02617Deposition types
    • H01L21/0262Reduction or decomposition of gaseous compounds, e.g. CVD
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/285Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
    • H01L21/28506Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
    • H01L21/28575Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising AIIIBV compounds
    • H01L21/28587Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising AIIIBV compounds characterised by the sectional shape, e.g. T, inverted T
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/28Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3157Partial encapsulation or coating
    • H01L23/3171Partial encapsulation or coating the coating being directly applied to the semiconductor body, e.g. passivation layer
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/20Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
    • H01L29/2003Nitride compounds
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/20Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
    • H01L29/201Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds including two or more compounds, e.g. alloys
    • H01L29/205Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds including two or more compounds, e.g. alloys in different semiconductor regions, e.g. heterojunctions
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/417Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H01L29/41725Source or drain electrodes for field effect devices
    • H01L29/41766Source or drain electrodes for field effect devices with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Chemical & Material Sciences (AREA)
  • Plasma & Fusion (AREA)
  • General Chemical & Material Sciences (AREA)
  • Junction Field-Effect Transistors (AREA)

Abstract

一種半導體裝置,具備:基板、被形成於前述基板上的第1氮化物半導體層、被形成於前述第1氮化物半導體層上,含有鎵元素的第2氮化物半導體層、於前述第2氮化物半導體層上,與前述第2氮化物半導體層接觸而形成的源極電極及汲極電極,被形成於前述第2氮化物半導體層之上,含有銦元素與鋁元素的第3氮化物半導體層、以及於前述第3氮化物半導體層之上,被形成於前述源極電極及汲極電極之間的閘極電極。

Description

半導體裝置
本發明之實施型態係關於半導體裝置。
於使用在通訊或雷達等的大電力用氮化鎵系半導體裝置,藉著於被形成在Si、SiC或藍寶石的基板上之GaN通道層以及AlGaN障壁層之上,形成被稱為InAlN帽蓋層或InAlGaN帽蓋層之層,可以使表面狀態安定,提高電流崩潰的抑制等元件特性。但是,有InAlN帽蓋層或InAlGaN帽蓋層的話,形成歐姆電極時要降低接觸電阻是困難的。
[發明所欲解決之課題]
本發明之實施型態,於使用在通訊或雷達等的大電力用氮化鎵系半導體裝置,提供高性能的元件。 [供解決課題之手段]
實施型態的半導體裝置,具備:基板、被形成於前述基板上的第1氮化物半導體層、被形成於前述第1氮化物半導體層上,含有鎵元素的第2氮化物半導體層、於前述第2氮化物半導體層上,與前述第2氮化物半導體層接觸而形成的源極電極及汲極電極,被形成於前述第2氮化物半導體層之上,含有銦元素與鋁元素的第3氮化物半導體層、以及於前述第3氮化物半導體層之上,被形成於前述源極電極及汲極電極之間的閘極電極。
根據前述半導體裝置,可以提供高性能的大電力用氮化鎵系半導體裝置。
(第1實施型態)   以下,參照圖式,說明相關於本實施型態之半導體裝置。
圖1係第1實施形態之半導體裝置100之剖面圖。於基板10上被形成作為通道層之氮化鎵層(GaN層、第1氮化物半導體層)20。於GaN層20上被形成作為障壁層之氮化鋁鎵層(AlGaN層、第2氮化物半導體層)30。進而於氮化鋁鎵層30上被形成作為帽蓋層之氮化銦鋁鎵層(InAlGaN層、第3氮化物半導體層)40。帽蓋層亦可為InAlN層。亦即,作為帽蓋層之第3氮化物半導體層40,為含有銦元素與鋁元素之氮化物半導體層。
於AlGaN層30上,源極電極50與汲極電極51隔著第1間隔而形成。此外,此源極電極50與汲極電極51之間,於InAlGaN層40上被形成閘極電極52。閘極電極52與源極電極50之間被形成第2間隔,此外,閘極電極52與汲極電極51之間被形成第3間隔。源極電極50的側面與InAlGaN層40相接,此外,汲極電極51的側面與InAlGaN層40相接。
進而,InAlGaN層40、源極電極50、汲極電極51、及閘極電極52之上,以覆蓋全體的方式形成保護層60。
基板10,使用矽(Si)、碳化矽(SiC)、藍寶石、氮化鎵(GaN)、鑽石等。但是於本實施型態,基板10的材料並不以這些為限。
GaN層20、AlGaN層30及InAlGaN層40為氮化物半導體。於本實施型態,這些層係組合鋁(Al)、鎵(Ga)、銦(In)等之III族元素與氮(N)之V族元素而成的III-V族半導體。
GaN與矽相比能帶間隙大,耐電壓性優異,所以用於可施加高電壓的大電力用功率元件。進而,GaN的飽和電子速度比矽還大,電子移動度與矽同等,所以GaN也作為微波用的高頻半導體裝置使用。
GaN層20(第1氮化物半導體層)與AlGaN層30(第2氮化物半導體層)係組合晶格間距離相近者而形成。
GaN層20與AlGaN層30分別的能帶間隙不相同。GaN層20與AlGaN層30接合時,接合面(異質界面)的附近被形成能態的量子阱,電子以高密度蓄積於量子阱,形成2次元電子氣體(2 Dimensional Electron Gas、2DEG)31。
InAlGaN層40,覆蓋AlGaN層30的上端,終結AlGaN層30表面的懸鍵(dangling bond)。亦即,InAlGaN層40,防止在AlGaN層30的表面形成阱能階(trap level),抑制半導體裝置100的特性劣化。
源極電極50與汲極電極51設於AlGaN層30之上,各電極50、51歐姆接觸於AlGaN層30。閘極電極52設於InAlGaN層40之上,閘極電極52肖特基 (Schottky)接觸於InAlGaN層40。形成歐姆電極之源極電極50與汲極電極51時,藉著蝕刻能帶間隙大的InAlGaN層40,於AlGaN層30上設源極電極50與汲極電極51,可以形成良好的歐姆接觸。
保護層60係以氮化膜等構成。氮化膜例如可以舉出氮化矽(SiN)等。保護層60,具有藉著覆蓋各電極而保護各電極不受水分等影響的任務。
使用圖2A~圖2D說明本實施型態之半導體裝置100的製造方法。在半導體裝置100,於基板10上藉由MOCVD(Metal Organic Chemical Vapor Deposition,金屬有機化學氣相沈積)法等使GaN結晶成長,於基板10上層積GaN層20。MOCVD法係把有機金屬與運載氣體供給至加熱的基板10上,藉由在基板10上使產生氣相的化學反應,於基板10上磊晶成長半導體層之方法。
於基板10上層積GaN層20後,藉由把有機金屬原料之三甲基鋁(TMA)、三甲基鎵(TMG)以及氨氣與運載氣體(氮或氫)一起供給,使其反應而在GaN層20上層積AlGaN層30。
於GaN層20上層積AlGaN層30後,同樣地藉由供給TMA、TMG、三甲基銦(TMI)與氨氣、運載氣體,使其反應而在AlGaN層30上層積InAlGaN層40(圖2A)。
但是,MOCVD法只是這些氮化物半導體層的層積方法之一例,於本實施型態,氮化物半導體層的層積方法不限於MOCVD法。
層積InAlGaN層40之後,藉由蝕刻處理除去一部分層積的InAlGaN層40(圖2B)。蝕刻方法例如使用感應耦合型反應性離子蝕刻(Inductivity Coupled Plasama ReactiveIon Etching:ICR-RIE)。在除去InAlGaN層40的部分於AlGaN層30上形成源極電極50與汲極電極51,此外,於InAlGaN層40上被形成閘極電極52。電極50、51、52,藉由熱處理(合金處理)供作成這些電極而設的金屬層而形成(圖2C)。
其後,於InAlGaN層40、各電極50、51、52之上以電漿化學氣相沉積(Plasma-enhanced Chemical Vapor Deposition)法等層積保護層60(圖2D)。但是,電漿CVD法只是這些保護層60的層積方法之一例,於本實施型態,保護層60的層積方法不限於電漿CVD法。
(第2實施形態)   圖3係第2實施型態之半導體裝置200之圖。
在第1實施型態,源極電極50及汲極電極51分別的側面與InAlGaN層40相接,但在第2實施形態,源極電極50與汲極電極51,不與InAlGaN層40接觸(非接觸)。總之,源極電極50與汲極電極51,係離開InAlGaN層40而配置的。
使用圖4A~圖4D說明第2實施型態之製造方法。首先,於基板10上層積GaN層20、AlGaN層30、InAlGaN層40。層積各層的步驟(圖4A)與第1實施型態相同,所以省略說明。
其次,為了形成源極電極50及汲極電極51藉由蝕刻處理把InAlGaN層除去一部分(圖4B)。
接著,形成源極電極50、汲極電極51、及閘極電極52。源極電極50與汲極電極51被形成於AlGaN層30上,閘極電極52被形成於InAlGaN層40上(圖4C)。源極電極50與汲極電極51以不與InAlGaN層40接觸的方式形成。
最後,以覆蓋InAlGaN40、AlGaN層30、源極電極50、汲極電極51、閘極電極52的方式,層積保護層60(圖4D)。又,蝕刻方法及層積保護層60的方法與第1實施型態相同。
在第2實施形態,源極電極50與汲極電極51亦可被形成在比對InAlGaN層40施以蝕刻的部分更窄的範圍,第2實施型態之半導體裝置200與第1實施型態之半導體裝置100相比為更容易製造的構造。亦即,第2實施形態與第1實施型態相比,具有提高製造性的優點。
又,在圖3及圖4C~圖4D,源極電極50與汲極電極51以不與InAlGaN層40相接的方式設置。但是,本實施型態之半導體裝置,不限定於這些完全不接觸的半導體裝置,也包含這些有一部分接觸的半導體裝置。例如,亦可以是源極電極50或汲極電極51的側面之至少一部分,與InAlGaN層40接觸的半導體裝置。
(第3實施形態)   圖5係第3實施型態之半導體裝置300之圖。
在第3實施型態,源極電極50與汲極電極51覆蓋InAlGaN層40的一部分。
使用圖6A~圖6D說明第3實施型態之製造方法。首先,於基板10上層積GaN層20、AlGaN層30、InAlGaN層40。層積各層的步驟(圖6A)與第1實施型態相同,所以省略說明。
其次,為了形成源極電極50及汲極電極51,僅形成源極電極50及汲極電極51的部分,藉由蝕刻處理把InAlGaN層40除去一部分(圖6B)。
接著,形成源極電極50、汲極電極51及閘極電極52。源極電極50與汲極電極51被形成於AlGaN層30上,閘極電極52被形成於InAlGaN層40上。此時,源極電極50與汲極電極51,以覆蓋InAlGaN層40的一部分的方式形成(圖6C)。
最後,以覆蓋InAlGaN40、源極電極50、汲極電極51、閘極電極52的方式,層積保護層60(圖6D)。
又,蝕刻處理的方法及層積保護層60的方法,與第1實施型態相同。
在第3實施形態,源極電極50與汲極電極51只要被形成在比對InAlGaN層40施以蝕刻的部分更寬的範圍即可,與第2實施型態同樣,第3實施型態之半導體裝置200與第1實施型態之半導體裝置相比為更容易製造的構造。此外,第3實施形態,源極電極50與汲極電極51與InAlGaN層40相接地形成,抑制電流崩潰的發生的緣故,可期待與第1實施型態同等的性能。
又,源極電極50與汲極電極51之分別的先端(覆蓋InAlGaN層40的部分)之形狀,沒有必要與圖5及圖6C~圖6D所示的形狀相同。
又,說明了數個實施型態,但對於InAlGaN層40之源極電極50與汲極電極51的位置或形狀並不以此為限,例如,源極電極50與汲極電極51為不同的實施型態亦可,也可以是一個電極為不同的實施型態的組合。
此外,說明了幾個實施形態,但這些實施形態只是提示作為例子之用,並未意圖限定發明的範圍。這些新穎的實施形態,能夠以其他種種形態來實施,在不逸脫發明要旨的範圍,可以進行種種的省略、置換、變更。這些實施形態或其變形,包含於發明的範圍或是要旨,而且包含於申請專利範圍所記載的發明以及其均等的範圍。
10‧‧‧基板
20‧‧‧GaN層(第1氮化物半導體層)
30‧‧‧AlGaN層(第2氮化物半導體層)
31‧‧‧2次元電子氣體(2 Dimensional Electron Gas、2DEG)
40‧‧‧InAlGaN層(第3氮化物半導體層)
50‧‧‧源極電極
51‧‧‧汲極電極
52‧‧‧閘極電極
100‧‧‧第1實施型態之半導體裝置
200‧‧‧第2實施型態之半導體裝置
300‧‧‧第3實施型態之半導體裝置
圖1係相關於第1實施型態的半導體裝置之剖面圖。   圖2A、圖2B、圖2C、圖2D係顯示相關於第1實施形態之半導體裝置之製造方法之圖。   圖3係例示相關於第2實施型態的半導體裝置之剖面圖。   圖4A、圖4B、圖4C、圖4D係顯示相關於第2實施形態之半導體裝置之製造方法之圖。   圖5係相關於第3實施型態的半導體裝置之剖面圖。   圖6A、圖6B、圖6C、圖6D係顯示相關於第3實施形態之半導體裝置之製造方法之圖。

Claims (10)

  1. 一種半導體裝置,其特徵為具備:   基板、   被形成於前述基板上的第1氮化物半導體層、   被形成於前述第1氮化物半導體層上,含有鎵元素的第2氮化物半導體層、   於前述第2氮化物半導體層上,與前述第2氮化物半導體層接觸而形成的源極電極及汲極電極,   被形成於前述第2氮化物半導體層之上,含有銦元素與鋁元素的第3氮化物半導體層、以及   於前述第3氮化物半導體層之上,被形成於前述源極電極及汲極電極之間的閘極電極。
  2. 如申請專利範圍第1項之半導體裝置,其中   前述源極電極或前述汲極電極之側面的至少一部分,與前述第3氮化物半導體層接觸。
  3. 如申請專利範圍第1項之半導體裝置,其中   前述源極電極或前述汲極電極之側面與前述第3氮化物半導體層為未接觸。
  4. 如申請專利範圍第1項之半導體裝置,其中   前述源極電極或前述汲極電極之一部分,覆蓋著前述第3氮化物半導體層之至少一部分。
  5. 如申請專利範圍第1項之半導體裝置,其中   前述源極電極與前述汲極電極之各個,與前述第3氮化物半導體層接觸。
  6. 如申請專利範圍第5項之半導體裝置,其中   前述源極電極與前述汲極電極之各個,其側面與前述第3氮化物半導體層接觸。
  7. 如申請專利範圍第1項之半導體裝置,其中   前述源極電極與前述汲極電極之各個,與前述第3氮化物半導體層為非接觸。
  8. 如申請專利範圍第5項之半導體裝置,其中   前述源極電極與前述汲極電極之各個,其一部分覆蓋著前述第3氮化物半導體層之至少一部分。
  9. 如申請專利範圍第1項之半導體裝置,其中   進而具備覆蓋前述第3氮化物半導體層、前述源極電極、前述汲極電極與前述閘極電極的保護層。
  10. 如申請專利範圍第1項之半導體裝置,其中   前述第1氮化物半導體層為通道層,前述第2氮化物半導體層為緩衝層,而且前述第3氮化物半導體層為帽蓋層。
TW107114999A 2017-12-26 2018-05-03 半導體裝置 TW201937730A (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2017-249374 2017-12-26
JP2017249374A JP2019114747A (ja) 2017-12-26 2017-12-26 半導体装置

Publications (1)

Publication Number Publication Date
TW201937730A true TW201937730A (zh) 2019-09-16

Family

ID=66951494

Family Applications (1)

Application Number Title Priority Date Filing Date
TW107114999A TW201937730A (zh) 2017-12-26 2018-05-03 半導體裝置

Country Status (3)

Country Link
US (1) US20190198655A1 (zh)
JP (1) JP2019114747A (zh)
TW (1) TW201937730A (zh)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11848362B2 (en) * 2019-04-18 2023-12-19 Intel Corporation III-N transistors with contacts of modified widths

Also Published As

Publication number Publication date
JP2019114747A (ja) 2019-07-11
US20190198655A1 (en) 2019-06-27

Similar Documents

Publication Publication Date Title
JP5114947B2 (ja) 窒化物半導体装置とその製造方法
US8207574B2 (en) Semiconductor device and method for manufacturing the same
US8633466B2 (en) Compound semiconductor device, method for producing the same, and power supply
JP6018360B2 (ja) 化合物半導体装置及びその製造方法
JP2007242853A (ja) 半導体基体及びこれを使用した半導体装置
JP2014207287A (ja) Hemtを備えた半導体装置
KR101878931B1 (ko) 반도체 소자 및 그 제조 방법
TW201737395A (zh) 半導體裝置及半導體裝置的製造方法
JP2010232610A (ja) 半導体装置及びその製造方法
US20180047822A1 (en) Semiconductor device
JP2018157141A (ja) 半導体装置及び半導体装置の製造方法
WO2013161478A1 (ja) 窒化物系半導体素子
JP2006210725A (ja) 半導体装置
TW201838178A (zh) 半導體元件
JP6905197B2 (ja) 化合物半導体装置及びその製造方法
JP5504660B2 (ja) 化合物半導体装置及びその製造方法
JP6530210B2 (ja) 半導体装置及びその製造方法
US10651305B2 (en) Compound semiconductor device with quantum well structure, power supply device, and high-frequency amplifier
TW201937730A (zh) 半導體裝置
JP6166508B2 (ja) 半導体装置及び半導体装置の製造方法
JP2016167522A (ja) 半導体装置
JP7099255B2 (ja) 化合物半導体装置、高周波増幅器及び電源装置
JP5648307B2 (ja) 縦型AlGaN/GaN−HEMTおよびその製造方法
JP5580012B2 (ja) ショットキーバリアダイオード及びその製造方法
US20150187925A1 (en) Enhancement-mode device