TW201933946A - LED driver and illumination system related to the same - Google Patents

Abstract

Herein disclosed is a driver for driving a light-emitting device. The driver includes a rectifier, a power factor corrector, and a current driver. The rectifier has at least one rectifying diode connected to an alternating-current input power source to generate a direct-current power source across a DC power line and a ground power line. The power factor corrector corrects the power factor of the current driver, and includes several diodes reversely connected in series between the DC and ground power lines. The current driver has at least one constant current source connected in series with the light emitting device between the DC and ground power lines. The constant current source is capable of providing a constant current to drive the light emitting device. The rectifying diode, the diodes, and the constant current source are commonly formed on one single semiconductor chip.

Description

發光二極體之驅動器與相關之照明系統Light-emitting diode driver and related lighting system

本發明係關於驅動發光二極體之驅動器與相關之照明系統，尤指具有良好功率因數以及架構簡單之驅動器與照明系統。The present invention relates to a driver for driving a light-emitting diode and related lighting systems, and more particularly to a driver and lighting system having a good power factor and a simple architecture.

近年來，因為良好的電光轉換效率以及較小的產品體積，發光二極體(light emitting diode)已經漸漸地取代陰極燈管或是鎢絲，作為背光或是照明系統的光源。只是，因為發光二極體的電壓電流特性（約3伏特，直流電驅動），一般市電的交流輸入電源並無法直接驅動發光二極體，而是需要一電源轉換器，將交流輸入電源轉換成適當的直流電源。In recent years, due to good electro-optical conversion efficiency and small product volume, light emitting diodes have gradually replaced cathode lamps or tungsten wires as backlights or light sources for illumination systems. However, because of the voltage and current characteristics of the LED (about 3 volts, DC drive), the general AC input power supply cannot directly drive the LED, but a power converter is needed to convert the AC input power into appropriate. DC power supply.

照明用電往往占用市電供電非常大的部分。因此針對照明所用的電源轉換器，法規上除了要求有非常低的轉換損失之外，還必須提供有良好的功率因數，功率因數介於0到1之間。一電子裝置的功率因數愈靠近1，表示該電子裝置越接近電阻式負載。Lighting power often takes up a very large part of the mains supply. Therefore, in addition to requiring very low conversion losses, the power converters used for illumination must provide a good power factor with a power factor between 0 and 1. The closer the power factor of an electronic device is to 1, the closer the electronic device is to the resistive load.

第1圖為習知的照明系統10，其中有橋式整流器12、功率因數校正器14、LED驅動電路16、以及一LED 18。功率因數校正器14可以是一個昇壓電路(booster)，LED驅動電路16可以是一降壓電路(buck converter)。但是，如昇壓電路或是降壓電路般的切換式電源轉換器，不但需要用到非常佔體積且昂貴的電感元件，整個系統架構也需要使用非常多的電子零件。因此，採用切換式電源轉換器的照明系統，其生產成本將會比較沒有市場競爭力。1 is a conventional illumination system 10 having a bridge rectifier 12, a power factor corrector 14, an LED drive circuit 16, and an LED 18. The power factor corrector 14 can be a booster and the LED driver circuit 16 can be a buck converter. However, switching power converters such as boost circuits or step-down circuits require not only very large and expensive inductor components, but also a large number of electronic components. Therefore, the lighting system using the switching power converter will have less production cost than the market.

實施例揭露一種驅動器，用以驅動一發光元件，包含有一整流電路、一功率因數校正器、以及一電流驅動電路。整流電路包含有至少一整流二極體，電連接至一交流輸入電源，用以產生一直流電源，跨於一直流電源線與一接地線之間。功率因數校正器，用以校正該驅動器之功率因數，包含有數個第一二極體，逆向串聯於該直流電源線與該接地線之間。電流驅動電路包含有至少一定電流源。該定電流源與該發光元件串接於直流電源線與接地線之間。該定電流源可提供一定電流，驅動該發光元件。整流二極體、等第一二極體、與定電流源，共同形成於一單一半導體晶片上。The embodiment discloses a driver for driving a light-emitting component, including a rectifier circuit, a power factor corrector, and a current drive circuit. The rectifier circuit includes at least one rectifying diode electrically connected to an AC input power source for generating a DC power source between the DC power line and a ground line. The power factor corrector is configured to correct the power factor of the driver, and includes a plurality of first diodes connected in reverse between the DC power line and the ground line. The current drive circuit includes at least a certain current source. The constant current source and the light emitting element are connected in series between the DC power line and the ground line. The constant current source can supply a certain current to drive the light emitting element. The rectifier diode, the first diode, and the constant current source are formed together on a single semiconductor wafer.

實施例揭露一種照明系統，包含有一單一半導體晶片、一第一電容、一第二電容、以及一發光二極體。單一半導體晶片封裝於一積體電路中。積體電路具有一第一驅動接腳以及一第二驅動接腳、二交流輸入接腳、一高電壓接腳、一低電壓接腳、第一以及第二功率因數校正接腳。第一電容電連接於高電壓接腳與第一功率因數校正接腳之間，第二電容電連接於低電壓接腳與第二功率因數校正接腳之間。發光二極體電連接於高電壓接腳與低電源接腳其中之一，與第一驅動接腳之間。交流輸入接腳用以電連接至一交流輸入電源。Embodiments disclose an illumination system including a single semiconductor wafer, a first capacitor, a second capacitor, and a light emitting diode. A single semiconductor chip is packaged in an integrated circuit. The integrated circuit has a first driving pin and a second driving pin, two AC input pins, a high voltage pin, a low voltage pin, and first and second power factor correction pins. The first capacitor is electrically connected between the high voltage pin and the first power factor correction pin, and the second capacitor is electrically connected between the low voltage pin and the second power factor correction pin. The light emitting diode is electrically connected between one of the high voltage pin and the low power pin, and between the first driving pin. The AC input pin is electrically connected to an AC input power source.

在本說明書中，有一些相同的符號，其表示具有相同或是類似之結構、功能、原理的元件，且為業界具有一般知識能力者可以依據本說明書之教導而推知。為說明書之簡潔度考量，相同之符號的元件將不再重述。In the present specification, there are some identical symbols, which indicate elements having the same or similar structures, functions, and principles, and those having general knowledge in the industry can be inferred from the teachings of the present specification. For the sake of simplicity of the description, elements of the same symbols will not be repeated.

在本發明的一實施例中，整個LED照明系統具有簡潔的電路設計，主要元件僅有封裝有一單一半導體晶片(chip)的一積體電路、兩個電容、以及當作光源的一LED。實施例中的LED照明系統可以不需要連接額外的電感元件。因此，LED照明系統之電路成本將會相當的低。此外，實施例中的LED照明系統也提供了相當優良的功率因數，可以符合大多數規範的要求。In an embodiment of the invention, the entire LED illumination system has a compact circuit design, the main components being only an integrated circuit packaged with a single semiconductor chip, two capacitors, and an LED as a light source. The LED lighting system of the embodiment may not require the connection of additional inductive components. Therefore, the circuit cost of the LED lighting system will be quite low. In addition, the LED lighting system of the embodiment also provides a fairly good power factor that meets the requirements of most specifications.

第2圖顯示一依據本發明一實施例的LED驅動器60，其可用來驅動LED 18。LED 18可以是一高壓LED，由許多微型LED（micro LED）串連在一起所構成。舉例來說，在一個實施例中，每個微型LED的正向電壓約3.4伏特，而LED 18由10多個微LED串聯而成，其等效正向電壓（forward voltage）約50V。2 shows an LED driver 60 that can be used to drive LEDs 18 in accordance with an embodiment of the present invention. LED 18 can be a high voltage LED that is constructed by a series of micro LEDs connected in series. For example, in one embodiment, each micro LED has a forward voltage of about 3.4 volts, and LED 18 is made up of more than 10 micro LEDs in series with an equivalent forward voltage of about 50 volts.

LED驅動器60大致有三級。連接到交流輸入電源V_AC-IN 的第一級是橋式整流器62。第二級是填谷電路(valley-fill circuit)64，做為一功率因數校正器，可以改善整個LED驅動器60的功率因數。第三級有兩個高電子遷移率場效電晶體(high electron mobility transistor，HEMT)T1與T2，作為電流驅動電路66，來提供一定電流，驅動LED 18。The LED driver 60 has roughly three stages. The first stage connected to the AC input power source V _AC-IN is a bridge rectifier 62. The second stage is a valley-fill circuit 64, which acts as a power factor corrector to improve the power factor of the entire LED driver 60. The third stage has two high electron mobility transistors (HEMT) T1 and T2 as current drive circuit 66 to provide a certain current to drive the LED 18.

橋式整流器62包含有四個整流二極體DB1-DB4。橋式整流器62將交流輸入電源V_AC-IN 整流，用以產生直流電源V_DC-IN ，跨於直流電源線VDD與接地線GND之間。舉例來說，交流輸入電源V_AC-IN 可以是一般市電所提供的110VAC或是220VAC。The bridge rectifier 62 includes four rectifying diodes DB1-DB4. The bridge rectifier 62 rectifies the AC input power source V _AC-IN to generate a DC power source V _DC-IN across the DC power line VDD and the ground line GND. For example, the AC input power source V _AC-IN can be 110 VAC or 220 VAC provided by a general utility.

填谷電路64電連接於直流電源線VDD與接地線GND之間，包含有三個二極體DVF1-DVF3與電容C1、C2。二極體DVF1-DVF3逆向串接於直流電源線VDD與接地線GND之間。在此實施例中，電容C1與C2的電容值大約相等，但本發明不限於此。從電路理論可推知，電容C1與C2的電容電壓V_C1 與V_C2 大約可以被充電到直流電源V_DC-IN 之電壓峰值V_PEAK 的一半(0.5*V_PEAK )。而當交流輸入電源V_AC-IN 的電壓絕對值低於0.5*V_PEAK 時，電容C1與C2可以對直流電源線VDD與接地線GND放電。只要電容C1與C2夠大，填谷電路64可以使直流電源V_DC-IN 的最小值電壓大約等於0.5V_PEAK ，提供足夠的電壓使LED 18持續發光。The valley filling circuit 64 is electrically connected between the DC power supply line VDD and the ground line GND, and includes three diodes DVF1-DVF3 and capacitors C1 and C2. The diode DVF1-DVF3 is reversely connected in series between the DC power supply line VDD and the ground line GND. In this embodiment, the capacitance values of the capacitors C1 and C2 are approximately equal, but the invention is not limited thereto. It can be inferred from the circuit theory that the capacitance voltages V _C1 and V C2 of the capacitors _C1 and _C2 can be charged to approximately half of the voltage peak V _PEAK of the DC power source V _DC-IN (0.5*V _PEAK ). When the absolute value of the voltage of the AC input power source V _AC-IN is lower than 0.5*V _PEAK , the capacitors C1 and C2 can discharge the DC power line VDD and the ground line GND. As long as the capacitors C1 and C2 are large enough, the valley filling circuit 64 can make the minimum voltage of the DC power source V _DC-IN approximately equal to 0.5 V _PEAK , providing sufficient voltage for the LED 18 to continue to emit light.

HEMT T1與T2都是耗盡模式(depletion mode)電晶體，意味著他們的臨界電壓(threshold voltage，V_TH )都是負值。每個HEMT T1與T2的閘極(gate)與源極(source)相互短路。以HEMT T1為例，當其汲源電壓(drain-to-source Voltage，V_DS )足夠大時，汲源電流(drain-to-source current，I_DS )，也就是從汲極流到源極的電流，將大約是一常數，幾乎與V_DS 無關。所以，不論HEMT T1或T2，都可以大約當作一定電流源，提供穩定的一定電流來驅動LED 18，使LED 18的發光強度維持一定，不會有閃爍問題。在第2圖中，HEMT T1驅動LED 18，兩者一起作為負載(load)，串接在直流電源線VDD與接地線GND之間。第2圖以虛線67連接了HEMT T2與LED 18，表示HEMT T2可以選擇性的來跟HEMT T1一同驅動LED 18，稍後將細部說明。Both HEMT T1 and T2 are depletion mode transistors, meaning that their threshold voltage (V _TH ) is negative. The gate and source of each of the HEMTs T1 and T2 are shorted to each other. Taking HEMT T1 as an example, when the drain-to-source voltage (V _DS ) is large enough, the drain-to-source current (I _DS ), that is, from the drain to the source The current will be approximately a constant, almost independent of V _DS . Therefore, regardless of HEMT T1 or T2, it can be regarded as a certain current source, providing a stable constant current to drive the LED 18, so that the luminous intensity of the LED 18 is maintained constant, and there is no flicker problem. In Fig. 2, HEMT T1 drives LEDs 18, which together act as a load, connected in series between DC power supply line VDD and ground line GND. Figure 2 connects HEMT T2 and LED 18 with dashed line 67, indicating that HEMT T2 can selectively drive LED 18 along with HEMT T1, as will be described in more detail later.

第3圖顯示交流輸入電源V_AC-IN 的電壓波形72、沒有填谷電路64時的直流電源V_DC-IN 之電壓波形74、以及有填谷電路64時的直流電源V_DC-IN 的電壓波形76。舉例來說，交流輸入電源V_AC-IN 是220VAC，為一正弦波，如同第3圖所示。電壓波形74表示為沒有填谷電路64時的虛擬結果。如果沒有填谷電路64，橋式整流器62將提供簡單的全波整流，所以會將電壓波形72中電壓值為負的部分，轉變成正，如同電壓波形74所示。填谷電路64會將電壓波形74中之波谷填入，或是使電壓波形74中之波谷不再那麼的深，如同電壓波形76所示。為了敘述上的方便，以下說明有時將採用電壓波形74之虛擬結果來講解事件發生的時間點。舉例來說，電壓波形74到達波峰時，代表的就是電壓波形72(交流輸入電源V_AC-IN )到達波峰或是波谷時。Figure 3 shows the voltage waveform 72 of the AC input power source V _AC-IN , the voltage waveform 74 of the DC power source V _DC-IN when there is no valley filling circuit 64, and the voltage of the DC power source V _DC-IN when the valley filling circuit 64 is present. Waveform 76. For example, the AC input power source V _AC-IN is 220VAC, which is a sine wave, as shown in Figure 3. Voltage waveform 74 is shown as a virtual result when there is no valley fill circuit 64. If there is no valley fill circuit 64, the bridge rectifier 62 will provide simple full-wave rectification, so the portion of the voltage waveform 72 where the voltage value is negative is converted to positive as shown by voltage waveform 74. The valley fill circuit 64 fills the valleys in the voltage waveform 74 or makes the valleys in the voltage waveform 74 less deep, as shown by the voltage waveform 76. For convenience of description, the following description will sometimes use the virtual result of the voltage waveform 74 to explain the point in time at which the event occurred. For example, when the voltage waveform 74 reaches the peak, it represents the voltage waveform 72 (the AC input power source V _AC-IN ) reaches the peak or valley.

在時段TP1中當電壓波形74大於0.5V_PEAK ，電壓波形74將隨時間上升直至V_PEAK 。LED 18發光的電能將直接來自交流輸入電源V_AC-IN ，所以電壓波形76等於電壓波形74。此時，一旦直流電源V_DC-IN 的電壓大於電容電壓V_C1 與V_C2 兩者的和，電容C1與C2將會被交流輸入電源V_AC-IN 所充電。當電壓波形74達峰值V_PEAK 時，電容電壓V_C1 與V_C2 大約都會是0.5V_PEAK 。During voltage period TP1 when voltage waveform 74 is greater than 0.5V _PEAK , voltage waveform 74 will rise over time until _VPEAK . The LED 18 illuminating power will come directly from the AC input power source V _AC-IN , so the voltage waveform 76 is equal to the voltage waveform 74 . At this time, once the voltage of the DC power source V _DC-IN is greater than the sum of the capacitor voltages V _C1 and V _C2 , the capacitors C1 and C2 will be charged by the AC input power source V _AC-IN . When the voltage waveform 74 reaches the peak value V _PEAK , the capacitor voltages V _C1 and V _C2 will be approximately 0.5V _PEAK .

時段TP2從電壓波形74達峰值V_PEAK 後開始。在時段TP2中，電壓波形74隨時間開始下降。LED 18發光的電能將直接來自交流輸入電源V_AC-IN ，所以電壓波形76等於電壓波形74。因為電容C1與C2沒有充放電，電容電壓V_C1 與V_C2 都將維持在0.5V_PEAK 。Period TP2 begins after voltage waveform 74 reaches peak V _PEAK . During time period TP2, voltage waveform 74 begins to decrease over time. The LED 18 illuminating power will come directly from the AC input power source V _AC-IN , so the voltage waveform 76 is equal to the voltage waveform 74 . Since the capacitors C1 and C2 are not charged or discharged, the capacitor voltages V _C1 and V _C2 will be maintained at 0.5V _PEAK .

時段TP3從電壓波形74低於0.5V_PEAK 後開始，大約就是電壓波形74之波谷出現的時間。在時段TP3內，電容C1會透過二極體DVF3放電，來供電給HEMT T1與LED 18。類似的，電容C2會透過二極體DVF1放電，一樣供電給HEMT T1與LED 18。電容電壓V_C1 與V_C2 將隨著時間降低，降低的速度視電容C1與C2的電容值而定。時段TP3終止於電壓波形74從波谷反彈後而高於電容電壓V_C1 或V_C2 時。之後由另一個時段TP1接續。如同第3圖之電壓波形76所示，只要電容C1與C2夠大，直流電源V_DC-IN 就可能提供足夠的電壓使LED 18持續發光。Period TP3 begins after voltage waveform 74 is below 0.5V _PEAK , approximately the time at which the valley of voltage waveform 74 occurs. During the period TP3, the capacitor C1 is discharged through the diode DVF3 to supply power to the HEMT T1 and the LED 18. Similarly, capacitor C2 will discharge through diode DVF1 and supply power to HEMT T1 and LED 18. The capacitor voltages V _C1 and V _C2 will decrease over time, depending on the capacitance values of capacitors C1 and C2. The time period TP3 ends when the voltage waveform 74 bounces off the valley and is higher than the capacitance voltage V _C1 or V _C2 . It is then continued by another time period TP1. As shown by the voltage waveform 76 of Figure 3, as long as the capacitances C1 and C2 are large enough, the DC power supply V _DC-IN may provide sufficient voltage for the LED 18 to continue to illuminate.

只要電容C1與C2夠大，填谷電路64所達到的功率因數，可以符合大多數國家的功率因數要求。As long as the capacitors C1 and C2 are large enough, the power factor achieved by the valley fill circuit 64 can meet the power factor requirements of most countries.

在一實施例中，第2圖中的整流二極體DB1-DB4、二極體DVF1-DVF3、以及HEMT T1與T2，都共同形成於一單一半導體晶片上。第4A圖顯示一半導體晶片80上之一金屬層104之圖案，並標示第2圖中的二極體與HEMT在半導體晶片80上的相對位置。半導體晶片80可以是一以氮化鎵為導通通道材料(GaN-based)的單晶微波積體電路(monolithic microwave integrated circuit， MMIC)。在第4A圖中，每個二極體的元件結構大約都相類似，而HEMT T1與T2的元件結構也相類似。第5圖顯示了，第4A圖中之HEMT T1沿著線ST-ST的晶片剖面圖；第6圖顯示了，第4A圖中之二極體DVF3沿著線SD-SD的晶片剖面圖。圖中其他的二極體與HEMT 之元件結構可以類推而得知。In one embodiment, the rectifying diodes DB1-DB4, diodes DVF1-DVF3, and HEMTs T1 and T2 in FIG. 2 are all formed together on a single semiconductor wafer. 4A shows a pattern of a metal layer 104 on a semiconductor wafer 80 and indicates the relative position of the diode in FIG. 2 to the HEMT on the semiconductor wafer 80. The semiconductor wafer 80 may be a monolithic microwave integrated circuit (MMIC) using gallium nitride as a GaN-based material. In Figure 4A, the element structure of each diode is approximately the same, and the element structures of HEMT T1 and T2 are similar. Fig. 5 is a cross-sectional view of the wafer of the HEMT T1 along line ST-ST in Fig. 4A; and Fig. 6 is a cross-sectional view of the wafer along line SD-SD of the diode DVF3 in Fig. 4A. The other diodes in the figure and the component structure of the HEMT can be analogized.

第5圖的例子中，矽基底92上之緩衝層94可以是摻雜有碳(C-doped)的本質(intrinsic)GaN。通道層96可以是本質(intrinsic)GaN，其上形成有一高價帶間隙(high-bandgap)層98，其材料可為本質之AlGaN。蓋層100可以是本質GaN。蓋層100、高價帶間隙層98與通道層96被圖案化而成為一平台區95(mesa)。二維電子雲（2D-electron gas）可以形成於通道層96內鄰接於高價帶間隙層98的量子井(quantum well)，作為導電通道。圖案化(patterned)的金屬層102的材料可以是鈦、鋁或是這兩種材料的疊層。在第5圖中，金屬層102在平台區95的上方形成兩個金屬片(metal strips)102a、102b，分別跟平台區95形成兩個歐姆接觸(ohmic contact)，使得金屬片102a、102b分別作為HEMT T1的源極與汲極。金屬層104的材料可以是鈦、金或是這兩種材料的疊層。舉例來說，由下而上，金屬層104有一鎳層(Ni)、一銅層(Cu)以及一鉑層(Pt)，其中鉑層可以增加稍後形成之護層105彼此之間的粘著度(adhesion)，防止在焊墊製程時產生剝離的問題。在其他實施例中，金屬層104也可以是鎳層(Ni)、金層(Au)以及鉑層(Pt)的疊層，或者鎳層(Ni)、金層(Au)以及鈦層(Ti)的疊層。在第5圖中，圖案化之金屬層104形成了金屬片104a、104b與104c。金屬片104b接觸了平台區95的中央上方，形成一蕭特基接觸(schottky contact)，作為HEMT T1的閘極。第5圖中的104a與104c分別接觸了102a、102b，提供HEMT T1的源極與汲極到其他電子元件的電性連接。請同時參考第5圖與第4A圖，可以發現HEMT T1的閘極(金屬片104b)，透過金屬層104，短路到金屬片104a，也短路到HEMT T1的源極。第5圖的右部分則顯示了HEMT T1的等效電路圖。金屬層104上方有護層105，其材料可以是氮氧化矽(silicon oxinitride，SiON)。護層105被圖案化，用來形成封裝時所需要的焊墊(bonding pad)。舉例來說，第5圖中，左半邊護層105沒有蓋住的部分，可以焊接至低電壓接腳VSS(稍後將解釋)之焊線(bonding wire)；而右半邊護層105沒有蓋住的部分，可以焊接至驅動接腳D1 (稍後將解釋)之焊線。In the example of FIG. 5, the buffer layer 94 on the germanium substrate 92 may be intrinsic GaN doped with carbon (C-doped). Channel layer 96 can be intrinsic GaN having a high-band gap layer 98 formed thereon, the material of which can be essentially AlGaN. The cap layer 100 can be intrinsic GaN. The cap layer 100, the high-value band gap layer 98 and the channel layer 96 are patterned to form a land area 95 (mesa). A two-dimensional electron cloud (2D-electron gas) may be formed in the quantum layer of the channel layer 96 adjacent to the high-value band gap layer 98 as a conductive channel. The material of the patterned metal layer 102 may be titanium, aluminum or a laminate of the two materials. In FIG. 5, the metal layer 102 forms two metal strips 102a, 102b above the land area 95, forming two ohmic contacts with the land area 95, respectively, such that the metal sheets 102a, 102b are respectively As the source and drain of HEMT T1. The material of the metal layer 104 may be titanium, gold or a laminate of the two materials. For example, from bottom to top, the metal layer 104 has a nickel layer (Ni), a copper layer (Cu), and a platinum layer (Pt), wherein the platinum layer can increase the adhesion between the protective layers 105 formed later. Adhesion prevents the problem of peeling during the soldering process. In other embodiments, the metal layer 104 may also be a stack of a nickel layer (Ni), a gold layer (Au), and a platinum layer (Pt), or a nickel layer (Ni), a gold layer (Au), and a titanium layer (Ti). The stack of ). In Fig. 5, the patterned metal layer 104 forms metal sheets 104a, 104b and 104c. The metal piece 104b contacts the center of the land area 95 to form a Schottky contact as the gate of the HEMT T1. 104a and 104c in Fig. 5 respectively contact 102a, 102b, and provide electrical connection of the source and the drain of the HEMT T1 to other electronic components. Referring to FIG. 5 and FIG. 4A simultaneously, it can be found that the gate of the HEMT T1 (metal piece 104b) is short-circuited to the metal piece 104a through the metal layer 104, and is also short-circuited to the source of the HEMT T1. The right part of Figure 5 shows the equivalent circuit diagram of HEMT T1. Above the metal layer 104 is a protective layer 105, which may be made of silicon oxinitride (SiON). The cover layer 105 is patterned to form the bonding pads required for packaging. For example, in FIG. 5, the portion of the left half of the sheath 105 that is not covered can be soldered to the bonding wire of the low voltage pin VSS (to be explained later); and the right half of the sheath 105 is not covered. The live part can be soldered to the wire of drive pin D1 (explained later).

為簡潔之緣故，第6圖與第5圖相同或類似之部分不再累述。第6圖中，金屬層102在平台區95的上方形成兩個金屬片102c、102d，圖案化之金屬層104則形成了金屬片104d、104e與104f。與第5圖相類似的，金屬片104e可作為一HEMT的閘極。雖然金屬片102d可以作為一HEMT的一源極，但金屬片102d上沒有接觸到金屬層104。在另一實施例中，金屬片102d可以不需要。金屬片104f接觸平台區95的一部分上表面與一側壁，形成另一個蕭特基接觸，可以作為一蕭特基二極體，其陰極等效上短路到第6圖之HEMT的源極。請同時參考第6圖與第4A圖。金屬片104e，透過金屬層104，短路到金屬片104f，其為蕭特基二極體之陽極。第6圖之右部分顯示了左半部之等效電路連接圖，電路行為上等效為一個二極體。第6圖之右部分同時顯示一特別之二極體符號120，來代表第6圖中的等效電路。二極體符號120也使用於第2圖中，表示整流二極體DB1-DB4與二極體DVF1-DVF3，每個都是由一HEMT與一蕭特基二極體所複合而成的二極體。For the sake of brevity, the same or similar parts of Fig. 6 and Fig. 5 will not be described again. In Fig. 6, the metal layer 102 forms two metal sheets 102c, 102d above the land area 95, and the patterned metal layer 104 forms metal sheets 104d, 104e and 104f. Similar to Fig. 5, the metal piece 104e can function as a gate of a HEMT. Although the metal piece 102d can serve as a source of a HEMT, the metal piece 102d does not contact the metal layer 104. In another embodiment, the metal sheet 102d may not be needed. The metal piece 104f contacts a portion of the upper surface of the land region 95 and a side wall to form another Schottky contact, which can serve as a Schottky diode whose cathode is equivalently shorted to the source of the HEMT of FIG. Please also refer to Figure 6 and Figure 4A. The metal piece 104e, through the metal layer 104, is short-circuited to the metal piece 104f, which is the anode of the Schottky diode. The right part of Figure 6 shows the equivalent circuit connection diagram for the left half, which is equivalent to a diode. The right part of Fig. 6 also shows a special diode symbol 120 to represent the equivalent circuit in Fig. 6. The diode symbol 120 is also used in Fig. 2 to show the rectifying diodes DB1-DB4 and the diodes DVF1-DVF3, each of which is a composite of a HEMT and a Schottky diode. Polar body.

第4B圖顯示將半導體晶片80封裝後的一積體電路130，其只有8個接腳(pin)，分別是：高電壓接腳VCC、功率因數校正接腳PF1與PF2、低電壓接腳VSS、交流輸入接腳AC+與AC-、驅動接腳D1與D2。請參閱第4A圖，其中也顯示了每個接腳，透過焊線(bonding wire)，電性短路到由金屬層104圖案化後所形成的金屬片，而這些金屬片也提供了半導體晶片80中電子元件相對應的輸入或輸出端點相互連接。舉例來說，驅動接腳D1電連接到HEMT T1的汲極，功率因數校正接腳PF1電連接到二極體DVF3的陰極。FIG. 4B shows an integrated circuit 130 encapsulating the semiconductor wafer 80, which has only eight pins, namely: a high voltage pin VCC, power factor correction pins PF1 and PF2, and a low voltage pin VSS. , AC input pin AC+ and AC-, drive pins D1 and D2. Referring to FIG. 4A, each of the pins is also shown, through a bonding wire, electrically shorted to a metal sheet formed by patterning of the metal layer 104, and the metal sheets also provide the semiconductor wafer 80. The corresponding input or output terminals of the electronic components are connected to each other. For example, the drive pin D1 is electrically connected to the drain of the HEMT T1, and the power factor correction pin PF1 is electrically connected to the cathode of the diode DVF3.

第7圖顯示依據本發明所實施的一照明系統200。積體電路130固定在印刷電路板202上。透過印刷電路202上的金屬線，電容C1電連接於高電壓接腳VCC與功率因數校正接腳PF1之間，電容C2電連接於低電壓接腳VSS與功率因數校正接腳PF2之間，LED 18電連接於高電壓接腳VCC與驅動接腳D1之間，交流輸入接腳AC+與AC-電連接到交流輸入電源V_AC-IN 。透過先前的解說可以了解，第7圖之照明系統200很簡潔的，僅僅用了4個電子零件(兩個電容C1與C2、積體電路130與LED 18)，就實現了第2圖中的LED驅動器60。沒有昂貴體積龐大的電感元件，照明系統200成本將可以非常的低，且整個產品體積也可以小而精簡。Figure 7 shows an illumination system 200 implemented in accordance with the present invention. The integrated circuit 130 is fixed to the printed circuit board 202. The capacitor C1 is electrically connected between the high voltage pin VCC and the power factor correction pin PF1 through the metal line on the printed circuit 202. The capacitor C2 is electrically connected between the low voltage pin VSS and the power factor correction pin PF2. 18 is electrically connected between the high voltage pin VCC and the driving pin D1, and the AC input pin AC+ and AC- are electrically connected to the AC input power source V _AC-IN . It can be understood from the previous explanation that the illumination system 200 of Fig. 7 is very simple, and only four electronic components (two capacitors C1 and C2, integrated circuit 130 and LED 18) are used, and the image in Fig. 2 is realized. LED driver 60. Without expensive and bulky inductive components, the cost of the lighting system 200 can be very low, and the overall product size can be small and streamlined.

第7圖中，積體電路130的驅動接腳D2(電連接到HEMT T2的汲極)，可以視交流輸入電源V_AC-IN 的交流電壓不同，而決定是否電連接至LED 18。換言之，積體電路130可以選擇性地用單單一個HEMT(T1)，或是用兩個HEMT(T1與T2)並聯來驅動LED 18發光。舉例來說，假定積體電路130中的HEMT T1與T2各別可提供大約一樣的1u單位定電流。當第7圖的照明系統200運用於交流輸入電源V_AC-IN 為110VAC時，可以選用正向電壓(forward voltage)為50V的LED作為LED 18，並且連接驅動接腳D1以及D2一起到LED 18，LED 18此時所消耗的功率約2u*50(=100u)。而當第7圖的照明系統200運用於交流輸入電源V_AC-IN 為220VAC時，可以選用正向電壓為100V的LED作為LED 18，並且單單連接驅動接腳D1到LED 18，並保持驅動接腳D2浮動空接，LED 18此時所消耗的功率約1u*100(=100u)。如此，儘管交流輸入電源V_AC-IN 的交流電壓不一樣，只要選用正向電壓不同的LED，LED 18消耗的功率可以大約相同(都是100u)，那照明系統200所產生的照明亮度就大約也會是相同。換言之，積體電路130不只是適用於220VAC的交流輸入電源，也可適用於110VAC的交流輸入電源。這對於照明系統200的製造商而言是非常方便的，可以節省照明系統200的零件庫存管理成本。In Fig. 7, the drive pin D2 of the integrated circuit 130 (electrically connected to the drain of the HEMT T2) can be electrically connected to the LED 18 depending on the AC voltage of the AC input power source V _AC-IN . In other words, the integrated circuit 130 can selectively drive the LED 18 to emit light by using a single HEMT (T1) or in parallel with two HEMTs (T1 and T2). For example, assume that HEMTs T1 and T2 in integrated circuit 130 can each provide approximately the same 1u unit constant current. When the illumination system 200 of FIG. 7 is applied to the AC input power source V _AC-IN of 110 _VAC , an LED having a forward voltage of 50 V can be selected as the LED 18, and the drive pins D1 and D2 are connected together to the LED 18 The power consumed by the LED 18 at this time is about 2u*50 (=100u). When the illumination system 200 of FIG. 7 is applied to the AC input power source V _AC-IN of 220 VAC, an LED with a forward voltage of 100 V can be selected as the LED 18, and the drive pins D1 to LED 18 are simply connected, and the drive is connected. The foot D2 floats and is connected, and the power consumed by the LED 18 at this time is about 1u*100 (=100u). Thus, although the AC voltage of the AC input power source V _AC-IN is different, as long as the LEDs with different forward voltages are selected, the power consumed by the LEDs 18 can be about the same (both 100u), and the illumination brightness produced by the illumination system 200 is approximately It will be the same. In other words, the integrated circuit 130 is not only suitable for an AC input power source of 220 VAC, but also for an AC input power source of 110 VAC. This is very convenient for the manufacturer of the lighting system 200, which can save on the parts inventory management cost of the lighting system 200.

在第2圖中，電流驅動電路66連接於LED 18與接地線GND之間，但本發明並不限於此。第8圖顯示另一依據本發明所實施的LED驅動器300，用來驅動LED 18。在第8圖中，電流驅動電路302具有HEMT T3與T4， HEMT T3與T4的汲極一起電連接到直流電源線VDD，LED 18電連接於接地線GND與電流驅動電路302之間。第9A圖顯示一半導體晶片310上之金屬層140的圖案，並標示第8圖中的二極體與HEMT的相對位置。第5圖也可代表第9A圖中之HEMT T3沿著線ST-ST的晶片剖面圖；第6圖也可代表第9A圖中之二極體DVF3沿著線SD-SD的晶片剖面圖。第9B圖顯示將半導體晶片310封裝後的一積體電路320，其只有8個接腳(pin)，分別是：高電壓接腳VCC、功率因數校正接腳PF1與PF2、低電壓接腳VSS、交流輸入接腳AC+與AC-、驅動接腳S1與S2。第10圖顯示依據本發明所實施的另一照明系統330，其實現了第8圖中的LED驅動器300。第8、9A、9B與10圖，可以參照先前第2、4A、4B與7圖以及相關之解說，而得知其原理、操作、以及優點，為簡潔故，不再累述。In Fig. 2, the current drive circuit 66 is connected between the LED 18 and the ground line GND, but the present invention is not limited thereto. Figure 8 shows another LED driver 300 implemented in accordance with the present invention for driving LEDs 18. In FIG. 8, the current driving circuit 302 has HEMTs T3 and T4, and the HEMTs T3 and T4 are electrically connected to the DC power supply line VDD, and the LEDs 18 are electrically connected between the ground line GND and the current driving circuit 302. Figure 9A shows the pattern of the metal layer 140 on a semiconductor wafer 310 and indicates the relative position of the diode in Figure 8 to the HEMT. Figure 5 can also represent a wafer cross-sectional view of HEMT T3 along line ST-ST in Figure 9A; Figure 6 can also represent a cross-sectional view of the wafer along line SD-SD of diode DVF3 in Figure 9A. FIG. 9B shows an integrated circuit 320 encapsulating the semiconductor wafer 310, which has only eight pins, namely: a high voltage pin VCC, power factor correction pins PF1 and PF2, and a low voltage pin VSS. , AC input pin AC+ and AC-, drive pins S1 and S2. Figure 10 shows another illumination system 330 implemented in accordance with the present invention that implements the LED driver 300 of Figure 8. Figures 8, 9A, 9B, and 10, which can be referred to the previous Figures 2, 4A, 4B, and 7 and related explanations, and the principles, operations, and advantages thereof are known, and are not exhaustive for the sake of brevity.

如同第11圖之實施例所示，額外的一穩壓電容19可以與LED 18並聯。穩壓電容19可以降低LED 18的跨壓V_LED 之變化，甚至增加LED 18在交流輸入電源V_AC-IN 之一週期時間內的工作週期(duty cycle)，減少LED 18閃爍(flickering)的可能性。As shown in the embodiment of Fig. 11, an additional voltage stabilizing capacitor 19 can be connected in parallel with the LED 18. The stabilizing capacitor 19 can reduce the variation of the LED 18 across the voltage V _LED , and even increase the duty cycle of the LED 18 in one cycle of the AC input power source V _AC-IN , reducing the possibility of LED 18 flickering. Sex.

第4A圖中的圖案僅僅是作為一個例子，本發明並不限於此。第12圖顯示另一半導體晶片上之一金屬層104之圖案。第12圖大致類似於第4A圖，為簡潔之緣故，彼此相同或類似之部分不再累述。在第4A圖中，位於每個二極體中間位置的一閘極，都只有透過一個金屬層104圖案化後的一上臂ARM1連接到其陽極(譬如第6圖中的金屬片104f)；位於每個HEMT中間位置的一閘極，也都是透過一個金屬層104圖案化後的一上臂ARM2連接到其源極(譬如第5圖中的金屬片104a)；。然而，在第12圖中，如同例示之閘區域GG，每個二極體中間位置的閘極，透過金屬層104圖案化後的上下兩臂ART與ARB連接到其陽極；而位於每個HEMT中間位置的一閘極，也都是透過金屬層104圖案化後的上下兩臂連接到其源極。與第4A圖之設計相較之下，第12圖中的二極體具有較高的崩潰電壓耐受能力。The pattern in Fig. 4A is merely an example, and the present invention is not limited thereto. Figure 12 shows a pattern of one of the metal layers 104 on another semiconductor wafer. Figure 12 is generally similar to Figure 4A, and for the sake of brevity, portions that are identical or similar to each other are not described again. In Fig. 4A, a gate located at the middle of each of the diodes is connected to its anode only by an upper arm ARM1 patterned through a metal layer 104 (such as the metal piece 104f in Fig. 6); A gate in the middle of each HEMT is also connected to its source (such as the metal piece 104a in FIG. 5) by an upper arm ARM2 patterned by a metal layer 104. However, in Fig. 12, as illustrated in the gate region GG, the gate at the intermediate position of each of the diodes, the upper and lower arms ART and ARB patterned through the metal layer 104 are connected to the anode thereof; and at each HEMT A gate in the middle position is also connected to the source by the upper and lower arms patterned by the metal layer 104. In contrast to the design of Figure 4A, the diode of Figure 12 has a higher breakdown voltage withstand capability.

第5圖與第6圖中的剖面圖也並非用來限制本發明的權利範圍。舉例來說，如第13圖所示，第4A圖中之二極體DVF3沿著線SD-SD依據另一種實施例之晶片剖面圖。第13圖與第6圖，為簡潔之緣故，彼此相同或類似之部分不再累述。與第6圖不同的，第13圖中的金屬片104e與蓋層100之間夾有一絕緣層103，其材料譬如說是氧化矽。絕緣層103的存在也可以增強二極體的崩潰電壓耐受能力。The cross-sectional views in Figures 5 and 6 are also not intended to limit the scope of the invention. For example, as shown in Fig. 13, the diode DVF3 in Fig. 4A is a cross-sectional view of the wafer according to another embodiment along line SD-SD. Figures 13 and 6, for the sake of brevity, portions that are identical or similar to each other are not described again. Different from Fig. 6, an insulating layer 103 is sandwiched between the metal piece 104e and the cap layer 100 in Fig. 13, and the material thereof is, for example, yttrium oxide. The presence of the insulating layer 103 can also enhance the breakdown voltage withstand capability of the diode.

第14圖顯示用來製作第13圖中之二極體的流程圖。步驟140先形成平台區。舉例來說，先在緩衝層94上分別形成通道層96、高價帶間隙層98、與蓋層100，然後以感應式耦合電漿蝕刻等方式圖案化這三層而完成平台區95。步驟142形成歐姆接觸。舉例來說，分別沉積鈦/鋁/鈦/金來做為金屬層102，之後對金屬層102圖案化，形成金屬片102a、102b等。步驟144形成絕緣層103。舉例來說，先沉積一二氧化矽層，然後圖案化，剩下的二氧化矽層便成為絕緣層103。步驟146形成蕭特基接觸與圖案化。舉例來說，步驟146先依序沉積鎳/金/鉑作為金屬層104，然後對金屬層104圖案化形成金屬片104a、104b、104c等。金屬層104與金屬層102之間為歐姆接觸，但金屬層104與平台區95則為蕭特基接觸。步驟148形成護層105，並對之圖案化，以形成焊墊開孔。當然，第14圖的流程圖也適用於製作第12圖中的HEMT。而藉由適當的調整，第14圖中的流程圖，也可以用來製作如第4A圖中的二極體與HEMT，例如省略步驟144，或者加入其他製程。Figure 14 shows a flow chart for making the diode of Figure 13. Step 140 first forms a platform area. For example, the channel layer 96, the high-cost band gap layer 98, and the cap layer 100 are respectively formed on the buffer layer 94, and then the three layers are patterned by inductively coupled plasma etching or the like to complete the land area 95. Step 142 forms an ohmic contact. For example, titanium/aluminum/titanium/gold is separately deposited as the metal layer 102, and then the metal layer 102 is patterned to form metal sheets 102a, 102b, and the like. Step 144 forms an insulating layer 103. For example, a layer of germanium dioxide is deposited first, then patterned, and the remaining layer of germanium dioxide becomes the insulating layer 103. Step 146 forms Schottky contact and patterning. For example, step 146 first deposits nickel/gold/platinum as metal layer 104, and then pattern metal layer 104 to form metal sheets 104a, 104b, 104c, and the like. The metal layer 104 is in ohmic contact with the metal layer 102, but the metal layer 104 and the land region 95 are Schottky contacts. Step 148 forms a cap layer 105 and patterns it to form pad openings. Of course, the flowchart of Fig. 14 is also applicable to the HEMT of Fig. 12. With appropriate adjustments, the flowchart in FIG. 14 can also be used to fabricate the diode and HEMT as in FIG. 4A, for example, omitting step 144, or adding other processes.

雖然第2圖與第5圖中的HEMT T1與T2可以視為定電流源，但是其可能不是一個完全理想的電流源。HEMT T1與T2的汲源電流(I_DS )，在飽和區時，可能依然跟汲源電電壓(V_DS )有些許相關。第15圖顯示了金氧半場效電晶體(MOSFET)與HEMT中，I_DS 對V_DS 關係。曲線150與152分別是針對以矽為基材的一金氧半場效電晶體(MOSFET)以及一HEMT。從曲線150可以發現，在金氧半場效電晶體中，I_DS 與V_DS 大約都是正相關，也就是V_DS 越大，I_DS 越大。但是HEMT則不同。從曲線152可以發現，在HEMT中，當V_DS 超過一特定值時，I_DS 與的關係，會從正相關變成負相關。而這個特定值可以透過製程上的參數，來加以設定。這HEMT的特性有一個特別的好處，當V_DS 因為市電電壓不穩而突然飆高時，I_DS 反而會下降，可能可以降低消耗於HEMT的電功率，所以避免HEMT被燒毀。Although HEMTs T1 and T2 in Figures 2 and 5 can be considered as constant current sources, they may not be a completely ideal current source. The source current (I _DS ) of HEMT T1 and T2 may still be slightly related to the source voltage (V _DS ) in the saturation region. Figure 15 shows the relationship between I _{DS and} V _{DS in} a gold oxide half field effect transistor (MOSFET) and a HEMT. Curves 150 and 152 are respectively for a MOS substrate and a HEMT. From curve 150, it can be found that in the metal oxide half field effect transistor, I _DS and V _DS are both approximately positively correlated, that is, the larger the V _DS is, the larger the I _DS is. But HEMT is different. From curve 152, it can be found that in the HEMT, when V _DS exceeds a certain value, the relationship of I _DS to will change from positive correlation to negative correlation. This specific value can be set by the parameters on the process. The characteristics of this HEMT have a special advantage. When the V _DS suddenly rises due to the unstable mains voltage, the I _DS will decrease, which may reduce the electric power consumed by the HEMT, so the HEMT is prevented from being burned.

在先前數個實施例中，LED驅動器有一填谷電路，但本發明並不限於此。第16圖顯示了另一LED驅動器500，用以驅動LED 518，其包含了數個LED 520₁ 、520₂ 、520₃ 串接在一起。LED驅動器500中並沒有填谷電路。LED驅動器500中的橋式整流器502與電流驅動電路504可以一起整合在一半導體晶片上，封裝成一積體電路。第17圖顯示一半導體晶片550上之一金屬層104之圖案，並標示第16圖中的二極體與HEMT在半導體晶片550上的相對位置。半導體晶片550整合了LED驅動器500中的橋式整流器502與電流驅動電路504。第18圖顯示將半導體晶片550封裝後的一積體電路552。第19圖顯示採用第18圖中之積體電路552實現LED驅動器500的一照明系統560。第16至19圖可以透過先前的教導而了解，故其細節不在此累述。從第19圖可以發現整個照明系統560採用了非常少量的電子零件(一電容CF、積體電路552與LED 518)。照明系統560成本將以降低，且整個產品體積也更加精簡。In the previous several embodiments, the LED driver has a valley filling circuit, but the present invention is not limited thereto. Figure 16 shows another LED driver 500 for driving LED 518, which includes a plurality of LEDs 520 ₁ , 520 ₂ , 520 ₃ connected in series. There is no valley fill circuit in the LED driver 500. The bridge rectifier 502 and the current driving circuit 504 in the LED driver 500 can be integrated together on a semiconductor wafer and packaged into an integrated circuit. Figure 17 shows a pattern of a metal layer 104 on a semiconductor wafer 550 and indicates the relative position of the diode of Figure 16 to the HEMT on the semiconductor wafer 550. The semiconductor wafer 550 integrates the bridge rectifier 502 and the current drive circuit 504 in the LED driver 500. FIG. 18 shows an integrated circuit 552 in which the semiconductor wafer 550 is packaged. Fig. 19 shows an illumination system 560 for implementing the LED driver 500 using the integrated circuit 552 of Fig. 18. Figures 16 through 19 can be understood through the previous teachings, so the details are not repeated here. From Fig. 19, it can be seen that the entire illumination system 560 employs a very small number of electronic components (a capacitor CF, integrated circuit 552 and LED 518). The cost of the lighting system 560 will be reduced and the overall product volume will be more streamlined.

第16與19圖並非用來限制積體電路552之應用。第20圖舉例一LED驅動器600，可用以說明積體電路552的另一應用。在第20圖中，橋式整流器502與電流驅動電路504一樣整合於積體電路552，電流驅動電路504中的HMET T1與T2可以選擇性的用來驅動LED 518，其包含了數個LED 520₁ 、520₂ 、520₃ 。LED驅動器600另有分段電路IC1與IC2，其可以依據直流電源V_DC-IN 的高低而成為短路電路或是開路電路。舉例來說，當直流電源V_DC-IN 比LED 520₃ 的正向電壓略高時，分段電路IC1與IC2都是短路電路，所以LED 520₃ 發光，而LED 520₁ 、520₂ 不發光；當直流電源V_DC-IN 增加到超過LED 520₂ 與520₃ 的正向電壓總和時，分段電路IC1為短路電路，分段電路IC2為開路電路，所以LED 520₂ 與520₃ 發光，而LED 520₁ 不發光；當直流電源V_DC-IN 再增加到超過LED 520₁ 、520₂ 與520₃ 的正向電壓總和時，分段電路IC1也跟著變成開路電路，所以LED 520₁ 、520₂ 與520₃ 都發光。使得LED驅動器600的電光轉換效率更好，功因與總諧波失真率都能得到良好的控制。The 16th and 19th views are not intended to limit the application of the integrated circuit 552. Figure 20 illustrates an LED driver 600 that can be used to illustrate another application of the integrated circuit 552. In FIG. 20, the bridge rectifier 502 is integrated in the integrated circuit 552 like the current driving circuit 504. The HMETs T1 and T2 in the current driving circuit 504 can be selectively used to drive the LED 518, which includes a plurality of LEDs 520. ₁ , 520 ₂ , 520 ₃ . The LED driver 600 has a segmentation circuit IC1 and IC2, which can be a short circuit or an open circuit depending on the level of the DC power supply V _DC-IN . For example, when the DC power supply V _DC-IN is slightly higher than the forward voltage of the LED 520 ₃ , the segment circuits IC1 and IC2 are short circuit circuits, so the LED 520 ₃ emits light, and the LEDs 520 ₁ , 520 ₂ do not emit light; when the DC power supply V _DC-iN increases beyond the sum of the forward voltage of LED ₅₂₀₂ and _5203, the short circuit segment of circuit IC1, IC2 segmenting circuit is open circuit, the LED ₅₂₀₂ and ₅₂₀₃ emit light, and the LED 520 ₁ does not emit light; when the DC power supply V _{DC-IN is} further increased to exceed the sum of the forward voltages of the LEDs 520 ₁ , 520 ₂ and 520 ₃ , the segmentation circuit IC1 also becomes an open circuit, so the LEDs 520 ₁ , 520 ₂ and 520 ₃ are all shining. The electro-optical conversion efficiency of the LED driver 600 is better, and the power factor and the total harmonic distortion rate can be well controlled.

依據本發明所實施的一積體電路並不限於只是整合了一橋式整流器與一電流驅動電路。先前所述的積體電路130與552僅僅作為例子。舉例來說，依據本發明所實施的一積體電路除了有橋式整流器與電流驅動電路之外，還整合有一些二極體，可用於第20圖中的分段電路IC1與IC2中。An integrated circuit implemented in accordance with the present invention is not limited to just integrating a bridge rectifier and a current drive circuit. The integrated circuits 130 and 552 previously described are merely examples. For example, an integrated circuit implemented in accordance with the present invention incorporates a plurality of diodes in addition to the bridge rectifier and the current driving circuit, and can be used in the segment circuits IC1 and IC2 in FIG.

本發明所實施的積體電路並不限於只包有耗盡模式的HEMT。在一些實施例中，積體電路包含有增強型模式(enhancement-mode)HEMT，其導通電流可以透過提供適當的閘電壓來加以控制，藉此改變所連接到的LED發出光源的強度。例如在第20圖中利用分段電路IC1與IC2調整啟動的LED520₁ 、520₂ 、520₃ 的同時，可以調整增強型模式HEMT的閘電壓以改變HEMT輸入到LED520₁ 、520₂ 、520₃ 的電流，進而改變LED520₁ 、520₂ 、520₃ 所發出的光強度。The integrated circuit implemented by the present invention is not limited to a HEMT including only a depletion mode. In some embodiments, the integrated circuit includes an enhancement-mode HEMT whose on-current can be controlled by providing an appropriate gate voltage, thereby changing the intensity of the source to which the LED is connected. For example, while the activated LEDs 520 ₁ , 520 ₂ , and 520 ₃ are adjusted by the segment circuits IC1 and IC2 in FIG. 20, the gate voltage of the enhanced mode HEMT may be adjusted to change the HEMT input to the LEDs 520 ₁ , 520 ₂ , 520 ₃ . The current, in turn, changes the intensity of the light emitted by LEDs 520 ₁ , 520 ₂ , 520 ₃ .

儘管先前所揭示的LED驅動器或是照明系統，每個都是用以驅動單一LED 518，但本發明並不限於此。在一些實施例中，可以有兩個或是以上的LED，以不同的電流，分別的被驅動。第21圖舉例一LED驅動器700，其中電流驅動電路504中的HEMT T1與T2，分別驅動LED 18R與18B。舉例來說，HEMT T1所提供的驅動電流小於HEMT T2所提供的驅動電流，而LED 18R大致為紅光LED，而LED 18B大致為藍光LED。Although the previously disclosed LED drivers or illumination systems are each used to drive a single LED 518, the invention is not limited thereto. In some embodiments, there may be two or more LEDs that are driven separately at different currents. Figure 21 illustrates an LED driver 700 in which HEMTs T1 and T2 in current drive circuit 504 drive LEDs 18R and 18B, respectively. For example, the HEMT T1 provides a drive current that is less than the drive current provided by the HEMT T2, while the LED 18R is roughly a red LED and the LED 18B is substantially a blue LED.

第6圖與第13圖中的二極體，分別都形成於單一平台區95上，但本發明並不限於此。第22圖顯示另一種實施例中，一二極體之晶片剖面圖。第22圖中與第6圖以及第13圖彼此相同或類似之部分，為簡潔之緣故，不再累述。第22圖中有兩個平台區95與95a。金屬片102e於平台區95a上，形成一歐姆接觸；而金屬片102d則在於平台區95上，形成另一歐姆接觸。金屬片102d與102e透過金屬片104g，彼此短路電連接。金屬片104f作為二極體的一陽極，金屬片104d則作為二極體的一陰極。第22圖中的結構，可以增強二極體的崩潰電壓耐受能力。The diodes in Figs. 6 and 13 are respectively formed on the single land area 95, but the present invention is not limited thereto. Figure 22 is a cross-sectional view showing a wafer of a diode in another embodiment. The same or similar portions in Fig. 22 and Fig. 6 and Fig. 13 are for the sake of brevity and will not be described again. There are two platform areas 95 and 95a in Fig. 22. The metal piece 102e forms an ohmic contact on the land area 95a, and the metal piece 102d is located on the land area 95 to form another ohmic contact. The metal pieces 102d and 102e are transmitted through the metal piece 104g, and are short-circuited and electrically connected to each other. The metal piece 104f serves as an anode of the diode, and the metal piece 104d serves as a cathode of the diode. The structure in Fig. 22 can enhance the breakdown voltage withstand capability of the diode.

以上所述僅為本發明之較佳實施例，凡依本發明申請專利範圍所做之均等變化與修飾，皆應屬本發明之涵蓋範圍。The above are only the preferred embodiments of the present invention, and all changes and modifications made to the scope of the present invention should be within the scope of the present invention.

10‧‧‧照明系統 10‧‧‧Lighting system

12‧‧‧橋式整流器 12‧‧‧Bridge rectifier

14‧‧‧功率因數校正器 14‧‧‧Power Factor Corrector

16‧‧‧LED驅動電路 16‧‧‧LED drive circuit

18、18B、18R‧‧‧LED 18, 18B, 18R‧‧‧ LED

19‧‧‧穩壓電容 19‧‧‧Steady capacitor

60‧‧‧LED驅動器 60‧‧‧LED driver

62‧‧‧橋式整流器 62‧‧‧Bridge rectifier

64‧‧‧填谷電路 64‧‧‧ Valley Filling Circuit

66‧‧‧電流驅動電路 66‧‧‧Current drive circuit

67‧‧‧虛線 67‧‧‧dotted line

72、74、76‧‧‧電壓波形 72, 74, 76‧‧‧ voltage waveforms

80‧‧‧半導體晶片 80‧‧‧Semiconductor wafer

92‧‧‧矽基底 92‧‧‧矽Base

94‧‧‧緩衝層 94‧‧‧buffer layer

95、95a‧‧‧平台區 95, 95a‧‧‧ platform area

96‧‧‧通道層 96‧‧‧channel layer

98‧‧‧高價帶間隙層 98‧‧‧High price with gap layer

100‧‧‧蓋層 100‧‧‧ cover

102‧‧‧金屬層 102‧‧‧metal layer

102a、102b、102c、102d、102e‧‧‧金屬片 102a, 102b, 102c, 102d, 102e‧‧‧ metal pieces

103‧‧‧絕緣層 103‧‧‧Insulation

104‧‧‧金屬層 104‧‧‧metal layer

104a、104b、104c、104d、104e、104f、104g‧‧‧金屬片 104a, 104b, 104c, 104d, 104e, 104f, 104g‧‧‧ metal pieces

105‧‧‧護層 105‧‧‧ Cover

120‧‧‧二極體符號 120‧‧‧diode symbol

130‧‧‧積體電路 130‧‧‧Integrated circuit

140、142、144、146、148‧‧‧步驟 140, 142, 144, 146, 148‧ ‧ steps

150、152‧‧‧曲線 150, 152‧‧‧ curve

200‧‧‧照明系統 200‧‧‧Lighting system

300‧‧‧LED驅動器 300‧‧‧LED driver

302‧‧‧電流驅動電路 302‧‧‧ Current drive circuit

330‧‧‧照明系統 330‧‧‧Lighting system

500‧‧‧LED驅動器 500‧‧‧LED driver

502‧‧‧橋式整流器 502‧‧‧Bridge rectifier

504‧‧‧電流驅動電路 504‧‧‧ Current drive circuit

518、520₁、520₂、520₃‧‧‧LED518, 520 ₁ , 520 ₂ , 520 ₃ ‧ ‧ LED

550‧‧‧半導體晶片 550‧‧‧Semiconductor wafer

552‧‧‧積體電路 552‧‧‧Integrated circuit

560‧‧‧照明系統 560‧‧‧Lighting system

600‧‧‧LED驅動器 600‧‧‧LED driver

700‧‧‧LED驅動器 700‧‧‧LED driver

AC+、AC-‧‧‧交流輸入接腳 AC+, AC-‧‧‧ AC input pins

ARM1、ARM2‧‧‧上臂 ARM1, ARM2‧‧‧ upper arm

ART、ARB‧‧‧上下兩臂 ART, ARB‧‧‧ upper and lower arms

C1、C2、CF‧‧‧電容 C1, C2, CF‧‧‧ capacitors

DB1-DB4‧‧‧整流二極體 DB1-DB4‧‧‧Rected Diode

DVF1-DVF3‧‧‧二極體 DVF1-DVF3‧‧‧ diode

D1、D2‧‧‧驅動接腳 D1, D2‧‧‧ drive pins

GND‧‧‧接地線 GND‧‧‧ Grounding wire

GG‧‧‧閘區域 GG‧‧‧ gate area

IC1、IC2‧‧‧分段電路 IC1, IC2‧‧‧ segment circuit

PF1、PF2‧‧‧功率因數校正接腳 PF1, PF2‧‧‧ power factor correction pin

S1、S2‧‧‧驅動接腳 S1, S2‧‧‧ drive pins

T1、T2、T3、T4‧‧‧HEMT（高電子遷移率場效電晶體） T1, T2, T3, T4‧‧‧ HEMT (High Electron Mobility Field Effect Transistor)

TP1、TP2、TP3‧‧‧時段 TP1, TP2, TP3‧‧‧

V_AC-IN‧‧‧交流輸入電源V _AC-IN ‧‧‧AC input power supply

VCC‧‧‧高電壓接腳 VCC‧‧‧ high voltage pin

V_DC-IN‧‧‧直流電源V _DC-IN ‧‧‧DC power supply

VDD‧‧‧直流電源線 VDD‧‧‧DC power cord

V_PEAK‧‧‧電壓峰值V _PEAK ‧‧‧ voltage peak

VSS‧‧‧低電壓接腳 VSS‧‧‧ low voltage pin

第1圖為習知的照明系統。Figure 1 is a conventional lighting system.

第2圖顯示一依據本發明一實施例的LED驅動器。 Figure 2 shows an LED driver in accordance with an embodiment of the present invention.

第3圖顯示三個電壓波形。 Figure 3 shows three voltage waveforms.

第4A圖顯示一半導體晶片上之一金屬層之圖案。 Figure 4A shows a pattern of a metal layer on a semiconductor wafer.

第4B圖顯示將第4A圖之半導體晶片封裝後的一積體電路示意圖。 Fig. 4B is a view showing an integrated circuit after packaging the semiconductor wafer of Fig. 4A.

第5圖顯示第4A圖中之HEMT T1沿著線ST-ST的剖面圖。 Fig. 5 is a cross-sectional view showing the HEMT T1 in Fig. 4A taken along line ST-ST.

第6圖顯示第4A圖中之二極體DVF3沿著線SD-SD的剖面圖。 Fig. 6 is a cross-sectional view showing the diode DVF3 in Fig. 4A along the line SD-SD.

第7圖顯示依據本發明一實施例的一照明系統。 Figure 7 shows an illumination system in accordance with an embodiment of the present invention.

第8圖顯示依據本發明另一實施例的LED驅動器。 Figure 8 shows an LED driver in accordance with another embodiment of the present invention.

第9A圖顯示另一半導體晶片上之一金屬層的圖案。 Figure 9A shows a pattern of one of the metal layers on another semiconductor wafer.

第9B圖顯示將第9A圖之半導體晶片封裝後的一積體電路示意圖。 Fig. 9B is a view showing an integrated circuit after packaging the semiconductor wafer of Fig. 9A.

第10圖顯示依據本發明另一實施例的一照明系統。 Figure 10 shows an illumination system in accordance with another embodiment of the present invention.

第11圖顯示LED與額外的一穩壓電容相並聯之電路圖。 Figure 11 shows a circuit diagram in which the LED is connected in parallel with an additional Zener capacitor.

第12圖顯示另一半導體晶片上之一金屬層之圖案。 Figure 12 shows a pattern of a metal layer on another semiconductor wafer.

第13圖顯示第4A圖中之二極體DVF3沿著線SD-SD的依據另一種實施例之晶片剖面圖。 Figure 13 is a cross-sectional view of the wafer according to another embodiment of the diode DVF3 of Figure 4A along line SD-SD.

第14圖顯示可以用來製作第13圖中之二極體的流程圖。 Figure 14 shows a flow chart that can be used to create the diode of Figure 13.

第15圖顯示依據本發明一實施例之金氧半場效電晶體(MOSFET)與HEMT中I_DS 對V_DS 關係。Figure 15 shows the relationship of I _DS vs. V _{DS in a} gold oxide half field effect transistor (MOSFET) in accordance with an embodiment of the present invention.

第16圖顯示依據本發明另一實施例之LED驅動器。 Figure 16 shows an LED driver in accordance with another embodiment of the present invention.

第17圖顯示依據本發明一實施例之一半導體晶片上之一金屬層之圖案。 Figure 17 shows a pattern of a metal layer on a semiconductor wafer in accordance with one embodiment of the present invention.

第18圖顯示將第17圖之半導體晶片封裝後的一積體電路。 Fig. 18 is a view showing an integrated circuit in which the semiconductor wafer of Fig. 17 is packaged.

第19圖顯示採用第18圖中之積體電路實現的一照明系統。 Fig. 19 shows an illumination system implemented by the integrated circuit of Fig. 18.

第20圖顯示依據本發明一實施例之一LED驅動器之電路設計。 Figure 20 shows a circuit design of an LED driver in accordance with an embodiment of the present invention.

第21圖顯示依據本發明又一實施例之一LED驅動器，具有多個LED。 Figure 21 shows an LED driver having a plurality of LEDs in accordance with yet another embodiment of the present invention.

第22圖顯示依據本發明一實施例之一二極體晶片之剖面圖。 Figure 22 is a cross-sectional view showing a diode wafer in accordance with an embodiment of the present invention.

Claims (10)

一種半導體晶片，包含有： 一緩衝層； 一整流電路，包含有一整流二極體形成於該緩衝層上； 以及 一電流驅動電路，包含一第一定電流源形成於該緩衝層上，並提供一定電流。A semiconductor wafer comprising: a buffer layer; a rectifier circuit comprising a rectifying diode formed on the buffer layer; as well as A current driving circuit includes a first constant current source formed on the buffer layer and providing a certain current. 如申請專利範圍第1項之半導體晶片，其中，該電流驅動電路更包含一第二定電流源選擇性的與該第一定電流源電性連接。The semiconductor wafer of claim 1, wherein the current driving circuit further comprises a second constant current source selectively electrically connected to the first constant current source. 如申請專利範圍第2項之半導體晶片，其中，該第二定電流源形成於該緩衝層之上。The semiconductor wafer of claim 2, wherein the second constant current source is formed on the buffer layer. 如申請專利範圍第1項之半導體晶片，其中，該第一定電流源為一高電子遷移率場效電晶體(high electron mobility transistor，HEMT)，其具有相互電連接的一源極以及一閘極。The semiconductor wafer of claim 1, wherein the first constant current source is a high electron mobility transistor (HEMT) having a source electrically connected to each other and a gate pole. 如申請專利範圍第1項之半導體晶片，其中，該整流二極體包含有電相連之一蕭特基二極體(schottky barrier diode)與一高電子遷移率場效電晶體。The semiconductor wafer of claim 1, wherein the rectifying diode comprises a Schottky barrier diode electrically connected to a high electron mobility field effect transistor. 如申請專利範圍第1項之半導體晶片，更包含一功率因數校正器電性連接該電流驅動電路與該發光元件。The semiconductor wafer of claim 1, further comprising a power factor corrector electrically connecting the current driving circuit and the light emitting element. 如申請專利範圍第6項之半導體晶片，其中，該功率因數校正器更包含彼此串連著的第一二極體與第二二極體。The semiconductor wafer of claim 6, wherein the power factor corrector further comprises a first diode and a second diode connected in series with each other. 如申請專利範圍第7項之半導體晶片，其中，該第一二極體的陽極與該第二二極體的陰極直接連接。The semiconductor wafer of claim 7, wherein the anode of the first diode is directly connected to the cathode of the second diode. 如申請專利範圍第7項之半導體晶片，其中，該第一二極體的陰極與該第二二極體的陽極不直接相連。The semiconductor wafer of claim 7, wherein the cathode of the first diode is not directly connected to the anode of the second diode. 如申請專利範圍第1項之半導體晶片，更包含一金屬層覆蓋該緩衝層。The semiconductor wafer of claim 1 further comprises a metal layer covering the buffer layer.