TW201926354A - Encoder and associated encoding method and flash memory controller - Google Patents

Encoder and associated encoding method and flash memory controller Download PDF

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TW201926354A
TW201926354A TW107135826A TW107135826A TW201926354A TW 201926354 A TW201926354 A TW 201926354A TW 107135826 A TW107135826 A TW 107135826A TW 107135826 A TW107135826 A TW 107135826A TW 201926354 A TW201926354 A TW 201926354A
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check code
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TWI665678B (en
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郭軒豪
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慧榮科技股份有限公司
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Abstract

An encoding method includes: processing a plurality of data blocks to generate a plurality of partial parity blocks, wherein the partial parity blocks includes a first portion and a second portion; using a first computing circuit to generate a first calculating result according the second portion of the partial parity blocks; using the first calculating result to adjust the first portion of the partial parity blocks; performing a circulant convolution operation upon the adjusted first portion to generate a first portion of parity blocks; using a second computing circuit to generate a second portion of the parity blocks according to at least the first portion of parity blocks; wherein the first portion of the parity blocks and the second portion of the parity blocks serve as a plurality of parity blocks generated in response to encoding the data blocks.

Description

編碼器及相關的編碼方法與快閃記憶體控制器Encoder and related encoding method and flash memory controller

本發明係有關於編碼器，尤指一種應用在快閃記憶體控制器中的編碼器。The present invention relates to an encoder, and more particularly to an encoder for use in a flash memory controller.

在一般的編碼器中，會具有一個校驗碼檢查矩陣(parity-check matrix)，以供編碼器檢查所產生出來的校驗碼是否正確。舉例來說，編碼器在對資料進行編碼以產生校驗碼之後，會將資料與校驗碼和此校驗碼檢查矩陣進行相乘，而若是相乘結果等於“0”則判斷編碼正確；而若是相乘結果不等於“0”則判斷編碼錯誤。因應此校驗碼檢查矩陣，編碼器會具有一相對應的校驗碼產生矩陣以供產生適合的校驗碼，然而，在某些情況下，校驗碼產生矩陣可能無法被找到，因此編碼器會需要進行多個矩陣乘法操作及/或補償/調整操作，以產生類似使用校驗碼產生矩陣所產生的校驗碼，因此會增加編碼器的複雜度。特別地，上述多個矩陣乘法操作通常會包含循環卷積(circulant convolution)計算，因此更會大幅增加編碼器的硬體成本。In a typical encoder, there will be a parity-check matrix for the encoder to check if the generated checksum is correct. For example, after the encoder encodes the data to generate the check code, the data is multiplied by the check code and the check code check matrix, and if the multiplication result is equal to “0”, the code is judged to be correct; If the multiplication result is not equal to "0", the coding error is judged. In response to this check code check matrix, the encoder will have a corresponding check code generation matrix for generating a suitable check code. However, in some cases, the check code generation matrix may not be found, so the code The device may need to perform multiple matrix multiplication operations and/or compensation/adjustment operations to produce a check code similar to that produced using the check code generation matrix, thus increasing the complexity of the encoder. In particular, the above plurality of matrix multiplication operations usually include a circular convolution calculation, and thus the hardware cost of the encoder is greatly increased.

因此，本發明的目的之一在於提出一種編碼器，其可以降低編碼器中的循環卷積計算所需要的硬體，以避免先前技術中所述之硬體成本大幅增加的情形。Accordingly, it is an object of the present invention to provide an encoder which can reduce the hardware required for the cyclic convolution calculation in the encoder to avoid a situation in which the hardware cost described in the prior art is greatly increased.

在本發明的一個實施例中，揭露了一種編碼器，其包含有一第一桶式移位器模組、一第一計算電路、一調整電路、一第一循環卷積計算電路以及一第二計算電路。該第一桶式移位器模組用以將多個資料區塊進行處理以產生多個局部校驗碼區塊，其中該多個局部校驗碼區塊包含了一第一部分及一第二部分；該第一計算電路耦接於該第一桶式移位器模組，且用以根據該第二部分以產生一第一計算結果；該調整電路用以根據該第一計算結果來調整該多個局部校驗碼區塊的該第一部分，以產生一調整後第一部分；該第一循環卷積計算電路耦接於該調整電路，且用以對該調整後第一部分進行循環卷積操作，以產生一第一部分的校驗碼區塊；以及該第二計算電路耦接於該第一循環卷積計算電路，且用以至少根據該第一部分的校驗碼區塊以產生一第二部分的校驗碼區塊；其中該第一部分的校驗碼區塊及該第二部分的校驗碼區塊係作為該編碼器針對該多個資料區塊所產生之多個校驗碼區塊。In an embodiment of the present invention, an encoder is disclosed, including a first barrel shifter module, a first calculation circuit, an adjustment circuit, a first circular convolution calculation circuit, and a second Calculation circuit. The first barrel shifter module is configured to process a plurality of data blocks to generate a plurality of partial check code blocks, wherein the plurality of partial check code blocks comprise a first portion and a second portion The first calculation circuit is coupled to the first barrel shifter module and configured to generate a first calculation result according to the second portion; the adjustment circuit is configured to adjust according to the first calculation result The first portion of the plurality of partial check code blocks to generate an adjusted first portion; the first circular convolution calculation circuit is coupled to the adjustment circuit, and configured to perform circular convolution on the adjusted first portion Operating to generate a first portion of the check code block; and the second computing circuit is coupled to the first circular convolution calculation circuit, and configured to generate a first according to at least the first portion of the check code block a two-part check code block; wherein the check code block of the first part and the check code block of the second part are used as a plurality of check codes generated by the encoder for the plurality of data blocks Block.

在本發明的另一個實施例中，揭露了一種快閃記憶體控制器，其中該快閃記憶體控制器係用來存取一快閃記憶體模組，且該快閃記憶體控制器包含有一記憶體、一微處理器以及一編碼器，其中該記憶體用來儲存一程式碼；該微處理器用來執行該程式碼以控制對該快閃記憶體模組之存取；且該編碼器用以對該多個資料區塊進行編碼以得到多個校驗碼區塊。此外，該編碼器包含有一第一桶式移位器模組、一第一計算電路、一調整電路、一第一循環卷積計算電路以及一第二計算電路。該第一桶式移位器模組用以將多個資料區塊進行處理以產生多個局部校驗碼區塊，其中該多個局部校驗碼區塊包含了一第一部分及一第二部分；該第一計算電路耦接於該第一桶式移位器模組，且用以根據該第二部分以產生一第一計算結果；該調整電路用以根據該第一計算結果來調整該多個局部校驗碼區塊的該第一部分，以產生一調整後第一部分；該第一循環卷積計算電路耦接於該調整電路，且用以對該調整後第一部分進行循環卷積操作，以產生一第一部分的校驗碼區塊；以及該第二計算電路耦接於該第一循環卷積計算電路，且用以至少根據該第一部分的校驗碼區塊以產生一第二部分的校驗碼區塊；其中該第一部分的校驗碼區塊及該第二部分的校驗碼區塊係作為該編碼器針對該多個資料區塊所產生之多個校驗碼區塊。In another embodiment of the present invention, a flash memory controller is disclosed, wherein the flash memory controller is used to access a flash memory module, and the flash memory controller includes a memory, a microprocessor, and an encoder, wherein the memory is used to store a code; the microprocessor is configured to execute the code to control access to the flash memory module; and the code The device is configured to encode the plurality of data blocks to obtain a plurality of check code blocks. In addition, the encoder includes a first barrel shifter module, a first calculation circuit, an adjustment circuit, a first circular convolution calculation circuit, and a second calculation circuit. The first barrel shifter module is configured to process a plurality of data blocks to generate a plurality of partial check code blocks, wherein the plurality of partial check code blocks comprise a first portion and a second portion The first calculation circuit is coupled to the first barrel shifter module and configured to generate a first calculation result according to the second portion; the adjustment circuit is configured to adjust according to the first calculation result The first portion of the plurality of partial check code blocks to generate an adjusted first portion; the first circular convolution calculation circuit is coupled to the adjustment circuit, and configured to perform circular convolution on the adjusted first portion Operating to generate a first portion of the check code block; and the second computing circuit is coupled to the first circular convolution calculation circuit, and configured to generate a first according to at least the first portion of the check code block a two-part check code block; wherein the check code block of the first part and the check code block of the second part are used as a plurality of check codes generated by the encoder for the plurality of data blocks Block.

在本發明的另一個實施例中，揭露了一種編碼方法，其包含有：將多個資料區塊進行處理以產生多個局部校驗碼區塊，其中該多個局部校驗碼區塊包含了一第一部分及一第二部分；使用一第一計算電路以根據該第二部分以產生一第一計算結果；根據該第一計算結果來調整該多個局部校驗碼區塊的該第一部分；對該調整後第一部分進行循環卷積操作，以產生一第一部分的校驗碼區塊；以及使用一第二計算電路以至少根據該第一部分的校驗碼區塊來產生一第二部分的校驗碼區塊；其中該第一部分的校驗碼區塊及該第二部分的校驗碼區塊係作為對該多個資料區塊進行編碼後所產生之多個校驗碼區塊。In another embodiment of the present invention, an encoding method is disclosed, including: processing a plurality of data blocks to generate a plurality of partial check code blocks, wherein the plurality of partial check code blocks includes a first portion and a second portion; using a first calculation circuit to generate a first calculation result according to the second portion; adjusting the plurality of partial verification code blocks according to the first calculation result a portion; performing a cyclic convolution operation on the adjusted first portion to generate a first portion of the check code block; and using a second calculation circuit to generate a second portion based on at least the check code block of the first portion a part of the check code block; wherein the check code block of the first part and the check code block of the second part are used as a plurality of check code areas generated by encoding the plurality of data blocks Piece.

在本發明的另一個實施例中，揭露了一種編碼器，其包含有一桶式移位器模組、一調整電路、一循環卷積計算電路以及一計算電路。該桶式移位器模組用以將多個資料區塊進行處理以產生多個局部校驗碼區塊，其中該多個局部校驗碼區塊包含了一第一部分及一第二部分；該調整電路用以根據該第二部分來調整該多個局部校驗碼區塊的該第一部分，以產生一調整後第一部分；該循環卷積計算電路耦接於該調整電路，且用以對該調整後第一部分進行循環卷積操作，以產生一第一部分的校驗碼區塊；以及該計算電路耦接於該循環卷積計算電路，且用以至少根據該第一部分的校驗碼區塊以產生一第二部分的校驗碼區塊；其中該第一部分的校驗碼區塊及該第二部分的校驗碼區塊係作為該編碼器針對該多個資料區塊所產生之多個校驗碼區塊。In another embodiment of the present invention, an encoder is disclosed that includes a barrel shifter module, an adjustment circuit, a cyclic convolution calculation circuit, and a calculation circuit. The bucket shifter module is configured to process a plurality of data blocks to generate a plurality of partial check code blocks, wherein the plurality of partial check code blocks comprise a first portion and a second portion; The adjusting circuit is configured to adjust the first portion of the plurality of partial check code blocks according to the second portion to generate an adjusted first portion; the circular convolution calculation circuit is coupled to the adjusting circuit, and configured to Performing a cyclic convolution operation on the first portion of the adjustment to generate a first portion of the check code block; and the calculation circuit is coupled to the circular convolution calculation circuit, and configured to perform at least the check code of the first portion Blocking a block to generate a second portion of the check code block; wherein the check code block of the first portion and the check code block of the second portion are generated by the encoder for the plurality of data blocks Multiple check code blocks.

請參考第1圖，第1圖為依據本發明一實施例之一種記憶裝置100的示意圖。記憶裝置100包含有一快閃記憶體（Flash Memory）模組120以及一快閃記憶體控制器110，且快閃記憶體控制器110用來存取快閃記憶體模組120。依據本實施例，快閃記憶體控制器110包含一微處理器112、一唯讀記憶體（Read Only Memory, ROM）112M、一控制邏輯114、一緩衝記憶體116、與一介面邏輯118。唯讀記憶體112M係用來儲存一程式碼112C，而微處理器112則用來執行程式碼112C以控制對快閃記憶體模組120之存取（Access）。控制邏輯114包含了一編碼器132以及一解碼器134，其中編碼器132用來對寫入到快閃記憶體模組120中的資料進行編碼以產生對應的校驗碼(或稱，錯誤更正碼(Error Correction Code)，ECC)，而解碼器134用來將從快閃記憶體模組120所讀出的資料進行解碼。Please refer to FIG. 1. FIG. 1 is a schematic diagram of a memory device 100 according to an embodiment of the invention. The memory device 100 includes a flash memory module 120 and a flash memory controller 110, and the flash memory controller 110 is used to access the flash memory module 120. According to the embodiment, the flash memory controller 110 includes a microprocessor 112, a read only memory (ROM) 112M, a control logic 114, a buffer memory 116, and an interface logic 118. The read-only memory 112M is used to store a code 112C, and the microprocessor 112 is used to execute the code 112C to control access to the flash memory module 120. The control logic 114 includes an encoder 132 and a decoder 134, wherein the encoder 132 is configured to encode the data written into the flash memory module 120 to generate a corresponding check code (or, error correction) The code (Error Correction Code), ECC), and the decoder 134 is used to decode the data read from the flash memory module 120.

於典型狀況下，快閃記憶體模組120包含了多個快閃記憶體晶片，而每一個快閃記憶體晶片包含複數個區塊（Block），而該控制器（例如：透過微處理器112執行程式碼112C之快閃記憶體控制器110）對快閃記憶體模組120進行複製、抹除、合併資料等運作係以區塊為單位來進行複製、抹除、合併資料。另外，一區塊可記錄特定數量的資料頁（Page），其中該控制器（例如：透過微處理器112執行程式碼112C之記憶體控制器110）對快閃記憶體模組120進行寫入資料之運作係以資料頁為單位來進行寫入。In a typical situation, the flash memory module 120 includes a plurality of flash memory chips, and each of the flash memory chips includes a plurality of blocks (eg, through a microprocessor). The flash memory controller 110 executing the code 112C performs copying, erasing, and merging data on the flash memory module 120, and copies, erases, and merges the data in units of blocks. In addition, a block can record a specific number of pages, wherein the controller (eg, the memory controller 110 executing the code 112C through the microprocessor 112) writes to the flash memory module 120. The operation of the data is written in units of data pages.

實作上，透過微處理器112執行程式碼112C之快閃記憶體控制器110可利用其本身內部之元件來進行諸多控制運作，例如：利用控制邏輯114來控制快閃記憶體模組120之存取運作（尤其是對至少一區塊或至少一資料頁之存取運作）、利用緩衝記憶體116進行所需之緩衝處理、以及利用介面邏輯118來與一主裝置（Host Device）130溝通。In practice, the flash memory controller 110 executing the code 112C through the microprocessor 112 can perform various control operations by using its own internal components, for example, using the control logic 114 to control the flash memory module 120. Access operations (especially for at least one block or at least one data page), buffer memory 116 for buffering, and interface logic 118 for communication with a host device 130 .

在一實施例中，記憶裝置100可以是可攜式記憶裝置（例如：符合SD/MMC、CF、MS、XD標準之記憶卡），且主裝置130為一可與記憶裝置連接的電子裝置，例如手機、筆記型電腦、桌上型電腦…等等。而在另一實施例中，記憶裝置100可以設置在一電子裝置中，例如設置在手機、筆記型電腦、桌上型電腦之中，而此時主裝置130可以是該電子裝置的一處理器。In an embodiment, the memory device 100 can be a portable memory device (for example, a memory card conforming to the SD/MMC, CF, MS, and XD standards), and the main device 130 is an electronic device connectable to the memory device. For example, mobile phones, notebook computers, desktop computers, etc. In another embodiment, the memory device 100 can be disposed in an electronic device, such as a mobile phone, a notebook computer, or a desktop computer, and the main device 130 can be a processor of the electronic device. .

在本實施例中，編碼器132為一低密度奇偶檢查碼（Low-Density Parity Check code，LDPC code）編碼器，且可以根據來自主裝置130的資料來產生對應的校驗碼，且所產生的校驗碼符合一校驗碼檢查矩陣。具體來說，參考第2圖，假設該校驗碼檢查矩陣為一大小為c*t的矩陣(例如，c=5，t=48)，而該校驗碼檢查矩陣可以分為左側的矩陣M(大小為c*(t-c))以及右側的矩陣K(大小為c*c)，為了找出與該校驗碼檢查矩陣所對應的校驗碼產生矩陣，可以先找出矩陣K的反矩陣K-1 (inverse matrix)，之後再將反矩陣(K-1 )與矩陣M相乘以得到矩陣P，而矩陣P的轉置矩陣(transpose matrix)便可以作為校驗碼產生矩陣。換句話說，在找到矩陣P的轉置矩陣之後，編碼器132可以將來自主裝置130的資料乘以矩陣P的轉置矩陣來得到對應於該些資料的校驗碼，而編碼器之後再將資料與校驗碼一起乘上該校驗碼檢查矩陣以判斷校驗碼是否正確。舉例來說，若是相乘結果等於“0”則判斷編碼正確；而若是相乘結果不等於“0”則判斷編碼錯誤。在判斷編碼正確之後，資料與對應的校驗碼便會被寫入至快閃記憶體模組120中的一個資料頁中。In this embodiment, the encoder 132 is a low-density parity check code (LDPC code) encoder, and the corresponding check code can be generated according to the data from the host device 130, and generated. The check code conforms to a check code check matrix. Specifically, referring to FIG. 2, it is assumed that the check code check matrix is a matrix of size c*t (for example, c=5, t=48), and the check code check matrix can be divided into a matrix on the left side. M (the size is c*(tc)) and the matrix K on the right side (the size is c*c). In order to find the check code generation matrix corresponding to the check code check matrix, the inverse of the matrix K can be found first. The matrix K -1 (inverse matrix), and then multiply the inverse matrix (K -1 ) by the matrix M to obtain the matrix P, and the transpose matrix of the matrix P can be used as a check code to generate a matrix. In other words, after finding the transposed matrix of the matrix P, the encoder 132 may multiply the data of the autonomous device 130 by the transposed matrix of the matrix P to obtain a check code corresponding to the data, and the encoder will The data is multiplied with the check code to check the check matrix to determine whether the check code is correct. For example, if the multiplication result is equal to "0", the code is judged to be correct; and if the multiplication result is not equal to "0", the coding error is judged. After determining that the encoding is correct, the data and the corresponding verification code are written to a data page in the flash memory module 120.

然而，在某些情況下，反矩陣K-1 可能無法被輕易找到，因此編碼器132會需要進行多個矩陣乘法操作及/或補償/調整操作來得到一個類似反矩陣K-1 的內容，以供找出校驗碼產生矩陣來產生校驗碼。本發明因此提出了一種電路架構，以使得編碼器132可以在盡可能節省硬體成本的情形下完成編碼器132的操作。需注意的是，編碼器132中有關於編碼的過程涉及許多複雜的數學運算，但由於本發明的重點是在於電路架構的設計，故相關的矩陣內容及推導過程的細節在此不予贅述。However, in some cases, the inverse matrix K -1 may not be easily found, so the encoder 132 may need to perform multiple matrix multiplication operations and/or compensation/adjustment operations to obtain a content similar to the inverse matrix K -1 , A check matrix is generated for finding a check code to generate a check code. The present invention therefore proposes a circuit architecture such that the encoder 132 can perform the operation of the encoder 132 with as much hardware cost savings as possible. It should be noted that the process of encoding in the encoder 132 involves many complicated mathematical operations. However, since the focus of the present invention is on the design of the circuit architecture, the details of the related matrix contents and the derivation process are not described herein.

參考第3圖，其為根據本發明一實施例之編碼器300的示意圖，其中編碼器300可以作為第1圖所示之編碼器132。如第3圖所示，編碼器300包含了一桶式移位器模組310、一第一計算電路320、一調整電路330、一循環卷積(circulant convolution)計算電路340、一補償電路342以及一第二計算電路350。在本實施例中，桶式移位器模組310包含了多個桶式移位器311、312、313、314、315以及多個累加電路317_1~317_5；第一計算電路320包含了一循環卷積計算電路322、一補償電路324以及一桶式移位器模組326；調整電路330包含了多個累加電路332、334、336；以及第二計算電路350包含了一桶式移位器模組352、一循環卷積計算電路354、一補償電路356、一包含兩個累加電路357、358的輸出電路。在本實施例中，編碼器300係將來自主裝置130的一筆資料分為多個資料區塊(在本實施例中該多個資料區塊為43個資料區塊DB_1~DB_43)，並將該多個資料區塊DB_1~DB_43進行編碼後產生多個校驗碼區塊(在本實施例中該多個校驗碼區塊為5個校驗碼區塊PB_1~PB_5)。需注意的是，上述之一個資料區塊與一個校驗碼區塊的大小是相同的，且資料區塊的大小可以由設計者所自行決定，例如192*192個位元。Referring to FIG. 3, which is a schematic diagram of an encoder 300 in accordance with an embodiment of the present invention, an encoder 300 can be used as the encoder 132 shown in FIG. As shown in FIG. 3, the encoder 300 includes a barrel shifter module 310, a first calculation circuit 320, an adjustment circuit 330, a circular convolution calculation circuit 340, and a compensation circuit 342. And a second calculation circuit 350. In this embodiment, the barrel shifter module 310 includes a plurality of barrel shifters 311, 312, 313, 314, 315 and a plurality of accumulating circuits 317_1 317 317_5; the first calculating circuit 320 includes a loop Convolution calculation circuit 322, a compensation circuit 324 and a barrel shifter module 326; adjustment circuit 330 includes a plurality of accumulation circuits 332, 334, 336; and second calculation circuit 350 includes a barrel shifter The module 352, a cyclic convolution calculation circuit 354, a compensation circuit 356, and an output circuit including two accumulation circuits 357, 358. In this embodiment, the encoder 300 divides a piece of data of the autonomous device 130 into a plurality of data blocks (in the embodiment, the plurality of data blocks are 43 data blocks DB_1~DB_43), and the The plurality of data blocks DB_1~DB_43 are encoded to generate a plurality of check code blocks (in the present embodiment, the plurality of check code blocks are 5 check code blocks PB_1~PB_5). It should be noted that the size of one of the above data blocks and one of the check code blocks are the same, and the size of the data block can be determined by the designer, for example, 192*192 bits.

在編碼器300的操作中，首先，桶式移位器模組310將資料區塊DB_1~DB_43進行處理以產生多個局部校驗碼(partial parity)區塊PPB_1~PPB_5。具體來說，桶式移位器311可以分別對資料區塊DB_1~DB_43進行移位操作，並透過累加電路317_1來將43個移位後資料區塊進行相加來得到局部校驗碼區塊PPB_1；桶式移位器312可以分別對資料區塊DB_1~DB_43進行移位操作，並透過累加電路317_2來將43個移位後資料區塊進行相加來得到局部校驗碼區塊PPB_2；類似地，桶式移位器313、314、315可以分別對資料區塊DB_1~DB_43進行移位操作，並透過累加電路317_3、317_4、317_5來將43個移位後資料區塊進行相加來分別得到局部校驗碼區塊PPB_3、PPB_4、PPB_5。In operation of the encoder 300, first, the barrel shifter module 310 processes the data blocks DB_1~DB_43 to generate a plurality of partial parity blocks PPB_1~PPB_5. Specifically, the bucket shifter 311 can perform a shift operation on the data blocks DB_1~DB_43, respectively, and add 43 post-shifted data blocks through the accumulating circuit 317_1 to obtain a partial check code block. PPB_1; the bucket shifter 312 can perform a shift operation on the data blocks DB_1~DB_43, respectively, and add 43 post-shifted data blocks through the accumulating circuit 317_2 to obtain a partial check code block PPB_2; Similarly, the barrel shifters 313, 314, 315 can perform shift operations on the data blocks DB_1~DB_43, respectively, and add 43 shifted data blocks through the accumulation circuits 317_3, 317_4, and 317_5. The local check code blocks PPB_3, PPB_4, and PPB_5 are obtained respectively.

局部校驗碼區塊PPB_1~PPB_5會被分兩個部分以進行不同的處理，其中第一部分包含了三個局部校驗碼區塊PPB_1~PPB_3，而第二部分包含了兩個局部校驗碼區塊PPB_4~PPB_5。在第一計算電路320的操作中，循環卷積計算電路322將局部校驗碼區塊PPB_4~PPB_5進行循環卷積操作以產生兩個中間區塊；補償電路324係為一可移除(optional)的元件，且用來補償循環卷積計算電路322所輸出的兩個中間區塊；桶式移位器模組326用以對該兩個中間區塊進行處理以產生三個計算結果區塊。在本實施例中，由於桶式移位器模組326係根據兩個中間區塊來產生三個計算結果區塊，故桶式移位器模組326可以包含6個桶式移位器(2*3=6)。The local check code blocks PPB_1~PPB_5 are divided into two parts for different processing, wherein the first part contains three partial check code blocks PPB_1~PPB_3, and the second part contains two partial check codes. Block PPB_4~PPB_5. In operation of the first calculation circuit 320, the circular convolution calculation circuit 322 performs a cyclic convolution operation on the partial check code blocks PPB_4 PPBB_5 to generate two intermediate blocks; the compensation circuit 324 is a removable (optional) And an element for compensating the two intermediate blocks output by the circular convolution calculation circuit 322; the barrel shifter module 326 is configured to process the two intermediate blocks to generate three calculation result blocks . In this embodiment, since the barrel shifter module 326 generates three calculation result blocks according to the two intermediate blocks, the barrel shifter module 326 can include six barrel shifters ( 2*3=6).

調整電路330中的累加電路332、334、336將桶式移位器模組326所產生的三個計算結果區塊分別與局部校驗碼區塊PPB_1~PPB_3進行相加，以產生調整後的局部校驗碼區塊。The accumulating circuits 332, 334, and 336 in the adjusting circuit 330 add the three calculated result blocks generated by the barrel shifter module 326 to the partial check code blocks PPB_1 PPBB_3, respectively, to generate the adjusted Local check code block.

接著，循環卷積計算電路340對調整後之第一部分的局部校驗碼區塊(即PPB_1~PPB_3)進行循環卷積操作，並透過補償電路342以產生校驗碼區塊PB_1~PB_3。需注意的是，補償電路342為一可移除的元件，亦即在不需要補償的情形下可以自編碼器300中移除而不會影響到其操作。Next, the circular convolution calculation circuit 340 performs a cyclic convolution operation on the adjusted partial partial parity code block (ie, PPB_1 PP PP_3), and transmits the parity code block PB_1 P PB_3 through the compensation circuit 342. It should be noted that the compensation circuit 342 is a removable component, that is, it can be removed from the encoder 300 without compensation, without affecting its operation.

接著，在第二計算電路350的操作中，桶式移位器模組352對校驗碼區塊PB_1~PB_3進行處理以產生兩個處理後區塊；循環卷積計算電路354將兩個處理後區塊進行循環卷積操作以產生兩個輸出區塊；補償電路356係為一可移除的元件，且用來補償循環卷積計算電路354所輸出的兩個輸出區塊；累加電路357、357分別將循環卷積計算電路322或是補償電路324所產生的中間區塊與循環卷積計算電路354或是補償電路356所產生的兩個輸出區塊進行相加，以產生校驗碼區塊PB_4~PB_5。在本實施例中，由於桶式移位器模組352係根據三個校驗碼區塊PB_1~PB_3來產生兩個處理後區塊，故桶式移位器模組352可以包含6個桶式移位器(3*2=6)Next, in operation of the second calculation circuit 350, the barrel shifter module 352 processes the check code blocks PB_1~PB_3 to generate two processed blocks; the circular convolution calculation circuit 354 performs two processes. The back block performs a cyclic convolution operation to generate two output blocks; the compensation circuit 356 is a removable element and is used to compensate for the two output blocks output by the circular convolution calculation circuit 354; the accumulation circuit 357 357, respectively, the intermediate block generated by the circular convolution calculation circuit 322 or the compensation circuit 324 is added to the two output blocks generated by the circular convolution calculation circuit 354 or the compensation circuit 356 to generate a check code. Block PB_4~PB_5. In this embodiment, since the barrel shifter module 352 generates two processed blocks according to the three check code blocks PB_1~PB_3, the barrel shifter module 352 can include 6 barrels. Shifter (3*2=6)

在產生校驗碼區塊PB_1~PB_5之後，編碼器會將資料區塊DB_1~DB_43連同校驗碼區塊PB_1~PB_5一起與校驗碼檢查矩陣相乘以判斷校驗碼區塊PB_1~PB_5是否正確。若是正確，快閃記憶體控制器110便會將資料區塊DB_1~DB_43連同校驗碼區塊PB_1~PB_5一起寫入到快閃記憶體模組120的一區塊的一資料頁中。After generating the check code blocks PB_1~PB_5, the encoder multiplies the data blocks DB_1~DB_43 together with the check code blocks PB_1~PB_5 with the check code check matrix to determine the check code blocks PB_1~PB_5. is it right or not. If it is correct, the flash memory controller 110 writes the data blocks DB_1~DB_43 together with the check code blocks PB_1~PB_5 to a data page of a block of the flash memory module 120.

在第3圖所示的電路架構中，桶式移位器模組310可以被比對為第2圖所示之矩陣M，而第一計算電路320、調整電路330、循環卷積計算電路340、補償電路342以及第二計算電路350則是用來產生一個類似於第2圖所示之反矩陣K-1 的內容，以在無法確實找到反矩陣K-1 的情形下可以產生校驗碼區塊PB_1~PB_5。此外，編碼器300具有三個循環卷積計算電路322、340、354，其中循環卷積計算電路322為2*2個循環矩陣/區塊相乘，循環卷積計算電路340為3*3個循環矩陣/區塊相乘，以及循環卷積計算電路354為2*2個循環矩陣/區塊相乘，因此總和來說編碼器300的循環矩陣/區塊相乘的次數為17次(4+9+4=17)。因此，由於編碼器300只需進行17次循環矩陣/區塊相乘操作便可以產生五個校驗碼區塊，故可以確實降低編碼器300的硬體成本。In the circuit architecture shown in FIG. 3, the barrel shifter module 310 can be aligned to the matrix M shown in FIG. 2, and the first calculation circuit 320, the adjustment circuit 330, and the circular convolution calculation circuit 340 The compensation circuit 342 and the second calculation circuit 350 are used to generate a content similar to the inverse matrix K -1 shown in FIG. 2 to generate a check code in the case where the inverse matrix K -1 cannot be found. Block PB_1~PB_5. Further, the encoder 300 has three circular convolution calculation circuits 322, 340, 354, wherein the circular convolution calculation circuit 322 is 2*2 cyclic matrix/block multiplication, and the circular convolution calculation circuit 340 is 3*3 The cyclic matrix/block multiplication, and the circular convolution calculation circuit 354 multiply 2*2 cyclic matrices/blocks, so the number of times the loop matrix/block of the encoder 300 is multiplied is 17 times (4) +9+4=17). Therefore, since the encoder 300 can generate five check code blocks by performing only 17 loop matrix/block multiplication operations, the hardware cost of the encoder 300 can be surely reduced.

參考第4圖，其為根據本發明另一實施例之編碼器400的示意圖，其中編碼器400可以作為第1圖所示之編碼器132。如第4圖所示，編碼器400包含了一桶式移位器模組410、一第一計算電路420、一調整電路430、一循環卷積計算電路440、一補償電路442以及一第二計算電路450。在本實施例中，桶式移位器模組410包含了多個桶式移位器411、412、413、414、415以及多個累加電路417_1~417_5；第一計算電路420兩個桶式移位器模組422、424；調整電路430包含了多個累加電路432、434、436、438；以及第二計算電路350包含了一桶式移位器模組452以及一輸出電路424。在本實施例中，編碼器400係將來自主裝置130的一筆資料分為多個資料區塊(在本實施例中該多個資料區塊為43個資料區塊DB_1~DB_43)，並將該多個資料區塊DB_1~DB_43進行編碼後產生多個校驗碼區塊(在本實施例中該多個校驗碼區塊為5個校驗碼區塊PB_1~PB_5)。需注意的是，上述之一個資料區塊與一個校驗碼區塊的大小是相同的，且資料區塊的大小可以由設計者所自行決定，例如192*192個位元。Referring to FIG. 4, which is a schematic diagram of an encoder 400 in accordance with another embodiment of the present invention, the encoder 400 can be used as the encoder 132 shown in FIG. As shown in FIG. 4, the encoder 400 includes a barrel shifter module 410, a first calculation circuit 420, an adjustment circuit 430, a cyclic convolution calculation circuit 440, a compensation circuit 442, and a second. Calculation circuit 450. In this embodiment, the barrel shifter module 410 includes a plurality of barrel shifters 411, 412, 413, 414, 415 and a plurality of accumulation circuits 417_1 ～ 417_5; the first calculation circuit 420 has two barrels. The shifter modules 422, 424; the adjustment circuit 430 includes a plurality of accumulation circuits 432, 434, 436, 438; and the second calculation circuit 350 includes a barrel shifter module 452 and an output circuit 424. In this embodiment, the encoder 400 divides a piece of data of the autonomous device 130 into a plurality of data blocks (in the embodiment, the plurality of data blocks are 43 data blocks DB_1~DB_43), and the The plurality of data blocks DB_1~DB_43 are encoded to generate a plurality of check code blocks (in the present embodiment, the plurality of check code blocks are 5 check code blocks PB_1~PB_5). It should be noted that the size of one of the above data blocks and one of the check code blocks are the same, and the size of the data block can be determined by the designer, for example, 192*192 bits.

在編碼器400的操作中，首先，桶式移位器模組410將資料區塊DB_1~DB_43進行處理以產生多個局部校驗碼(partial parity)區塊PPB_1~PPB_5。具體來說，桶式移位器411可以分別對資料區塊DB_1~DB_43進行移位操作，並透過累加電路417_1來將43個移位後資料區塊進行相加來得到局部校驗碼區塊PPB_1；桶式移位器412可以分別對資料區塊DB_1~DB_43進行移位操作，並透過累加電路417_2來將43個移位後資料區塊進行相加來得到局部校驗碼區塊PPB_2；類似地，桶式移位器413、414、415可以分別對資料區塊DB_1~DB_43進行移位操作，並透過累加電路417_3、417_4、417_5來將43個移位後資料區塊進行相加來分別得到局部校驗碼區塊PPB_3、PPB_4、PPB_5。In operation of the encoder 400, first, the barrel shifter module 410 processes the data blocks DB_1~DB_43 to generate a plurality of partial parity blocks PPB_1~PPB_5. Specifically, the barrel shifter 411 can perform a shift operation on the data blocks DB_1~DB_43, respectively, and add 43 post-shifted data blocks through the accumulation circuit 417_1 to obtain a partial check code block. PPB_1; the bucket shifter 412 can perform a shift operation on the data blocks DB_1~DB_43, and add 43 post-shifted data blocks through the accumulating circuit 417_2 to obtain a partial check code block PPB_2; Similarly, the barrel shifters 413, 414, 415 can perform shift operations on the data blocks DB_1~DB_43, respectively, and add 43 shifted data blocks through the accumulation circuits 417_3, 417_4, and 417_5. The local check code blocks PPB_3, PPB_4, and PPB_5 are obtained respectively.

局部校驗碼區塊PPB_1~PPB_5會被分兩個部分以進行不同的處理，其中第一部分包含了四個局部校驗碼區塊PPB_1~PPB_4，而第二部分包含了一個局部校驗碼區塊PPB_5。在第一計算電路420的操作中，桶式移位器模組422對局部校驗碼區塊PPB_5進行移位操作以產生一中間區塊，且桶式移位器模組424對該中間區塊進行處理以產生四個計算結果區塊。The local check code blocks PPB_1~PPB_5 are divided into two parts for different processing, wherein the first part contains four partial check code blocks PPB_1~PPB_4, and the second part contains a partial check code area. Block PPB_5. In operation of the first computing circuit 420, the barrel shifter module 422 performs a shift operation on the partial check code block PPB_5 to generate an intermediate block, and the barrel shifter module 424 applies the intermediate block. The block is processed to produce four blocks of calculation results.

調整電路430中的累加電路432、434、436、438將桶式移位器模組424所產生的四個計算結果區塊分別與局部校驗碼區塊PPB_1~PPB_4進行相加，以產生調整後的局部校驗碼區塊。The accumulating circuits 432, 434, 436, and 438 in the adjusting circuit 430 add the four calculated result blocks generated by the barrel shifter module 424 to the partial check code blocks PPB_1 PPPPB_4, respectively, to generate an adjustment. After the local check code block.

接著，循環卷積計算電路440對調整後之第一部分的局部校驗碼區塊(即PPB_1~PPB_4)進行循環卷積操作，並透過補償電路442以產生校驗碼區塊PB_1~PB_4。需注意的是，補償電路442為一可移除的元件，亦即在不需要補償的情形下可以自編碼器400中移除而不會影響到其操作。Next, the circular convolution calculation circuit 440 performs a cyclic convolution operation on the adjusted partial partial parity code block (ie, PPB_1 PP PP_4), and transmits the parity code block PB_1 P PB_4 through the compensation circuit 442. It should be noted that the compensation circuit 442 is a removable component, that is, it can be removed from the encoder 400 without compensation, without affecting its operation.

接著，在第二計算電路450的操作中，桶式移位器模組452對校驗碼區塊PB_1~PB_4進行處理以產生一個處理後區塊；輸出電路454將桶式移位器模組422所產生的中間區塊與桶式移位器模組452所產生的輸出區塊進行相加，以產生校驗碼區塊PB_5。Next, in operation of the second calculation circuit 450, the barrel shifter module 452 processes the check code blocks PB_1~PB_4 to generate a processed block; the output circuit 454 places the barrel shifter module The intermediate block generated by 422 is added to the output block generated by the barrel shifter module 452 to generate a check code block PB_5.

在產生校驗碼區塊PB_1~PB_5之後，編碼器會將資料區塊DB_1~DB_43連同校驗碼區塊PB_1~PB_5一起與校驗碼檢查矩陣相乘以判斷校驗碼區塊PB_1~PB_5是否正確。若是正確，快閃記憶體控制器110便會將資料區塊DB_1~DB_43連同校驗碼區塊PB_1~PB_5一起寫入到快閃記憶體模組120的一區塊的一資料頁中。After generating the check code blocks PB_1~PB_5, the encoder multiplies the data blocks DB_1~DB_43 together with the check code blocks PB_1~PB_5 with the check code check matrix to determine the check code blocks PB_1~PB_5. is it right or not. If it is correct, the flash memory controller 110 writes the data blocks DB_1~DB_43 together with the check code blocks PB_1~PB_5 to a data page of a block of the flash memory module 120.

在第4圖所示的電路架構中，桶式移位器模組410可以被比對為第2圖所示之矩陣M，而第一計算電路420、調整電路430、循環卷積計算電路440、補償電路442以及第二計算電路450則是用來產生一個類似於第2圖所示之反矩陣K-1 的內容，以在無法確實找到反矩陣K-1 的情形下可以產生校驗碼區塊PB_1~PB_5。此外，編碼器400僅具有一個循環卷積計算電路440，其中循環卷積計算電路440為4*4個循環矩陣/區塊相乘。因此，由於編碼器400只需進行16次循環矩陣/區塊相乘操作便可以產生五個校驗碼區塊，故可以確實降低編碼器400的硬體成本。In the circuit architecture shown in FIG. 4, the barrel shifter module 410 can be aligned to the matrix M shown in FIG. 2, and the first calculation circuit 420, the adjustment circuit 430, and the circular convolution calculation circuit 440 The compensation circuit 442 and the second calculation circuit 450 are used to generate a content similar to the inverse matrix K -1 shown in FIG. 2 to generate a check code in the case where the inverse matrix K -1 cannot be found. Block PB_1~PB_5. Furthermore, encoder 400 has only one circular convolution calculation circuit 440, wherein circular convolution calculation circuit 440 is 4*4 cyclic matrix/block multiplication. Therefore, since the encoder 400 can generate five check code blocks by performing only 16 cycle matrix/block multiplication operations, the hardware cost of the encoder 400 can be surely reduced.

另一方面，若是校驗碼檢查矩陣中的矩陣K具有某一種特定的型式，例如矩陣K的最後一行與最後一列的數值均為“0”時，第4圖所示的編碼器400中的元件可以進一步地減少，例如以下所述之第5圖所示的實施例。On the other hand, if the matrix K in the check code check matrix has a certain type, for example, the values of the last row and the last column of the matrix K are both "0", the encoder 400 shown in FIG. The components can be further reduced, such as the embodiment shown in Figure 5 below.

參考第5圖，其為根據本發明另一實施例之編碼器500的示意圖，其中編碼器500可以作為第1圖所示之編碼器132。如第5圖所示，編碼器500包含了一桶式移位器模組510、一調整電路530、一循環卷積計算電路540、一補償電路542以及一計算電路550。在本實施例中，桶式移位器模組510包含了多個桶式移位器511、512、513、514、515以及多個累加電路517_1~517_5。在本實施例中，編碼器500係將來自主裝置130的一筆資料分為多個資料區塊(在本實施例中該多個資料區塊為43個資料區塊DB_1~DB_43)，並將該多個資料區塊DB_1~DB_43進行編碼後產生多個校驗碼區塊(在本實施例中該多個校驗碼區塊為5個校驗碼區塊PB_1~PB_5)。需注意的是，上述之一個資料區塊與一個校驗碼區塊的大小是相同的，且資料區塊的大小可以由設計者所自行決定，例如192*192個位元。Referring to Fig. 5, which is a schematic diagram of an encoder 500 in accordance with another embodiment of the present invention, an encoder 500 can be used as the encoder 132 shown in Fig. 1. As shown in FIG. 5, the encoder 500 includes a barrel shifter module 510, an adjustment circuit 530, a cyclic convolution calculation circuit 540, a compensation circuit 542, and a calculation circuit 550. In the present embodiment, the barrel shifter module 510 includes a plurality of barrel shifters 511, 512, 513, 514, 515 and a plurality of accumulation circuits 517_1 517 517_5. In this embodiment, the encoder 500 divides a piece of data of the autonomous device 130 into a plurality of data blocks (in the embodiment, the plurality of data blocks are 43 data blocks DB_1~DB_43), and the The plurality of data blocks DB_1~DB_43 are encoded to generate a plurality of check code blocks (in the present embodiment, the plurality of check code blocks are 5 check code blocks PB_1~PB_5). It should be noted that the size of one of the above data blocks and one of the check code blocks are the same, and the size of the data block can be determined by the designer, for example, 192*192 bits.

在編碼器500的操作中，首先，桶式移位器模組510將資料區塊DB_1~DB_43進行處理以產生多個局部校驗碼(partial parity)區塊PPB_1~PPB_5。具體來說，桶式移位器511可以分別對資料區塊DB_1~DB_43進行移位操作，並透過累加電路517_1來將43個移位後資料區塊進行相加來得到局部校驗碼區塊PPB_1；桶式移位器512可以分別對資料區塊DB_1~DB_43進行移位操作，並透過累加電路517_2來將43個移位後資料區塊進行相加來得到局部校驗碼區塊PPB_2；類似地，桶式移位器513、514、515可以分別對資料區塊DB_1~DB_43進行移位操作，並透過累加電路517_3、517_4、517_5來將43個移位後資料區塊進行相加來分別得到局部校驗碼區塊PPB_3、PPB_4、PPB_5。In operation of the encoder 500, first, the barrel shifter module 510 processes the data blocks DB_1~DB_43 to generate a plurality of partial parity blocks PPB_1~PPB_5. Specifically, the barrel shifter 511 can perform a shift operation on the data blocks DB_1~DB_43, respectively, and add 43 post-shifted data blocks through the accumulating circuit 517_1 to obtain a partial check code block. PPB_1; the bucket shifter 512 can perform a shift operation on the data blocks DB_1~DB_43 respectively, and add 43 post-shifted data blocks through the accumulating circuit 517_2 to obtain a partial check code block PPB_2; Similarly, the barrel shifters 513, 514, 515 can perform shift operations on the data blocks DB_1~DB_43, respectively, and add 43 shifted data blocks through the accumulation circuits 517_3, 517_4, 517_5. The local check code blocks PPB_3, PPB_4, and PPB_5 are obtained respectively.

局部校驗碼區塊PPB_1~PPB_5會被分兩個部分以進行不同的處理，其中第一部分包含了四個局部校驗碼區塊PPB_1~PPB_4，而第二部分包含了一個局部校驗碼區塊PPB_5。調整電路530中的累加電路532、534、536、538分別將局部校驗碼區塊PPB_5的內容加入到局部校驗碼區塊PPB_1~PPB_4中，以產生調整後的局部校驗碼區塊。The local check code blocks PPB_1~PPB_5 are divided into two parts for different processing, wherein the first part contains four partial check code blocks PPB_1~PPB_4, and the second part contains a partial check code area. Block PPB_5. The accumulating circuits 532, 534, 536, 538 in the adjusting circuit 530 respectively add the contents of the partial check code block PPB_5 to the partial check code blocks PPB_1 PPPPB_4 to generate an adjusted partial check code block.

接著，循環卷積計算電路540對調整後之第一部分的局部校驗碼區塊(即PPB_1~PPB_4)進行循環卷積操作，並透過補償電路542以產生校驗碼區塊PB_1~PB_4。需注意的是，補償電路542為一可移除的元件，亦即在不需要補償的情形下可以自編碼器500中移除而不會影響到其操作。Next, the circular convolution calculation circuit 540 performs a cyclic convolution operation on the adjusted partial partial parity code block (ie, PPB_1 PP PP_4), and transmits the parity code block PB_1 P PB_4 through the compensation circuit 542. It should be noted that the compensation circuit 542 is a removable component, that is, it can be removed from the encoder 500 without compensation, without affecting its operation.

接著，計算電路550將局部校驗碼區塊PPB_5與校驗碼區塊PB_1~PB_4進行相加，以產生校驗碼區塊PB_5。Next, the calculation circuit 550 adds the partial check code block PPB_5 and the check code blocks PB_1 to PB_4 to generate the check code block PB_5.

在產生校驗碼區塊PB_1~PB_5之後，編碼器會將資料區塊DB_1~DB_43連同校驗碼區塊PB_1~PB_5一起與校驗碼檢查矩陣相乘以判斷校驗碼區塊PB_1~PB_5是否正確。若是正確，快閃記憶體控制器110便會將資料區塊DB_1~DB_43連同校驗碼區塊PB_1~PB_5一起寫入到快閃記憶體模組120的一區塊的一資料頁中。After generating the check code blocks PB_1~PB_5, the encoder multiplies the data blocks DB_1~DB_43 together with the check code blocks PB_1~PB_5 with the check code check matrix to determine the check code blocks PB_1~PB_5. is it right or not. If it is correct, the flash memory controller 110 writes the data blocks DB_1~DB_43 together with the check code blocks PB_1~PB_5 to a data page of a block of the flash memory module 120.

在第5圖所示的電路架構中，桶式移位器模組510可以被比對為第2圖所示之矩陣M，而調整電路530、循環卷積計算電路540、補償電路542以及計算電路550則是用來產生一個類似於第2圖所示之反矩陣K-1 的內容，以在無法確實找到反矩陣K-1 的情形下可以產生校驗碼區塊PB_1~PB_5。此外，編碼器500僅具有一個循環卷積計算電路540，其中循環卷積計算電路540為4*4個循環矩陣/區塊相乘。因此，由於編碼器500只需進行16次循環矩陣/區塊相乘操作便可以產生五個校驗碼區塊，故可以確實降低編碼器500的硬體成本。另一方面，相較於第4圖的實施例，由於少了第一計算電路420以及第二計算電路450中的部分元件，故可以進一步地降低成本。In the circuit architecture shown in FIG. 5, the barrel shifter module 510 can be aligned to the matrix M shown in FIG. 2, and the adjustment circuit 530, the circular convolution calculation circuit 540, the compensation circuit 542, and the calculation Circuit 550 is used to generate a content similar to the inverse matrix K -1 shown in Fig. 2 to generate check code blocks PB_1 - PB_5 in the event that the inverse matrix K -1 cannot be found. Furthermore, encoder 500 has only one circular convolution calculation circuit 540, wherein circular convolution calculation circuit 540 is 4*4 cyclic matrix/block multiplication. Therefore, since the encoder 500 can generate five check code blocks by performing only 16 loop matrix/block multiplication operations, the hardware cost of the encoder 500 can be surely reduced. On the other hand, compared with the embodiment of Fig. 4, since some of the components in the first calculation circuit 420 and the second calculation circuit 450 are missing, the cost can be further reduced.

參考第6圖，其為根據本發明一實施例之一種編碼方法的流程圖，同時參考第1~6圖及以上實施例所揭露的內容，編碼方法的流程如下所述。Referring to FIG. 6, which is a flowchart of an encoding method according to an embodiment of the present invention, and referring to the contents disclosed in FIGS. 1~6 and the above embodiments, the flow of the encoding method is as follows.

步驟600：流程開始。Step 600: The process begins.

步驟602：將多個資料區塊進行處理以產生多個局部校驗碼區塊，其中該多個局部校驗碼區塊包含了一第一部分及一第二部分。Step 602: Processing a plurality of data blocks to generate a plurality of partial check code blocks, wherein the plurality of partial check code blocks comprise a first portion and a second portion.

步驟604：使用一第一計算電路以根據該第二部分以產生一第一計算結果。Step 604: Use a first calculation circuit to generate a first calculation result according to the second portion.

步驟606：根據該第一計算結果來調整該多個局部校驗碼區塊的該第一部分，以產生一調整後第一部分。Step 606: Adjust the first portion of the plurality of partial check code blocks according to the first calculation result to generate an adjusted first portion.

步驟608：對該調整後第一部分進行循環卷積操作，以產生一第一部分的校驗碼區塊。Step 608: Perform a cyclic convolution operation on the adjusted first portion to generate a first portion of the check code block.

步驟610：使用一第二計算電路以至少根據該第一部分的校驗碼區塊來產生一第二部分的校驗碼區塊，其中該第一部分的校驗碼區塊及該第二部分的校驗碼區塊係作為對該多個資料區塊進行編碼後所產生之多個校驗碼區塊。Step 610: Use a second calculating circuit to generate a second partial check code block according to at least the first part of the check code block, where the first part of the check code block and the second part The check code block is a plurality of check code blocks generated by encoding the plurality of data blocks.

簡要歸納本發明，在本發明之編碼器中，其透過將局部校驗碼區塊分為兩個部分來進行操作，以在可以確實產生校驗碼區塊的情形下降低編碼器中的循環卷積計算所需要的硬體。因此，本發明之編碼器可以避免先前技術中所述之硬體成本大幅增加的情形。 以上所述僅為本發明之較佳實施例，凡依本發明申請專利範圍所做之均等變化與修飾，皆應屬本發明之涵蓋範圍。Briefly summarized in the present invention, in the encoder of the present invention, it operates by dividing the partial check code block into two parts to reduce the loop in the encoder in the case where the check code block can be surely generated. The hardware required for convolution calculations. Therefore, the encoder of the present invention can avoid the situation in which the hardware cost described in the prior art is greatly increased. The above are only the preferred embodiments of the present invention, and all changes and modifications made to the scope of the present invention should be within the scope of the present invention.

100‧‧‧記憶裝置100‧‧‧ memory device

110‧‧‧快閃記憶體控制器110‧‧‧Flash Memory Controller

112‧‧‧微處理器112‧‧‧Microprocessor

112C‧‧‧程式碼112C‧‧‧ Code

112M‧‧‧唯讀記憶體112M‧‧‧Reading memory

114‧‧‧控制邏輯114‧‧‧Control logic

116‧‧‧緩衝記憶體116‧‧‧Buffered memory

118‧‧‧介面邏輯118‧‧‧Interface logic

120‧‧‧快閃記憶體模組120‧‧‧Flash Memory Module

130‧‧‧主裝置130‧‧‧Main device

132、300、400、500‧‧‧編碼器132, 300, 400, 500‧‧‧ encoder

134‧‧‧解碼器134‧‧‧Decoder

310、326、352、410、422、424、452、510‧‧‧桶式移位器模組310, 326, 352, 410, 422, 424, 452, 510‧‧‧ barrel shifter modules

311、312、313、314、315、411、412、413、414、415、511、512、513、514、515‧‧‧桶式移位器311, 312, 313, 314, 315, 411, 412, 413, 414, 415, 511, 512, 513, 514, 515‧‧‧ barrel shifter

317_1~317_5、332、334、336、357、358、417_1~417_5、432、434、436、438、517_1~517_5、532、534、536、538‧‧‧累加電路317_1~317_5, 332, 334, 336, 357, 358, 417_1~417_5, 432, 434, 436, 438, 517_1~517_5, 532, 534, 536, 538‧‧‧

320、420‧‧‧第一計算電路320, 420‧‧‧ first calculation circuit

322、340、354、440、540‧‧‧循環卷積計算電路322, 340, 354, 440, 540‧‧‧cyclic convolution calculation circuit

324、342、356、442、542‧‧‧補償電路324, 342, 356, 442, 542 ‧ ‧ compensation circuit

330、430、530‧‧‧調整電路330, 430, 530‧‧‧ adjustment circuit

350、450‧‧‧第二計算電路350, 450‧‧‧ second calculation circuit

454‧‧‧輸出電路454‧‧‧Output circuit

550‧‧‧計算電路550‧‧‧Computation circuit

600~610‧‧‧步驟600~610‧‧‧Steps

DB_1~DB_43‧‧‧資料區塊DB_1~DB_43‧‧‧data block

PPB_1~PPB_5‧‧‧局部校驗碼區塊PPB_1~PPB_5‧‧‧Local check code block

PB_1~PB_5‧‧‧校驗碼區塊 PB_1~PB_5‧‧‧ check code block

第1圖為依據本發明一實施例之一種記憶裝置的示意圖。 第2圖為校驗碼檢查矩陣及校驗碼產生矩陣的示意圖。 第3圖為根據本發明一實施例之編碼器的示意圖。 第4圖為根據本發明另一實施例之編碼器的示意圖。 第5圖為根據本發明另一實施例之編碼器的示意圖。 第6圖為根據本發明一實施例之一種編碼方法的流程圖。1 is a schematic diagram of a memory device in accordance with an embodiment of the present invention. Figure 2 is a schematic diagram of a check code check matrix and a check code generation matrix. Figure 3 is a schematic illustration of an encoder in accordance with an embodiment of the present invention. Figure 4 is a schematic illustration of an encoder in accordance with another embodiment of the present invention. Figure 5 is a schematic illustration of an encoder in accordance with another embodiment of the present invention. Figure 6 is a flow chart of an encoding method in accordance with an embodiment of the present invention.

Claims (10)

一種設置在一快閃記憶體控制器中的編碼器，包含有： 一第一桶式移位器模組，用以將多個資料區塊進行處理以產生多個局部校驗碼(partial parity)區塊，其中該多個局部校驗碼區塊包含了一第一部分及一第二部分； 一第一計算電路，耦接於該第一桶式移位器模組，用以根據該第二部分以產生一第一計算結果； 一第一輸出電路，用以根據該第一部分以及該第一計算結果以產生一第一部分的校驗碼區塊；以及 一第二計算電路，耦接於該第一循環卷積計算電路，用以至少根據該第一部分的校驗碼區塊以產生一第二部分的校驗碼區塊； 其中該第一部分的校驗碼區塊及該第二部分的校驗碼區塊係作為該編碼器針對該多個資料區塊所產生之多個校驗碼區塊，且該多個資料區塊以及該多個校驗碼區塊係被寫入至一快閃記憶體中。An encoder disposed in a flash memory controller includes: a first barrel shifter module for processing a plurality of data blocks to generate a plurality of partial parity codes (partial parity a block, wherein the plurality of partial check code blocks include a first portion and a second portion; a first computing circuit coupled to the first barrel shifter module for a second portion to generate a first calculation result; a first output circuit for generating a first portion of the check code block according to the first portion and the first calculation result; and a second calculation circuit coupled to The first cyclic convolution calculation circuit is configured to generate a second partial check code block according to at least the first part of the check code block; wherein the first part of the check code block and the second part The check code block is used as a plurality of check code blocks generated by the encoder for the plurality of data blocks, and the plurality of data blocks and the plurality of check code blocks are written to A flash memory. 如申請專利範圍第1項所述之編碼器，其中該第二部分包含了至少兩個局部校驗碼區塊，且該第一計算電路與該第二計算電路均包含了循環卷積操作。The encoder of claim 1, wherein the second portion includes at least two partial check code blocks, and the first calculation circuit and the second calculation circuit both comprise a cyclic convolution operation. 如申請專利範圍第2項所述之編碼器，其中該第一部分包含了C1個局部校驗碼區塊，該第二部分包含了C2個局部校驗碼區塊，且該第一計算電路包含有： 一第二循環卷積計算電路，用以將C2個局部校驗碼區塊進行循環卷積操作以產生C2個中間區塊；以及 一第二桶式移位器模組，耦接於該第二循環卷積計算電路，用以對該C2個中間區塊進行處理以產生C1個計算結果區塊以作為該第一計算結果； 其中該第一輸出電路根據該C1個計算結果區塊與該C1個局部校驗碼區塊以產生該第一部分的校驗碼區塊。The encoder of claim 2, wherein the first part comprises C1 partial check code blocks, the second part comprises C2 partial check code blocks, and the first calculation circuit comprises There is: a second circular convolution calculation circuit for performing a cyclic convolution operation on the C2 partial parity code blocks to generate C2 intermediate blocks; and a second barrel shifter module coupled to The second cyclic convolution calculation circuit is configured to process the C2 intermediate blocks to generate C1 calculation result blocks as the first calculation result; wherein the first output circuit is based on the C1 calculation result blocks And the C1 partial check code block to generate the check code block of the first part. 如申請專利範圍第3項所述之編碼器，其中該第一部分的校驗碼區塊包含了C1個校驗碼區塊，且該第二計算電路包含有： 一第三桶式移位器模組，用以對該C1個校驗碼區塊進行處理以產生C2個處理後區塊； 一第三循環卷積計算電路，耦接於該第三桶式移位器模組，用以將C2個處理後區塊進行循環卷積操作以產生C2個輸出區塊； 一第二輸出電路，耦接於該第三循環卷積計算電路，用以根據該C2個中間區塊來調整該C2個輸出區塊，以產生C2個校驗碼區塊來作為該第二部分的校驗碼區塊。The encoder of claim 3, wherein the first portion of the check code block includes C1 check code blocks, and the second calculation circuit comprises: a third barrel shifter a module for processing the C1 check code blocks to generate C2 processed blocks; a third circular convolution calculation circuit coupled to the third barrel shifter module for Performing a cyclic convolution operation on the C2 processing blocks to generate C2 output blocks; a second output circuit coupled to the third circular convolution calculation circuit for adjusting the C2 intermediate blocks C2 output blocks are used to generate C2 check code blocks as the check code block of the second part. 如申請專利範圍第1項所述之編碼器，其中該第一計算電路以及該第二計算電路均不包含任何的循環卷積操作。The encoder of claim 1, wherein the first computing circuit and the second computing circuit do not include any cyclic convolution operations. 如申請專利範圍第5項所述之編碼器，其中該第一部分包含了C1個局部校驗碼區塊，該第二部分包含了C2個局部校驗碼區塊，C2等於1，且該第一計算電路包含有： 一第二桶式移位器模組，用以對該C2個局部校驗碼區塊進行處理以產生C1個計算結果區塊以作為該第一計算結果； 其中該第一輸出電路根據該C1個計算結果區塊以及該C1個局部校驗碼區塊以產生該第一部分的校驗碼區塊。The encoder of claim 5, wherein the first part comprises C1 partial check code blocks, the second part comprises C2 partial check code blocks, C2 is equal to 1, and the A calculation circuit includes: a second barrel shifter module for processing the C2 partial check code blocks to generate C1 calculation result blocks as the first calculation result; wherein the An output circuit generates the first portion of the check code block according to the C1 calculation result block and the C1 local check code block. 如申請專利範圍第6項所述之編碼器，其中該第一部分的校驗碼區塊包含了C1個校驗碼區塊，且該第二計算電路包含有： 一第三桶式移位器模組，用以對該C1個校驗碼區塊進行處理以產生C2個處理後區塊； 一第二輸出電路，耦接於該第三桶式移位器模組，用以根據該C2個中間區塊來調整該C2個輸出區塊，以產生C2個校驗碼區塊來作為該第二部分的校驗碼區塊。The encoder of claim 6, wherein the first portion of the check code block includes C1 check code blocks, and the second calculation circuit comprises: a third barrel shifter a module for processing the C1 check code blocks to generate C2 processed blocks; a second output circuit coupled to the third barrel shifter module for using the C2 The intermediate block adjusts the C2 output blocks to generate C2 check code blocks as the check code block of the second part. 如申請專利範圍第1項所述之編碼器，其為在該快閃記憶體控制器中的一低密度奇偶檢查碼（Low-Density Parity Check code，LDPC code）編碼電路。The encoder of claim 1, which is a low-density parity check code (LDPC code) encoding circuit in the flash memory controller. 一種快閃記憶體控制器，該快閃記憶體控制器係用來存取一快閃記憶體模組，且該快閃記憶體控制器包含有： 一記憶體，用來儲存一程式碼； 一微處理器，用來執行該程式碼以控制對該快閃記憶體模組之存取；以及 一編碼器，用以對多個資料區塊進行編碼以得到多個校驗碼區塊，其中該編碼器包含有： 一第一桶式移位器模組，用以將該多個資料區塊進行處理以產生多個局部校驗碼(partial parity)區塊，其中該多個局部校驗碼區塊包含了一第一部分及一第二部分； 一第一計算電路，耦接於該第一桶式移位器模組，用以根據該第二部分以產生一第一計算結果； 一輸出電路，用以根據該第一部分以及該第一計算結果以產生一第一部分的校驗碼區塊；以及 一第二計算電路，耦接於該第一循環卷積計算電路，用以至少根據該第一部分的校驗碼區塊以產生一第二部分的校驗碼區塊； 其中該第一部分的校驗碼區塊及該第二部分的校驗碼區塊係作為該編碼器針對該多個資料區塊所產生之多個校驗碼區塊。A flash memory controller is used to access a flash memory module, and the flash memory controller includes: a memory for storing a code; a microprocessor for executing the code to control access to the flash memory module; and an encoder for encoding the plurality of data blocks to obtain a plurality of check code blocks, The encoder includes: a first barrel shifter module configured to process the plurality of data blocks to generate a plurality of partial parity blocks, wherein the plurality of partial parity blocks The code block includes a first portion and a second portion; a first calculation circuit coupled to the first barrel shifter module for generating a first calculation result according to the second portion; An output circuit for generating a first portion of the check code block according to the first portion and the first calculation result; and a second calculation circuit coupled to the first circular convolution calculation circuit for at least Generating a block according to the check code block of the first part a check code block of the second part; wherein the check code block of the first part and the check code block of the second part are used as a plurality of check codes generated by the encoder for the plurality of data blocks Block. 如申請專利範圍第9項所述之快閃記憶體控制器，其中該第二部分包含了至少兩個局部校驗碼區塊，且該第一計算電路與該第二計算電路均包含了循環卷積操作。The flash memory controller of claim 9, wherein the second portion includes at least two partial check code blocks, and the first calculation circuit and the second calculation circuit both include a loop Convolution operation.
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