TWI711279B

TWI711279B - Encoder and associated encoding method and flash memory controller

Info

Publication number: TWI711279B
Application number: TW108137044A
Authority: TW
Inventors: 郭軒豪
Original assignee: 慧榮科技股份有限公司
Priority date: 2018-10-12
Filing date: 2018-10-12
Publication date: 2020-11-21
Also published as: TW202015347A

Abstract

The present invention provides an encoder of a flash memory controller, where the encoder includes a barrel shifter module, an inverse matrix calculating circuit and a calculating circuit. In the operations of the encoder, the barrel shifter module processes a plurality of data blocks to generate a plurality of partial parity blocks including a first portion, a second portion and a third portion; the inverse matrix calculating circuit performs an inverse matrix calculating operations upon the first portion to generate a first portion of parity blocks; and the calculating circuit performs an inverse matrix calculating operations upon the second portion and the third portion according to the first portion of the parity blocks, to generate a second portion of the parity blocks and a third portion of the parity of blocks, wherein the first portion of the parity blocks, the second portion of the parity blocks, and the third portion of the parity of blocks serve as a plurality of parity blocks generated in response to encoding the data blocks.

Description

編碼器及相關的編碼方法與快閃記憶體控制器 Encoder and related encoding method and flash memory controller

本發明係有關於編碼器，尤指一種應用在快閃記憶體控制器中的編碼器。 The present invention relates to an encoder, especially an encoder used in a flash memory controller.

在一般的編碼器中，會具有一個校驗碼檢查矩陣(parity-check matrix)，以供編碼器檢查所產生出來的校驗碼是否正確。舉例來說，編碼器在對資料進行編碼以產生校驗碼之後，會將資料與校驗碼和此校驗碼檢查矩陣進行相乘，而若是相乘結果等於“0”則判斷編碼正確；而若是相乘結果不等於“0”則判斷編碼錯誤。因應此校驗碼檢查矩陣，編碼器會具有一相對應的校驗碼產生矩陣以供產生適合的校驗碼，然而，在某些情況下，校驗碼產生矩陣可能無法被找到，因此編碼器會需要進行多個矩陣乘法操作及/或補償/調整操作，以產生類似使用校驗碼產生矩陣所產生的校驗碼，因此會增加編碼器的複雜度。特別地，上述多個矩陣乘法操作通常會包含循環卷積(circulant convolution)計算，因此更會大幅增加編碼器的硬體成本。 In general encoders, there will be a parity-check matrix for the encoder to check whether the generated parity-check matrix is correct. For example, after the encoder encodes the data to generate the check code, it multiplies the data with the check code and the check code check matrix, and if the multiplication result is equal to "0", it judges that the code is correct; And if the result of the multiplication is not equal to "0", then the coding error is judged. In response to this check code check matrix, the encoder will have a corresponding check code generation matrix for generating a suitable check code. However, in some cases, the check code generation matrix may not be found, so the code The encoder may need to perform multiple matrix multiplication operations and/or compensation/adjustment operations to generate a check code similar to that generated by using a check code to generate a matrix, thus increasing the complexity of the encoder. In particular, the above-mentioned multiple matrix multiplication operations usually include circulant convolution calculations, which will greatly increase the hardware cost of the encoder.

因此，本發明的目的之一在於提出一種編碼器，其可以降低編碼器中的循環卷積計算所需要的硬體，以避免先前技術中所述之硬體成本大幅增加的情形。 Therefore, one of the objectives of the present invention is to provide an encoder which can reduce the The hardware required for the circular convolution calculation in, to avoid the substantial increase in hardware costs described in the prior art.

在本發明的一個實施例中，揭露了一種應用在一快閃記憶體控制器中的編碼器，其包含有一桶式移位器模組、一反矩陣計算電路以及一計算電路。在該編碼器的操作中，該桶式移位器模組用以將多個資料區塊進行處理以產生多個局部校驗碼區塊，其中該多個局部校驗碼區塊包含了一第一部分、一第二部分以及一第三部分；該第一反矩陣計算電路耦接於該桶式移位器模組，且用以對該第一部分進行反矩陣運算以產生一第一部分的校驗碼區塊；該計算電路耦接於該桶式移位器模組以及該調整電路，且用以根據該第一部分的校驗碼區塊來對該第二部分以及該第三部分進行反矩陣運算，以產生一第二部分的校驗碼區塊以及一第三部分的校驗碼區塊；其中該第一部分的校驗碼區塊、該第二部分的校驗碼區塊以及該第三部分的校驗碼區塊係作為該編碼器針對該多個資料區塊所產生之多個校驗碼區塊，且該多個資料區塊以及該多個校驗碼區塊係被寫入至一快閃記憶體中。 In one embodiment of the present invention, an encoder applied in a flash memory controller is disclosed, which includes a barrel shifter module, an inverse matrix calculation circuit, and a calculation circuit. In the operation of the encoder, the barrel shifter module is used to process a plurality of data blocks to generate a plurality of partial check code blocks, wherein the plurality of partial check code blocks include a A first part, a second part and a third part; the first inverse matrix calculation circuit is coupled to the barrel shifter module, and is used to perform an inverse matrix operation on the first part to generate a first part of the calibration Check code block; the calculation circuit is coupled to the barrel shifter module and the adjustment circuit, and is used to reverse the second part and the third part according to the check code block of the first part Matrix operation to generate a second part of the check code block and a third part of the check code block; wherein the first part of the check code block, the second part of the check code block and the The check code block of the third part is used as the check code block generated by the encoder for the multiple data blocks, and the multiple data blocks and the multiple check code blocks are Write to a flash memory.

在本發明的另一個實施例中，揭露了一種快閃記憶體控制器，其中該快閃記憶體控制器係用來存取一快閃記憶體模組，且該快閃記憶體控制器包含有一記憶體、一微處理器以及一編碼器，其中該記憶體用來儲存一程式碼，該微處理器用來執行該程式碼以控制對該快閃記憶體模組之存取，以及該編碼器用以對該多個資料區塊進行編碼以得到多個校驗碼區塊。該編碼器包含有一桶式移位器模組、一反矩陣計算電路以及一計算電路。在該編碼器的操作中，該桶式移位器模組用以將多個資料區塊進行處理以產生多個局部校驗碼區塊，其中該多個局部校驗碼區塊包含了一第一部分、一第二部分以及一第三部分；該第一反矩陣計算電路耦接於該桶式移位器模組，且用以對該第一部分進行反矩陣運算以產生一第一部分的校驗碼區塊；該計算電路耦接於該桶式移位器模組以及該調整電路，且用以根據該第一部分的校驗碼區塊來對該第二部分以及該第三部分進行反矩陣運算，以產生一第二部分的校驗碼區塊以及一第三部分的校驗碼區塊；其中該第一部分的校驗碼區塊、該第二部分的校驗碼區塊以及該第三部分的校驗碼區塊係作為該編碼器針對該多個資料區塊所產生之多個校驗碼區塊，且該多個資料區塊以及該多個校驗碼區塊係被寫入至一快閃記憶體中。 In another embodiment of the present invention, a flash memory controller is disclosed, wherein the flash memory controller is used to access a flash memory module, and the flash memory controller includes There is a memory, a microprocessor and an encoder, wherein the memory is used to store a program code, the microprocessor is used to execute the program code to control access to the flash memory module, and the code The device is used to encode the multiple data blocks to obtain multiple check code blocks. The encoder includes a barrel shifter module, an inverse matrix calculation circuit, and a calculation circuit. In the operation of the encoder, the barrel shifter module is used to process a plurality of data blocks to generate a plurality of partial check code blocks, wherein the plurality of partial check code blocks include a Part one, part two and part three; The first inverse matrix calculation circuit is coupled to the barrel shifter module, and is used to perform an inverse matrix operation on the first part to generate a check code block of the first part; the calculation circuit is coupled to the barrel Type shifter module and the adjustment circuit, and used to perform inverse matrix operation on the second part and the third part according to the check code block of the first part to generate a check code of the second part Block and a third part of the check code block; wherein the first part of the check code block, the second part of the check code block and the third part of the check code block are used as the code The device generates a plurality of check code blocks for the plurality of data blocks, and the plurality of data blocks and the plurality of check code blocks are written into a flash memory.

在本發明的另一個實施例中，揭露了一種應用在一快閃記憶體控制器的編碼方法，其包含有以下步驟：將多個資料區塊進行處理以產生多個局部校驗碼區塊，其中該多個局部校驗碼區塊包含了一第一部分、一第二部分以及一第三部分；對該第一部分進行反矩陣運算以產生一第一部分的校驗碼區塊；根據該第一部分的校驗碼區塊來對該第二部分以及該第三部分進行反矩陣運算，以產生一第二部分的校驗碼區塊以及一第三部分的校驗碼區塊，其中該第一部分的校驗碼區塊、該第二部分的校驗碼區塊以及該第三部分的校驗碼區塊係作為該編碼器針對該多個資料區塊所產生之多個校驗碼區塊；以及將該多個資料區塊以及該多個校驗碼區塊係寫入至一快閃記憶體中。 In another embodiment of the present invention, an encoding method applied to a flash memory controller is disclosed, which includes the following steps: processing multiple data blocks to generate multiple local check code blocks , Wherein the multiple partial check code blocks include a first part, a second part, and a third part; perform an inverse matrix operation on the first part to generate a first part check code block; according to the first part Part of the check code block to perform inverse matrix operation on the second part and the third part to generate a second part of the check code block and a third part of the check code block, wherein the first part A part of the check code block, the second part of the check code block, and the third part of the check code block are used as a plurality of check code areas generated by the encoder for the plurality of data blocks Block; and the plurality of data blocks and the plurality of check code blocks are written into a flash memory.

100:記憶裝置 100: memory device

110:快閃記憶體控制器 110: Flash memory controller

112:微處理器 112: Microprocessor

112C:程式碼 112C: Code

112M:唯讀記憶體 112M: Read only memory

114:控制邏輯 114: Control logic

116:緩衝記憶體 116: buffer memory

118:介面邏輯 118: Interface logic

120:快閃記憶體模組 120: Flash memory module

130:主裝置 130: main device

132、300、400、500:編碼器 132, 300, 400, 500: encoder

134:解碼器 134: Decoder

302、304:區域 302, 304: area

400:編碼器 400: encoder

410:桶式移位器模組 410: Barrel shifter module

420:第一反矩陣計算電路 420: The first inverse matrix calculation circuit

430、440:計算電路 430, 440: calculation circuit

431、434、435、441:桶式移位器模組 431, 434, 435, 441: Barrel shifter module

432:第一調整電路 432: first adjustment circuit

433:第二反矩陣計算電路 433: Second Inverse Matrix Calculation Circuit

436:第二調整電路 436: second adjustment circuit

437:第三反矩陣計算電路 437: Third Inverse Matrix Calculation Circuit

442:第四反矩陣計算電路 442: The fourth inverse matrix calculation circuit

443:第三調整電路 443: third adjustment circuit

500~508:步驟 500~508: steps

DB_1~DB_N:資料區塊 DB_1~DB_N: data block

PB_a、PB_s、PB_b:校驗碼區塊 PB_a, PB_s, PB_b: check code block

第1圖為依據本發明一實施例之一種記憶裝置的示意圖。 FIG. 1 is a schematic diagram of a memory device according to an embodiment of the invention.

第2圖為校驗碼檢查矩陣及校驗碼產生矩陣的示意圖。 Figure 2 is a schematic diagram of the check code check matrix and the check code generation matrix.

第3圖為矩陣K的示意圖。 Figure 3 is a schematic diagram of the matrix K.

第4圖為根據本發明一實施例之編碼器的示意圖。 Figure 4 is a schematic diagram of an encoder according to an embodiment of the invention.

第5圖為根據本發明一實施例之一種編碼方法的流程圖。 Figure 5 is a flowchart of an encoding method according to an embodiment of the present invention.

第1圖為依據本發明一實施例之一種記憶裝置100的示意圖。記憶裝置100包含有一快閃記憶體(Flash Memory)模組120以及一快閃記憶體控制器110，且快閃記憶體控制器110用來存取快閃記憶體模組120。依據本實施例，快閃記憶體控制器110包含一微處理器112、一唯讀記憶體(Read Only Memory,ROM)112M、一控制邏輯114、一緩衝記憶體116、與一介面邏輯118。唯讀記憶體112M係用來儲存一程式碼112C，而微處理器112則用來執行程式碼112C以控制對快閃記憶體模組120之存取(Access)。控制邏輯114包含了一編碼器132以及一解碼器134，其中編碼器132用來對寫入到快閃記憶體模組120中的資料進行編碼以產生對應的校驗碼(或稱，錯誤更正碼(Error Correction Code)，ECC)，而解碼器134用來將從快閃記憶體模組120所讀出的資料進行解碼。 FIG. 1 is a schematic diagram of a memory device 100 according to an embodiment of the invention. The memory device 100 includes a flash memory (Flash Memory) module 120 and a flash memory controller 110, and the flash memory controller 110 is used to access the flash memory module 120. According to this embodiment, the flash memory controller 110 includes a microprocessor 112, a read-only memory (ROM) 112M, a control logic 114, a buffer memory 116, and an interface logic 118. The read-only memory 112M is used to store a program code 112C, and the microprocessor 112 is used to execute the program code 112C to control access to the flash memory module 120. The control logic 114 includes an encoder 132 and a decoder 134. The encoder 132 is used to encode the data written in the flash memory module 120 to generate a corresponding check code (or, error correction). Code (Error Correction Code, ECC), and the decoder 134 is used to decode the data read from the flash memory module 120.

於典型狀況下，快閃記憶體模組120包含了多個快閃記憶體晶片，而每一個快閃記憶體晶片包含複數個區塊(Block)，而該控制器(例如：透過微處理器112執行程式碼112C之快閃記憶體控制器110)對快閃記憶體模組120進行複製、抹除、合併資料等運作係以區塊為單位來進行複製、抹除、合併資料。另外，一區塊可記錄特定數量的資料頁(Page)，其中該控制器(例如：透過微處理器112執行程式碼112C之記憶體控制器110)對快閃記憶體模組120進行寫入資料之運作係以資料頁為單位來進行寫入。 In a typical situation, the flash memory module 120 includes a plurality of flash memory chips, and each flash memory chip includes a plurality of blocks, and the controller (for example, through a microprocessor) 112. The flash memory controller 110 that executes the program code 112C) copies, erases, and merges data on the flash memory module 120. The operations such as copying, erasing, and merging data are performed in units of blocks. In addition, a block can record a specific number of pages, in which the controller (for example, the memory controller 110 executing the program code 112C through the microprocessor 112) writes the flash memory module 120 The operation of the data is to write in the data page unit.

實作上，透過微處理器112執行程式碼112C之快閃記憶體控制器110 可利用其本身內部之元件來進行諸多控制運作，例如：利用控制邏輯114來控制快閃記憶體模組120之存取運作(尤其是對至少一區塊或至少一資料頁之存取運作)、利用緩衝記憶體116進行所需之緩衝處理、以及利用介面邏輯118來與一主裝置(Host Device)130溝通。 In practice, the flash memory controller 110 that executes the program code 112C through the microprocessor 112 It can use its own internal components to perform many control operations, for example: use the control logic 114 to control the access operations of the flash memory module 120 (especially the access operations to at least one block or at least one data page) , Use the buffer memory 116 to perform the required buffer processing, and use the interface logic 118 to communicate with a host device 130.

在一實施例中，記憶裝置100可以是可攜式記憶裝置(例如：符合SD/MMC、CF、MS、XD標準之記憶卡)，且主裝置130為一可與記憶裝置連接的電子裝置，例如手機、筆記型電腦、桌上型電腦...等等。而在另一實施例中，記憶裝置100可以設置在一電子裝置中，例如設置在手機、筆記型電腦、桌上型電腦之中，而此時主裝置130可以是該電子裝置的一處理器。 In one embodiment, the memory device 100 may be a portable memory device (for example, a memory card conforming to SD/MMC, CF, MS, and XD standards), and the main device 130 is an electronic device that can be connected to the memory device. Such as mobile phones, laptops, desktop computers... etc. In another embodiment, the memory device 100 may be installed in an electronic device, such as a mobile phone, a notebook computer, or a desktop computer, and the main device 130 may be a processor of the electronic device. .

在本實施例中，編碼器132為一低密度奇偶檢查碼(Low-Density Parity Check code，LDPC code)編碼電路，且可以根據來自主裝置130的資料來產生對應的校驗碼，且所產生的校驗碼符合一校驗碼檢查矩陣。具體來說，參考第2圖，假設該校驗碼檢查矩陣為一大小為c*t的矩陣(例如，c=5，t=48，或是其他任意適合的數值)，而該校驗碼檢查矩陣可以分為左側的矩陣M(大小為c*(t-c))以及右側的矩陣K(大小為c*c)，為了找出與該校驗碼檢查矩陣所對應的校驗碼產生矩陣，可以先找出矩陣K的反矩陣K^-1(inverse matrix)，之後再將反矩陣(K^-1)與矩陣M相乘以得到矩陣P，而矩陣P的轉置矩陣(transpose matrix)便可以作為校驗碼產生矩陣。換句話說，在找到矩陣P的轉置矩陣之後，編碼器132可以將來自主裝置130的資料乘以矩陣P的轉置矩陣來得到對應於該些資料的校驗碼，而編碼器之後再將資料與校驗碼一起乘上該校驗碼檢查矩陣以判斷校驗碼是否正確。舉例來說，若是相乘結果等於“0”則判斷編碼正確；而若是相乘結果不等於“0”則判斷編碼錯誤。在判斷編碼正確之後，資料與對應的校驗碼便會被寫入至快閃記憶體模組120中的一個資料頁中。 In this embodiment, the encoder 132 is a Low-Density Parity Check code (LDPC code) encoding circuit, and can generate a corresponding check code based on the data from the main device 130, and the generated The check code conforms to a check code check matrix. Specifically, referring to Figure 2, assume that the check code check matrix is a matrix of size c*t (for example, c=5, t=48, or any other suitable value), and the check code The check matrix can be divided into the matrix M on the left (size c*(tc)) and the matrix K on the right (size c*c). In order to find the check code generation matrix corresponding to the check code check matrix, You can find the inverse matrix K ^-1 (inverse matrix) of matrix K first, and then multiply the inverse matrix (K ^-1 ) with matrix M to get matrix P, and the transpose matrix of matrix P can be Generate matrix as check code. In other words, after finding the transposed matrix of matrix P, the encoder 132 can multiply the data of the autonomous device 130 by the transposed matrix of matrix P to obtain the check code corresponding to the data, and the encoder will then The data and the check code are multiplied by the check code check matrix to determine whether the check code is correct. For example, if the multiplication result is equal to "0", it is judged that the encoding is correct; if the multiplication result is not equal to "0", it is judged that the encoding is wrong. After the code is judged to be correct, the data and the corresponding check code will be written into a data page in the flash memory module 120.

需注意的是上述該校驗碼檢查矩陣的每一個單元都在實作上為一區塊，而該區塊可以是一個方陣(例如64*64的矩陣或是192*192的矩陣)，亦即該校驗碼檢查矩陣包含了c*t個區塊。 It should be noted that each unit of the check code check matrix mentioned above is implemented as a block, and the block can be a square matrix (for example, a 64*64 matrix or a 192*192 matrix). That is, the check code check matrix contains c*t blocks.

然而，在某些情況下，反矩陣K^-1可能無法被輕易找到，因此編碼器132會需要進行多個矩陣乘法操作及/或補償/調整操作來得到一個類似反矩陣K^-1的內容，以供找出校驗碼產生矩陣來產生校驗碼。本發明因此提出了一種電路架構，以使得編碼器132可以在盡可能節省硬體成本的情形下完成編碼器132的操作。需注意的是，編碼器132中有關於編碼的過程涉及許多複雜的數學運算，但由於本發明的重點是在於電路架構的設計，故相關的矩陣內容及推導過程的細節在此不予贅述。 However, in some cases, the inverse matrix K ^-1 may not be easily found, so the encoder 132 will need to perform multiple matrix multiplication operations and/or compensation/adjustment operations to obtain a content similar to the inverse matrix K ^-1 In order to find the check code generation matrix to generate the check code. The present invention therefore proposes a circuit architecture so that the encoder 132 can complete the operation of the encoder 132 while saving hardware costs as much as possible. It should be noted that the encoding process in the encoder 132 involves many complex mathematical operations, but since the focus of the present invention is the design of the circuit architecture, the related matrix content and the details of the derivation process will not be repeated here.

第3圖為根據本發明一實施例之矩陣K的示意圖。其中矩陣K的行與列可以分別被區分為三段，而每一段分別具有a個區塊、s個區塊以及b個區塊。在本實施例中，第3圖所示之矩陣K的最右上角的區域302是空白區域，亦即區域302內的所有區塊中的所有數值均為“0”；斜線部分的區域304則是一個非零區域，亦即區域304內的所有區塊都一定包含了一個非零的數值；此外，矩陣K的其他區域則不限於空白區域或是非零區域。以下所示之編碼器132係針對第3圖所示的矩陣K來進行設計，但本發明並不以此為限。 Figure 3 is a schematic diagram of a matrix K according to an embodiment of the invention. The rows and columns of the matrix K can be divided into three sections, and each section has a block, s block, and b block. In this embodiment, the area 302 in the upper right corner of the matrix K shown in Figure 3 is a blank area, that is, all the values in all the blocks in the area 302 are "0"; the area 304 in the diagonal line is It is a non-zero area, that is, all blocks in the area 304 must contain a non-zero value; in addition, other areas of the matrix K are not limited to blank areas or non-zero areas. The encoder 132 shown below is designed for the matrix K shown in FIG. 3, but the present invention is not limited to this.

第4圖，其為根據本發明一實施例之編碼器400的示意圖，其中編碼器400可以作為第1圖所示之編碼器132。如第4圖所示，編碼器400包含了一桶式移位器模組410、一第一反矩陣計算電路420以及一計算電路430，其中計算電路430包含了三個桶式移位器模組431、434與435、一第一調整電路432、一第二反矩陣計算電路433、一第二調整電路436、一第三反矩陣計算電路437以及一計算電路440，其中計算電路440包含了一桶式移位器模組441、一第四反矩陣計算電路442以及一第三調整電路443。在本實施例中，桶式移位器模組410、431、434、435、441可以使用多個桶式移位器以及多個累加電路來實作，而第一反矩陣計算電路420、第二反矩陣計算電路433、第三反矩陣計算電路437以及第四反矩陣計算電路442則可以使用循環卷積計算電路以及補償電路來實作。在本實施例中，編碼器400係將來自主裝置130的一筆資料分為多個資料區塊(在本實施例中該多個資料區塊為N個資料區塊DB_1~DB_N)，並將該多個資料區塊DB_1~DB_N進行編碼後產生多個校驗碼區塊(在本實施例中該多個校驗碼區塊為(a+s+b)個校驗碼區塊PB_a、PB_s、PB_b)。需注意的是，上述之一個資料區塊與一個校驗碼區塊的大小是相同的，且資料區塊的大小可以由設計者所自行決定，例如64*64個位元或是192*192個位元。 Fig. 4 is a schematic diagram of an encoder 400 according to an embodiment of the present invention, where the encoder 400 can be used as the encoder 132 shown in Fig. 1. As shown in Figure 4, the encoder 400 contains a barrel Shifter module 410, a first inverse matrix calculation circuit 420, and a calculation circuit 430. The calculation circuit 430 includes three barrel shifter modules 431, 434 and 435, a first adjustment circuit 432, and a calculation circuit 430. A second inverse matrix calculation circuit 433, a second adjustment circuit 436, a third inverse matrix calculation circuit 437, and a calculation circuit 440, wherein the calculation circuit 440 includes a barrel shifter module 441 and a fourth inverse matrix Calculation circuit 442 and a third adjustment circuit 443. In this embodiment, the barrel shifter modules 410, 431, 434, 435, and 441 can be implemented using multiple barrel shifters and multiple accumulating circuits, and the first inverse matrix calculation circuit 420, the second The second inverse matrix calculation circuit 433, the third inverse matrix calculation circuit 437, and the fourth inverse matrix calculation circuit 442 can be implemented using a cyclic convolution calculation circuit and a compensation circuit. In this embodiment, the encoder 400 divides a piece of data from the autonomous device 130 into multiple data blocks (in this embodiment, the multiple data blocks are N data blocks DB_1~DB_N), and divide the data After multiple data blocks DB_1~DB_N are encoded, multiple check code blocks are generated (in this embodiment, the multiple check code blocks are (a+s+b) check code blocks PB_a, PB_s , PB_b). It should be noted that the size of a data block and a check code block mentioned above are the same, and the size of the data block can be determined by the designer, such as 64*64 bits or 192*192 Bits.

在編碼器400的操作中，首先，桶式移位器模組410將資料區塊DB_1~DB_N進行處理以產生多個局部校驗碼(partial parity)區塊。具體來說，桶式移位器模組410可以透過內部的第一個桶式移位器分別對資料區塊DB_1~DB_N進行移位操作，並透過累加電路來將移位後資料區塊進行相加來得到第一個局部校驗碼區塊；接著，透過內部的第二個桶式移位器分別對資料區塊DB_1~DB_N進行移位操作，並透過累加電路來將移位後資料區塊進行相加來得到第二個局部校驗碼區塊...以此類推，桶式移位器模組410共產生(a+s+b)個局部校驗碼區塊。 In the operation of the encoder 400, first, the barrel shifter module 410 processes the data blocks DB_1 to DB_N to generate a plurality of partial parity blocks. Specifically, the barrel shifter module 410 can perform shift operations on the data blocks DB_1~DB_N respectively through the internal first barrel shifter, and perform shift operations on the shifted data blocks through the accumulation circuit. Add up to get the first partial check code block; then, the data blocks DB_1~DB_N are respectively shifted through the internal second barrel shifter, and the shifted data is transferred through the accumulation circuit The blocks are added to obtain the second partial check code block... and so on, the barrel shifter module 410 generates (a+s+b) partial check code blocks in total.

局部校驗碼區塊會被分三個部分以進行不同的處理，其中第一部分包含了a個局部校驗碼區塊、第二部分包含了s個局部校驗碼區塊、而第三部分包含了b個局部校驗碼區塊。在第一反矩陣計算電路420的操作中，其對該a個局部校驗碼區塊進行反矩陣運算(亦即，循環卷積操作以及補償運算)，以產生a個校驗碼區塊PB_a。接著，計算電路430根據該a個校驗碼區塊PB_a、該s個局部校驗碼區塊以及該b個局部校驗碼區塊來產生s個校驗碼區塊PB_s以及b個校驗碼區塊PB_b。 The partial check code block will be divided into three parts for different processing. The first part contains a partial check code block, the second part contains s partial check code blocks, and the third part Contains b local check code blocks. In the operation of the first inverse matrix calculation circuit 420, it performs an inverse matrix operation (that is, a cyclic convolution operation and a compensation operation) on the a local check code block to generate a check code block PB_a . Next, the calculation circuit 430 generates s check code blocks PB_s and b check codes according to the a check code blocks PB_a, the s local check code blocks, and the b local check code blocks. Code block PB_b.

詳細來說，首先，桶式移位器模組431會對該a個校驗碼區塊PB_a進行處理以產生b個處理後區塊，之後第一調整電路432將該b個處理後區塊與該b個局部校驗碼區塊相加以產生一調整後第三部分資料。接著，第二反矩陣計算電路433對該調整後第三部分資料進行反矩陣運算以產生一第一運算結果，桶式移位器模組435對該a個校驗碼區塊PB_a進行處理以產生s個第一處理後區塊，桶式移位器模組434對該第一運算結果進行處理以產生s個第二處理後區塊，且第二調整電路436將該s個第一處理後區塊、該s個第二處理後區塊以及該s個局部校驗碼區塊相加以產生一調整後第二部分資料。接著，第三反矩陣計算電路437對該調整後第二部分資料進行反矩陣運算以產生該s個校驗碼區塊PB_s。接著，桶式移位器模組441對該s個校驗碼區塊PB_s結果進行處理以產生b個處理後區塊，第四反矩陣計算電路442對該b個處理後區塊進行反矩陣運算以產生一第二運算結果，以及第三調整電路443根據該第一運算結果以及該第二運算結果以產生該b個校驗碼區塊PB_b。 In detail, first, the barrel shifter module 431 processes the a check code block PB_a to generate b processed blocks, and then the first adjustment circuit 432 performs the b processed blocks Add the b local check code blocks to generate an adjusted third part of data. Next, the second inverse matrix calculation circuit 433 performs an inverse matrix operation on the adjusted third part of the data to generate a first operation result, and the barrel shifter module 435 processes the a check code block PB_a to S first processed blocks are generated, the barrel shifter module 434 processes the first operation result to generate s second processed blocks, and the second adjustment circuit 436 processes the s first blocks The post block, the s second processed blocks, and the s partial check code blocks are added together to generate an adjusted second part of data. Then, the third inverse matrix calculation circuit 437 performs an inverse matrix operation on the adjusted second part of data to generate the s check code blocks PB_s. Then, the barrel shifter module 441 processes the results of the s check code blocks PB_s to generate b processed blocks, and the fourth inverse matrix calculation circuit 442 performs inverse matrix on the b processed blocks Operate to generate a second operation result, and the third adjustment circuit 443 generates the b check code blocks PB_b according to the first operation result and the second operation result.

在產生校驗碼區塊PB_a、PB_s、PB_b之後，編碼器300會將資料區塊DB_1~DB_N連同校驗碼區塊PB_a、PB_s、PB_b一起與校驗碼檢查矩陣相乘以判斷校驗碼區塊PB_a、PB_s、PB_b是否正確。若是正確，快閃記憶體控制器110便會將資料區塊DB_1~DB_N連同校驗碼區塊PB_a、PB_s、PB_b一起寫入到快閃記憶體模組120的一區塊的一資料頁中。 After generating the check code blocks PB_a, PB_s, PB_b, the encoder 300 multiplies the data blocks DB_1~DB_N together with the check code blocks PB_a, PB_s, PB_b with the check code check matrix To determine whether the check code blocks PB_a, PB_s, and PB_b are correct. If it is correct, the flash memory controller 110 will write the data blocks DB_1~DB_N together with the check code blocks PB_a, PB_s, PB_b into a data page of a block of the flash memory module 120 .

在第4圖所示的電路架構中，桶式移位器模組410可以被比對為第2圖所示之矩陣M，而第一反矩陣計算電路420以及計算電路430則是用來產生一個類似於第2圖所示之反矩陣K^-1的內容，以在無法確實找到反矩陣K^-1的情形下可以產生校驗碼區塊PB_a、PB_s、PB_b。此外，編碼器400在實作上可以大幅降低循環卷積計算電路(包含於反矩陣計算電路中)的數量。舉例來說，假設K為10*10的方陣，且a=4、s=1、=5，則先前技術中編碼器所需要使用100個循環卷積計算電路(10*10=100)；在本實施例中，第一反矩陣計算電路420需要16個循環卷積計算電路(a=4，4*4=16)，第二反矩陣計算電路433需要25個循環卷積計算電路(b=5，5*5=25)，第三反矩陣計算電路437僅需要一個循環卷積計算電路，而第四反矩陣計算電路442需要25個循環卷積計算電路，因此本實施例僅需要67個循環卷積計算電路，因此可以確實降低編碼器400的硬體成本。 In the circuit architecture shown in Figure 4, the barrel shifter module 410 can be compared to the matrix M shown in Figure 2, and the first inverse matrix calculation circuit 420 and the calculation circuit 430 are used to generate A content similar to the inverse matrix K ^-1 shown in Figure 2 can be used to generate check code blocks PB_a, PB_s, and PB_b when the inverse matrix K ^-1 cannot be found. In addition, the encoder 400 can greatly reduce the number of cyclic convolution calculation circuits (included in the inverse matrix calculation circuit) in practice. For example, assuming that K is a square matrix of 10*10, and a=4, s=1, =5, the encoder in the prior art needs to use 100 cyclic convolution calculation circuits (10*10=100); In this embodiment, the first inverse matrix calculation circuit 420 requires 16 cyclic convolution calculation circuits (a=4, 4*4=16), and the second inverse matrix calculation circuit 433 requires 25 cyclic convolution calculation circuits (b= 5, 5*5=25), the third inverse matrix calculation circuit 437 only needs one cyclic convolution calculation circuit, and the fourth inverse matrix calculation circuit 442 needs 25 cyclic convolution calculation circuits, so this embodiment only needs 67 The circular convolution calculation circuit can indeed reduce the hardware cost of the encoder 400.

此外，由於本實施例中的第一反矩陣計算電路420可以立即將桶式移位器模組410所輸出的a個局部校驗碼區塊進行反矩陣計算，以產生a個校驗碼區塊來輸出到後端的電路，因此若是後續的第二反矩陣計算電路433、第三反矩陣計算電路437以及第四反矩陣計算電路442的計算不複雜的話，編碼器400可以在沒有延遲的情形下不斷地輸出校驗碼區塊至後端電路，以增進整體系統的效能。 In addition, since the first inverse matrix calculation circuit 420 in this embodiment can immediately perform inverse matrix calculation on a partial check code blocks output by the barrel shifter module 410 to generate a check code areas Block output to the back-end circuit. Therefore, if the calculations of the subsequent second inverse matrix calculation circuit 433, third inverse matrix calculation circuit 437, and fourth inverse matrix calculation circuit 442 are not complicated, the encoder 400 can work without delay The check code block is continuously output to the back-end circuit to improve the performance of the overall system.

參考第5圖，其為根據本發明一實施例之一種編碼方法的流程圖，同時參考第1~5圖及以上實施例所揭露的內容，編碼方法的流程如下所述。 Referring to FIG. 5, which is a flowchart of an encoding method according to an embodiment of the present invention, and referring to the contents disclosed in FIGS. 1 to 5 and the above embodiments, the flow of the encoding method is as follows.

步驟500：流程開始。 Step 500: The process starts.

步驟502：將多個資料區塊進行處理以產生多個局部校驗碼區塊，其中該多個局部校驗碼區塊包含了一第一部分、一第二部分以及一第三部分。 Step 502: Process a plurality of data blocks to generate a plurality of partial check code blocks, wherein the plurality of partial check code blocks include a first part, a second part, and a third part.

步驟504：對該第一部分進行反矩陣運算以產生一第一部分的校驗碼區塊。 Step 504: Perform an inverse matrix operation on the first part to generate a check code block of the first part.

步驟506：根據該第一部分的校驗碼區塊來對該第二部分以及該第三部分進行反矩陣運算，以產生一第二部分的校驗碼區塊以及一第三部分的校驗碼區塊，其中該第一部分的校驗碼區塊、該第二部分的校驗碼區塊以及該第三部分的校驗碼區塊係作為該編碼器針對該多個資料區塊所產生之多個校驗碼區塊。 Step 506: Perform an inverse matrix operation on the second part and the third part according to the check code block of the first part to generate a check code block of the second part and a check code of the third part Block, where the first part of the check code block, the second part of the check code block, and the third part of the check code block are used as the encoder generated for the plurality of data blocks Multiple check code blocks.

步驟508：將該多個資料區塊以及該多個校驗碼區塊係寫入至一快閃記憶體中。 Step 508: Write the plurality of data blocks and the plurality of check code blocks into a flash memory.

簡要歸納本發明，在本發明之編碼器中，其透過將局部校驗碼區塊分為三個部分來進行操作，以在可以確實產生校驗碼區塊的情形下降低編碼器中的循環卷積計算所需要的硬體。因此，本發明之編碼器可以避免先前技術中所述之硬體成本大幅增加的情形。以上所述僅為本發明之較佳實施例，凡依本發明申請專利範圍所做之均等變化與修飾，皆應屬本發明之涵蓋範圍。 To briefly summarize the present invention, in the encoder of the present invention, it operates by dividing the partial check code block into three parts, so as to reduce the cycle in the encoder under the condition that the check code block can be generated. The hardware required for convolution calculations. Therefore, the encoder of the present invention can avoid the substantial increase in hardware cost described in the prior art. The foregoing descriptions are only preferred embodiments of the present invention, and all equivalent changes and modifications made in accordance with the scope of the patent application of the present invention shall fall within the scope of the present invention.

400:編碼器 400: encoder

410:桶式移位器模組 410: Barrel shifter module

430、440:計算電路 430, 440: calculation circuit

432:第一調整電路 432: first adjustment circuit

433:第二反矩陣計算電路 433: Second Inverse Matrix Calculation Circuit

436:第二調整電路 436: second adjustment circuit

437:第三反矩陣計算電路 437: Third Inverse Matrix Calculation Circuit

443:第三調整電路443 443: Third adjustment circuit 443

DB_1~DB_N:資料區塊 DB_1~DB_N: data block

PB_a、PB_s、PB_b:校驗碼區塊 PB_a, PB_s, PB_b: check code block

Claims

一種編碼器，包含有：一桶式移位器模組，用以將多個資料區塊進行處理以產生多個局部校驗碼(partial parity)區塊，其中該多個局部校驗碼區塊包含了一第一部分、一第二部分以及一第三部分；其中該編碼器所使用的一校驗碼檢查矩陣可以分割為一第一矩陣與一第二矩陣，該第二矩陣為一方陣，該第二矩陣的每一行由上而下被區分為a個區塊、s個區塊及b個區塊，該第二矩陣的每一列由左至右被區分為a個區塊、s個區塊及b個區塊，且最右上角的a*b的區塊均為空白區塊；以及該多個局部校驗碼區塊之該第一部分、該第二部分以及該第三部分的數量分別為a個局部校驗碼區塊、s個局部校驗碼區塊與b個局部校驗碼區塊；一第一反矩陣計算電路，耦接於該桶式移位器模組，用以對該第一部分進行反矩陣運算以產生一第一部分的校驗碼區塊；以及一計算電路，耦接於該桶式移位器模組以及該第一反矩陣計算電路，用以根據該第一部分的校驗碼區塊來對該第二部分以及該第三部分進行反矩陣運算，以產生一第二部分的校驗碼區塊以及一第三部分的校驗碼區塊；其中該第一部分的校驗碼區塊、該第二部分的校驗碼區塊以及該第三部分的校驗碼區塊係作為該編碼器針對該多個資料區塊所產生之多個校驗碼區塊。 An encoder includes: a barrel shifter module for processing a plurality of data blocks to generate a plurality of partial parity blocks, wherein the plurality of partial parity blocks The block includes a first part, a second part, and a third part; wherein a check code check matrix used by the encoder can be divided into a first matrix and a second matrix, and the second matrix is a square matrix , Each row of the second matrix is divided into a block, s block, and b block from top to bottom, and each column of the second matrix is divided into a block, s from left to right Blocks and b blocks, and the blocks a*b in the upper right corner are all blank blocks; and the first part, the second part, and the third part of the plurality of local check code blocks The numbers of are respectively a partial check code blocks, s partial check code blocks and b partial check code blocks; a first inverse matrix calculation circuit is coupled to the barrel shifter module , For performing an inverse matrix operation on the first part to generate a check code block of the first part; and a calculation circuit coupled to the barrel shifter module and the first inverse matrix calculation circuit for Performing an inverse matrix operation on the second part and the third part according to the check code block of the first part to generate a check code block of the second part and a check code block of the third part; The first part of the check code block, the second part of the check code block, and the third part of the check code block are used as a plurality of check codes generated by the encoder for the plurality of data blocks. Code verification block.

如申請專利範圍第1項所述之編碼器，其中該計算電路包含有：一第一調整電路，耦接於該第一反矩陣計算電路，用以根據該第一部分的校驗碼區塊來調整該多個局部校驗碼區塊的該第三部分以產生一調整後第三部分；一第二反矩陣計算電路，耦接於該第一調整電路，用以對該調整後第三部分進行反矩陣運算以產生一第一運算結果；一第二調整電路，耦接於該桶式移位器模組、該第一反矩陣計算電路以及該第二反矩陣計算電路，用以根據該第一部分的校驗碼區塊以及該第一運算結果來調整該多個局部校驗碼區塊的該第二部分以產生一調整後第二部分；一第三反矩陣計算電路，耦接於該第二調整電路，用以對該調整後第二部分進行反矩陣運算以產生一第二部分的校驗碼區塊；以及另一計算電路，耦接於該第二反矩陣計算電路以及第三反矩陣計算電路，用以根據該第一運算結果以及該第二部分的校驗碼區塊以產生一第三部分的校驗碼區塊。 According to the encoder described in claim 1, wherein the calculation circuit includes: a first adjustment circuit, coupled to the first inverse matrix calculation circuit, and used to calculate according to the check code block of the first part Adjust the third part of the multiple partial check code blocks to produce an adjustment The last third part; a second inverse matrix calculation circuit, coupled to the first adjustment circuit, for performing an inverse matrix operation on the adjusted third part to generate a first operation result; a second adjustment circuit, coupled Connected to the barrel shifter module, the first inverse matrix calculation circuit, and the second inverse matrix calculation circuit for adjusting the plurality of check code blocks according to the first part of the check code block and the first calculation result The second part of the partial check code block is used to generate an adjusted second part; a third inverse matrix calculation circuit is coupled to the second adjustment circuit for performing an inverse matrix operation on the adjusted second part To generate a second part of the check code block; and another calculation circuit, coupled to the second inverse matrix calculation circuit and the third inverse matrix calculation circuit, according to the first calculation result and the second part To generate a third part of the check code block.

如申請專利範圍第1項所述之編碼器，其為一低密度奇偶檢查碼(Low-Density Parity Check code，LDPC code)編碼電路。 The encoder described in item 1 of the scope of patent application is a Low-Density Parity Check code (LDPC code) encoding circuit.

一種快閃記憶體控制器，包含有：一記憶體，用來儲存一程式碼；一微處理器，用來執行該程式碼以控制對該快閃記憶體模組之存取；以及一編碼器，包含有：一桶式移位器模組，用以將多個資料區塊進行處理以產生多個局部校驗碼(partial parity)區塊，其中該多個局部校驗碼區塊包含了一第一部分、一第二部分以及一第三部分；其中該編碼器所使用的一校驗碼檢查矩陣可以分割為一第一矩陣與一第二矩陣，該第二矩陣為一方陣，該第二矩陣的每一行由上而下被區分為a個區塊、s個區塊及b個區塊，該第二矩陣的每一列由左至右被區分為a個區塊、s個區塊及b個區塊，且最右上角的a*b的區塊均為空白區塊；以及該多個局部校驗碼區塊之該第一部分、該第二部分以及該第三部分的數量分別為a個局部校驗碼區塊、s個局部校驗碼區塊與b個局部校驗碼區塊；一第一反矩陣計算電路，耦接於該桶式移位器模組，用以對該第一部分進行反矩陣運算以產生一第一部分的校驗碼區塊；以及一計算電路，耦接於該桶式移位器模組以及該第一反矩陣計算電路，用以根據該第一部分的校驗碼區塊來對該第二部分以及該第三部分進行反矩陣運算，以產生一第二部分的校驗碼區塊以及一第三部分的校驗碼區塊；其中該第一部分的校驗碼區塊、該第二部分的校驗碼區塊以及該第三部分的校驗碼區塊係作為該編碼器針對該多個資料區塊所產生之多個校驗碼區塊。 A flash memory controller, comprising: a memory for storing a program code; a microprocessor for executing the program code to control access to the flash memory module; and a code The device includes: a barrel shifter module for processing a plurality of data blocks to generate a plurality of partial parity blocks, wherein the plurality of partial parity blocks include A first part, a second part and a third part; wherein a check code check matrix used by the encoder can be divided into a first matrix and a second matrix, the second matrix As a square matrix, each row of the second matrix is divided into a block, s block and b block from top to bottom, and each column of the second matrix is divided into a block from left to right Blocks, s blocks and b blocks, and the blocks a*b in the upper right corner are all blank blocks; and the first part, the second part, and the plurality of partial check code blocks The number of the third part is a local check code block, s local check code block and b local check code block; a first inverse matrix calculation circuit is coupled to the barrel shift A device module for performing an inverse matrix operation on the first part to generate a check code block of the first part; and a calculation circuit coupled to the barrel shifter module and the first inverse matrix calculation circuit , Used to perform inverse matrix operations on the second part and the third part according to the check code block of the first part to generate a check code block of the second part and a check code of the third part Block; wherein the first part of the check code block, the second part of the check code block, and the third part of the check code block are used as the encoder generated for the plurality of data blocks Multiple check code blocks.

如申請專利範圍第4項所述之快閃記憶體控制器，其中該計算電路包含有：一第一調整電路，耦接於該第一反矩陣計算電路，用以根據該第一部分的校驗碼區塊來調整該多個局部校驗碼區塊的該第三部分以產生一調整後第三部分；一第二反矩陣計算電路，耦接於該第一調整電路，用以對該調整後第三部分進行反矩陣運算以產生一第一運算結果；一第二調整電路，耦接於該桶式移位器模組、該第一反矩陣計算電路以及該第二反矩陣計算電路，用以根據該第一部分的校驗碼區塊以及該第一運算結果來調整該多個局部校驗碼區塊的該第二部分以產生一調整後第二部分；一第三反矩陣計算電路，耦接於該第二調整電路，用以對該調整後第二部分進行反矩陣運算以產生一第二部分的校驗碼區塊；以及另一計算電路，耦接於該第二反矩陣計算電路以及第三反矩陣計算電路，用以根據該第一運算結果以及該第二部分的校驗碼區塊以產生一第三部分的校驗碼區塊。 The flash memory controller described in claim 4, wherein the calculation circuit includes: a first adjustment circuit coupled to the first inverse matrix calculation circuit for checking according to the first part Code block to adjust the third part of the plurality of partial check code blocks to generate an adjusted third part; a second inverse matrix calculation circuit is coupled to the first adjustment circuit for the adjustment The third part performs an inverse matrix operation to generate a first operation result; a second adjustment circuit is coupled to the barrel shifter module, the first inverse matrix calculation circuit, and The second inverse matrix calculation circuit is used for adjusting the second part of the plurality of partial check code blocks according to the check code block of the first part and the first operation result to generate an adjusted second part A third inverse matrix calculation circuit, coupled to the second adjustment circuit, for performing inverse matrix operations on the adjusted second part to generate a second part of the check code block; and another calculation circuit, It is coupled to the second inverse matrix calculation circuit and the third inverse matrix calculation circuit for generating a third part of the check code block according to the first operation result and the second part of the check code block.

如申請專利範圍第4項所述之快閃記憶體控制器，其中該編碼器為一低密度奇偶檢查碼(Low-Density Parity Check code，LDPC code)編碼電路。 The flash memory controller described in item 4 of the scope of patent application, wherein the encoder is a Low-Density Parity Check code (LDPC code) encoding circuit.

一種編碼方法，包含有：將多個資料區塊進行處理以產生多個局部校驗碼(partial parity)區塊，其中該多個局部校驗碼區塊包含了一第一部分、一第二部分以及一第三部分；其中該編碼器所使用的一校驗碼檢查矩陣可以分割為一第一矩陣與一第二矩陣，該第二矩陣為一方陣，該第二矩陣的每一行由上而下被區分為a個區塊、s個區塊及b個區塊，該第二矩陣的每一列由左至右被區分為a個區塊、s個區塊及b個區塊，且最右上角的a*b的區塊均為空白區塊；以及該多個局部校驗碼區塊之該第一部分、該第二部分以及該第三部分的數量分別為a個局部校驗碼區塊、s個局部校驗碼區塊與b個局部校驗碼區塊；對該第一部分進行反矩陣運算以產生一第一部分的校驗碼區塊；以及根據該第一部分的校驗碼區塊來對該第二部分以及該第三部分進行反矩陣運算，以產生一第二部分的校驗碼區塊以及一第三部分的校驗碼區塊，其中該第一部分的校驗碼區塊、該第二部分的校驗碼區塊以及該第三部分的校驗碼區塊係作為該編碼器針對該多個資料區塊所產生之多個校驗碼區塊。 An encoding method includes: processing multiple data blocks to generate multiple partial parity blocks, wherein the multiple partial parity blocks include a first part and a second part And a third part; wherein a check code check matrix used by the encoder can be divided into a first matrix and a second matrix, the second matrix is a square matrix, and each row of the second matrix is from the top The bottom is divided into a block, s block and b block. Each row of the second matrix is divided into a block, s block and b block from left to right, and the most The blocks of a*b in the upper right corner are all blank blocks; and the numbers of the first part, the second part and the third part of the plurality of partial check code blocks are respectively a partial check code areas Block, s partial check code blocks and b partial check code blocks; perform inverse matrix operation on the first part to generate a first part check code block; and according to the first part check code area Block to reverse the second part and the third part Operation to generate a second part of the check code block and a third part of the check code block, wherein the first part of the check code block, the second part of the check code block and the first part The three-part check code block is used as multiple check code blocks generated by the encoder for the multiple data blocks.

如申請專利範圍第7項所述之編碼方法，其中根據該第一部分的校驗碼區塊來對該第二部分以及該第三部分進行反矩陣運算以產生該第二部分的校驗碼區塊以及該第三部分的校驗碼區塊的步驟包含有：根據該第一部分的校驗碼區塊來調整該多個局部校驗碼區塊的該第三部分以產生一調整後第三部分；對該調整後第三部分進行反矩陣運算以產生一第一運算結果；根據該第一部分的校驗碼區塊以及該第一運算結果來調整該多個局部校驗碼區塊的該第二部分以產生一調整後第二部分；對該調整後第二部分進行反矩陣運算以產生一第二部分的校驗碼區塊；以及根據該第一運算結果以及該第二部分的校驗碼區塊以產生一第三部分的校驗碼區塊。 The encoding method described in item 7 of the scope of patent application, wherein the second part and the third part are inverse matrix operations based on the check code block of the first part to generate the check code area of the second part Block and the third part of the check code block includes: adjusting the third part of the plurality of partial check code blocks according to the first part of the check code block to generate an adjusted third Part; perform an inverse matrix operation on the adjusted third part to generate a first operation result; adjust the plurality of partial check code blocks according to the check code block of the first part and the first operation result The second part is used to generate an adjusted second part; the inverse matrix operation is performed on the adjusted second part to generate a check code block of the second part; and the check code block of the second part is generated according to the first calculation result and the second part of The verification code block generates a third part of the verification code block.

如申請專利範圍第7項所述之編碼方法，其使用一低密度奇偶檢查碼(Low-Density Parity Check code，LDPC code)編碼電路來執行。 For example, the encoding method described in item 7 of the scope of patent application is implemented using a Low-Density Parity Check code (LDPC code) encoding circuit.