TW201918919A - Physically unclonable function generator - Google Patents

Physically unclonable function generator Download PDF

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TW201918919A
TW201918919A TW107120682A TW107120682A TW201918919A TW 201918919 A TW201918919 A TW 201918919A TW 107120682 A TW107120682 A TW 107120682A TW 107120682 A TW107120682 A TW 107120682A TW 201918919 A TW201918919 A TW 201918919A
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puf
dynamic
coupled
node
terminal
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呂士濂
科馬克 麥可 歐康尼爾
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台灣積體電路製造股份有限公司
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    • H—ELECTRICITY
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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L9/00—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols
    • H04L9/08—Key distribution or management, e.g. generation, sharing or updating, of cryptographic keys or passwords
    • H04L9/0861—Generation of secret information including derivation or calculation of cryptographic keys or passwords
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    • H04L9/32—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols including means for verifying the identity or authority of a user of the system or for message authentication, e.g. authorization, entity authentication, data integrity or data verification, non-repudiation, key authentication or verification of credentials
    • H04L9/3247—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols including means for verifying the identity or authority of a user of the system or for message authentication, e.g. authorization, entity authentication, data integrity or data verification, non-repudiation, key authentication or verification of credentials involving digital signatures
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
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    • H04L9/32—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols including means for verifying the identity or authority of a user of the system or for message authentication, e.g. authorization, entity authentication, data integrity or data verification, non-repudiation, key authentication or verification of credentials
    • H04L9/3271—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols including means for verifying the identity or authority of a user of the system or for message authentication, e.g. authorization, entity authentication, data integrity or data verification, non-repudiation, key authentication or verification of credentials using challenge-response
    • H04L9/3278—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols including means for verifying the identity or authority of a user of the system or for message authentication, e.g. authorization, entity authentication, data integrity or data verification, non-repudiation, key authentication or verification of credentials using challenge-response using physically unclonable functions [PUF]
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    • B25—HAND TOOLS; PORTABLE POWER-DRIVEN TOOLS; MANIPULATORS
    • B25J—MANIPULATORS; CHAMBERS PROVIDED WITH MANIPULATION DEVICES
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Abstract

A physical unclonable function (PUF) generator comprising: a plurality of PUF cells, wherein each of the plurality of PUF cells comprises a first MOS transistor and a second MOS transistor, wherein terminal S of the first MOS transistor is connected to terminal D of the second MOS transistor at a dynamic node, terminal D of the first MOS transistor is coupled to a first bus and terminal G of the first NMOS transistor is coupled to a second bus, and terminals S and G of the second NMOS transistor are coupled to ground; a plurality of dynamic flip-flop (DFF) circuits wherein each of the plurality of DFF circuits is coupled to each of the plurality of PUF cells respectively; a population count circuit coupled to the plurality of DFF circuits; and an evaluation logic circuit.

Description

物理不可複製功能產生器Physical non-replicable function generator

本發明的實施例是有關於一種物理不可複製功能產生器。Embodiments of the present invention are directed to a physical non-reproducible function generator.

隨著積體電路越來越多地用於為各種不同應用提供不同類型的資訊的電子裝置中，越來越需要充分保護可存儲在電子裝置內的敏感和/或關鍵資訊，以將對此類資訊的存取限制於僅具有存取許可權的其它裝置。此類應用的一些實例包含驗證裝置、保護裝置內的機密資訊以及確保兩個或多於兩個裝置之間的通信的安全。普遍認為亂數產生器在電腦時代至關重要。產生真正亂數的高品質亂數產生器對於加密應用是理想的。舉例來說，真亂數被用作用於加密資訊和消息的加密金鑰。As integrated circuits are increasingly used in electronic devices that provide different types of information for a variety of different applications, there is an increasing need to adequately protect sensitive and/or critical information that can be stored in electronic devices to Access to class information is limited to other devices that only have access permissions. Some examples of such applications include verifying devices, protecting confidential information within the device, and ensuring communication between two or more devices. It is widely believed that chaotic generators are crucial in the computer age. High quality random number generators that produce true random numbers are ideal for cryptographic applications. For example, a true random number is used as an encryption key for encrypting information and messages.

物理不可複製功能（physically unclonable function；PUF）產生器是一種通常位於積體電路內的物理結構，其回應於到PUF產生器的輸入（例如，詢問/請求）而提供大量對應輸出（例如，回應）。存在多種不同實施方法，包含基於延遲鏈（delay-chain-based）的PUF產生器和基於記憶體（memory-based）的PUF產生器。基於記憶體的PUF產生器將記憶體裝置（通常是靜態隨機存取記憶體（static random-access memory, SRAM）或動態隨機存取記憶體（dynamic random-access memory, DRAM）裝置）的陣列的變化轉譯成二進位序列。兩種方法均是基於由半導體製造製程（例如，幾何尺寸和摻雜濃度）中的固有變化所引起的裝置之間的物理性質的隨機性。候選的PUF產生器應該是獨特的、不可複製的且可信賴的。此外，其還應具有小面積、高吞吐率、低延時和低功耗。當前，基於SRAM的PUF產生器和基於DRAM的PUF產生器均遭受各種限制。舉例來說，基於SRAM的PUF產生器只能在啟動時存取，且不會提供強大的PUF配置。需要開發一種可在運行時詢問同時提供強大的PUF配置的PUF產生器。A physically unclonable function (PUF) generator is a physical structure that is typically located within an integrated circuit that provides a large number of corresponding outputs (eg, responses in response to inputs (eg, queries/requests) to the PUF generator). ). There are a number of different implementation methods, including a delay-chain-based PUF generator and a memory-based PUF generator. A memory-based PUF generator will array an array of memory devices (typically static random-access memory (SRAM) or dynamic random-access memory (DRAM) devices) The changes are translated into binary sequences. Both methods are based on the random nature of the physical properties between devices caused by inherent variations in semiconductor fabrication processes (eg, geometry and doping concentration). Candidate PUF generators should be unique, non-reproducible, and trustworthy. In addition, it should have a small area, high throughput, low latency and low power consumption. Currently, both SRAM-based PUF generators and DRAM-based PUF generators suffer from various limitations. For example, an SRAM-based PUF generator can only be accessed at startup and does not provide a powerful PUF configuration. There is a need to develop a PUF generator that can be queried at runtime while providing a powerful PUF configuration.

本發明的一實施例公開一種物理不可複製功能產生器，包括：多個物理不可複製功能單元，其中所述多個物理不可複製功能單元中的每一個包括第一金屬氧化物半導體電晶體和第二金屬氧化物半導體電晶體，其中所述第一金屬氧化物半導體電晶體的源極在動態節點處連接到所述第二金屬氧化物半導體電晶體的汲極，所述第一金屬氧化物半導體電晶體的汲極耦接到第一匯流排及所述第一金屬氧化物半導體電晶體的閘極耦接到第二匯流排，以及所述第二金屬氧化物半導體電晶體的源極和閘極耦接到地面；多個動態正反器電路，其中所述多個動態正反器電路中的每一個分別耦接到所述多個物理不可複製功能單元中的每一個，其中所述多個動態正反器電路各自配置成監測所述多個物理不可複製功能單元中的每一個上的所述動態節點上的電壓電平；群體計數電路，其耦接到所述多個動態正反器電路，其中所述群體計數電路配置成確定具有反轉邏輯狀態的物理不可複製功能單元的第一數目；以及評估邏輯電路，其具有耦接到所述群體計數電路的輸入和耦接到所述多個動態正反器電路的輸出，其中所述評估邏輯電路配置成將所述第一數目與物理不可複製功能單元的總數的一半相比較。An embodiment of the present invention discloses a physical non-reproducible function generator, including: a plurality of physical non-reproducible functional units, wherein each of the plurality of physical non-reproducible functional units includes a first metal oxide semiconductor transistor and a a metal oxide semiconductor transistor, wherein a source of the first metal oxide semiconductor transistor is connected to a drain of the second metal oxide semiconductor transistor at a dynamic node, the first metal oxide semiconductor a gate of the transistor coupled to the first bus bar and a gate of the first metal oxide semiconductor transistor is coupled to the second bus bar, and a source and a gate of the second metal oxide semiconductor transistor a pole coupled to the ground; a plurality of dynamic flip-flop circuits, wherein each of the plurality of dynamic flip-flop circuits is coupled to each of the plurality of physical non-reproducible functional units, wherein the plurality Dynamic flip-flop circuits each configured to monitor a voltage level on the dynamic node on each of the plurality of physical non-reproducible functional units; a population count a circuit coupled to the plurality of dynamic flip-flop circuits, wherein the population counting circuit is configured to determine a first number of physical non-reproducible functional units having an inverted logic state; and an evaluation logic circuit having a coupling An input to the population counting circuit and an output coupled to the plurality of dynamic flip-flop circuits, wherein the evaluation logic is configured to compare the first number to a half of a total number of physical non-reproducible functional units .

本發明的一實施例公開一種配置用於產生物理不可複製功能簽名的物理不可複製功能產生器的方法，所述方法包括：將多個物理不可複製功能單元耦接到多個動態正反器電路，並耦接到群體計數器以及另外耦接到評估邏輯電路，其中所述多個物理不可複製功能單元中的每一個包括第一金屬氧化物半導體電晶體和第二金屬氧化物半導體電晶體；通過所述多個第一金屬氧化物半導體電晶體中的每一個將所述多個物理不可複製功能單元中的多個動態節點充電到多個第一電壓；通過所述多個第二金屬氧化物半導體電晶體中的每一個將所述多個動態節點放電到多個第二電壓；使用對應的動態正反器電路來監測所述多個第二電壓中的每一個；當所述第二電壓變得小於第三電壓時，將所述多個物理不可複製功能單元的邏輯狀態從第一邏輯狀態反轉到第二邏輯狀態；以及當具有反轉邏輯狀態的物理不可複製功能單元的數目超過物理不可複製功能單元的總數的一半時，產生物理不可複製功能簽名。An embodiment of the invention discloses a method for configuring a physical non-replicable function generator for generating a physical non-reproducible function signature, the method comprising: coupling a plurality of physical non-reproducible functional units to a plurality of dynamic flip-flop circuits And coupled to the population counter and additionally coupled to the evaluation logic circuit, wherein each of the plurality of physical non-reproducible functional units comprises a first metal oxide semiconductor transistor and a second metal oxide semiconductor transistor; Each of the plurality of first metal oxide semiconductor transistors charges a plurality of the plurality of dynamic non-reproducible functional units to a plurality of first voltages; through the plurality of second metal oxides Each of the semiconductor transistors discharges the plurality of dynamic nodes to a plurality of second voltages; using a corresponding dynamic flip-flop circuit to monitor each of the plurality of second voltages; when the second voltage Reversing the logic state of the plurality of physical non-replicable functional units from the first logic state to the second logic state when becoming less than the third voltage And when half of the total number of physical state having inverted logic function unit can not be copied over physical unclonable function unit generates a physical unclonable function signatures.

本發明的一實施例公開一種用於產生物理不可複製功能簽名的物理不可複製功能產生器，所述物理不可複製功能產生器包括：多個物理不可複製功能單元，其中所述多個物理不可複製功能單元中的每一個包括五個金屬氧化物半導體電晶體，其中第一金屬氧化物半導體電晶體和第二金屬氧化物半導體電晶體配置成對第一動態節點充電和放電，第三金屬氧化物半導體電晶體和第四金屬氧化物半導體電晶體配置成對第二動態節點充電，以及第五金屬氧化物半導體電晶體配置成使所述第二動態節點放電以便重置所述第二動態節點；多個動態正反器電路，其中所述多個動態正反器電路中的每一個分別耦接到所述多個物理不可複製功能單元中的每一個，其中所述多個動態正反器電路各自配置成監測所述多個物理不可複製功能單元中的每一個上的所述動態節點上的電壓電平；群體計數電路，其耦接到所述多個動態正反器電路，其中所述群體計數電路配置成確定具有反轉邏輯狀態的物理不可複製功能單元的第一數目；以及評估邏輯電路，其具有耦接到所述群體計數電路的輸入和耦接到所述多個動態正反器電路的輸出，其中所述評估邏輯電路配置成將所述第一數目與物理不可複製功能單元的總數的一半相比較。An embodiment of the present invention discloses a physical non-replicable function generator for generating a physical non-replicable function signature, the physical non-reproducible function generator comprising: a plurality of physical non-replicable functional units, wherein the plurality of physical non-replicable functional units Each of the functional units includes five metal oxide semiconductor transistors, wherein the first metal oxide semiconductor transistor and the second metal oxide semiconductor transistor are configured to charge and discharge the first dynamic node, the third metal oxide The semiconductor transistor and the fourth metal oxide semiconductor transistor are configured to charge the second dynamic node, and the fifth metal oxide semiconductor transistor is configured to discharge the second dynamic node to reset the second dynamic node; a plurality of dynamic flip-flop circuits, wherein each of the plurality of dynamic flip-flop circuits is coupled to each of the plurality of physical non-reproducible functional units, wherein the plurality of dynamic flip-flop circuits Each configured to monitor the dynamic node on each of the plurality of physical non-replicable functional units a voltage level; a population counting circuit coupled to the plurality of dynamic flip-flop circuits, wherein the population counting circuit is configured to determine a first number of physical non-replicable functional units having inverted logic states; and evaluation logic a circuit having an input coupled to the population counting circuit and an output coupled to the plurality of dynamic flip-flop circuits, wherein the evaluation logic is configured to convert the first number to a physical non-reproducible functional unit Compare the half of the total.

以下公開內容描述用以實施主題的不同特徵的各種示範性實施例。下文描述元件和佈置的特定實例以簡化本公開。當然，這些僅為實例且並非旨在為限制性的。舉例來說，將理解，當元件被稱作“連接到”另一元件或“耦接到”另一元件時，其可直接連接到另一元件或耦接到另一元件，或可存在一個或多個介入元件。The following disclosure describes various exemplary embodiments for implementing different features of the subject matter. Specific examples of elements and arrangements are described below to simplify the disclosure. Of course, these are merely examples and are not intended to be limiting. For example, when an element is referred to as "connected to" or "coupled" to another element, it can be Or multiple interventional components.

物理不可複製功能（PUF）產生器通常用於認證和秘密金鑰存儲而不需要安全電可擦除可程式設計唯讀記憶體（electrically erasable programmable read-only memory；EEPROM）和/或其它昂貴的硬體（例如，電池支援的靜態隨機存取記憶體）。PUF產生器基於其由固有的製程變化所引起的獨特物理性質匯出金鑰而不是將金鑰存儲在數位記憶體中，以將其本身與即使由相同製造製程產生的其它性質區別開來。通常，此類金鑰被稱作“PUF簽名”。多個不同參數可用于定義此類簽名，例如閘極延遲、閾值電壓、基於SRAM的裝置的開機狀態和/或積體電路的各種物理特性中的任一種。此外，電荷衰減（例如，放電過程）也可用作PUF簽名，其通常用於基於DRAM的PUF產生器中。在本公開的實施例中，提出產生PUF簽名的電路和方法。電路和方法使用包括多個PUF單元的基於衰減的CMOS偽DRAM PUF（pseudo-DRAM PUF）產生器，其中多個PUF單元中的每一個包括至少兩個CMOS電晶體。固有製程變化引起多個PUF單元中的每一個的不同電流漏泄路徑，且因此引起預充電動態節點（pre-charge dynamic node）處的不同暫態放電行為的獨特組合。此類電流漏泄路徑包括亞閾值電流（sub-threshold current）、閘極漏電流、閘極誘發的汲極漏電流、反向偏置電流等。通過不斷監測放電行為和將處於特定取樣時間的動態節點上的電壓值與觸發點進行比較，可確定對應PUF單元的輸出邏輯“0”或“1”。在一個實施例中，當PUF產生器中的對應PUF單元的動態節點的總數（例如，N）的一半反轉（即，從1切換到0）時，可獲得PUF簽名，即所有PUF單元在取樣時間的邏輯狀態的N位元二進位序列。然而，在另一實施例中，PUF單元中的第一動態節點的放電用於對同一PUF單元中的預充電的第二動態節點充電。當PUF產生器中的對應PUF單元的第二動態節點的總數（例如，N）的一半反轉（即，從0切換到1）時，可獲得PUF簽名。Physical non-replicable function (PUF) generators are commonly used for authentication and secret key storage without the need for electrically erasable programmable read-only memory (EEPROM) and/or other expensive Hardware (for example, battery-backed SRAM). The PUF generator recurs the key based on its unique physical properties caused by inherent process variations rather than storing the key in digital memory to distinguish itself from other properties produced by the same manufacturing process. Typically, such keys are referred to as "PUF signatures." A number of different parameters can be used to define such signatures, such as gate delay, threshold voltage, turn-on state of the SRAM-based device, and/or any of a variety of physical characteristics of the integrated circuit. In addition, charge decay (eg, a discharge process) can also be used as a PUF signature, which is typically used in DRAM-based PUF generators. In an embodiment of the present disclosure, a circuit and method for generating a PUF signature is presented. The circuit and method use an attenuation-based CMOS pseudo DRAM PUF (Pseudo-DRAM PUF) generator including a plurality of PUF cells, wherein each of the plurality of PUF cells includes at least two CMOS transistors. The inherent process variation causes different current leakage paths for each of the plurality of PUF cells, and thus causes a unique combination of different transient discharge behaviors at the pre-charge dynamic node. Such current leakage paths include sub-threshold currents, gate leakage currents, gate induced drain leakage currents, reverse bias currents, and the like. The output logic "0" or "1" of the corresponding PUF unit can be determined by continuously monitoring the discharge behavior and comparing the voltage value on the dynamic node at a particular sampling time to the trigger point. In one embodiment, when half of the total number of dynamic nodes (eg, N) of corresponding PUF units in the PUF generator is inverted (ie, switched from 1 to 0), PUF signatures may be obtained, ie, all PUF units are The N-bit binary sequence of the logic state of the sampling time. However, in another embodiment, the discharge of the first dynamic node in the PUF unit is used to charge a pre-charged second dynamic node in the same PUF unit. The PUF signature may be obtained when half of the total number of second dynamic nodes (eg, N) of the corresponding PUF unit in the PUF generator is inverted (ie, switched from 0 to 1).

圖1A說明根據本公開的各種實施例的PUF產生器100的示範性框圖。應注意，系統100僅為實例且不意圖限制本公開。因此，應理解，可在圖1的系統100之前、期間以及之後提供額外的操作，且可以在本文中僅簡要地描述一些其它操作。FIG. 1A illustrates an exemplary block diagram of a PUF generator 100 in accordance with various embodiments of the present disclosure. It should be noted that system 100 is merely an example and is not intended to limit the disclosure. Accordingly, it should be understood that additional operations may be provided before, during, and after the system 100 of FIG. 1, and that some other operations may only be briefly described herein.

在一些實施例中，PUF產生器100包括多個PUF單元103（例如，103-1、103-2、...以及103-N）和有限狀態機（finite state machine；FSM）120，其中有限狀態機 120包括多個動態正反器電路104、群體計數器（population counter；Popcount）以及評估邏輯電路。多個PUF單元103分別耦接在第一匯流排101與第二匯流排102之間，其中第一匯流排101具有電壓電平Vcc且第二匯流排102進行充電以便將“1”寫入多個PUF單元103。在一些實施例中，多個PUF單元103中的每一個包括2個NMOS電晶體，其將於圖1B中更加詳細地論述。多個動態正反器電路104分別耦接到端子CLK處的第三匯流排110、端子ENPR處的第四匯流排112以及端子EN處的第五匯流排106。多個PUF單元103的輸出端子接著耦接到對應動態正反器 104的端子D。多個動態正反器電路104的輸出端子接著耦接到群體計數器 105。確定N位元輸入中“0”的數目的群體計數器 105的輸出端子接著連接到評估邏輯電路107。評估邏輯電路107的輸出端子電耦接到反相器，所述反相器接著連接到第五匯流排106。In some embodiments, PUF generator 100 includes a plurality of PUF units 103 (eg, 103-1, 103-2, ..., and 103-N) and a finite state machine (FSM) 120, of which limited The state machine 120 includes a plurality of dynamic flip-flop circuits 104, a population counter (popcount), and an evaluation logic circuit. The plurality of PUF units 103 are respectively coupled between the first bus bar 101 and the second bus bar 102, wherein the first bus bar 101 has a voltage level Vcc and the second bus bar 102 is charged to write "1" more. PUF unit 103. In some embodiments, each of the plurality of PUF cells 103 includes two NMOS transistors, which will be discussed in more detail in FIG. 1B. A plurality of dynamic flip-flop circuits 104 are respectively coupled to the third bus bar 110 at the terminal CLK, the fourth bus bar 112 at the terminal ENPR, and the fifth bus bar 106 at the terminal EN. The output terminals of the plurality of PUF units 103 are then coupled to the terminals D of the corresponding dynamic flip-flops 104. The output terminals of the plurality of dynamic flip-flop circuits 104 are then coupled to the population counter 105. The output terminal of the group counter 105 that determines the number of "0"s in the N-bit input is then connected to the evaluation logic circuit 107. The output terminal of the evaluation logic circuit 107 is electrically coupled to an inverter, which is then connected to the fifth bus bar 106.

群體計數器 105可為使用遺傳演算法的習知的電腦運算，在某些實施例中，其通常可以使用跨越大範圍演算法的基於軟體的技術來實現。這些演算法包括串列移位元、查表、算術邏輯計數、模擬群體計數、漢明距離位垂直計數器（hamming distance bit vertical counter）、頻分等。可替代地，根據其它實施例，群體計數器 105可使用硬體電路來配置。群體計數器 105的硬體電路可包括半加器、全加器、進位保留加法器等，以及至少一個邏輯門（異或們、及閘等）。群體計數器 105的邏輯門的數目由輸入的數目定義並因此由PUF單元104的數目定義，群體計數器 105的複雜性也如此定義。在一些實施例中，使邏輯門的數目減到最小以最小化延遲，且可實施最少充電次數以最大化速度以及其它性能（包含成本和互連件的數目）。在某些實施例中，群體計數器 105是軟體技術和硬體技術的組合以獲得改善的性能。The population counter 105 can be a conventional computer operation using a genetic algorithm, which in certain embodiments can typically be implemented using software-based techniques that span a wide range of algorithms. These algorithms include tandem shift elements, look-up tables, arithmetic logic counts, simulated population counts, hamming distance bit vertical counters, frequency divisions, and the like. Alternatively, according to other embodiments, the community counter 105 can be configured using hardware circuitry. The hardware circuit of the group counter 105 may include a half adder, a full adder, a carry reserve adder, etc., and at least one logic gate (exclusive OR, gate, etc.). The number of logic gates of the population counter 105 is defined by the number of inputs and is therefore defined by the number of PUF units 104, the complexity of which is also defined as such. In some embodiments, the number of logic gates is minimized to minimize latency, and the minimum number of charges can be implemented to maximize speed and other performance (including cost and number of interconnects). In some embodiments, the group counter 105 is a combination of software technology and hardware technology to achieve improved performance.

根據各種實施例，如果在取樣時間具有反轉邏輯狀態（例如，從低切換到高，或從高切換到低）的群體計數器 105的輸入的數目等於或大於N/2，那麼評估邏輯電路107輸出高電平（例如，邏輯“1”）。將高電平施加到第五匯流排106，且通過反相器108進一步施加到多個動態正反器電路 104的端子EN。多個動態正反器電路 104的端子EN上的低電平終止取樣過程且在取樣時間輸出包括PUF單元104的N位元邏輯狀態的二進位序列的PUF簽名作為PUF簽名109。否則，多個動態正反器電路 104在不同的取樣時間繼續取樣過程，且群體計數器 105繼續從多個動態正反器電路 104接收邏輯狀態，直到評估電路107在檢測到輸入的總數的一半具有反轉邏輯狀態時而終止取樣過程為止。According to various embodiments, if the number of inputs of the population counter 105 having an inverted logic state (eg, switching from low to high, or from high to low) at the sampling time is equal to or greater than N/2, then the evaluation logic 107 The output is high (for example, logic "1"). A high level is applied to the fifth bus bar 106 and further applied to the terminal EN of the plurality of dynamic flip-flop circuits 104 through the inverter 108. The low level on the terminal EN of the plurality of dynamic flip-flop circuits 104 terminates the sampling process and outputs a PUF signature including the binary sequence of the N-bit logical state of the PUF unit 104 as the PUF signature 109 at the sampling time. Otherwise, the plurality of dynamic flip-flop circuits 104 continue the sampling process at different sampling times, and the population counter 105 continues to receive logic states from the plurality of dynamic flip-flop circuits 104 until the evaluation circuit 107 has detected half of the total number of inputs. The logic state is reversed and the sampling process is terminated.

圖1B說明根據本公開的各種實施例的PUF產生器100中的PUF單元103的電路圖。根據一些實施例，PUF單元103包括2個串聯連接的電晶體，其中第一電晶體113的端子S（即源極）（113-S）在動態節點115處連接到第二電晶體114的端子D（即汲極）。第一電晶體113的端子D（113-D）電連接到第一匯流排101，且第一電晶體113的端子G（即閘極）（113-G）電連接到第二匯流排102。第二電晶體114的端子S（114-S）和端子G（114-G）連接到接地（GND）。FIG. 1B illustrates a circuit diagram of a PUF unit 103 in a PUF generator 100, in accordance with various embodiments of the present disclosure. According to some embodiments, the PUF unit 103 includes two transistors connected in series, wherein the terminal S (ie, source) (113-S) of the first transistor 113 is connected to the terminal of the second transistor 114 at the dynamic node 115. D (ie bungee jumping). The terminal D (113-D) of the first transistor 113 is electrically connected to the first bus bar 101, and the terminal G (ie, gate) (113-G) of the first transistor 113 is electrically connected to the second bus bar 102. The terminal S (114-S) and the terminal G (114-G) of the second transistor 114 are connected to the ground (GND).

根據本公開的一些實施例，第一電晶體113和第二電晶體114各自可實施為各種類型的電晶體（例如，雙極結型電晶體（bipolar junction transistor；BJT）、高電子遷移率電晶體（high-electron mobility transistor；HEMT）等）中的任一種，同時保持在本公開的範圍內。實際上，第一電晶體113和第二電晶體114各自可實施為n型金屬氧化物半導體（n-type metal-oxide-semiconductor；NMOS）場效應電晶體（field-effect-transistors；FET）（下文簡稱為“第一NMOS電晶體113和第二NMOS電晶體114”）。According to some embodiments of the present disclosure, each of the first transistor 113 and the second transistor 114 may be implemented as various types of transistors (eg, bipolar junction transistors (BJT), high electron mobility) Any of a high-electron mobility transistor (HEMT) or the like while remaining within the scope of the present disclosure. In fact, each of the first transistor 113 and the second transistor 114 can be implemented as an n-type metal-oxide-semiconductor (NMOS) field-effect-transistors (FET) ( Hereinafter referred to as "first NMOS transistor 113 and second NMOS transistor 114").

當將高電平施加於第二匯流排102上時，第一NMOS電晶體113導通。隨後將端子113-S上拉且因此將動態節點115上拉到Vcc以便在PUF單元103中寫入“1”且保持在Vcc下，直到從第二匯流排102中移除高電平為止。根據各種實施例，影響存儲在PUF單元103的動態節點115上的總電荷的初始電壓值由第一NMOS電晶體113的閾值電壓（Vtl）和Vcc值確定，所述初始電壓值等於Vcc-Vt1。第一NMOS電晶體113的閾值電壓（Vtl）是在端子（源極與汲極）之間形成導電路徑所需的最小閘極-源極電壓差。在將低電平施加於第二匯流排102上之後，第一NMOS電晶體113斷開。在上述充電過程期間存儲在動態節點115上的總電荷接著經受由第二NMOS電晶體114中的各種電流漏泄路徑所引起的放電過程。出於相同的原因，可觀察到動態節點115上電壓相對於時間的衰減。動態節點115上的暫態放電行為（即，電壓相對於時間）主要受第二NMOS電晶體114控制，且可通過動態正反器電路104取樣，其在下文中得以進一步詳細論述。When a high level is applied to the second bus bar 102, the first NMOS transistor 113 is turned on. Terminal 113-S is then pulled up and thus dynamic node 115 is pulled up to Vcc to write a "1" in PUF unit 103 and remain at Vcc until a high level is removed from second busbar 102. According to various embodiments, an initial voltage value affecting the total charge stored on the dynamic node 115 of the PUF unit 103 is determined by a threshold voltage (Vtl) and a Vcc value of the first NMOS transistor 113, the initial voltage value being equal to Vcc-Vt1 . The threshold voltage (Vtl) of the first NMOS transistor 113 is the minimum gate-to-source voltage difference required to form a conductive path between the terminals (source and drain). After a low level is applied to the second bus bar 102, the first NMOS transistor 113 is turned off. The total charge stored on the dynamic node 115 during the above charging process is then subjected to a discharge process caused by various current leakage paths in the second NMOS transistor 114. For the same reason, the attenuation of the voltage on the dynamic node 115 with respect to time can be observed. The transient discharge behavior on dynamic node 115 (i.e., voltage versus time) is primarily controlled by second NMOS transistor 114 and may be sampled by dynamic flip-flop circuit 104, which is discussed in further detail below.

圖1C說明根據本公開的各種實施例的PUF產生器100中的基於真單相時鐘CMOS的動態正反器電路104的電路圖。基於真單相時鐘CMOS的動態正反器電路（下文簡稱為“DFF”）104包括4級聯反相器124和多工器130。4個級聯的反相器124中的每一個包括1個p型金屬氧化物半導體（p-type metal-oxide-semiconductor；PMOS）電晶體121和2個NMOS電晶體122。因此，在DFF 104中有4個PMOS電晶體121和8個NMOS電晶體122，其中計時開關電晶體是NMOS電晶體122-1、NMOS電晶體122-4以及PMOS電晶體121-2。復位電晶體是NMOS電晶體122-8。在第一反相器124-1中，第一PMOS電晶體121-1的源極端子（121-1-S）耦接到第一NMOS電晶體122-1的汲極端子（122-1-D），且第一NMOS電晶體122-1的源極端子（122-1-S）在節點139處耦接到第二NMOS電晶體122-2的汲極端子（122-2-D）。第一PMOS電晶體121-1的汲極端子（121-1-D）和第二NMOS電晶體122-2的源極端子（122-2-S）分別耦接到第一匯流排101和接地。第一PMOS電晶體121-1的閘極端子和第二NMOS電晶體122-2的閘極端子連接到節點150，而第一NMOS電晶體122-1的閘極端子（122-1-G）連接到時鐘信號（CLK）。第二反相器124-2以類似方式配置，除了第二PMOS電晶體121-2的閘極端子和第四NMOS電晶體122-4的閘極端子耦接到CLK，且第三NMOS電晶體122-3的閘極端子連接到節點139以外。第三反相器124-3也以類似方式配置，除了第三PMOS電晶體121-3的閘極端子和第六NMOS電晶體122-6的閘極端子耦接到節點140，且第五NMOS電晶體122-5的閘極端子連接到CLK以外。在第四反相器124-4中，第四PMOS電晶體121-4的源極端子（121-4-S）在節點123處耦接到第七NMOS電晶體122-7的汲極端子（122-7-D）。第四PMOS電晶體121-4的汲極端子（121-4-D）和第七NMOS電晶體122-7的源極端子（122-7-S）分別耦接到第一匯流排101和接地。第四PMOS電晶體121-4的閘極端子和第七NMOS電晶體122-7的閘極端子耦接到第八NMOS電晶體122-8的汲極端子（122-8-D），其進一步耦接到節點141。第八NMOS電晶體122-8的源極端子（122-8-S）和閘極端子（122-8-G）分別耦接到接地和ENPR。FIG. 1C illustrates a circuit diagram of a true single phase clock CMOS based dynamic flip flop circuit 104 in a PUF generator 100, in accordance with various embodiments of the present disclosure. A dynamic flip-flop circuit (hereinafter simply referred to as "DFF") 104 based on a true single-phase clock CMOS includes a 4-cascade inverter 124 and a multiplexer 130. Each of the four cascaded inverters 124 includes 1 A p-type metal-oxide-semiconductor (PMOS) transistor 121 and two NMOS transistors 122 are provided. Therefore, there are four PMOS transistors 121 and eight NMOS transistors 122 in the DFF 104, wherein the timing switch transistors are an NMOS transistor 122-1, an NMOS transistor 122-4, and a PMOS transistor 121-2. The reset transistor is an NMOS transistor 122-8. In the first inverter 124-1, the source terminal (121-1-S) of the first PMOS transistor 121-1 is coupled to the first terminal of the first NMOS transistor 122-1 (122-1- D), and the source terminal (122-1-S) of the first NMOS transistor 122-1 is coupled to the 汲 terminal (122-2-D) of the second NMOS transistor 122-2 at node 139. The drain terminal (121-1-D) of the first PMOS transistor 121-1 and the source terminal (122-2-S) of the second NMOS transistor 122-2 are coupled to the first bus bar 101 and ground, respectively . The gate terminal of the first PMOS transistor 121-1 and the gate terminal of the second NMOS transistor 122-2 are connected to the node 150, and the gate terminal of the first NMOS transistor 122-1 (122-1-G) Connect to the clock signal (CLK). The second inverter 124-2 is configured in a similar manner except that the gate terminal of the second PMOS transistor 121-2 and the gate terminal of the fourth NMOS transistor 122-4 are coupled to CLK, and the third NMOS transistor The gate terminal of 122-3 is connected to node 139. The third inverter 124-3 is also configured in a similar manner except that the gate terminal of the third PMOS transistor 121-3 and the gate terminal of the sixth NMOS transistor 122-6 are coupled to the node 140, and the fifth NMOS The gate terminal of transistor 122-5 is connected to the outside of CLK. In the fourth inverter 124-4, the source terminal (121-4-S) of the fourth PMOS transistor 121-4 is coupled at node 123 to the 汲 terminal of the seventh NMOS transistor 122-7 ( 122-7-D). The drain terminal (121-4-D) of the fourth PMOS transistor 121-4 and the source terminal (122-7-S) of the seventh NMOS transistor 122-7 are coupled to the first bus bar 101 and ground, respectively . The gate terminal of the fourth PMOS transistor 121-4 and the gate terminal of the seventh NMOS transistor 122-7 are coupled to the 汲 terminal (122-8-D) of the eighth NMOS transistor 122-8, which further Coupled to node 141. The source terminal (122-8-S) and the gate terminal (122-8-G) of the eighth NMOS transistor 122-8 are coupled to ground and ENPR, respectively.

DFF 104的狀態轉變發生在CLK的上升沿。在一些實施例中，這個邊沿觸發的DFF 104以小功率消耗執行正反器操作，且可在集成式高速運算中實現。在操作期間，當CLK處於低相位時，第一反相器124-1從節點150取樣。第二反相器124-2是處於“預充電”模式下的動態反相器，其中第二PMOS電晶體121-2將節點140充電到高電平（例如，Vcc）。第三反相器124-3處於“保持”模式，因為第三PMOS電晶體121-3和第五NMOS電晶體122-5是斷開的。因此，在CLK的低相位期間，第三反相器124-3將其先前值保持在節點141上且保持穩定。在一些實施例中，使用由具有陡峭轉變斜率的時鐘產生器產生的CLK。舉例來說，可引入本地緩衝器以保證CLK的品質。在CLK的上升沿上，且當節點139在上升沿上處於高電平時，節點140放電。第三反相器124-3在CLK的高相位期間導通，且節點140上的值接著傳遞到節點141。在CLK的正相位上，如果節點150上的輸入轉變為高電平，那麼節點139轉變為低電平。因此，節點150處的輸入應保持穩定直到CLK的上升沿傳播到節點140。如果節點141處於高電平，那麼第四PMOS電晶體121-4斷開且第四反相器124-4中的第七NMOS電晶體122-7導通，導致節點123放電到低電平。如果節點141處於低電平，那麼第四PMOS電晶體121-4導通且第四反相器124-4中的第七NMOS電晶體122-7斷開，導致節點123充電到高電平。第四反相器124-4可通過對導通第八NMOS電晶體122-8的端子ENPR上的節點142施加高電平來重置。接著將節點141下拉到接地，所述接地隨後導通第四PMOS電晶體121-4，然後將節點123上拉到高電平（例如Vcc）。The state transition of DFF 104 occurs at the rising edge of CLK. In some embodiments, this edge triggered DFF 104 performs flip-flop operation with low power consumption and can be implemented in integrated high speed operation. During operation, when CLK is in a low phase, first inverter 124-1 samples from node 150. The second inverter 124-2 is a dynamic inverter in a "precharge" mode in which the second PMOS transistor 121-2 charges the node 140 to a high level (eg, Vcc). The third inverter 124-3 is in the "hold" mode because the third PMOS transistor 121-3 and the fifth NMOS transistor 122-5 are off. Thus, during the low phase of CLK, the third inverter 124-3 maintains its previous value on node 141 and remains stable. In some embodiments, CLK generated by a clock generator having a steep transition slope is used. For example, a local buffer can be introduced to ensure the quality of the CLK. On the rising edge of CLK, and when node 139 is at a high level on the rising edge, node 140 discharges. The third inverter 124-3 is turned on during the high phase of CLK, and the value on node 140 is then passed to node 141. On the positive phase of CLK, if the input on node 150 transitions to a high level, node 139 transitions to a low level. Therefore, the input at node 150 should remain stable until the rising edge of CLK propagates to node 140. If node 141 is at a high level, fourth PMOS transistor 121-4 is turned off and seventh NMOS transistor 122-7 of fourth inverter 124-4 is turned on, causing node 123 to discharge to a low level. If node 141 is at a low level, fourth PMOS transistor 121-4 is turned on and seventh NMOS transistor 122-7 of fourth inverter 124-4 is turned off, causing node 123 to charge to a high level. The fourth inverter 124-4 can be reset by applying a high level to the node 142 on the terminal ENPR of the eighth NMOS transistor 122-8. Node 141 is then pulled down to ground, which then turns on fourth PMOS transistor 121-4 and then pulls node 123 high (eg, Vcc).

多工器 130的輸入端子0耦接到節點123，同時多工器 130的輸入端子1耦接到對應PUF單元103的動態節點115，且多工器 130的輸出端子耦接到節點150。最後，多工器 130的端子EN 106耦接到第五匯流排106。當將低電平施加於多工器 130的端子EN 106上時，選擇輸入端子0且因此選擇節點123上的值作為DFF 104的節點150上的輸入。在端子EN 106切換到高電平時，通過4級聯反相器的回饋保持輸出穩定。當將高電平施加於多工器 130的端子EN 106上時，選擇輸入端子1且因此選擇對應PUF單元103的動態節點115上的值。類似地，在端子EN 106切換到低電平時，通過4級聯反相器的回饋保持輸出穩定。在一些實施例中，多工器 130可使用多個反及閘來構建，所述多個反及閘將在下文更加詳細地描述於圖1D中。The input terminal 0 of the multiplexer 130 is coupled to the node 123 while the input terminal 1 of the multiplexer 130 is coupled to the dynamic node 115 of the corresponding PUF unit 103, and the output terminal of the multiplexer 130 is coupled to the node 150. Finally, the terminal EN 106 of the multiplexer 130 is coupled to the fifth bus bar 106. When a low level is applied to terminal EN 106 of multiplexer 130, input terminal 0 is selected and thus the value on node 123 is selected as the input on node 150 of DFF 104. When the terminal EN 106 is switched to the high level, the output is stabilized by the feedback of the 4-stage inverter. When a high level is applied to the terminal EN 106 of the multiplexer 130, the input terminal 1 is selected and thus the value on the dynamic node 115 of the corresponding PUF unit 103 is selected. Similarly, when the terminal EN 106 is switched to the low level, the output is stabilized by the feedback of the 4-cascade inverter. In some embodiments, multiplexer 130 can be constructed using a plurality of inverse gates, which will be described in more detail below in FIG. 1D.

如上文所論述，根據各種實施例，除了PUF單元103的變化外，製造期間的固有製程變化也可能會造成DFF 104的變化，這會影響PUF簽名。具體地說，動態正反器的CMOS電晶體的物理性質的變化可促成正反器性能（例如，建立時間、保持時間以及傳播延遲）的變化。更具體地說，電晶體（尤其是第二反相器和第三反相器中那些下拉NMOS電晶體（例如，NMOS電晶體122-3、NMOS電晶體122 -4、NMOS電晶體122-5以及NMOS電晶體122-6））的不同暫態放電回應可確定不同的觸發點。也就是說，對於兩個相同的暫態放電行為，由於觸發點不同，兩個DFF 104可產生兩個不同的PUF簽名。As discussed above, in accordance with various embodiments, in addition to changes in PUF unit 103, inherent process variations during manufacturing may also cause changes in DFF 104, which may affect PUF signatures. In particular, changes in the physical properties of a CMOS transistor of a dynamic flip-flop can contribute to changes in flip-flop performance (eg, settling time, hold time, and propagation delay). More specifically, transistors (especially those of the second inverter and the third inverter) are pulled down NMOS transistors (for example, NMOS transistor 122-3, NMOS transistor 122-4, NMOS transistor 122-5) And different transient discharge responses of NMOS transistors 122-6)) can determine different trigger points. That is, for two identical transient discharge behaviors, the two DFFs 104 can generate two different PUF signatures due to different trigger points.

圖1D說明根據本公開的各種實施例的PUF產生器100的DFF 104中的具有雙輸入的多工器電路130的框圖和其真值表。多工器130選擇2個類比輸入或數位輸入中的一種，且將所選擇的輸入轉發到輸出。在某些實施例中，多工器電路130包括3個反及閘151、反及閘152及反及閘153，以及1個反相器154。反及閘是產生輸出的邏輯門，所述輸出只有在其所有輸入為真時才為假。第一反及閘的輸入端子155和輸入端子156分別連接到對應PUF單元103的動態節點115和第五匯流排106。第二反及閘的一個輸入端子通過反相器154連接到第五匯流排106，而另一輸入端子157連接到圖1C的DFF 104的第四PMOS電晶體121-4與第七NMOS電晶體122-7之間的節點123。第一反及閘151的輸出端子158和第二反及閘152的輸出端子159連接到第三反及閘153的輸入端子。第三反及閘153的輸出端子150接著連接到圖1C的DFF 104的第一PMOS電晶體121-1的端子G和第二NMOS電晶體122-2的端子G。FIG. 1D illustrates a block diagram of a multiplexer circuit 130 with dual inputs and its truth table in the DFF 104 of the PUF generator 100, in accordance with various embodiments of the present disclosure. The multiplexer 130 selects one of two analog input or digital input and forwards the selected input to the output. In some embodiments, multiplexer circuit 130 includes three anti-gates 151, anti-gate 152 and anti-gate 153, and an inverter 154. The inverse gate is a logic gate that produces an output that is false only if all of its inputs are true. The input terminal 155 and the input terminal 156 of the first reverse gate are connected to the dynamic node 115 and the fifth busbar 106 of the corresponding PUF unit 103, respectively. One input terminal of the second reverse gate is connected to the fifth bus bar 106 through the inverter 154, and the other input terminal 157 is connected to the fourth PMOS transistor 121-4 and the seventh NMOS transistor of the DFF 104 of FIG. 1C. Node 123 between 122-7. The output terminal 158 of the first anti-gate 151 and the output terminal 159 of the second anti-gate 152 are connected to the input terminal of the third anti-gate 153. The output terminal 150 of the third NAND gate 153 is then connected to the terminal G of the first PMOS transistor 121-1 of the DFF 104 of FIG. 1C and the terminal G of the second NMOS transistor 122-2.

在一些實施例中，反相器154可為其兩個輸入均連接到第五匯流排106的反及閘。在一些實施例中，反相器154是處於反相配置下的運算放大器（operational amplifier），其中運算放大器的正極端子連接到接地，且負極端子通過具有電阻RF的回饋電阻器直接連接到其輸出。在輸入電阻為RIN時，輸出隨後由增益（RF/RIN比）和負極端子上的輸入電壓電平定義。在一些實施例中，可使RF等於RIN且可實現具有單位增益的反相功能。In some embodiments, inverter 154 can be connected to the inverse of the fifth busbar 106 for both of its inputs. In some embodiments, inverter 154 is an operational amplifier in an inverting configuration, wherein the positive terminal of the operational amplifier is connected to ground and the negative terminal is directly connected to its output through a feedback resistor having a resistive RF . When the input resistance is RIN, the output is then defined by the gain (RF/RIN ratio) and the input voltage level on the negative terminal. In some embodiments, RF can be made equal to RIN and an inverting function with unity gain can be implemented.

在操作期間，當將低電平（即，邏輯“0”）施加於節點156上時，節點157通過多工器 130將其輸入電平傳遞到節點159作為輸出，而節點155處的輸入被阻斷。當將高電平（即，邏輯“1”）施加於節點156上時，節點155通過多工器 130將其輸入電平傳遞到節點158作為輸出，而節點157處的輸入被阻斷。During operation, when a low level (i.e., a logic "0") is applied to node 156, node 157 passes its input level through multiplexer 130 to node 159 as an output, while the input at node 155 is Blocked. When a high level (i.e., a logic "1") is applied to node 156, node 155 passes its input level through multiplexer 130 to node 158 as an output, while the input at node 157 is blocked.

圖1E說明根據本公開的各種實施例的圖1C的多工器 130中的反及閘151、反及閘152以及反及閘153的電路圖和其真值表。在一些實施例中，反及閘151/ 反及閘152/ 反及閘153可為NMOS 反及閘或PMOS 反及閘。在某些實施例中，反及閘151/ 反及閘152/ 反及閘153可為CMOS 反及閘。1E illustrates a circuit diagram and its truth table for the inverse gate 151, the inverse gate 152, and the inverse gate 153 of the multiplexer 130 of FIG. 1C, in accordance with various embodiments of the present disclosure. In some embodiments, the anti-gate 151 / anti-gate 152 / anti-gate 153 can be an NMOS NAND gate or a PMOS NAND gate. In some embodiments, the anti-gate 151 / anti-gate 152 / anti-gate 153 can be a CMOS NAND gate.

反及閘151/ 反及閘152/ 反及閘153包括2個PMOS電晶體161和162以及兩個NMOS電晶體163和164，其中第一PMOS電晶體161的端子S（161-S）耦接到第一NMOS電晶體163的端子D（163-D），且第一NMOS電晶體163的端子S（163-S）耦接到第二NMOS電晶體164的端子D（164-D）。第一PMOS電晶體161的端子D耦接到第一匯流排101。第二NMOS電晶體164的端子S（164-S）電耦接到接地。在一些實施例中，將第一PMOS電晶體161的端子G和第一NMOS電晶體163的端子G連接，並且進一步電耦接到第一反及閘151中的對應PUF單元103的動態節點115或第二反及閘152中的對應DFF 104的輸出節點123。在一些實施例中，第二NMOS電晶體164的端子G在第一反及閘151中的節點156處耦接到第五匯流排106，或通過第二反及閘152中的反相器154耦接到匯流排106。第二PMOS電晶體162的端子G耦接到第二NMOS電晶體164的端子G，而第二PMOS電晶體162的端子D和端子S分別耦接到第一匯流排101和第一PMOS電晶體161的端子S。第一PMOS電晶體161的端子S和第二PMOS電晶體162的端子S耦接到輸出節點158/輸出節點159/輸出節點150。The reverse gate 151/reverse gate 152/reverse gate 153 includes two PMOS transistors 161 and 162 and two NMOS transistors 163 and 164, wherein the terminal S (161-S) of the first PMOS transistor 161 is coupled The terminal D (163-D) of the first NMOS transistor 163 is coupled to the terminal D (164-D) of the second NMOS transistor 164. The terminal D of the first PMOS transistor 161 is coupled to the first bus bar 101. The terminal S (164-S) of the second NMOS transistor 164 is electrically coupled to ground. In some embodiments, the terminal G of the first PMOS transistor 161 and the terminal G of the first NMOS transistor 163 are connected, and further electrically coupled to the dynamic node 115 of the corresponding PUF unit 103 in the first inverse gate 151 Or the output node 123 of the corresponding DFF 104 in the second inverse gate 152. In some embodiments, terminal G of second NMOS transistor 164 is coupled to fifth busbar 106 at node 156 in first inverting gate 151, or through inverter 154 in second inverting gate 152. It is coupled to the bus bar 106. The terminal G of the second PMOS transistor 162 is coupled to the terminal G of the second NMOS transistor 164, and the terminal D and the terminal S of the second PMOS transistor 162 are coupled to the first bus bar 101 and the first PMOS transistor, respectively. Terminal S of 161. The terminal S of the first PMOS transistor 161 and the terminal S of the second PMOS transistor 162 are coupled to the output node 158 / output node 159 / output node 150.

在操作期間，當將高電平（即，邏輯“1”）施加於節點156上時，通過第二NMOS電晶體163將端子162-S上的電平下拉到接地。節點155/節點157將其反相輸入電平傳遞到節點158/節點159/節點150，其由上拉PMOS電晶體161或下拉NMOS電晶體163引起。當將低電平（即，邏輯“0”）施加於節點156上時，節點158/節點159/節點150上的電平不依賴於節點155/節點157上的電平，這是因為節點158/節點159/節點150始終由第二PMOS電晶體162上拉到高電平（即，Vcc）。During operation, when a high level (i.e., a logic "1") is applied to node 156, the level on terminal 162-S is pulled down to ground by second NMOS transistor 163. Node 155/node 157 passes its inverted input level to node 158/node 159/node 150, which is caused by pull-up PMOS transistor 161 or pull-down NMOS transistor 163. When a low level (i.e., a logic "0") is applied to node 156, the level on node 158/node 159/node 150 does not depend on the level on node 155/node 157 because node 158 /Node 159 / Node 150 is always pulled up by the second PMOS transistor 162 to a high level (ie, Vcc).

圖2說明根據本公開的各種實施例的在PUF單元103的動態節點115上和在由圖1A的PUF產生器100用來產生PUF簽名204的對應DFF 104的輸出節點123上的示範性信號200。為簡單起見，根據一些實施例，這裡使用產生4位元PUF簽名的4單元PUF產生器來進行論述。還應注意，為清楚說明起見，圖中各種特徵構件未必按比例繪製，且可任意地增大或減小。2 illustrates an exemplary signal 200 on dynamic node 115 of PUF unit 103 and on output node 123 of corresponding DFF 104 used by PUF generator 100 of FIG. 1A to generate PUF signature 204, in accordance with various embodiments of the present disclosure. . For simplicity, in accordance with some embodiments, a 4-cell PUF generator that generates a 4-bit PUF signature is used herein. It should also be noted that, for clarity of description, various features are not necessarily drawn to scale and may be arbitrarily increased or reduced.

在高電平狀態與低電平狀態之間振盪的方波形式的時鐘信號201通常用於同步數位電路中。此實施例中所使用的時鐘信號201具有50%占空比以及固定恒定頻率。在某些實施例中，任何類型的時鐘信號可與不同頻率或占空比一起使用。A clock signal 201 in the form of a square wave oscillating between a high state and a low state is typically used in a synchronous digital circuit. The clock signal 201 used in this embodiment has a 50% duty cycle and a fixed constant frequency. In some embodiments, any type of clock signal can be used with different frequencies or duty cycles.

根據各種實施例，PUF單元103的動態節點115上的線性暫態放電行為202用於說明PUF簽名的產生過程。為清楚起見，標號202-1、標號202-2、標號202-3以及標號202-4分別用以指代第一PUF單元103、第二PUF單元103、第三PUF單元103以及第四PUF單元103的動態節點115上的暫態放電行為。暫態放電行為202取決於管控存儲在動態節點115上的電荷以漏電流的形式漏泄的機構。在一些實施例中，暫態放電行為是電晶體的幾何結構（溝道長度、閘極氧化物厚度等）、介電常數、閾值電壓（Vt）、放電之前的初始電壓（Vcc-Vt）、電載流子的遷移率、溫度等的函數。在一些實施例中，第二NMOS電晶體114大於第一NMOS電晶體113，以便加快PUF簽名的產生過程。在一些實施例中，暫態放電行為202可為指數型的。動態節點115處不同的暫態放電行為520可導致不同放電時間，且最重要的是，導致不同的到達觸發點205的時間， 其中DFF 104輸出反轉的邏輯狀態。為了清楚起見，根據一些實施例，恒定觸發點205（即，Vcc/2）用於所有DFF 104。在另一實施例中，可使用由DFF 104的變化所引起的不同觸發點205。在一些實施例中，當由DFF電路所定義的不同觸發點205與相同的PUF單元一起使用時，可產生不同的PUF簽名。因此，PUF簽名由PUF單元103結合DFF 104而獨特地定義。According to various embodiments, the linear transient discharge behavior 202 on the dynamic node 115 of the PUF unit 103 is used to illustrate the generation process of the PUF signature. For the sake of clarity, reference numerals 202-1, 202-2, 202-3, and 202-4 are used to refer to the first PUF unit 103, the second PUF unit 103, the third PUF unit 103, and the fourth PUF, respectively. Transient discharge behavior on dynamic node 115 of unit 103. The transient discharge behavior 202 depends on the mechanism governing the leakage of charge stored on the dynamic node 115 in the form of leakage current. In some embodiments, the transient discharge behavior is the geometry of the transistor (channel length, gate oxide thickness, etc.), dielectric constant, threshold voltage (Vt), initial voltage before discharge (Vcc-Vt), A function of the mobility, temperature, etc. of the electric carriers. In some embodiments, the second NMOS transistor 114 is larger than the first NMOS transistor 113 in order to speed up the PUF signature generation process. In some embodiments, the transient discharge behavior 202 can be exponential. Different transient discharge behaviors 520 at the dynamic node 115 can result in different discharge times and, most importantly, result in different times of reaching the trigger point 205, where the DFF 104 outputs the inverted logic state. For clarity, a constant trigger point 205 (ie, Vcc/2) is used for all DFFs 104, in accordance with some embodiments. In another embodiment, different trigger points 205 caused by changes in the DFF 104 can be used. In some embodiments, different PUF signatures may be generated when different trigger points 205 defined by the DFF circuitry are used with the same PUF unit. Thus, the PUF signature is uniquely defined by the PUF unit 103 in conjunction with the DFF 104.

4個PUF單元103的動態節點115-1、動態節點115-2、動態節點115-3以及動態節點115-4處的充電之後的初始電壓分別是Vcc-Vt1、Vcc-Vt2、Vcc-Vt3以及Vcc-Vt4，其中Vtl、Vt2、Vt3以及Vt4分別是第一PUF單元103、第二PUF單元103、第三PUF單元103以及第四PUF單元103的第一NMOS電晶體113的閾值電壓。根據此實施例，放電之前的這些初始電壓值具有如下關係：0＜ Vcc-Vt2＜ Vcc-Vt3 ＜ Vcc-Vtl ＜ Vcc-Vt4 ＜ Vcc。不同閾值是由引起電晶體的物理性質的變化的製造過程中的變化（例如氧化物厚度、摻雜濃度、摻雜波動、氧化物和襯底的介電常數等）所產生。不同初始電壓電平進一步產生存儲在動態節點115上的不同總電荷。The initial voltages after charging at the dynamic node 115-1, the dynamic node 115-2, the dynamic node 115-3, and the dynamic node 115-4 of the four PUF units 103 are Vcc-Vt1, Vcc-Vt2, Vcc-Vt3, and Vcc-Vt4, where Vtl, Vt2, Vt3, and Vt4 are threshold voltages of the first NMOS transistor 113 of the first PUF unit 103, the second PUF unit 103, the third PUF unit 103, and the fourth PUF unit 103, respectively. According to this embodiment, these initial voltage values before discharge have the following relationship: 0 < Vcc - Vt2 < Vcc - Vt3 < Vcc - Vtl < Vcc - Vt4 < Vcc. Different thresholds are produced by variations in the manufacturing process (eg, oxide thickness, doping concentration, doping fluctuations, oxide and dielectric constant of the substrate, etc.) that cause changes in the physical properties of the transistor. Different initial voltage levels further produce different total charges stored on dynamic node 115.

圖2中還說明了來自DFF 104的節點123的對應輸出203。在暫態放電行為202從初始電壓轉變到觸發點205的同時或之後，當時鐘信號從低（邏輯“0”）電平切換到高（邏輯“1”）電平時，DFF 104可在其輸出上產生低電平（邏輯“0”）。由於第一PUF單元103-1的第二NMOS電晶體114的潛在高漏電流所導致的第一PUF單元103-1中的快速放電行為（202-1），動態節點115-1處的暫態行為觸發第一DFF 104-1反轉其邏輯狀態且在取樣時間t4輸出“0”。類似地，所有均慢于放電行為202-1的放電行為202-2、放電行為202-3以及放電行為202-4分別觸發對應的DFF 104以在取樣時間t6、取樣時間t4以及取樣時間tl5輸出“0”。根據各種實施例，因為放電行為202-3在取樣時間t4的上升沿之前越過觸發點205，儘管放電行為202-3的放電相較於202-1的放電較慢，但在兩個對應的DFF 104均輸出“0”時的時間實際上相同（即，t4）。The corresponding output 203 of node 123 from DFF 104 is also illustrated in FIG. At or after the transition of the transient discharge behavior 202 from the initial voltage to the trigger point 205, the DFF 104 may be at its output when the clock signal switches from a low (logic "0") level to a high (logic "1") level. A low level (logic "0") is generated. Transient state at the dynamic node 115-1 due to the rapid discharge behavior (202-1) in the first PUF unit 103-1 due to the potentially high leakage current of the second NMOS transistor 114 of the first PUF unit 103-1 The behavior triggers the first DFF 104-1 to invert its logic state and outputs "0" at the sampling time t4. Similarly, all of the discharge behavior 202-2, the discharge behavior 202-3, and the discharge behavior 202-4, which are slower than the discharge behavior 202-1, trigger the corresponding DFF 104 to output at the sampling time t6, the sampling time t4, and the sampling time t15, respectively. "0". According to various embodiments, because the discharge behavior 202-3 crosses the trigger point 205 before the rising edge of the sampling time t4, although the discharge of the discharge behavior 202-3 is slower than the discharge of 202-1, in the corresponding two DFFs The time when 104 outputs "0" is actually the same (ie, t4).

在取樣點t4處，第二PUF單元/動態正反器對和第四PUF單元/動態正反器對兩者均遞送零點的輸出。群體計數器檢測零點的數目（即，2），隨後將其與PUF單元的總數（即，4）進行比較。接著在取樣時間t4終止取樣，且隨後將記錄的4位元輸出“0101”用作此PUF產生器的PUF簽名204。At sample point t4, the second PUF unit/dynamic flip-flop pair and the fourth PUF unit/dynamic flip-flop pair both deliver an output of zero. The group counter detects the number of zeros (i.e., 2) and then compares it to the total number of PUF units (i.e., 4). The sampling is then terminated at sampling time t4, and then the recorded 4-bit output "0101" is used as the PUF signature 204 of this PUF generator.

圖3說明根據本公開的各種實施例的使用PUF產生器100產生PUF簽名的方法300的流程圖。在各種實施例中，根據各種實施例，方法300的操作由圖1A到圖1E中所說明的相應元件執行。出於論述的目的，方法300的以下實施例將結合圖1A到圖1E以及圖2來描述。方法300的所說明實施例僅為實例。因此，應理解，各種操作中的任一種可省略、重新排序和/或添加，同時保持在本公開的範圍內。FIG. 3 illustrates a flow diagram of a method 300 of generating a PUF signature using PUF generator 100, in accordance with various embodiments of the present disclosure. In various embodiments, the operation of method 300 is performed by the respective elements illustrated in Figures 1A-1E, in accordance with various embodiments. For purposes of discussion, the following embodiments of method 300 will be described in conjunction with FIGS. 1A-1E and 2. The illustrated embodiment of method 300 is merely an example. Accordingly, it should be understood that any of a variety of operations may be omitted, reordered, and/or added while remaining within the scope of the present disclosure.

根據各種實施例，方法300從將多個PUF單元的多個動態節點充電到高電平（例如，邏輯“1”）的操作302開始。在匯流排102上施加高電平會導通多個第一NMOS電晶體，接著將多個動態節點上拉到高電平，以便用邏輯“1”編寫多個動態節點。存儲在多個動態節點處的精確電荷由多個第一NMOS電晶體的對應閾值電壓定義。According to various embodiments, method 300 begins with operation 302 of charging a plurality of dynamic nodes of a plurality of PUF units to a high level (eg, a logic "1"). Applying a high level on the bus bar 102 turns on a plurality of first NMOS transistors, and then pulls a plurality of dynamic nodes up to a high level to write a plurality of dynamic nodes with a logic "1." The precise charge stored at the plurality of dynamic nodes is defined by the corresponding threshold voltages of the plurality of first NMOS transistors.

方法300繼續進行操作304，其中以固定時間間隔對多個動態節點的暫態放電行為取樣。如上文所描述，對應於多個PUF單元的多個動態正反器電路可用於執行取樣，如圖1A到圖1E以及圖2中所繪示及論述。與多個動態節點相關聯的暫態放電行為由對應的第二NMOS電晶體上的漏電流引起，所述漏電流包含寄生亞閾值電流、由福勒諾德海姆穿隧（Fowler-Nordheim tunneling）所產生的閘極漏電流、閘極誘發的汲極漏電流、反向偏置電流等。固有製程變化導致多個動態節點處的放電行為的變化。當時鐘信號從低電平切換到高電平時，對PUF單元的多個動態節點處的電壓值取樣且將其與對應動態正反器電路所定義的觸發點進行比較。如果動態節點上的電壓值高於觸發點，那麼產生邏輯“1”，且類似地，如果電壓值下降到低於觸發點，那麼其邏輯狀態反轉且產生邏輯“0”。The method 300 continues with operation 304 in which the transient discharge behavior of a plurality of dynamic nodes is sampled at fixed time intervals. As described above, a plurality of dynamic flip-flop circuits corresponding to a plurality of PUF units can be used to perform sampling, as depicted and discussed in FIGS. 1A-1E and 2. The transient discharge behavior associated with the plurality of dynamic nodes is caused by a leakage current on the corresponding second NMOS transistor, which includes a parasitic sub-threshold current, tunneling by Fowler-Nordheim (Fowler-Nordheim tunneling) The gate leakage current generated by the gate, the gate leakage current induced by the gate, the reverse bias current, and the like. Inherent process variations result in changes in the discharge behavior at multiple dynamic nodes. When the clock signal is switched from low to high, the voltage values at the plurality of dynamic nodes of the PUF unit are sampled and compared to the trigger points defined by the corresponding dynamic flip-flop circuit. A logic "1" is generated if the voltage value on the dynamic node is above the trigger point, and similarly, if the voltage value falls below the trigger point, its logic state is inverted and a logic "0" is generated.

根據各種實施例，方法300繼續進行操作306，其中通過群體計數器接收並計數具有邏輯“0”的動態節點的總數且將所述總數與PUF產生器電路100中的多個動態節點的總數（即，N）相比較。如果具有邏輯“0”的動態節點的總數小於N/2，那麼方法300繼續進行操作304，其中在第二取樣時間對多個動態節點執行新的取樣。如果具有邏輯“0”的動態節點的總數等於或大於N/2，那麼方法300接著進行操作308，其中輸出在特定取樣時間產生的N位元二進位符號作為PUF簽名。如上文在圖1A到圖1E以及圖2中所論述，動態節點放電所需的時間和輸出邏輯“0”所需的時間受到存儲在動態節點上的總電荷、第二NMOS電晶體上的總漏電流以及由對應動態正反器電路所定義的觸發點的影響。According to various embodiments, method 300 continues with operation 306 in which the total number of dynamic nodes having a logical "0" is received and counted by the community counter and the total number is the total number of dynamic nodes in the PUF generator circuit 100 (ie, , N) compared. If the total number of dynamic nodes having a logical "0" is less than N/2, then method 300 proceeds to operation 304 where new samples are performed on the plurality of dynamic nodes at the second sampling time. If the total number of dynamic nodes having a logical "0" is equal to or greater than N/2, then method 300 proceeds to operation 308 where the N-bit binary symbol generated at a particular sampling time is output as a PUF signature. As discussed above in Figures 1A through 1E and Figure 2, the time required for dynamic node discharge and the time required to output a logic "0" are affected by the total charge stored on the dynamic node, the total on the second NMOS transistor. Leakage current and the effect of the trigger point defined by the corresponding dynamic flip-flop circuit.

圖4A說明根據本公開的各種實施例的PUF產生器400的示範性框圖。應注意，系統400僅為實例且不意圖限制本公開。因此，應理解，可在圖4A的系統400之前、期間以及之後提供額外的操作，且可以在本文中僅簡要地描述一些其它操作。FIG. 4A illustrates an exemplary block diagram of a PUF generator 400 in accordance with various embodiments of the present disclosure. It should be noted that system 400 is merely an example and is not intended to limit the disclosure. Accordingly, it should be understood that additional operations may be provided before, during, and after the system 400 of FIG. 4A, and that some other operations may only be briefly described herein.

相比於圖1A，除了第一匯流排101和第二匯流排102之外，向多個PUF單元410提供第三匯流排412（讀使能匯流排）和第四匯流排413（預放電匯流排）。將來自PUF單元410的輸出連接到有限狀態機電路120。更具體地說，輸出連接到對應DFF 104，接著連接到如圖1A、圖1C到圖1E中所描述及論述的群體計數器 105和評估邏輯電路107。In comparison to FIG. 1A, in addition to the first bus bar 101 and the second bus bar 102, a plurality of PUF units 410 are provided with a third bus bar 412 (read enable bus bar) and a fourth bus bar 413 (pre-discharge bus bar) row). The output from PUF unit 410 is coupled to finite state machine circuit 120. More specifically, the output is coupled to the corresponding DFF 104, and then to the population counter 105 and evaluation logic 107 as described and discussed in Figures 1A, 1C-1E.

圖4B說明根據本公開的各種實施例的圖4A的PUF產生器400的PUF單元410的電路圖。PUF單元410包括3個NMOS電晶體（即，NMOS電晶體414、NMOS電晶體415以及NMOS電晶體418）和2個PMOS電晶體（即，PMOS電晶體416和PMOS電晶體417）。第一NMOS電晶體414的源極端子（414-S）和第二NMOS電晶體415的汲極端子（415-D）耦接在第一動態節點419處，而第一NMOS電晶體414的汲極端子（414-D）和第二NMOS電晶體415的源極端子（415-S）分別耦接到第一匯流排101和接地。第一NMOS電晶體414的閘極端子和第二NMOS電晶體415的閘極端子分別耦接到第二匯流排102和接地。第一PMOS電晶體416的源極端子（416-S）直接耦接到第二PMOS電晶體417的汲極端子（417-D），且第二PMOS電晶體417的源極端子（417-S）在第二動態節點420處耦接到第三NMOS電晶體418的汲極端子（418-D）。第一PMOS電晶體416的汲極端子（416-D）和閘極端子（416-G）分別耦接到第一匯流排101和第三匯流排412。第二PMOS電晶體417的閘極端子（417-G）耦接到第一動態節點419。最後，第三NMOS電晶體418的閘極端子（418-G）和源極端子（418-S）分別耦接到第四匯流排413和接地。第一匯流排101提供電平為Vcc的電壓。第二匯流排102用於對第一NMOS電晶體414充電，而第三匯流排412用於通過導通第一上拉PMOS電晶體416來使得能夠讀取第二動態節點420。第四匯流排413用於通過第三下拉NMOS電晶體418來對PUF單元410的第二動態節點420預放電。FIG. 4B illustrates a circuit diagram of PUF unit 410 of PUF generator 400 of FIG. 4A, in accordance with various embodiments of the present disclosure. The PUF unit 410 includes three NMOS transistors (ie, an NMOS transistor 414, an NMOS transistor 415, and an NMOS transistor 418) and two PMOS transistors (ie, a PMOS transistor 416 and a PMOS transistor 417). The source terminal (414-S) of the first NMOS transistor 414 and the 汲 terminal (415-D) of the second NMOS transistor 415 are coupled at the first dynamic node 419, and the NMOS of the first NMOS transistor 414 The source terminal (415-S) of the terminal (414-D) and the second NMOS transistor 415 are coupled to the first bus bar 101 and ground, respectively. The gate terminal of the first NMOS transistor 414 and the gate terminal of the second NMOS transistor 415 are coupled to the second bus bar 102 and ground, respectively. The source terminal (416-S) of the first PMOS transistor 416 is directly coupled to the drain terminal (417-D) of the second PMOS transistor 417, and the source terminal of the second PMOS transistor 417 (417-S) At the second dynamic node 420 is coupled to the drain terminal (418-D) of the third NMOS transistor 418. The first terminal (416-D) and the gate terminal (416-G) of the first PMOS transistor 416 are coupled to the first bus bar 101 and the third bus bar 412, respectively. A gate terminal (417-G) of the second PMOS transistor 417 is coupled to the first dynamic node 419. Finally, the gate terminal (418-G) and the source terminal (418-S) of the third NMOS transistor 418 are coupled to the fourth bus bar 413 and ground, respectively. The first bus bar 101 provides a voltage of level Vcc. The second bus bar 102 is for charging the first NMOS transistor 414, and the third bus bar 412 is for enabling the second dynamic node 420 to be read by turning on the first pull-up PMOS transistor 416. The fourth bus bar 413 is for pre-discharging the second dynamic node 420 of the PUF unit 410 through the third pull-down NMOS transistor 418.

通過對匯流排102施加高電平而導通第一NMOS電晶體414之後，由第一NMOS電晶體414對第一動態節點419充電。將第一動態節點419處的電壓電平上拉到電壓電平Vcc-Vtl，其中Vtl是第一NMOS電晶體414的閾值電壓。當將低電平施加於第三匯流排412上時，第一上拉PMOS電晶體416導通。最初，因為將第一動態節點419充電到高電平Vcc-Vt，第二PMOS電晶體417因此斷開，在通過對第三NMOS電晶體418施加高電平而預放電之後的第二動態節點420保持在低電平。在由於第一NMOS電晶體415上的漏電流而使第一動態節點419放電期間，存在一個其中第一動態節點419上的電壓電平變得足夠低以導通第二PMOS電晶體417以便將第二動態節點420充電到高電平的時間，該高電平等於Vcc-Vt3-Vt4，其中Vt3和Vt4是第一PMOS電晶體416和第二PMOS電晶體417的閾值電壓。After the first NMOS transistor 414 is turned on by applying a high level to the bus bar 102, the first dynamic node 419 is charged by the first NMOS transistor 414. The voltage level at the first dynamic node 419 is pulled up to a voltage level Vcc-Vtl, where Vtl is the threshold voltage of the first NMOS transistor 414. When a low level is applied to the third bus bar 412, the first pull-up PMOS transistor 416 is turned on. Initially, because the first dynamic node 419 is charged to a high level Vcc-Vt, the second PMOS transistor 417 is thus turned off, the second dynamic node after being pre-discharged by applying a high level to the third NMOS transistor 418. 420 remains at a low level. During the discharge of the first dynamic node 419 due to the leakage current on the first NMOS transistor 415, there is a voltage level in which the first dynamic node 419 becomes sufficiently low to turn on the second PMOS transistor 417 for the first When the second dynamic node 420 is charged to a high level, the high level is equal to Vcc - Vt3 - Vt4, where Vt3 and Vt4 are the threshold voltages of the first PMOS transistor 416 and the second PMOS transistor 417.

圖5說明根據本公開的各種實施例的在第一動態節點（419）和第二動態節點（420）上以及在由圖4A的PUF產生器400用來產生PUF簽名505的DFF 104的輸出節點123上的示範性信號500與時間的關係。為簡單起見，根據一些實施例，此次使用產生4位元PUF簽名的4單元PUF產生器來進行論述。應注意，這僅為實例且不意圖限制本公開。應注意，為清楚說明起見，圖中的各種特徵構件未按必比例繪製，且可任意地增大或減小。5 illustrates output nodes of DFF 104 on first dynamic node (419) and second dynamic node (420) and used by PUF generator 400 of FIG. 4A to generate PUF signature 505, in accordance with various embodiments of the present disclosure. The exemplary signal 500 on 123 is related to time. For simplicity, this is discussed using a 4-element PUF generator that produces a 4-bit PUF signature, according to some embodiments. It should be noted that this is merely an example and is not intended to limit the disclosure. It should be noted that, for the sake of clarity, the various features in the figures are not necessarily drawn to scale and may be arbitrarily increased or decreased.

這裡不重複四個PUF單元中的第一動態節點419的放電過程，因先前在圖2中已描述。第一動態節點419的暫態放電行為通過導通第二PMOS電晶體417來觸發第二動態節點420的充電。開始對第二動態節點420充電的觸發點506受PUF單元410的第二PMOS電晶體417的閾值電壓（Vt4 ）控制。根據各種實施例，四個第二PMOS電晶體417的閾值電壓由於固有製程變化而不同，所述固有製程變化可用以產生獨特的PUF簽名。The discharge process of the first dynamic node 419 of the four PUF units is not repeated here as previously described in FIG. The transient discharge behavior of the first dynamic node 419 triggers charging of the second dynamic node 420 by turning on the second PMOS transistor 417. The trigger point 506 that begins charging the second dynamic node 420 is controlled by the threshold voltage (V t4 ) of the second PMOS transistor 417 of the PUF unit 410. According to various embodiments, the threshold voltages of the four second PMOS transistors 417 are different due to inherent process variations that may be used to generate a unique PUF signature.

再次參考圖5，虛線506-1（Vt1-1 ）、虛線506-2（Vt1-2 ）、虛線506-3（Vt1-3 ）以及虛線506-4（Vt1-4 ）分別表示第一PUF單元410、第二PUF單元410、第三PUF單元410以及第四PUF單元410中的第二NMOS電晶體415的閾值電壓。虛線506與對應的暫態放電行為502之間的交叉點是導通對應第二PMOS電晶體417的時間。在一些實施例中，Vt1-4 ＞Vt1-2 ＞Vt1-1 ＞Vt1-3 可能會影響存儲在第一動態節點419上的總電荷，且在相同的暫態放電行為下，不同閾值電壓可導致第二PMOS電晶體在不同時間點導通以便對第二動態節點420充電。Referring again to FIG. 5, a broken line 506-1 (V t1-1 ), a broken line 506-2 (V t1-2 ), a broken line 506-3 (V t1-3 ), and a broken line 506-4 (V t1-4 ) respectively represent Threshold voltages of the first NMOS transistor 415 in the first PUF unit 410, the second PUF unit 410, the third PUF unit 410, and the fourth PUF unit 410. The intersection between the dashed line 506 and the corresponding transient discharge behavior 502 is the time to turn on the corresponding second PMOS transistor 417. In some embodiments, V t1-4> V t1-2> V t1-1> V t1-3 may affect the overall charge is stored on a first dynamic node 419, and at the same discharge transient behavior, Different threshold voltages may cause the second PMOS transistor to conduct at different points in time to charge the second dynamic node 420.

圖5中還繪示了4個PUF單元410的第二動態節點420上的暫態充電行為503（即，電壓對比時間）。4個第二動態節點420在第一PUF單元410、第二PUF單元410、第三PUF單元410以及第四PUF單元410中的第二PMOS電晶體417分別在tc1、tc2、tc3以及tc4導通之後開始充電。在一些實施例中，4個第二動態節點420中的每一個的充電消耗時間不同（即，斜率不同）。一旦4個第二動態節點420充滿電，則其上的電壓可使用Vcc-Vt3-Vt4來計算。因此，在來自第一PMOS電晶體416和第二PMOS電晶體417的不同閾值電壓下，充電後的第二動態節點420處的電壓可能不同。出於清楚的目的，常量Vcc-Vt3-Vt4用於所有4個第二動態節點420。如上文所論述，使DFF 104檢測邏輯狀態的轉變的觸發點可能不同且由DFF 104（尤其是放電電晶體）定義。出於清楚的目的，恒定觸發點還用於4個DFF 104。通過不斷監測第二動態節點420處的暫態充電行為503（例如，電壓對比時間）且將處於特定取樣時間的第二動態節點上的電壓值與觸發點507進行比較，可確定對應PUF單元的輸出邏輯“0”或“1”。在某些實施例中，第二PUF單元410的第二動態節點420首先充電到高電平，接著是第一PUF單元410、第四PUF單元410以及第三PUF單元410的第二動態節點420充電到高電平。The transient charging behavior 503 (ie, voltage versus time) on the second dynamic node 420 of the four PUF units 410 is also depicted in FIG. The second PMOS transistors 417 of the four second dynamic nodes 420 in the first PUF unit 410, the second PUF unit 410, the third PUF unit 410, and the fourth PUF unit 410 are turned on after tc1, tc2, tc3, and tc4, respectively. Start charging. In some embodiments, the charge consumption time of each of the four second dynamic nodes 420 is different (ie, the slope is different). Once the four second dynamic nodes 420 are fully charged, the voltage on them can be calculated using Vcc-Vt3-Vt4. Thus, at different threshold voltages from the first PMOS transistor 416 and the second PMOS transistor 417, the voltage at the second dynamic node 420 after charging may be different. For the sake of clarity, the constant Vcc-Vt3-Vt4 is used for all four second dynamic nodes 420. As discussed above, the trigger points that cause the DFF 104 to detect a transition of the logic state may be different and are defined by the DFF 104 (especially a discharge transistor). For the sake of clarity, a constant trigger point is also used for the 4 DFFs 104. By continuously monitoring the transient charging behavior 503 at the second dynamic node 420 (eg, voltage versus time) and comparing the voltage value at the second dynamic node at a particular sampling time with the trigger point 507, the corresponding PUF unit can be determined. Output logic "0" or "1". In some embodiments, the second dynamic node 420 of the second PUF unit 410 is first charged to a high level, followed by a first dynamic node 420 of the first PUF unit 410, the fourth PUF unit 410, and the third PUF unit 410. Charge to high level.

對應DFF 104的輸出節點123上的二進位輸出繪示於圖5的方框504中。在暫態充電行為503從初始低電壓轉變到觸發點507的同時或之後，當時鐘信號501從低（邏輯“0”）電平切換到高（邏輯“1”）電平時，DFF 104可在其輸出上產生高電平（邏輯“1”）。根據一些實施例，第二PMOS電晶體還充當放大器。第一DFF電路104、第二DFF電路104、第三DFF電路104以及第四DFF電路104分別在取樣時間t10、取樣時間t8、取樣時間tl4以及取樣時間tl4將邏輯狀態從0切換到1。此外，在取樣時間t10，兩個PUF單元已將邏輯狀態從0切換到1，且將處於取樣時間t10的所有PUF單元的邏輯狀態的組合的1100二進位序列用作PUF簽名。DFF 104中的第一NMOS電晶體和第二NMOS電晶體、第一PMOS電晶體和第二PMOS電晶體以及放電電晶體的製造中的固有製程變化決定放電過程/充電過程和觸發點，其全部有助於獨特的PUF簽名的產生。The binary output on output node 123 corresponding to DFF 104 is depicted in block 504 of FIG. Simultaneously with or after the transient charging behavior 503 transitions from the initial low voltage to the trigger point 507, when the clock signal 501 switches from a low (logic "0") level to a high (logic "1") level, the DFF 104 can A high level (logic "1") is generated on its output. According to some embodiments, the second PMOS transistor also acts as an amplifier. The first DFF circuit 104, the second DFF circuit 104, the third DFF circuit 104, and the fourth DFF circuit 104 switch the logic state from 0 to 1 at the sampling time t10, the sampling time t8, the sampling time t14, and the sampling time t14, respectively. Furthermore, at sampling time t10, the two PUF units have switched the logic state from 0 to 1, and the combined 1100 bin sequence of the logical states of all PUF units at sampling time t10 is used as the PUF signature. The inherent process variations in the fabrication of the first NMOS transistor and the second NMOS transistor, the first PMOS transistor and the second PMOS transistor, and the discharge transistor in the DFF 104 determine the discharge process/charge process and the trigger point, all of which Helps create unique PUF signatures.

圖6說明根據各種實施例的使用PUF產生器400產生PUF簽名的方法600的流程圖。方法600以操作602開始，其中通過對匯流排413施加高電平而將多個第二動態節點420預放電到接地。方法600繼續進行操作604，其中通過對匯流排102施加高電平而將多個第一動態節點419充電到高電平，例如Vcc。方法600繼續進行操作606，其中將高電平施加於匯流排412上以使得能夠讀取多個第二動態節點420。方法600繼續進行操作608，其中以固定時間間隔對由多個PUF單元中的多個第一動態節點419上的不同放電過程和多個DFF電路（圖1C）中的輸出節點123上的觸發過程所引起的多個第二動態節點420的不同充電過程取樣。將從低電平（即，“0”）充電到高電平（即，“1”）的第二動態節點420的總數與第二動態節點420的總數（例如，N）相比較。在操作610，如果少於N/2的第二動態節點420充電到“1”，那麼方法600繼續進行操作608以重複取樣操作和檢測操作。如果大於或等於N/2的第二動態節點420充電到“1”，那麼方法600繼續進行操作612，產生基於多個PUF單元和DFF電路的狀態的PUF簽名。FIG. 6 illustrates a flow diagram of a method 600 of generating a PUF signature using PUF generator 400, in accordance with various embodiments. The method 600 begins with operation 602 in which a plurality of second dynamic nodes 420 are pre-discharged to ground by applying a high level to the bus bar 413. The method 600 continues with operation 604 in which a plurality of first dynamic nodes 419 are charged to a high level, such as Vcc, by applying a high level to the bus bar 102. The method 600 continues with operation 606 in which a high level is applied to the bus bar 412 to enable reading of the plurality of second dynamic nodes 420. The method 600 continues with operation 608 in which a different discharge process on a plurality of first dynamic nodes 419 of the plurality of PUF units and a triggering process on the output node 123 in the plurality of DFF circuits (FIG. 1C) are performed at fixed time intervals. The different charging processes of the plurality of second dynamic nodes 420 are sampled. The total number of second dynamic nodes 420 that are charged from a low level (ie, "0") to a high level (ie, "1") is compared to the total number of second dynamic nodes 420 (eg, N). At operation 610, if the second dynamic node 420 less than N/2 is charged to "1," then the method 600 proceeds to operation 608 to repeat the sampling operation and the detecting operation. If the second dynamic node 420 greater than or equal to N/2 is charged to "1," then the method 600 proceeds to operation 612 to generate a PUF signature based on the states of the plurality of PUF units and DFF circuits.

在一實施例中，物理不可複製功能產生器包括：多個物理不可複製功能單元，其中所述多個物理不可複製功能單元中的每一個包括第一金屬氧化物半導體電晶體和第二金屬氧化物半導體電晶體，其中第一金屬氧化物半導體電晶體的源極在動態節點處連接到第二金屬氧化物半導體電晶體的汲極，第一金屬氧化物半導體電晶體的汲極耦接到第一匯流排且第一n型金屬氧化物半導體電晶體的閘極耦接到第二匯流排，且第二n型金屬氧化物半導體電晶體的源極和閘極耦接到地面；多個動態正反器電路，其中所述多個動態正反器電路中的每一個分別耦接到多個物理不可複製功能單元中的每一個；群體計數電路，其耦接到多個動態正反器電路；以及評估邏輯電路，其具有耦接到群體計數電路的輸入和耦接到多個動態正反器電路的輸出。在一實施例中，所述第一金屬氧化物半導體電晶體和所述第二金屬氧化物半導體電晶體各自包括N型金屬氧化物半導體電晶體。在一實施例中，所述第二匯流排在第一時間耦接到高電壓電平以便將所述動態節點充電到與所述第一匯流排上的電壓不同的第一電壓。在一實施例中，所述第二匯流排在第二時間耦接到低電壓電平以便在第三時間通過所述第二金屬氧化物半導體電晶體將所述動態節點放電到第二電壓。在一實施例中，所述多個動態正反器電路配置成確定相應物理不可複製功能單元的所述動態節點何時從第一邏輯狀態反轉到第二邏輯狀態。在一實施例中，所述多個動態正反器電路配置多個第三電壓。在一實施例中，當所述物理不可複製功能單元的所述動態節點上在所述第三時間的所述第二電壓變得低於所述對應動態正反器電路的第三電壓時，確定從所述第一邏輯狀態到所述第二邏輯狀態的所述反轉。在一實施例中，所述群體計數電路配置成檢測處於所述第二邏輯狀態的物理不可複製功能單元的數目。在一實施例中，所述評估邏輯電路配置成將處於所述第二邏輯狀態的物理不可複製功能單元的數目與所述物理不可複製功能產生器中的物理不可複製功能單元的總數相比較以產生物理不可複製功能簽名。在一實施例中，當處於所述第二邏輯狀態的物理不可複製功能單元的所述數目等於或高於所述物理不可複製功能產生器中的物理不可複製功能單元的所述總數的一半時，所述物理不可複製功能簽名在第四時間產生。在一實施例中，所述物理不可複製功能簽名是包括所述物理不可複製功能產生器中的所述多個物理不可複製功能單元中的每一個的邏輯狀態的組合的多位元二進位序列。In an embodiment, the physical non-reproducible function generator includes: a plurality of physical non-reproducible functional units, wherein each of the plurality of physical non-reproducible functional units includes a first metal oxide semiconductor transistor and a second metal oxide a semiconductor transistor, wherein a source of the first metal oxide semiconductor transistor is connected to a drain of the second metal oxide semiconductor transistor at a dynamic node, and a drain of the first metal oxide semiconductor transistor is coupled to the first a bus bar and a gate of the first n-type metal oxide semiconductor transistor is coupled to the second bus bar, and a source and a gate of the second n-type metal oxide semiconductor transistor are coupled to the ground; a flip-flop circuit, wherein each of the plurality of dynamic flip-flop circuits is coupled to each of a plurality of physical non-reproducible functional units; a population counting circuit coupled to the plurality of dynamic flip-flop circuits And an evaluation logic circuit having an input coupled to the group counting circuit and an output coupled to the plurality of dynamic flip-flop circuits. In an embodiment, the first metal oxide semiconductor transistor and the second metal oxide semiconductor transistor each comprise an N-type metal oxide semiconductor transistor. In an embodiment, the second bus bar is coupled to a high voltage level at a first time to charge the dynamic node to a first voltage that is different from a voltage on the first bus bar. In an embodiment, the second bus bar is coupled to a low voltage level at a second time to discharge the dynamic node to the second voltage through the second metal oxide semiconductor transistor at a third time. In an embodiment, the plurality of dynamic flip-flop circuits are configured to determine when the dynamic node of the respective physical non-replicable functional unit is inverted from the first logic state to the second logic state. In an embodiment, the plurality of dynamic flip-flop circuits are configured with a plurality of third voltages. In an embodiment, when the second voltage at the third time on the dynamic node of the physical non-reproducible functional unit becomes lower than a third voltage of the corresponding dynamic flip-flop circuit, The inversion from the first logic state to the second logic state is determined. In an embodiment, the population counting circuit is configured to detect the number of physical non-replicable functional units in the second logical state. In an embodiment, the evaluation logic is configured to compare a number of physical non-replicable functional units in the second logical state with a total number of physical non-replicable functional units in the physical non-reproducible function generator Generate a physical non-replicable feature signature. In an embodiment, when the number of physical non-replicable functional units in the second logical state is equal to or higher than half of the total number of physical non-replicable functional units in the physical non-reproducible function generator The physical non-replicable function signature is generated at the fourth time. In an embodiment, the physical non-replicable function signature is a multi-bit binary sequence including a combination of logical states of each of the plurality of physical non-reproducible functional units in the physical non-reproducible function generator .

在另一實施例中，一種配置用於產生物理不可複製功能簽名的物理不可複製功能產生器的方法，所述方法包括：將多個物理不可複製功能單元耦接到多個動態正反器電路，及耦接到群體計數器且進一步耦接到評估邏輯電路，其中多個物理不可複製功能單元中的每一個包括第一金屬氧化物半導體電晶體和第二金屬氧化物半導體電晶體；通過多個第一金屬氧化物半導體電晶體中的每一個將多個物理不可複製功能單元中的多個動態節點充電到多個第一電壓；通過多個第二金屬氧化物半導體電晶體中的每一個將多個動態節點放電到多個第二電壓；使用對應的動態正反器電路監測多個第二電壓中的每一個；當第二電壓變得小於第三電壓時，將多個物理不可複製功能單元的邏輯狀態從第一邏輯狀態反轉到第二邏輯狀態；以及當具有反轉邏輯狀態的物理不可複製功能單元的數目超過物理不可複製功能單元的總數的一半時，產生物理不可複製功能簽名。在一實施例中，所述第一金屬氧化物半導體電晶體配置成具有在所述動態節點處耦接到所述第二金屬氧化物半導體電晶體的汲極端子的源極端子、耦接到第一匯流排的汲極以及耦接到第二匯流排的閘極端子。在一實施例中，在一實施例中，所述第二金屬氧化物半導體電晶體配置成具有耦接到地面的源極端子和閘極端子。在一實施例中，所述第一金屬氧化物半導體電晶體和所述第二金屬氧化物半導體電晶體各自包括N型金屬氧化物半導體電晶體。在一實施例中，對應物理不可複製功能單元的所述動態節點上的所述第一電壓由對應物理不可複製功能單元的所述第一金屬氧化物半導體電晶體的閾值電壓確定。在一實施例中，所述動態節點放電到所述第二電壓所需的時間由通過對應物理不可複製功能單元的所述第二金屬氧化物半導體電晶體的電流漏泄來確定。在一實施例中，所述第三電壓由所述對應動態正反器電路確定。In another embodiment, a method of configuring a physical non-replicable function generator for generating a physical non-replicable function signature, the method comprising: coupling a plurality of physical non-reproducible functional units to a plurality of dynamic flip-flop circuits And coupled to the population counter and further coupled to the evaluation logic circuit, wherein each of the plurality of physical non-reproducible functional units comprises a first metal oxide semiconductor transistor and a second metal oxide semiconductor transistor; Each of the first metal oxide semiconductor transistors charges a plurality of dynamic nodes of the plurality of physically non-reproducible functional units to the plurality of first voltages; through each of the plurality of second metal oxide semiconductor transistors The plurality of dynamic nodes are discharged to the plurality of second voltages; each of the plurality of second voltages is monitored using a corresponding dynamic flip-flop circuit; and the plurality of physical non-reproducible functions are performed when the second voltage becomes less than the third voltage The logical state of the cell is inverted from the first logic state to the second logic state; and when the physical state with the inverted logic state is not replicable The number of units can be more than half of the total physical unclonable function unit generates a physical unclonable function signatures. In an embodiment, the first metal oxide semiconductor transistor is configured to have a source terminal coupled to the first terminal of the second metal oxide semiconductor transistor at the dynamic node, coupled to The drain of the first bus bar and the gate terminal of the second bus bar. In an embodiment, in an embodiment, the second metal oxide semiconductor transistor is configured to have a source terminal and a gate terminal coupled to the ground. In an embodiment, the first metal oxide semiconductor transistor and the second metal oxide semiconductor transistor each comprise an N-type metal oxide semiconductor transistor. In an embodiment, the first voltage on the dynamic node corresponding to the physical non-reproducible functional unit is determined by a threshold voltage of the first metal oxide semiconductor transistor corresponding to the physical non-reproducible functional unit. In an embodiment, the time required for the dynamic node to discharge to the second voltage is determined by current leakage through the second metal oxide semiconductor transistor corresponding to the physically non-reproducible functional unit. In an embodiment, the third voltage is determined by the corresponding dynamic flip-flop circuit.

然而，在另一實施例中，一種用於產生物理不可複製功能簽名的物理不可複製功能產生器，所述物理不可複製功能產生器包括：多個物理不可複製功能單元，其中多個物理不可複製功能單元中的每一個包括五個金屬氧化物半導體電晶體，其中第一金屬氧化物半導體電晶體和第二金屬氧化物半導體電晶體配置成對第一動態節點充電和放電，第三金屬氧化物半導體電晶體和第四金屬氧化物半導體電晶體配置成對第二動態節點充電，且第五金屬氧化物半導體電晶體配置成使第二動態節點放電以便重置第二動態節點；多個動態正反器電路，其中多個動態正反器電路中的每一個分別耦接到多個物理不可複製功能單元中的每一個；群體計數電路，其耦接到多個動態正反器電路；以及評估邏輯電路，其具有耦接到群體計數電路的輸入和耦接到多個動態正反器電路的輸出。在一實施例中，第一金屬氧化物半導體電晶體、第二金屬氧化物半導體電晶體以及第五金屬氧化物半導體電晶體各自包括n型金屬氧化物半導體電晶體。在一實施例中，第三金屬氧化物半導體電晶體和第四金屬氧化物半導體電晶體各自包括p型金屬氧化物半導體電晶體。在一實施例中，所述第一金屬氧化物半導體電晶體配置成具有在所述第一動態節點處耦接到所述第二金屬氧化物半導體電晶體的汲極端子的源極端子、耦接到第一匯流排的汲極以及耦接到第二匯流排的閘極端子。在一實施例中，所述第二金屬氧化物半導體電晶體配置成具有耦接到地面的源極端子和閘極端子。在一實施例中，所述第三金屬氧化物半導體電晶體配置成具有耦接到第一匯流排的汲極端子、耦接到第三匯流排的閘極端子以及耦接到第四金屬氧化物半導體電晶體的汲極端子的源極端子。在一實施例中，所述第四金屬氧化物半導體電晶體配置成具有在第二動態節點處耦接到所述第五金屬氧化物半導體電晶體的汲極端子的源極端子和耦接到所述第一動態節點的閘極端子。在一實施例中，所述第五金屬氧化物半導體電晶體配置成具有耦接第四匯流排的閘極端子、耦接到地面的源極端子。However, in another embodiment, a physical non-replicable function generator for generating a physical non-replicable function signature, the physical non-reproducible function generator comprising: a plurality of physical non-replicable functional units, wherein the plurality of physical non-reproducible Each of the functional units includes five metal oxide semiconductor transistors, wherein the first metal oxide semiconductor transistor and the second metal oxide semiconductor transistor are configured to charge and discharge the first dynamic node, the third metal oxide The semiconductor transistor and the fourth metal oxide semiconductor transistor are configured to charge the second dynamic node, and the fifth metal oxide semiconductor transistor is configured to discharge the second dynamic node to reset the second dynamic node; a counter circuit, wherein each of the plurality of dynamic flip-flop circuits is coupled to each of a plurality of physical non-reproducible functional units; a population counting circuit coupled to the plurality of dynamic flip-flop circuits; and an evaluation a logic circuit having an input coupled to the group counting circuit and coupled to the plurality of dynamic flip-flop circuits Output. In an embodiment, the first metal oxide semiconductor transistor, the second metal oxide semiconductor transistor, and the fifth metal oxide semiconductor transistor each comprise an n-type metal oxide semiconductor transistor. In an embodiment, the third metal oxide semiconductor transistor and the fourth metal oxide semiconductor transistor each comprise a p-type metal oxide semiconductor transistor. In one embodiment, the first metal oxide semiconductor transistor is configured to have a source terminal, coupled to a first terminal of the second metal oxide semiconductor transistor at the first dynamic node A drain connected to the first bus bar and a gate terminal coupled to the second bus bar. In an embodiment, the second metal oxide semiconductor transistor is configured to have a source terminal and a gate terminal coupled to the ground. In an embodiment, the third metal oxide semiconductor transistor is configured to have a 汲 terminal coupled to the first bus bar, a gate terminal coupled to the third bus bar, and coupled to the fourth metal oxide The source terminal of the 汲 terminal of the semiconductor transistor. In an embodiment, the fourth metal oxide semiconductor transistor is configured to have a source terminal coupled to the anode terminal of the fifth metal oxide semiconductor transistor at a second dynamic node and coupled to a gate terminal of the first dynamic node. In an embodiment, the fifth metal oxide semiconductor transistor is configured to have a gate terminal coupled to the fourth bus bar, and a source terminal coupled to the ground.

然而，在另一實施例中，一種配置用於產生物理不可複製功能簽名的物理不可複製功能產生器的方法，所述方法包括：將多個物理不可複製功能單元耦接到多個動態正反器電路，及耦接到群體計數器且進一步耦接到評估邏輯電路，其中多個物理不可複製功能單元中的每一個包括第一電晶體、第二電晶體、第三電晶體、第四電晶體以及第五電晶體；通過多個第一金屬氧化物半導體電晶體中的每一個將多個物理不可複製功能單元中的每一個第一動態節點充電到多個第一電壓；通過多個第二金屬氧化物半導體電晶體中的每一個將每一個第一動態節點放電到多個第二電壓；當第二電壓變得小於第四電壓時，將對應第二動態節點中的每一個充電到第三電壓；使用對應的動態正反器電路監測多個第三電壓中的每一個；當第三電壓變得大於第五電壓時，將多個物理不可複製功能單元的邏輯狀態從第一邏輯狀態反轉到第二邏輯狀態；以及當具有反轉邏輯狀態的物理不可複製功能單元的數目超過物理不可複製功能單元的總數的一半時，產生物理不可複製功能簽名。However, in another embodiment, a method of configuring a physical non-replicable function generator for generating a physical non-replicable function signature, the method comprising: coupling a plurality of physical non-reproducible functional units to a plurality of dynamic positive and negative And coupled to the group counter and further coupled to the evaluation logic circuit, wherein each of the plurality of physical non-reproducible functional units comprises a first transistor, a second transistor, a third transistor, a fourth transistor And a fifth transistor; charging each of the plurality of physical non-reproducible functional units to the plurality of first voltages by each of the plurality of first metal oxide semiconductor transistors; Each of the metal oxide semiconductor transistors discharges each of the first dynamic nodes to a plurality of second voltages; when the second voltage becomes smaller than the fourth voltage, each of the corresponding second dynamic nodes is charged to the first Three voltages; monitoring each of the plurality of third voltages using a corresponding dynamic flip-flop circuit; when the third voltage becomes greater than the fifth voltage, the plurality of things The logical state of the non-replicable functional unit is reversed from the first logical state to the second logical state; and when the number of physical non-replicable functional units having the inverted logical state exceeds half of the total number of physical non-replicable functional units Copy the feature signature.

儘管已根據示範性實施例描述本公開，但本公開不限於此。實際上，所附權利要求書應該廣泛地理解為包含本公開的其它變體和實施例，所述其它變體和實施例可由本領域的一般技術人員在不脫離本公開的等效物的範疇和範圍的情況下制得。Although the present disclosure has been described in accordance with the exemplary embodiments, the present disclosure is not limited thereto. Rather, the appended claims are to be construed as broadly construed in the scope of the invention. And the case of the range is made.

100、400‧‧‧PUF產生器100, 400‧‧‧PUF generator

101、102、106、110、112、412、413‧‧‧匯流排101, 102, 106, 110, 112, 412, 413 ‧ ‧ busbars

103、103-1、103-2、103-3、103-N、410‧‧‧PUF單元103, 103-1, 103-2, 103-3, 103-N, 410‧‧‧PUF units

104、104-1、104-2、104-3、104-N‧‧‧動態正反器電路104, 104-1, 104-2, 104-3, 104-N‧‧‧ dynamic flip-flop circuits

105‧‧‧群體計數器105‧‧‧ group counter

107‧‧‧評估邏輯電路107‧‧‧Evaluation logic

108、124、124-1、124-2、124-3、124-4、154‧‧‧反相器108, 124, 124-1, 124-2, 124-3, 124-4, 154‧‧ ‧ inverter

109、204、505‧‧‧PUF簽名109, 204, 505‧‧‧ PUF signature

113-D、113-G、113-S、114-D、114-G、114-S‧‧‧端子113-D, 113-G, 113-S, 114-D, 114-G, 114-S‧‧‧ terminals

115、115-1、115-2、115-3、115-4、419、420‧‧‧動態節點115, 115-1, 115-2, 115-3, 115-4, 419, 420‧‧‧ dynamic nodes

120‧‧‧有限狀態機/FSM電路120‧‧‧Limited state machine/FSM circuit

121、121-1、121-2、121-3、121-4、161、162、416、417‧‧‧PMOS電晶體121, 121-1, 121-2, 121-3, 121-4, 161, 162, 416, 417‧‧ ‧ PMOS transistors

121-1-D、121-4-D、122-2-D、122-7-D、122-8-D、414-D、415-D、417-D、418-D‧‧‧汲極端子121-1-D, 121-4-D, 122-2-D, 122-7-D, 122-8-D, 414-D, 415-D, 417-D, 418-D‧‧汲 Extreme child

121-1-S、121-4-S、122-2-S、122-7-S、122-8-S、414-S、415-S、416-S、417-S、418-S‧‧‧源極端子121-1-S, 121-4-S, 122-2-S, 122-7-S, 122-8-S, 414-S, 415-S, 416-S, 417-S, 418-S‧ ‧ ‧ source terminal

122-1-G、122-8-G、416-G、417-G、418-G‧‧‧閘極端子122-1-G, 122-8-G, 416-G, 417-G, 418-G‧‧ ‧ gate terminal

113、114、122、122-1、122-2、122-3、122-4、122-5、122-6、122-7、122-8、163、164、414、415、418‧‧‧NMOS電晶體113, 114, 122, 122-1, 122-2, 122-3, 122-4, 122-5, 122-6, 122-7, 122-8, 163, 164, 414, 415, 418‧‧ NMOS transistor

123、139、140、141、142、150、155、156、157、158、159‧‧‧節點123, 139, 140, 141, 142, 150, 155, 156, 157, 158, 159‧‧‧ nodes

130‧‧‧多工器130‧‧‧Multiplexer

151、152、153‧‧‧反及閘151, 152, 153‧‧ ‧ anti-gate

161-S、163-S、164-S‧‧‧端子S161-S, 163-S, 164-S‧‧‧ Terminal S

163-D、164-D‧‧‧端子D163-D, 164-D‧‧‧ terminal D

200、500‧‧‧信號200, 500‧‧‧ signals

201、501‧‧‧時鐘信號201, 501‧‧‧ clock signal

202、202-1、202-2、202-3、202-4、502、520‧‧‧暫態放電行為202, 202-1, 202-2, 202-3, 202-4, 502, 520‧‧‧ Transient discharge behavior

503‧‧‧暫態充電行為503‧‧‧Transient charging behavior

203‧‧‧輸出203‧‧‧ output

205、506、507‧‧‧觸發點205, 506, 507‧‧‧ trigger points

300、600‧‧‧方法300, 600‧‧‧ method

302、304、306、602、604、606、608、610、612‧‧‧操作302, 304, 306, 602, 604, 606, 608, 610, 612‧‧‧ operations

504‧‧‧方框504‧‧‧ box

506-1、506-2、506-3、506-4‧‧‧虛線Lines 506-1, 506-2, 506-3, 506-4‧‧‧

t4、t6、t8、t10、t14、t15‧‧‧取樣時間T4, t6, t8, t10, t14, t15‧‧‧ sampling time

當結合附圖閱讀時，根據以下詳細描述來最好地理解本公開的各方面。應注意，各種特徵構件未必按比例繪製。實際上，為了清楚說明起見，可任意地增大或減小各種特徵構件的尺寸和幾何結構。 圖1A說明根據本公開的各種實施例的PUF產生器的示範性框圖。 圖1B說明根據本公開的各種實施例的圖1A的PUF產生器的PUF單元的電路圖。 圖1C說明根據本公開的各種實施例的圖1A的PUF產生器的基於真單相時鐘（true single-phase clock；TSPC）互補金屬氧化物半導體（complementary metal-oxide-semiconductor，CMOS）的動態正反器（D-flip-flop；DFF）電路的電路圖。 圖1D說明根據本公開的各種實施例的圖1C的動態正反器電路中的雙輸入多工器（multiplexer；MUX）電路的框圖和其真值表。 圖1E說明根據本公開的各種實施例的圖1D的多工器電路的反及（Negative-AND；NAND）閘的電路圖和其真值表。 圖2說明根據本公開的各種實施例的在動態節點上和在由圖1A的PUF產生器用來產生PUF簽名的動態正反器電路的輸出節點上的示範性信號。 圖3說明根據本公開的各種實施例的基於圖1A的PUF產生器產生PUF簽名的方法的示範性流程圖。 圖4A說明根據本公開的各種實施例的PUF產生器的示範性框圖。 圖4B說明根據本公開的各種實施例的圖4A的PUF產生器的PUF單元的電路圖。 圖5說明根據本公開的各種實施例的在第一動態節點和第二動態節點上以及在由圖4A的PUF產生器用來產生PUF簽名的動態正反器電路的輸出節點上的示範性信號。 圖6說明根據本公開的各種實施例的基於圖4A的PUF產生器產生PUF簽名的方法的示範性流程圖。The aspects of the present disclosure are best understood from the following detailed description. It should be noted that various features are not necessarily drawn to scale. In fact, the size and geometry of the various feature members can be arbitrarily increased or decreased for clarity of illustration. FIG. 1A illustrates an exemplary block diagram of a PUF generator in accordance with various embodiments of the present disclosure. FIG. 1B illustrates a circuit diagram of a PUF unit of the PUF generator of FIG. 1A, in accordance with various embodiments of the present disclosure. 1C illustrates a dynamic single-phase clock (TSPC) complementary metal-oxide-semiconductor (CMOS) dynamic positive of the PUF generator of FIG. 1A, in accordance with various embodiments of the present disclosure. Circuit diagram of a D-flip-flop (DFF) circuit. 1D illustrates a block diagram of a two-input multiplexer (MUX) circuit in the dynamic flip-flop circuit of FIG. 1C and its truth table, in accordance with various embodiments of the present disclosure. 1E illustrates a circuit diagram of a Negative-AND (NAND) gate of the multiplexer circuit of FIG. 1D and its truth table, in accordance with various embodiments of the present disclosure. 2 illustrates exemplary signals on a dynamic node and on an output node of a dynamic flip-flop circuit used by the PUF generator of FIG. 1A to generate a PUF signature, in accordance with various embodiments of the present disclosure. 3 illustrates an exemplary flow diagram of a method of generating a PUF signature based on the PUF generator of FIG. 1A, in accordance with various embodiments of the present disclosure. 4A illustrates an exemplary block diagram of a PUF generator, in accordance with various embodiments of the present disclosure. 4B illustrates a circuit diagram of a PUF unit of the PUF generator of FIG. 4A, in accordance with various embodiments of the present disclosure. 5 illustrates exemplary signals on an output node of a dynamic flip-flop circuit used by a PUF generator of FIG. 4A to generate a PUF signature, in accordance with various embodiments of the present disclosure, and on a first dynamic node and a second dynamic node. 6 illustrates an exemplary flow diagram of a method of generating a PUF signature based on the PUF generator of FIG. 4A, in accordance with various embodiments of the present disclosure.

Claims (1)

一種物理不可複製功能產生器，包括： 多個物理不可複製功能單元，其中所述多個物理不可複製功能單元中的每一個包括第一金屬氧化物半導體電晶體和第二金屬氧化物半導體電晶體，其中所述第一金屬氧化物半導體電晶體的源極在動態節點處連接到所述第二金屬氧化物半導體電晶體的汲極，所述第一金屬氧化物半導體電晶體的汲極耦接到第一匯流排及所述第一金屬氧化物半導體電晶體的閘極耦接到第二匯流排，以及所述第二金屬氧化物半導體電晶體的源極和閘極耦接到地面； 多個動態正反器電路，其中所述多個動態正反器電路中的每一個分別耦接到所述多個物理不可複製功能單元中的每一個，其中所述多個動態正反器電路各自配置成監測所述多個物理不可複製功能單元中的每一個上的所述動態節點上的電壓電平； 群體計數電路，其耦接到所述多個動態正反器電路，其中所述群體計數電路配置成確定具有反轉邏輯狀態的物理不可複製功能單元的第一數目；以及 評估邏輯電路，其具有耦接到所述群體計數電路的輸入和耦接到所述多個動態正反器電路的輸出，其中所述評估邏輯電路配置成將所述第一數目與物理不可複製功能單元的總數的一半相比較。A physical non-reproducible function generator, comprising: a plurality of physical non-reproducible functional units, wherein each of the plurality of physical non-reproducible functional units comprises a first metal oxide semiconductor transistor and a second metal oxide semiconductor transistor Wherein the source of the first metal oxide semiconductor transistor is connected to the drain of the second metal oxide semiconductor transistor at a dynamic node, and the drain of the first metal oxide semiconductor transistor is coupled a gate to the first bus bar and the first metal oxide semiconductor transistor is coupled to the second bus bar, and a source and a gate of the second metal oxide semiconductor transistor are coupled to the ground; Dynamic flip-flop circuits, wherein each of the plurality of dynamic flip-flop circuits is coupled to each of the plurality of physical non-reproducible functional units, wherein each of the plurality of dynamic flip-flop circuits Configuring to monitor a voltage level on the dynamic node on each of the plurality of physical non-replicable functional units; a population counting circuit coupled to the Dynamic flip-flop circuits, wherein the population counting circuit is configured to determine a first number of physical non-reproducible functional units having inverted logic states; and an evaluation logic circuit having an input coupled to the population counting circuit and An output coupled to the plurality of dynamic flip-flop circuits, wherein the evaluation logic is configured to compare the first number to a half of a total number of physical non-replicable functional units.
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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI758845B (en) * 2020-05-08 2022-03-21 台灣積體電路製造股份有限公司 Memory device, random number generator and method for operating the same
TWI803351B (en) * 2022-06-14 2023-05-21 新唐科技股份有限公司 Key generation unit with physical unclonable function, key generator and circuit system

Families Citing this family (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11196574B2 (en) * 2017-08-17 2021-12-07 Taiwan Semiconductor Manufacturing Company, Ltd. Physically unclonable function (PUF) generation
EP4287104A3 (en) * 2018-01-29 2024-01-17 Panasonic Intellectual Property Corporation of America Control method, controller, data structure, and electric power transaction system
US11206146B2 (en) * 2019-08-01 2021-12-21 University Of Kentucky Research Foundation Architecture for generating physically unclonable function response
US11438180B2 (en) * 2020-02-10 2022-09-06 Taiwan Semiconductor Manufacturing Company Limited Systems and methods for providing reliable physically unclonable functions
US20210258173A1 (en) * 2020-02-18 2021-08-19 International Business Machines Corporation Gain cell memory based physically unclonable function
US11528151B2 (en) * 2020-04-01 2022-12-13 Taiwan Semiconductor Manufacturing Company, Ltd. Physically unclonable function (PUF) generation
WO2022023280A2 (en) * 2020-07-27 2022-02-03 Robert Bosch Gmbh A system and method for generation and validation of puf identifier of a battery pack
CN111865615B (en) * 2020-07-30 2022-07-19 南京博芯电子技术有限公司 APUF circuit with detectable reliability and working method
CN112511308B (en) * 2020-11-19 2022-12-16 深圳大学 Physical unclonable function circuit structure based on grid overhang modulation
FR3118829B1 (en) * 2021-01-14 2024-06-21 Commissariat A Lenergie Atomique Et Aux Energies Alternatives MATRIX OF ELEMENTARY SWITCHES FORMING A MESSAGE, ASSOCIATED WRITING AND READING PROCESSES
CN113095035B (en) * 2021-03-16 2022-04-12 宁波大学 Subthreshold dynamic delay type PUF circuit
CN113364599B (en) * 2021-06-15 2022-05-13 湖南大学 Dual-state physical unclonable function circuit
CN117454448B (en) * 2023-12-25 2024-03-19 湖北工业大学 Static hidden DFF-PUF composite circuit

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8300450B2 (en) * 2010-11-03 2012-10-30 International Business Machines Corporation Implementing physically unclonable function (PUF) utilizing EDRAM memory cell capacitance variation
US9048834B2 (en) * 2013-01-16 2015-06-02 Intel Corporation Grouping of physically unclonable functions
JP6224401B2 (en) * 2013-10-04 2017-11-01 ルネサスエレクトロニクス株式会社 Semiconductor memory
WO2015148659A1 (en) * 2014-03-25 2015-10-01 Mai Kenneth Wei-An Methods for generating reliable responses in physical unclonable functions (pufs) and methods for designing strong pufs
US9515835B2 (en) * 2015-03-24 2016-12-06 Intel Corporation Stable probing-resilient physically unclonable function (PUF) circuit
US10090025B2 (en) * 2016-10-13 2018-10-02 Cisco Technology, Inc. Discharging electric charge in integrated circuit unless in-specification condition(s) detected
US9966954B1 (en) * 2017-02-03 2018-05-08 The Regents Of The University Of Michigan Physically unclonable function design

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI758845B (en) * 2020-05-08 2022-03-21 台灣積體電路製造股份有限公司 Memory device, random number generator and method for operating the same
US11626157B2 (en) 2020-05-08 2023-04-11 Taiwan Semiconductor Manufacturing Company, Ltd. SRAM power-up random number generator
TWI803351B (en) * 2022-06-14 2023-05-21 新唐科技股份有限公司 Key generation unit with physical unclonable function, key generator and circuit system

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US20190165938A1 (en) 2019-05-30
US11664258B2 (en) 2023-05-30

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