CN113051629B

CN113051629B - Integrated circuit for realizing on-off PUF (physical unclonable function) based on-chip fuse

Info

Publication number: CN113051629B
Application number: CN202110259822.1A
Authority: CN
Inventors: 顾豪爽; 詹慕文; 万美琳; 章珍珍; 张寅�; 贺章擎; 胡永明
Original assignee: Hubei University
Current assignee: Hubei University
Priority date: 2021-03-10
Filing date: 2021-03-10
Publication date: 2022-06-17
Anticipated expiration: 2041-03-10
Also published as: CN113051629A

Abstract

The invention discloses an integrated circuit for realizing an on-off PUF (physical unclonable function) based on-chip fuses, which adopts two completely consistent on-chip fuses which are connected in series between a power supply and the ground, and a drain-source resistor of a cut-off low-threshold MOS (metal oxide semiconductor) tube is accessed to a public end of the two on-chip fuses to be used as a pull-up resistor or a pull-down resistor, and the public end is used as an output key value of the PUF; when the process deviation causes that a fuse wire on a certain chip is firstly fused, the common terminal is pulled up to a power supply or pulled down to the ground by the fuse wires on the rest un-fused chips; and when the process deviation is small, so that the two on-chip fuses are all fused, the output end is pulled up to a power supply or pulled down to the ground through the cut-off drain-source resistor of the low-threshold MOS tube. The invention is only composed of two on-chip fuses and one MOS transistor, and the key value is permanently fixed and directly output after one-time electric fusing, the structure is simple, and the key output speed is high.

Description

Integrated circuit for realizing on-off PUF (physical unclonable function) based on-chip fuse

Technical Field

The invention relates to a key generation circuit of a security chip, in particular to an integrated circuit for realizing a PUF (physical unclonable function) based on-chip fuses, belonging to the technical field of information security integrated circuits.

Background

In a security chip, a Physical Unclonable Function (PUF) is usually used to provide a key required by the security chip, and the PUF detects random changes in Physical characteristics of materials constituting circuit devices in the integrated circuit production process, so that even a chip manufacturer and a circuit designer cannot use the same circuit to copy the same key, and an attacker cannot derive the original key through reverse engineering. Nowadays, there are various PUF structures, such as transient effect ring oscillator type and Arbiter type PUFs based on delay units, RO type PUFs based on differences in oscillation frequencies of ring oscillators, SRAM PUFs based on minimum data retention voltage detection, PUFs based on resistive random access memories and magnetic random access memories, etc., but these traditional PUFs sample mismatches among characteristics of noise, resistance, oscillation frequency, delay, threshold voltage, etc., of devices or circuits, and are very susceptible to voltage and temperature, while new memories such as new magnetic random access memories are incompatible with standard CMOS processes, and need special processing, which greatly increases chip cost. In addition, the manner of performing post-production trimming on the unstable PUF cells by using hand voting and an Error Correction Code (ECC) also incurs a large digital circuit overhead. Therefore, the conventional PUF has the problems of low stability, high correction hardware cost and the like.

In order to avoid the problem of low stability caused by sampling of the analog characteristics of a circuit or a device by a traditional PUF, an On-Off (On-Off) type PUF is researched and provided, a very simple design scheme is to reduce the distance between two metal interconnection lines to be smaller than the minimum distance allowed by the process, in the actual production process of a chip, because the process photoetching resolution is limited, the two interconnection lines are possibly connected together, the connection probability is influenced by the random deviation of the process, and the connection state of the two interconnection lines is randomly switched On or Off after the actual chip is produced. The PUF implementation mode is not influenced by temperature and environment, the connection line is permanently determined after the chip is produced, the stability is 100%, the implementation cost is very low, and an additional correction circuit is not needed. However, it should be noted that, in this implementation, it is difficult to control the bias characteristic of the output key, the connection state between the interconnection lines is easily affected by the distance, when the distance is a little longer, the approximate rates of the two interconnection lines do not intersect, and when the distance is a little shorter, the approximate rates intersect, it is very difficult to obtain 50% of the intersection probability, it is necessary to perform multiple analyses and iterations on the process itself to obtain an appropriate distance, and the situation of each time of wafer casting is different, and it is very difficult to design and easily affected by the process to achieve convergence under different process conditions.

In order to obtain better bias characteristics, another effective on-off PUF implementation is to use on-chip wire fusing, that is, on-chip fuse fusing, to obtain a permanently stable PUF key. Referring to CN106952890A, a PUF scheme based on the principle of fusing off a wire inside a chip and a circuit implementation thereof are proposed, as shown in fig. 1, taking a two-segment wire as an example, a fuse 1 and a fuse 2 are narrower metal wires, which are connected together through a wider metal wire, and the left end of the fuse 1 is connected to a power supply through a switch S1, and the right end of the fuse 2 is connected to ground through a switch S2. The circuit firstly passes through a mismatch sampling stage, namely S1 and S2 are conducted simultaneously, a path is formed between power grounds, large current is generated, and due to the fact that mismatch exists in production of the fuse wire 1 and the fuse wire 2, one metal wire in the fuse wire 1 and the fuse wire 2 is larger in resistance value and easier to fuse. Thus, when one of the fuse 1 and the fuse 2 is blown first, the S1 and the S2 are opened, the S5 is closed, the S3 and the S4 are respectively closed, whether the fuse 1 or the fuse 2 is blown is further detected by detecting the S3 and the S4, namely, whether current exists between power grounds, and then the blowing condition of the fuse 1 and the fuse 2 is coded by adopting a coding circuit, and the final coded value is the output key of the PUF.

The implementation method can obtain the bias characteristic which is less affected by the process, but it should be noted that, because the two fuses are both blown, when the two fuses are both blown, the common terminal of the two fuses is in a high-resistance state, and the output value of the common terminal cannot be determined, so that the common terminal of the two fuses cannot be directly used as a secret key to be output, and only a complex current detection circuit and a coding circuit can be adopted to realize the output of the PUF secret key. Therefore, after a large number of switches, coding control circuits and current detection circuits are adopted to realize the on-off detection of the fuse, the circuit cost is greatly increased. Meanwhile, in order to obtain an output key value, when sampling the key each time, it needs to take a plurality of clock cycles to respectively perform on-off control of S1, S2, S3, S4 and S5, thereby greatly reducing key sampling and output rates.

In summary, the existing on-chip fuse-based on-off PUF has the problems of poor bias characteristics, high circuit cost and low sampling speed, and a stable, simple and efficient circuit structure needs to be found to avoid the use of a large number of switches, detection circuits and codes so as to reduce the circuit cost and improve the sampling rate.

Disclosure of Invention

The invention provides a simple integrated circuit of a high-stability on-off PUF based on-chip fuses, wherein the left end and the right end of each of two on-chip fuses are respectively and directly connected with a power supply and the ground, the common end of each of the two on-chip fuses is directly used as an output key value of the PUF, when the integrated circuit is powered on, the two fuses pass through heavy current, if the fuses connected with the power supply are fused, the common input end is connected to the ground through the fuses connected with the ground, and the output is 0; and when the fuse connected to ground is blown, the common input terminal is connected to the power supply through the fuse connected to the power supply, and the output is 1. Meanwhile, in order to avoid the situation that the two fuses are all fused and the common end is in a high-resistance state, the common output end is pulled down to the ground or pulled up to the power supply through the large resistor, and when the two fuses are all fused, the common output end can be pulled down to the ground or pulled up to the power supply, so that a determined output value is obtained. The circuit does not need to be controlled by a switch, a current detection circuit and a coding circuit are not needed to detect the state of a fuse, a stable PUF key value is directly output after the circuit is electrified, the circuit is simple, and the key sampling and output speed is high.

In order to achieve the purpose, the invention adopts the following scheme:

an integrated circuit for realizing an on-off Physical Unclonable Function (PUF) based on-chip fuses is characterized in that two completely consistent on-chip fuses are connected between a power supply and the ground in series, a cut-off low-threshold MOS (metal oxide semiconductor) tube drain-source resistor is connected to a common end of the two on-chip fuses to serve as a pull-up resistor or a pull-down resistor, and the common end serves as an output key value of the PUF; when the process deviation causes that a fuse wire on a certain chip is firstly fused, the common terminal is pulled up to a power supply or pulled down to the ground by the fuse wires on the rest un-fused chips; and when the process deviation is small, so that the two on-chip fuses are all fused, the output end is pulled up to a power supply or pulled down to the ground through the cut-off drain-source resistor of the low-threshold MOS tube.

Further, the on-chip fuse is composed of two large and middle slender metal or polysilicon conductive interconnection lines, and the width of the on-chip fuse is as low as the minimum size allowed by the process.

Furthermore, the sizes and the shapes of the two on-chip fuses are completely consistent, the two on-chip fuses are well matched in the layout process, the two on-chip fuses are completely consistent in environment, so that random process deviation is obtained under the completely same design environment, and the two fuses are randomly fused.

Furthermore, the pull-up resistor or the pull-down resistor of the common end is respectively composed of a cut-off small-size low-threshold NMOS tube or PMOS tube, and the chip area is reduced as much as possible while a high pull-up and pull-down resistance value is obtained; the low-threshold NMOS tube or the PMOS tube has a proper high drain-source impedance when being cut off, the direct current power consumption from a power supply to the ground can be effectively reduced under the condition that one fuse wire is fused, and the quick charging and discharging time can still be provided under the condition that two fuse wires are fused.

Furthermore, the width of the conductive interconnection line connecting the common terminal and the pull-up resistor or the pull-down resistor is larger than that of the fuse on the chip, so that the situation that the conductive interconnection line connecting the pull-up resistor or the pull-down resistor is fused is avoided.

The invention has the beneficial effects that:

the invention directly serially connects two completely consistent on-chip fuses in a power supply and the ground, a public end of the two completely consistent on-chip fuses is used as an output key value of a PUF (physical unclonable function), and meanwhile, a pull-up or pull-down resistor formed by a cut-off low-threshold MOS (metal oxide semiconductor) tube drain-source resistor is connected to the public end, and when a certain fuse is firstly fused due to process deviation, the public end is pulled up to the power supply or pulled down to the ground by the remaining unblown fuse; and when the process deviation is small, the two fuses are blown, and the common end is pulled up to a power supply or pulled down to the ground through the drain-source resistance of the cut-off low-threshold MOS tube. The invention has simple structure and high speed. Firstly, the fuse on the chip is only composed of two fuses on the chip and one MOS transistor, an additional switch, a current detection circuit and an encoding circuit are not needed, and the circuit is very simple. And secondly, the PUF is permanently fixed and directly outputs a key value after being electrically fused once, the key is not required to be sampled and output in multiple clock cycles, and the sampling and output speed of the key is high.

Drawings

Fig. 1 is a PUF scheme based on the principle of fusing internal wires of a chip, proposed by the patent of reference to the invention;

FIG. 2 is a schematic circuit diagram of an integrated circuit implementing an on-off PUF based on-chip fuses according to the present invention;

FIG. 3 is a layout of an integrated circuit implementing an on-off PUF based on-chip fuses of the present invention;

FIG. 4 is an equivalent circuit diagram of the integrated circuit of the invention for implementing the on-off PUF based on the on-chip fuse when the fuse is blown.

Detailed Description

The invention is further described below in conjunction with the appended drawings and detailed description examples of which are illustrated in the accompanying drawings, wherein like or similar reference numerals refer to the same or similar elements or elements having the same or similar function throughout. The embodiments described below are exemplary and are intended to be illustrative, but not limiting, of the present invention, and any modifications, equivalents, or improvements made within the spirit and principle of the present invention, which are not described in detail in the technical solutions below, are known in the art, and are intended to be included within the scope of the claims of the present invention.

Implementation example: fig. 2 and fig. 3 show an embodiment of an integrated circuit for implementing an on-off PUF based on-chip fuses according to the present invention, wherein fig. 2 is a circuit principle, and fig. 3 is a layout manner thereof. In fig. 2, the fuse 1 and the fuse 2 are two identical conductive lines formed by on-chip interconnection lines, the two ends of each conductive line are large, the middle of each conductive line is long and narrow, the width of the middle long and thin line is the minimum width allowed by the process, and the specific layout is shown in fig. 3. One end of the fuse 1 is connected with a power supply, the other end is connected with one end of the fuse 2 to form a common end, and the other end of the fuse 2 is connected with the ground. The common terminal of the two fuses is used as the output terminal of the PUF, and the common terminal can determine the default potential in two ways: (1) as shown in fig. 2(a) and fig. 3(a), the common terminal determines that the default potential is 0 through a pull-down resistor formed by a cut-off low-threshold NMOS transistor; (2) as shown in fig. 2(b) and fig. 3(b), the common terminal is determined to have a default potential of 1 by a pull-up resistor formed by a low-threshold PMOS transistor which is turned off. In fig. 3, the width of the interconnect line connected to the pull-up and pull-down resistors is greater than the width of the long thin line in the middle of the fuse to prevent the interconnect line from being blown first during the blowing process.

Taking fig. 2(a) and fig. 3(a) as an example, when circuit design and layout are performed, the fuse 1, the fuse 2 and the external environment thereof are completely consistent, but due to process deviation in the actual production process of the chip, random deviation exists in the electrical and thermal characteristics of the two fuses, after power-on, a path is formed between the power supply at the left end of the fuse 1 and the right end of the fuse 2, a large current will be formed in the fuse, if the slender line resistance of the fuse 1 after the production of the chip is higher, the fuse 1 will be blown first, because the cut-off low-threshold NMOS transistor drain-source resistance is much larger than the resistance of the fuse 2, the output end will be pulled down to the ground by the fuse 2, the output is 0, and the equivalent circuit diagram is as shown in fig. 4 (a). On the contrary, if the slim line resistance of the fuse 2 is higher after the chip is produced, the fuse 2 will blow first, and at this time, the output terminal will be pulled up from the fuse 1 to the power supply, and the output is 1, and the equivalent circuit diagram thereof is shown in fig. 4 (b). In addition, if the process variation of the fuse 1 and the fuse 2 is not large, there is a possibility that both fuses are blown, and at this time, the output is still 0 by pulling down the drain-source resistance of the turned-off low-threshold NMOS transistor to ground, and the equivalent circuit diagram is shown in fig. 4 (c).

It should be noted that the drain-source resistance of the turned-off low-threshold NMOS transistor is used as the pull-down resistance, because when the NMOS transistor is turned off, the drain-source end of the NMOS transistor is equivalent to a circuit break, and the drain-source resistance of the NMOS transistor is large, so that a large pull-down resistance can be obtained on the premise of a very small area overhead. The reason why the low threshold NMOS is used is that when both fuses are blown, if a normal threshold NMOS is used, the drain-source resistance is very large when the NMOS is turned off, and even larger than the resistance of the blown fuse, so that there is a risk that the time for the output terminal to discharge to the ground is long, and even the output voltage is unknown. When the low-threshold NMOS is cut off, the drain-source resistance of the low-threshold NMOS is larger but is far smaller than that of the normal-threshold NMOS, so that higher pull-down resistance and lower static power consumption can be obtained when the fuse 2 is fused, and meanwhile, shorter discharge time of an output end can be obtained when the two fuses are fused simultaneously.

The situation shown in fig. 2(b) and fig. 3(b) is similar to the above situation, except that when both fuses are blown, the output is 1 by default pulled up to the power supply through the drain-source resistance of the PMOS transistor that is turned off.

It can be seen that after the on-chip fuse-based on-off PUF structure is adopted, the whole circuit is only composed of 2 interconnection fuse wires with very small area and 1 MOS, a switch, a current detection circuit and a coding circuit are not needed, after the circuit is electrically fused for one time, the circuit is permanently fixed, clock control is not needed, the sampling and output speed of an output key is high, and the application range of the circuit is greatly expanded.

The above description is only for the preferred embodiment of the present invention, but the scope of the present invention is not limited thereto, and any person skilled in the art should be considered to be within the technical scope of the present invention, and the technical solutions and the inventive concepts thereof according to the present invention should be equivalent or changed within the scope of the present invention.

Claims

1. An integrated circuit for realizing an on-off Physical Unclonable Function (PUF) based on-chip fuses is characterized in that two completely consistent on-chip fuses are connected between a power supply and the ground in series, a cut-off low-threshold MOS (metal oxide semiconductor) tube drain-source resistor is connected to a common end of the two on-chip fuses to serve as a pull-up resistor or a pull-down resistor, and the common end serves as an output key value of the PUF; when the process deviation causes that a fuse wire on a certain chip is firstly fused, the common terminal is pulled up to a power supply or pulled down to the ground by the fuse wires on the rest un-fused chips; and when the process deviation is small, so that the two on-chip fuses are all fused, the output end is pulled up to a power supply or pulled down to the ground through the cut-off drain-source resistor of the low-threshold MOS tube.

2. An integrated circuit implementing a Physically Unclonable Function (PUF) of the on-off type based on-chip fuses as claimed in claim 1, characterized in that the on-chip fuses are formed by metal or polysilicon conductive interconnects with large ends and slender middle, and the width is as low as the minimum size allowed by the process.

3. The integrated circuit for realizing the on-off Physical Unclonable Function (PUF) based on the on-chip fuses as claimed in claim 1, wherein the size and the shape of the two on-chip fuses are completely consistent, the two on-chip fuses are well matched in the layout process, and the two on-chip fuses are completely consistent in environment, so that random process deviation is obtained under the completely same design environment, and the two fuses are randomly blown.

4. The integrated circuit for realizing the on-off Physical Unclonable Function (PUF) based on the on-chip fuse as claimed in claim 1, wherein the pull-up resistor or the pull-down resistor of the common terminal is respectively composed of a cut-off small-size low-threshold NMOS transistor or PMOS transistor, and the chip area is reduced as much as possible while a higher pull-up and pull-down resistance value is obtained; the low-threshold NMOS tube or the PMOS tube has a proper high drain-source impedance when being cut off, the direct current power consumption from a power supply to the ground can be effectively reduced under the condition that one fuse wire is fused, and the quick charging and discharging time can still be provided under the condition that two fuse wires are fused.

5. The integrated circuit for realizing the PUF based on the on-chip fuse, according to claim 1, wherein the width of the conductive interconnection line connecting the common terminal with the pull-up resistor or the pull-down resistor is larger than that of the on-chip fuse, so as to avoid the situation that the conductive interconnection line connecting the pull-up resistor or the pull-down resistor is blown.