TW201914384A - Method for manufacturing cupper pillar on pcb - Google Patents
Method for manufacturing cupper pillar on pcb Download PDFInfo
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本發明是關於一種在印刷電路板上製造銅柱的方法，特別是在印刷電路板的抗鍍乾膜圖形上電鍍形成銅柱的方法。 BACKGROUND OF THE INVENTION 1. Field of the Invention This invention relates to a method of fabricating a copper pillar on a printed circuit board, and more particularly to a method of electroplating a copper pillar on a resistive dry film pattern of a printed circuit board.
印刷電路板(Printed Circuit Board，PCB)是在絕緣基材上，配以電導線路的一種結構性電子元件。當積體電路製程進入微米(um)時代時，PCB之線寬、線距則以毫米(mm)為設計目標。如今，積體電路已進入奈米(nano)製程，而PCB亦步入微米時代，因此，高密度互連(High-Density Interconnection，HDI)技術已廣泛應用在PCB產業。 A Printed Circuit Board (PCB) is a structured electronic component on an insulating substrate with conductive traces. When the integrated circuit process enters the micron (um) era, the line width and line spacing of the PCB are designed in millimeters (mm). Nowadays, integrated circuits have entered the nano process, and PCBs have entered the micron era. Therefore, High-Density Interconnection (HDI) technology has been widely used in the PCB industry.
習知的HDI製程之一，是在銅箔基板上鑽孔，再化學沉積形成表面銅層，接著以圖形電鍍填孔，最後去除抗鍍膜並蝕刻掉表面銅層。然而，這項技術在製作銅柱(copper pillars)時，需要重複數次填孔程序才能疊加到要求的高度或深度，且無法製作特殊型式的銅柱。 One of the conventional HDI processes is to drill holes in a copper foil substrate, chemically deposit a surface copper layer, then fill holes with pattern plating, and finally remove the plating resist and etch away the surface copper layer. However, this technique requires several refilling procedures to be repeated to the required height or depth when making copper pillars, and it is not possible to make special types of copper posts.
為解決上述問題，另一種HDI製程被提出來：是在銅箔基板上以抗鍍乾膜製作圖形後，直接電鍍銅於圖形上，最後蝕 刻掉表面銅層並剝除乾膜，得到獨立的金屬銅柱。或者，在電鍍前先化學沉積一銅層。但無論使用哪一種方式，目前仍面臨許多瓶頸，包括： In order to solve the above problems, another HDI process has been proposed: after the pattern is formed on the copper foil substrate with the anti-plating dry film, the copper is directly electroplated on the pattern, and finally the surface copper layer is etched away and the dry film is peeled off to obtain an independent Metal copper column. Alternatively, a copper layer is chemically deposited prior to electroplating. But no matter which method is used, there are still many bottlenecks, including:
A.需在高電流密度(12-20ASD)下進行電鍍程序，總耗電量高達17~28.3安培小時(Ah)，不符經濟效益。 A. Electroplating procedures should be carried out at high current density (12-20ASD), and the total power consumption is as high as 17~28.3 ampere-hours (Ah), which is not economical.
B.抗鍍乾膜表面進行導電化程序時，常需使用鹼性藥劑。但鹼性藥劑與乾膜產生的化學作用會造成乾膜剝離脫落，因此製程良率無法提昇。 B. When the surface of the anti-plated dry film is subjected to a conductive process, an alkaline agent is often used. However, the chemical action of the alkaline agent and the dry film causes the dry film to peel off, so the process yield cannot be improved.
C.金屬銅柱表面的均勻性不佳，且非銅柱部位的面銅層極厚，需倚賴後續的蝕刻程序補救，有良率降低的風險。 C. The uniformity of the surface of the metal copper column is not good, and the copper layer of the non-copper column is extremely thick, which relies on the subsequent etching procedure to remedy, and there is a risk of yield reduction.
為使乾膜鍍銅程序能有效進行，以達到量產的效益，本發明將針對上述問題提出解決之道。 In order to make the dry film copper plating process effective, in order to achieve mass production benefits, the present invention will solve the above problems.
本發明的目的在於提供一種在印刷電路板上製造銅柱的方法，具有製程良率高、總消耗電量低及銅柱品質良好等優點。 It is an object of the present invention to provide a method for manufacturing a copper pillar on a printed circuit board, which has the advantages of high process yield, low total power consumption, and good quality of the copper pillar.
本發明方法主要包括下列步驟：A.製作乾膜圖形-在一基板上形成具孔洞圖形且不溶於非鹼性溶液的抗鍍乾膜；B.修飾rGO於乾膜孔洞中(以下稱SLOTOGO程序)-使氧化石墨烯(Graphene Oxide，GO)吸附於抗鍍乾膜的孔 洞內壁，再以還原劑將氧化石墨烯(GO)還原為還原氧化石墨烯(rGO)；C.電鍍填孔-實施電鍍程序，使銅離子於乾膜孔洞內的rGO導電層上沉積金屬銅；D.去除表面銅層及抗鍍乾膜-去除表面銅層並剝除抗鍍乾膜，留下金屬銅柱。 The method of the invention mainly comprises the following steps: A. preparing a dry film pattern - forming an anti-plating dry film having a hole pattern and being insoluble in a non-alkaline solution on a substrate; B. modifying rGO in a dry film hole (hereinafter referred to as SLOTOGO program) - adsorption of graphene oxide (GO) to the inner wall of the anti-plating dry film, and reduction of graphene oxide (GO) to reduced graphene oxide (rGO) with a reducing agent; C. electroplating and filling - Performing an electroplating procedure to deposit copper ions on the rGO conductive layer in the dry film hole; D. removing the surface copper layer and resisting the dry plating film - removing the surface copper layer and stripping the anti-plating dry film, leaving the metal copper pillar .
上述的抗鍍乾膜可為任何種類的乾膜，並無特別限制。但為適用於本發明的rGO修飾程序，應以不會溶解於非鹼性溶液的較佳。目前市面上常見的感光性乾膜以鹼可溶者為主，因此多以碳酸鈉做顯影劑，並以氫氧化鈉或氫氧化鉀等溶液剝除。 The above-mentioned dry plating resist film may be any type of dry film, and is not particularly limited. However, it is preferred that the rGO modification procedure applicable to the present invention does not dissolve in a non-alkaline solution. At present, the photosensitive dry film commonly used in the market is mainly alkali-soluble, so sodium carbonate is often used as a developer, and is stripped with a solution such as sodium hydroxide or potassium hydroxide.
因本發明方法可適用於各種形式及大小的孔洞，上述步驟A的孔洞並無特別限制。針對具有高深寬比(AR)的孔洞，例如AR為0.4-5，平均直徑或寬度為50-200μm的孔洞，本發明的電鍍效果顯然較目前的技術為佳。 Since the method of the present invention can be applied to pores of various forms and sizes, the pores of the above step A are not particularly limited. For holes having a high aspect ratio (AR), such as holes having an average diameter of 0.4 to 5 and an average diameter or a width of 50 to 200 μm, the plating effect of the present invention is clearly better than the prior art.
上述步驟A的基板表面可覆有銅箔，銅箔表面可先形成線路及/或銅柱底座，再貼覆電鍍銅柱所需的乾膜。 The surface of the substrate of the above step A may be coated with a copper foil, and the surface of the copper foil may be first formed with a line and/or a copper pillar base, and then the dry film required for electroplating the copper pillar is attached.
上述步驟B的rGO修飾程序包括在乾膜表面形成高分子層、吸附GO及還原GO等，皆於酸性溶液中進行，較佳為pH=2-6。 The rGO modification procedure of the above step B includes forming a polymer layer on the surface of the dry film, adsorbing GO, and reducing GO, etc., all in an acidic solution, preferably pH=2-6.
上述步驟C電鍍程序的電流密度並無特別限制，較佳為0.5-5.0ASD，更佳為0.5-2.0ASD。 The current density of the plating process of the above step C is not particularly limited, and is preferably 0.5 to 5.0 ASD, more preferably 0.5 to 2.0 ASD.
10‧‧‧基板 10‧‧‧Substrate
20‧‧‧銅箔 20‧‧‧ copper foil
30、31、32‧‧‧乾膜 30, 31, 32‧‧‧ dry film
40、41、42‧‧‧rGO 40, 41, 42‧‧‧rGO
50、51、52‧‧‧電鍍銅 50, 51, 52‧‧‧ electroplated copper
第1圖為本發明方法實施例1的製程示意圖。 FIG. 1 is a schematic diagram of a process of Embodiment 1 of the method of the present invention.
第2圖為本發明方法實施例2的製程示意圖。 FIG. 2 is a schematic diagram of a process of Embodiment 2 of the method of the present invention.
第3圖為本發明方法所製造的銅柱影像。 Figure 3 is an image of a copper pillar manufactured by the method of the present invention.
以下實施步驟的操作條件可視環境逕行調整搭配，文中所述僅為建議之較佳範圍。 The operating conditions of the following implementation steps can be adjusted and matched according to the environment. The above description is only the recommended range.
實施例1製造基板表面的銅柱陣列Embodiment 1 A copper pillar array for manufacturing a substrate surface
第1圖為實施例1的流程示意圖。 Fig. 1 is a schematic flow chart of the first embodiment.
A. 製作乾膜圖形A. Making dry film graphics
取一表面覆有銅箔20的基板10，對其表面進行清潔、微蝕刻後，貼覆一層厚度為170um的感光性乾膜。藉由UV曝光、碳酸鈉顯影等程序，在欲電鍍的位置形成具有孔洞圖形的抗鍍乾膜30。 A substrate 10 having a surface covered with a copper foil 20 was taken, and the surface thereof was cleaned and micro-etched, and then a photosensitive dry film having a thickness of 170 μm was applied. The plating resist dry film 30 having a hole pattern is formed at a position to be plated by a procedure such as UV exposure or sodium carbonate development.
本實施例係以直徑100um、高度170um的圓柱型銅柱為例，但實際上只要選取適當厚度的乾膜，配合圖形轉移程序，即可製作不同尺寸及型式的銅柱；例如直徑50-200um、深寬比(Aspect Ratio，AR)0.4-5的方形或橢圓形銅柱。 In this embodiment, a cylindrical copper column with a diameter of 100 um and a height of 170 um is taken as an example, but in practice, a copper film of different sizes and types can be produced by selecting a dry film of appropriate thickness and a pattern transfer procedure; for example, a diameter of 50-200 um. Square or elliptical copper columns with an aspect ratio (AR) of 0.4-5.
B. 修飾rGO於孔洞中(SLOTOGO程序)B. Modifying rGO in the hole (SLOTOGO program)
將基板浸入調節劑水溶液中，使孔洞及表面形成高分子層。調節劑水溶液濃度為1-10g/L，pH=3-6，溫度為40-60℃。1-10分鐘後，取出水洗並吹乾。 The substrate is immersed in an aqueous solution of a regulator to form a polymer layer in the pores and the surface. The concentration of the aqueous solution of the regulator is 1-10 g/L, pH = 3-6, and the temperature is 40-60 °C. After 1-10 minutes, take out the water and blow dry.
調節劑可選用聚基銨含脲基聚合物(Polyquaternium-2，PQT-2)、聚乙烯基季銨鹽(Quaternary polyvinylimidazole，PVI)、聚二烯丙基二甲基氯化銨(Poly(diallyldimethylammonium chloride)，PDACH)、聚酰胺-環氧氯丙烷(polyamidoamine-epichlorohydrin，PAE)或超支化吉米奇季銨鹽(Hyperbranched Gemini quaternary ammonium salt，PN-320)。調節劑水溶液較佳操作範圍為：4-10g/L，pH=3-5，溫度50-60℃。 The regulator can be selected from polyammonium-containing urea-based polymer (Polyquaternium-2, PQT-2), quaternary polyvinylimidazole (PVI), and polydiallyldimethylammonium (Poly(diallyldimethylammonium). Chloride), PDACH), polyamidoamine-epichlorohydrin (PAE) or Hyperbranched Gemini quaternary ammonium salt (PN-320). The preferred operating range of the aqueous solution of the conditioning agent is: 4-10 g/L, pH = 3-5, and the temperature is 50-60 °C.
接著，將基板浸入氧化石墨烯(Graphene Oxide，GO)水溶液中，使氧化石墨烯吸附並鍵結於孔洞內壁的高分子層。氧化石墨烯溶液濃度為0.1-1g/L，pH=2-4，溫度為15-35℃。GO水溶液較佳操作條件為：0.5-1g/L，pH=3-4，室溫。1-10分鐘後，取出水洗並吹乾。 Next, the substrate is immersed in an aqueous solution of graphene oxide (GO) to adsorb and bond the graphene oxide to the polymer layer on the inner wall of the pore. The graphene oxide solution has a concentration of 0.1 to 1 g/L, a pH of 2-4, and a temperature of 15-35 °C. The preferred operating conditions for the GO aqueous solution are: 0.5-1 g/L, pH = 3-4, room temperature. After 1-10 minutes, take out the water and blow dry.
最後，將基板放入還原劑溶液，將GO還原形成還原氧化石墨烯(rGO)層40。還原劑可選用氯化亞錫(SnCl2)、抗壞血酸或氫碘酸(HI)。還原劑溶液pH=2-4，浸泡時間20-30分鐘，溶液溫度60-90℃，濃度0.5-2M。 Finally, the substrate is placed in a reducing agent solution to reduce GO to form a reduced graphene oxide (rGO) layer 40. The reducing agent may be selected from stannous chloride (SnCl 2 ), ascorbic acid or hydroiodic acid (HI). The reducing agent solution has a pH of 2-4, a soaking time of 20-30 minutes, a solution temperature of 60-90 ° C, and a concentration of 0.5-2 M.
在SLOTOGO程序中，因全程使用酸性藥劑，不會造成抗鍍乾膜剝離，因此乾膜孔洞內壁的導電化得以順利完成。 In the SLOTOGO program, the use of an acidic agent throughout the process does not cause the peeling of the dry plating film, so that the conduction of the inner wall of the dry film hole can be smoothly completed.
C. 電鍍填孔及表面銅層C. Electroplating and surface copper layer
電鍍前，先以酸性清潔劑(SCHLOTTER公司的產品SLOTOCLEAN S20，0.5-5%)清洗基板，除去表面的雜質。15-30℃下進行3-10分鐘後，取出水洗。接著，將基板浸入微蝕刻溶液(SCHLOTTER公司的產品SLOTOETCH 584，10-40g/L)中，進一步除去氧化皮膜。15-30℃下進行3-10分鐘後，取出水洗。 Prior to electroplating, the substrate was cleaned with an acidic detergent (SLLOTCLEAN S20, 0.5-5% from SCHLOTTER) to remove impurities from the surface. After 3-10 minutes at 15-30 ° C, the water was taken out. Next, the substrate was immersed in a microetching solution (SLOTOETCH 584, 10-40 g/L of SCHLOTTER) to further remove the oxide film. After 3-10 minutes at 15-30 ° C, the water was taken out.
將清洗後的基板浸入電鍍溶液中進行電鍍作業，使用SCHLOETTER的2.5L電解槽。電鍍溶液包括CuSO4(220g/L)，H2SO4(40g/L)，氯離子(60ppm)，載運劑(SCHLOTTER公司的產品SLOTOCOUP 31，5ml/L)，光澤劑(SCHLOTTER公司的產品SLOTOCOUP 32，0.2ml/L)，整平劑(SCHLOTTER公司的產品SLOTOCOUP 33，0.18ml/L)。 The cleaned substrate was immersed in a plating solution for electroplating, and a 2.5 L electrolytic cell of SCHLOETTER was used. The plating solution includes CuSO4 (220g/L), H2SO4 (40g/L), chloride ion (60ppm), carrier (SLOTOCOUP 31, 5ml/L from SCHLOTTER), and gloss agent (SLOTOCOUP 32 from SCHLOTTER), 0.2ml /L), leveling agent (SLLOTCOUP 33, SCHLOTTER product, 0.18ml/L).
電流密度為0.5-5.0ASD，時間為90-150分鐘，總消耗電量約為1.25~5Ah。較佳操作條件為電流密度0.5-2.0ASD，時間為120-150分鐘，總消耗電量約為1.25~2.5Ah。更佳的電流密度甚至可低至0.5-1.0ASD。銅離子於乾膜孔洞內的rGO導電層上沉積金屬銅50，乾膜表面的銅層則非常薄。 The current density is 0.5-5.0 ASD, the time is 90-150 minutes, and the total power consumption is about 1.25~5Ah. The preferred operating conditions are a current density of 0.5-2.0 ASD, a time of 120-150 minutes, and a total power consumption of about 1.25-2.5 Ah. Better current densities can be as low as 0.5-1.0 ASD. Copper ions deposit metal copper 50 on the rGO conductive layer in the dry film hole, and the copper layer on the dry film surface is very thin.
D. 去除抗鍍乾膜及表面銅層D. Removing the anti-plated dry film and the surface copper layer
蝕刻去除表面銅層後，以KOH或NaOH等鹼性藥劑將抗鍍乾膜剝除，留下均勻且等高的獨立金屬銅柱50。銅柱直徑為100um，高度為170um。 After etching to remove the surface copper layer, the anti-plating dry film is stripped with an alkaline agent such as KOH or NaOH to leave a uniform and equal height of the independent metal copper pillar 50. The copper column has a diameter of 100um and a height of 170um.
實施例2 製造印刷電路板上的線路及銅柱Example 2 Manufacturing of Circuits and Copper Posts on Printed Circuit Boards
第2圖為實施例2的流程示意圖。 Fig. 2 is a schematic flow chart of the second embodiment.
A. 製作線路及銅柱底座乾膜圖形A. Making lines and copper column base dry film graphics
取一覆有銅箔20的基板10，對其表面進行清潔、微蝕刻後，貼覆一層適當厚度的抗鍍乾膜31。藉由曝光、顯影，在欲電鍍的位置形成細線路及銅柱底座圖形。 A substrate 10 covered with a copper foil 20 is taken, and the surface thereof is cleaned and micro-etched, and then a layer of anti-plating dry film 31 of a suitable thickness is applied. By exposure and development, a thin line and a copper pillar base pattern are formed at the position to be plated.
B. PPR電鍍B. PPR plating
對銅箔基板實施週期性脈衝反向(Periodic Pulse Reverse，PPR)垂直電鍍程序，電鍍溶液包括CuSO4(80g/L)，H2SO4(200g/L)，氯離子(100ppm)，添加劑(SCHLOTTER公司的產品SLOTOCOUP CU211，10ml/L；SLOTOCOUP CU212，0.15ml/L)。正向電流密度為2ASD，正向與反向的電流密度比為1：2，正向與反向的時間比為20：1，正常攪拌強度，電鍍時間為60分鐘。 Perform periodic pulse reverse (PPR) vertical plating on copper foil substrates. The plating solution includes CuSO4 (80g/L), H2SO4 (200g/L), chloride ion (100ppm), and additives (products of SCHLOTTER). SLOTOCOUP CU211, 10ml/L; SLOTOCOUP CU212, 0.15ml/L). The forward current density is 2ASD, the current-to-reverse current density ratio is 1:2, the forward-to-reverse time ratio is 20:1, the normal stirring intensity, and the plating time is 60 minutes.
電鍍完成後，去除抗鍍乾膜，結果可得到表面及剖面皆平整的線路51及銅柱底座。 After the electroplating is completed, the anti-plating dry film is removed, and as a result, the line 51 and the copper post base having a smooth surface and a cross section can be obtained.
C. 製作銅柱乾膜圖形C. Making copper column dry film graphics
在上述形成線路的基板表面貼覆一層較厚的抗鍍乾膜32。藉由曝光、顯影，在欲電鍍的位置形成孔洞圖形。 A thick anti-plating dry film 32 is applied to the surface of the substrate on which the wiring is formed. A hole pattern is formed at a position to be plated by exposure and development.
D. 修飾rGO於乾膜孔洞中(SLOTOGO程序)D. Modifying rGO in dry film pores (SLOTOGO program)
重複實施例1的步驟B，使孔洞內壁的氧化石墨烯(GO)還原為還原氧化石墨烯(rGO)41。 Step B of Example 1 was repeated to reduce graphene oxide (GO) on the inner wall of the pore to reduced graphene oxide (rGO) 41.
E. 電鍍填孔及表面銅層(電鍍銅柱成型)E. Electroplated hole filling and surface copper layer (electroplated copper column forming)
對銅箔基板實施直流電電鍍程序，電鍍溶液包括CuSO4(220g/L)，H2SO4(40g/L)，氯離子(60ppm)，載運劑(SCHLOTTER公司的產品SLOTOCOUP 31，5ml/L)，光澤劑(SCHLOTTER公司的產品SLOTOCOUP 32，0.2ml/L)，整平劑(SCHLOTTER公司的產品SLOTOCOUP 33，0.18ml/L)。電流密度為0.5~2ASD，電鍍時間120~150min。 Direct current electroplating procedure for copper foil substrate, including CuSO4 (220g/L), H2SO4 (40g/L), chloride ion (60ppm), carrier (SLLOTCOUP 31, 5ml/L from SCHLOTTER), gloss agent ( SCHLOTTER's product SLOTOCOUP 32, 0.2ml/L), leveling agent (SLLOTCOUP 33, SCHLOTTER product, 0.18ml/L). The current density is 0.5~2ASD, and the plating time is 120~150min.
F. 去除表面銅層及抗鍍乾膜F. Removal of surface copper layer and anti-plating dry film
以蝕刻去除表面銅層後，將抗鍍乾膜剝除，留下細線路51及均勻且等高的金屬銅柱52。 After the surface copper layer is removed by etching, the anti-plating dry film is stripped, leaving a thin line 51 and a uniform and contoured metal copper pillar 52.
第3圖顯示本發明方法實施例1所製造的銅柱影像。圖(a)及(b)分別顯示去除面銅前後，電鍍銅沉積效果極佳，表面均勻而平整。圖(c)的銅柱陣列亦均勻而等高，適合應用在封裝材料的散熱板上，亦可作為積體電路晶片(IC)與印刷電路板之間的中介載板(interposer)。 Fig. 3 is a view showing a copper pillar image produced in Example 1 of the method of the present invention. Figures (a) and (b) show that the copper plating effect is excellent before and after the removal of the surface copper, and the surface is uniform and flat. The copper pillar array of Figure (c) is also uniform and contoured, suitable for use on a heat sink of a package material, or as an interposer between an integrated circuit chip (IC) and a printed circuit board.
綜上，本發明在印刷電路板上製造銅柱的方法具有下列特徵及優點： In summary, the method of manufacturing a copper post on a printed circuit board of the present invention has the following features and advantages:
A.利用rGO修飾抗鍍乾膜表面(亦即SLOTOGO程序)全程皆使用酸性藥劑，不會使乾膜自基板剝離，大幅地降低了製程的困難度。 A. Using rGO to modify the surface of the anti-plated dry film (also known as SLOTOGO program), the acidic agent is used throughout the process, and the dry film is not peeled off from the substrate, which greatly reduces the difficulty of the process.
B.僅需利用低電流密度(0.5-5.0ASD，甚至0.5-1.0ASD)即可達成金屬銅柱填充，相較習知技術所使用的電流密度(約12-20ASD)，完全無法與本案相比。 B. Metal copper column filling can be achieved only by using low current density (0.5-5.0 ASD, or even 0.5-1.0 ASD). Compared with the current density (about 12-20 ASD) used in the prior art, it is completely impossible to compare with the case. ratio.
C.習知技術的總消耗電量約為17~28.3Ah，本發明僅需1.25-5Ah，為習知技術的1/10，因此為極具競爭力的製程。 C. The total power consumption of the prior art is about 17 to 28.3 Ah, and the present invention requires only 1.25-5 Ah, which is 1/10 of the conventional technology, and thus is a highly competitive process.
D.利用rGO作為導電層，搭配低電流密度鍍銅，可得到較佳的金屬銅結構(orientation)；即使在高深寬比(AR 0.4-5，直徑50-200μm)的孔洞中，仍有非常良好的填孔效率，可以得到非常均勻且等高的銅柱。 D. Using rGO as a conductive layer, with low current density copper plating, can obtain better metal copper structure; even in the high aspect ratio (AR 0.4-5, diameter 50-200μm) holes, there is still very Good hole filling efficiency results in a very uniform and contoured copper column.
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| CN111383991A (en) * | 2020-03-19 | 2020-07-07 | 张宇明 | Conductive hole and preparation method and application thereof |
| CN114196484A (en) * | 2021-11-17 | 2022-03-18 | 广东世运电路科技股份有限公司 | Pore-finishing agent for manufacturing printed circuit board |
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| TWI703301B (en) * | 2019-07-05 | 2020-09-01 | 華通電腦股份有限公司 | The manufacture method of the heat dissipation component |
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| CN105448755B (en) * | 2016-01-15 | 2019-02-15 | 中芯长电半导体（江阴）有限公司 | A kind of encapsulating method and structure of copper pillar bump |
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| CN111383991A (en) * | 2020-03-19 | 2020-07-07 | 张宇明 | Conductive hole and preparation method and application thereof |
| CN111383991B (en) * | 2020-03-19 | 2023-09-22 | 张宇明 | Conductive hole and preparation method and application thereof |
| US20220295645A1 (en) * | 2021-03-11 | 2022-09-15 | Albert Yeh | Method for optimized filling hole and manufacturing fine line on printed circuit board |
| US11729917B2 (en) * | 2021-03-11 | 2023-08-15 | Triallian Corporation | Method for optimized filling hole and manufacturing fine line on printed circuit board |
| CN114196484A (en) * | 2021-11-17 | 2022-03-18 | 广东世运电路科技股份有限公司 | Pore-finishing agent for manufacturing printed circuit board |
| CN114196484B (en) * | 2021-11-17 | 2023-09-29 | 广东世运电路科技股份有限公司 | Hole-forming agent for manufacturing printed circuit board |
| CN114434894A (en) * | 2022-02-21 | 2022-05-06 | 江西柔顺科技有限公司 | Copper foil graphite film and preparation method thereof |
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