TW201911434A - 半導體裝置及半導體封裝 - Google Patents
半導體裝置及半導體封裝 Download PDFInfo
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- TW201911434A TW201911434A TW106130580A TW106130580A TW201911434A TW 201911434 A TW201911434 A TW 201911434A TW 106130580 A TW106130580 A TW 106130580A TW 106130580 A TW106130580 A TW 106130580A TW 201911434 A TW201911434 A TW 201911434A
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- 239000004065 semiconductor Substances 0.000 claims abstract description 112
- 239000011241 protective layer Substances 0.000 claims description 93
- 238000002161 passivation Methods 0.000 abstract 5
- 239000010410 layer Substances 0.000 description 35
- 239000002184 metal Substances 0.000 description 14
- 238000000034 method Methods 0.000 description 11
- 239000011229 interlayer Substances 0.000 description 9
- 238000004088 simulation Methods 0.000 description 9
- 239000008393 encapsulating agent Substances 0.000 description 8
- 230000017525 heat dissipation Effects 0.000 description 6
- 230000000149 penetrating effect Effects 0.000 description 5
- 229910000679 solder Inorganic materials 0.000 description 3
- 239000000463 material Substances 0.000 description 2
- 239000004593 Epoxy Substances 0.000 description 1
- 238000004140 cleaning Methods 0.000 description 1
- 239000000084 colloidal system Substances 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 238000001459 lithography Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 239000012778 molding material Substances 0.000 description 1
- 238000004806 packaging method and process Methods 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 238000007517 polishing process Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 239000000758 substrate Substances 0.000 description 1
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- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
一種半導體封裝包括晶粒、保護層、多個第一導電性通孔、多個第二導電性通孔、多個導熱性通孔以及連接圖案。所述晶粒包括多個第一接墊及多個第二接墊。所述保護層設置在所述晶粒上。所述多個第一導電性通孔及所述多個第二導電性通孔延伸穿過所述保護層並分別接觸所述第一接墊及所述第二接墊。所述多個導熱性通孔設置在所述保護層之上。所述導熱性通孔中的每一個與所述第一導電性通孔及所述第二導電性通孔間隔開。所述連接圖案設置在所述保護層上且連接所述第一導電性通孔及所述導熱性通孔。所述導熱性通孔透過所述連接圖案及所述第一導電性通孔連接到所述第一接墊。
Description
本發明是有關於一種半導體裝置及半導體封裝。
半導體裝置被用於例如個人電腦、手機、數碼相機、及其他電子設備等各種電子應用中。半導體裝置通常是透過以下方式來製作:在半導體基板上依序沉積多個絕緣層或介電層、導電層、以及半導體材料層;以及利用曝光顯影(lithography)製程對所述各種材料層進行圖案化以在其上形成電路元件及元件。許多積體電路通常是在單個半導體晶圓上製成。晶圓的晶粒可在晶圓級上進行處理及封裝,且已開發出各種技術用於晶圓級封裝。
本發明實施例提供一種半導體裝置及半導體封裝,其可提升半導體裝置的散熱效率。
在本發明的一實施例中,半導體裝置包括晶粒、保護層、多個第一導電性通孔、多個第二導電性通孔、多個導熱性通孔以及連接圖案。所述晶粒包括多個第一接墊及多個第二接墊。所述保護層設置在所述晶粒上。所述多個第一導電性通孔及所述多個第二導電性通孔延伸穿過所述保護層並分別接觸所述第一接墊及所述第二接墊。所述多個導熱性通孔設置在所述保護層之上,其中各導熱性通孔與所述第一導電性通孔及所述第二導電性通孔間隔開。所述連接圖案設置在所述保護層上且連接所述第一導電性通孔及所述導熱性通孔。所述導熱性通孔透過所述連接圖案及所述第一導電性通孔連接到所述第一接墊。
在本發明的一實施例中,半導體裝置包括晶粒、保護層、導電框架以及多個第三通孔。所述晶粒包括多個第一接墊及多個第二接墊。所述保護層設置在所述晶粒上並暴露出所述第一接墊及所述第二接墊。所述導電框架設置在所述保護層上且包括多個第一通孔及多個第二通孔,所述第一通孔貫穿所述保護層以分別接觸所述第一接墊,所述第二通孔完全設置在所述保護層的上方且透過所述導電框架連接到所述第一接墊。所述第三通孔貫穿所述保護層以分別接觸所述第二接墊。
在本發明的一實施例中,半導體封裝包括模封半導體裝置以及重佈線結構。所述模封半導體裝置包括半導體裝置及包封所述半導體裝置的封裝膠體。所述半導體裝置包括晶粒、保護層、導電框架以及多個第三通孔。所述晶粒包括多個第一接墊及多個第二接墊。所述保護層設置在所述晶粒上且暴露出所述第一接墊及所述第二接墊。所述導電框架設置在所述保護層上且包括多個第一通孔及多個第二通孔,所述第一通孔貫穿所述保護層以分別接觸所述第一接墊,所述第二通孔設置在所述保護層的上方且透過所述導電框架連接到所述第一接墊。所述多個第三通孔貫穿所述保護層以接觸所述第二接墊。所述重佈線結構設置在所述模封半導體裝置上且包括多個第一重佈線通孔,其中所述第一重佈線通孔中的第一組第一重佈線通孔連接所述第一通孔且所述第一重佈線通孔中的第二組第一重佈線通孔連接所述第二通孔。
為讓本發明的上述特徵和優點能更明顯易懂,下文特舉實施例,並配合所附圖式作詳細說明如下。
以下揭露內容提供用於實作所提供主題的不同特徵的許多不同的實施例或實例。以下闡述元件及排列的具體實例以簡化本發明實施例。當然,這些僅為實例且不旨在進行限制。舉例來說,以下說明中將第一特徵形成在第二特徵「之上」或第二特徵「上」可包括其中第一特徵及第二特徵被形成為直接接觸的實施例,且也可包括其中第一特徵與第二特徵之間可形成有附加特徵、進而使得所述第一特徵與所述第二特徵可能不直接接觸的實施例。另外,本公開內容可能在各種實例中重複使用參考編號及/或字母。這種重複使用是出於簡潔及清晰的目的,而不是自身表示所論述的各種實施例及/或配置之間的關係。
此外,為易於說明,本文中可能使用例如「之下(beneath)」、「下面(below)」、「下部的(lower)」、「上方(above)”、「上部的(upper)」等空間相對性用語來闡述圖中所示的一個元件或特徵與另一(其他)元件或特徵的關係。所述空間相對性用語旨在除圖中所繪示的取向外還囊括裝置在使用或操作中的不同取向。設備可具有其他取向(旋轉90度或處於其他取向)且本文中所用的空間相對性描述語可同樣相應地進行解釋。
另外,為易於說明,本文中可能使用例如“第一(first)”、“第二(second)”、“第三(third)”、“第四(fourth)”等用語來闡述與圖中所示者相似或不同的一個或多個元件或特徵,且可根據呈現次序或本說明的上下文來可互換地使用所述用語。
圖1是根據本發明一些示例性實施例的半導體裝置的示意性剖視圖。圖2A到圖2F說明根據本發明一些示例性實施例的半導體裝置的示意性平面圖。應注意,圖1說明圖2A中的半導體裝置100沿截面線A-A’截取的的剖視圖。參照圖1及圖2,在示例性實施例中,半導體裝置100可包括晶粒110、保護層120、導電框架130以及多個第三通孔160。晶粒110可包括多個第一接墊112及多個第二接墊113。在一些實施例中,第一接墊112可以是晶粒110的電源接墊,所述電源接墊可連接到晶粒110的Vdd
電源供應線,且第二接墊113可以是晶粒110的信號接墊。保護層120設置在晶粒110上,且包括多個開口OP用於暴露出第一接墊112及第二接墊113。如圖2A到圖2F所示,導電框架130設置在保護層120上。導電框架130包括多個第一通孔132及多個第二通孔134。在一些實施例中,半導體裝置100可進一步包括設置在保護層120上的另一保護層140,且可暴露出或可不暴露出第一通孔132及第二通孔134。應注意,為了更好地說明導電框架130在保護層120上的佈局,在圖2A到圖2F中省略繪示了設置在保護層120上的保護層140。
在一些實施例中,第一通孔132及第三通孔160設置在開口OP處。第一通孔132透過開口OP分別接觸第一接墊112,且第三通孔160透過開口OP分別接觸第二接墊113。換句話說,第一通孔132及第三通孔160經由開口OP貫穿保護層120,以接觸第一接墊112及第二接墊113。在一些實施例中,第二通孔134設置在保護層120的上方而不貫穿保護層120。第二通孔134中的每一個均與開口OP中與其距離最近的一個開口OP保持距離。也就是說,第二通孔134並不填充在開口OP中也不透過開口OP直接接觸第一接墊112。第二通孔134與開口OP之間的距離可相同。在其他實施例中,第二通孔134與開口OP之間的距離可不相同。在一些實施例中,第一通孔132與第二通孔134透過連接圖案136而相互連接。因此,如圖2A到圖2F所示,第一通孔132、第二通孔134以及連接圖案136可形成導電框架130。在一個實施例中,第一通孔132可以是用於直接連接晶粒110的第一接墊112的多個第一導電性通孔。第三通孔160可以是用於直接連接晶粒110的第二接墊113的多個第二導電性通孔。第二通孔134可以是用於透過導電框架130的連接圖案136及第一通孔132而連接到第一接墊112的導熱性通孔,以幫助排散來自晶粒110的熱量。在一個實施例中,第一通孔132分別設置在第一接墊112正上方。也就是說,保護層120上的第二通孔134不與第一接墊112重疊,而是僅透過連接圖案136及第一通孔132而間接連接到第一接墊112。
在示例性實施例中,半導體裝置100可進一步包括多個第四通孔150,所述第四通孔150與導電框架130隔離,如圖2A到圖2F所示。應注意,在圖2A到圖2F中,由細線繪示的圓圈表示第一通孔132(及圖2A中的第三通孔160),由粗線繪示的圓圈表示第二通孔134,且由虛線繪示的圓圈表示第四通孔150。在一些實施例中,第四通孔150可以是用以接觸晶粒110的多個接地接墊(例如,圖3A到圖3C中所示的接地接墊114)的接地通孔。在一個實施例中,第四通孔150可被第一通孔132環繞。應注意,圖2A到圖2F中所示的第四通孔150的佈局僅用於說明目的。第四通孔150的設置並不僅限於此。
參照圖2A,在所述實施例中,第一通孔132及第二通孔134中的第一組第二通孔134環繞保護層120的一區域R1,且第二通孔134中的第二組第二通孔134設置在區域R1內且被第一通孔132及第一組第二通孔134環繞。因此,導電框架130環繞保護層120的區域R1以連接第一通孔132與第一組第二通孔134,並朝區域R1的中心延伸以如圖2A所示連接第二組第二通孔134。在一些實施例中,連接圖案136可進一步包括第一連接圖案136a及第二連接圖案136b。第一連接圖案136a環繞保護層120的區域R1以連接第一通孔132與第一組第二通孔134。第二連接圖案136b連接第一通孔132與設置在區域R1內的第二組第二通孔134。透過此種配置,分佈在保護層120上的金屬密度可增大,以提高半導體裝置的散熱效率。應注意,圖2A所示的導電框架130的佈局僅用於說明目的。第一通孔132、第二通孔134以及連接圖案136的佈局並不僅限於此。
應注意,圖2B到圖2F中的所示的半導體裝置100中的每一個均含有許多與之前參照圖2A所公開的半導體裝置100相同或類似的特徵。出於清晰及簡潔目的,對相同或類似的特徵可不再予以贅述,且相同或類似的參考編號指示相同或相似的元件。此外,為圖式簡潔起見,在圖2B到圖2F中省略了第三通孔160的設置,且第三通孔160的設置並不僅限於本發明實施例。圖2A所示的半導體裝置100與圖2B到圖2F所示的半導體裝置100中的每一個之間的主要差異闡述如下。
參照圖2B,在所述實施例中,第一通孔132與第二通孔134一起環繞保護層120的區域R1。因此,導電框架130的連接圖案136環繞保護層120的區域R1,以連接第一通孔132與第二通孔134。
參照圖2C,在所述實施例中,第一通孔132環繞保護層120的區域R1,而第二通孔134中的至少一些第二通孔134設置在區域R1內並被第一通孔132環繞。因此,第一連接圖案136a環繞保護層120的區域R1以連接第一通孔132,且第二連接圖案136b朝區域R1的中心延伸以連接第一通孔132與設置在區域R1內的第二通孔134。
參照圖2D,在所述實施例中,第一通孔132及第二通孔134中的第一組第二通孔134環繞保護層120的區域R1,而第二通孔134中的第二組第二通孔134設置在區域R1內並被第一通孔132及第一組第二通孔134環繞。因此,第一連接圖案136a環繞保護層120的區域R1,以連接第一通孔132與第一組第二通孔134。第二連接圖案136b朝區域R1的中心延伸,用於在第一連接圖案136a與第二組第二通孔134之間進行連接。
參照圖2E,在所述實施例中,第一通孔132及第二通孔134中的第一組第二通孔134環繞保護層120的區域R1,而第二通孔134中的第二組第二通孔134設置在區域R1內並被第一通孔132及第一組第二通孔134環繞。因此,第一連接圖案136a環繞保護層120的區域R1,以連接第一通孔132與第一組第二通孔134。第二連接圖案136b朝區域R1的中心延伸,用於以格柵形式在第一連接圖案136a與第二組第二通孔134之間進行連接。
參照圖2F,在所述實施例中,第一通孔132及第二通孔134中的第一組第二通孔134環繞保護層120的區域R1,而第二通孔134中的第二組第二通孔134設置在區域R1內並被第一通孔132及第一組第二通孔134環繞。因此,第一連接圖案136a環繞保護層120的區域R1,以連接第一通孔132與第一組第二通孔134。第二連接圖案136b朝區域R1的中心延伸,用於以格柵形式在第一連接圖案136a與第二組第二通孔134之間進行連接,且用於以格柵形式在第二連接圖案136b與第二組第二通孔134之間進行連接。應注意,本發明實施例並不限制區域R1的大小及形狀。圖2A到圖2F所示的區域R1的大小及形狀可彼此相同或可彼此不同。
圖3A到圖3C說明根據本發明一些示例性實施例的半導體封裝的製程的示意性剖視圖。在圖1及圖2中所述的相同或類似的元件將使用相同的參考編號,且本文中將不再對相同的元件予以贅述。在一些實施例中,示出一個晶粒來代表晶片的多個晶粒,且示出單個封裝來代表多個半導體封裝。參照圖3A到圖3C,在一些實施例中,在圖1中所述的半導體裝置100可應用到集成扇出型(Integrated Fan-Out,InFO)封裝以形成圖3C所示的半導體封裝10,且製程闡述如下。應注意,為圖式簡潔起見,在圖3A到圖3C中省略了第三通孔160及第二接墊113。
參照圖3A,在示例性實施例中,可在載體20上形成多個層間通孔(through interlayer vias)310,且圖1所示的半導體裝置100可設置在載體20上。應注意,在此階段中,另一保護層140a可覆蓋晶粒110的有源表面。在一些實施例中,保護層140a可覆蓋導電框架130。然後,封裝膠體200a包封層間通孔310及半導體裝置100,以形成圖3A所示的模封半導體裝置300a。
參照圖3B,可對模封半導體裝置300a執行薄化製程以暴露出層間貫孔310的頂表面、第一通孔132的頂表面、第二通孔134的頂表面以及第四通孔150的頂表面,從而形成圖3B所示的模封半導體裝置300。在所述實施例中,封裝膠體200暴露出層間貫孔310的頂表面,且保護層140暴露出第一通孔132、第二通孔134以及第四通孔150的頂表面。在一些實施例中,所述薄化製程可包括研磨製程或化學機械拋光(chemical mechanical polishing,CMP)製程。在所述薄化製程之後,可視情況執行清潔步驟,以清潔並移除從薄化步驟產生的殘餘物。然而,本發明實施例並不僅限於此,且所述薄化製程可透過任何其他適當的方法來執行。
參照圖3C,可在模封半導體裝置300上形成重佈線結構400。可選擇性地設置焊料球及其他元件以電連接到重佈線結構400及/或層間貫孔310。可移除載體20,而半導體封裝10的製造製程可被大致上完成。
據此,半導體封裝10可包括模封半導體裝置300以及重佈線結構400。模封半導體裝置300可包括上述的半導體裝置100以及至少包封半導體裝置100的側表面的封裝膠體200。在一些實施例中,封裝膠體200可包含例如環氧樹脂或任意其他適當類型的模封材料。重佈線結構400設置在模封半導體裝置300上。在一些實施例中,重佈線結構400設置在模封半導體裝置300的暴露出第一通孔132及第二通孔134的第一側S1上。重佈線結構400包括多個第一重佈線通孔412a及412b。在一些實施例中,第一重佈線通孔中的第一組第一重佈線通孔412a連接到第一通孔132,且第一重佈線通孔中的第二組第一重佈線通孔412b連接到第二通孔134。此外,第一重佈線結構400可進一步包括連接到第三通孔160的第三組第一重佈線通孔。
在一些實施例中,模封半導體裝置300可進一步包括層間貫孔310,層間貫孔310延伸貫穿封裝膠體200以電連接到重佈線結構400。在一些實施例中,層間貫孔310的兩端可如圖3C所示從封裝膠體200暴露出,用於電連接位於模封半導體裝置300的第一側S1上的導電元件(例如,重佈線路)與位於模封半導體裝置300的第二側S2(與第一側S1相對)上的導電元件(例如,焊料球)。因此,半導體封裝10可透過層間貫孔310電連接到位在模封半導體裝置300的第一側S1/第二側S2的其他電子元件。在一些實施例中,半導體封裝10可透過多個焊料球電連接到印刷電路板500。
在一些實施例中,重佈線結構400可進一步包括第一介電層414、第一重佈線路416、第二介電層424以及多個第二重佈線通孔422a及422b。第一介電層414設置在模封半導體裝置300的第一側S1上,且第一重佈線通孔412a及412b貫穿第一介電層414以連接第一通孔132及第二通孔134。在一些實施例中,重佈線結構400可進一步包括用於連接第四通孔150的多個接地重佈線通孔418。第一重佈線路416設置在第一介電層414上並連接第一重佈線通孔412a及412b。第二介電層424設置在第一介電層414上,且第二重佈線通孔422a及422b貫穿第二介電層424並連接第一重佈線路416。類似地,可在第二介電層424上連續地堆疊更多個介電層、重佈線通孔以及重佈線路以形成重佈線結構400的多個層,且對應于第二通孔134的重佈線通孔可依序彼此連接以進一步增強半導體封裝10的散熱效率。應注意,出於舉例的目的,在圖3C中所繪示的重佈線結構400具有四層重佈線路及重佈線通孔,但重佈線結構400中的層的數目並不僅限於此。
圖4說明根據本發明一些示例性實施例的不同半導體封裝的熱阻模擬結果。圖4中的表顯示在具有不同金屬密度的不同半導體封裝(例示於圖4所示的俯視圖A到俯視圖H中)中對熱阻的減小的模擬結果。圖4所示的俯視圖A到俯視圖H顯示在不同半導體封裝中位於保護層120(在所述表的行(b)中指示為層“PM0”)上的導電框架130及第四通孔150的不同佈局。以細線繪示的通孔表示第一通孔132,以粗線繪示的通孔表示第二通孔134,且以虛線繪示的通孔表示第四通孔150。在圖2A到圖2F中所述的相同或類似的元件將使用相同的參考編號,且本文中將不再對相同的元件予以贅述。
因此,列(1)到列(8)分別示出圖4所示俯視圖A到俯視圖H中的半導體封裝的特性。在圖4所示的俯視圖C中示出的導電框架130的佈局與圖2C中示出的佈局相同,因此對相同或類似的特徵可不再予以贅述,且相同或類似的參考編號指示相同或相似的元件。因此,保護層120上的金屬密度顯著增大(相比於圖4所示的俯視圖A中作為參考指標的半導體封裝的金屬密度)。此外,在所述實施例中,第二通孔134的數目被例示為4。透過此種配置,參照圖4所示表的列(3),保護層120(即,表的列(b)中的“PM0”)上的金屬密度是19.5%。因此,半導體封裝的熱阻減小12%(相比於圖4所示的俯視圖A中作為參考指標的半導體封裝的熱阻)。
在圖4所示的俯視圖D中示出的導電框架130的佈局與圖2B中示出的佈局相同,因此對相同或類似的特徵可不再予以贅述,且相同或類似的參考編號指示相同或相似的元件。在所述實施例中,第二通孔134的數目增加到8。透過此種配置,參照圖4所示表的列(4),保護層120(即,表的列(b)中的“PM0”)上的金屬密度是17.6%,且半導體封裝的熱阻減小16.4%(相比於圖4所示的俯視圖A中作為參考指標的半導體封裝的熱阻)。
在圖4所示的俯視圖E中示出的導電框架130的佈局與圖2A中示出的佈局相同,因此對相同或類似的特徵可不再予以贅述,且相同或類似的參考編號指示相同或相似的元件。因此,參照圖4所示表的列(5),保護層120(即,表的列(b)中的“PM0”)上的金屬密度是23.5%,且半導體封裝的熱阻減小23.2%(相比於圖4所示的俯視圖A中作為參考指標的半導體封裝的熱阻)。
在圖4所示的俯視圖F中示出的導電框架130的佈局與圖2D中示出的佈局相同,因此對相同或類似的特徵可不再予以贅述,且相同或類似的參考編號指示相同或相似的元件。在所述實施例中,第二通孔134的數目增加到21。透過此種配置,參照圖4所示表的列(6),保護層120(層PM0)上的金屬密度是30.8%,且半導體封裝的熱阻減小34%(相比於圖4所示的俯視圖A中作為參考指標的半導體封裝的熱阻)。
根據類似的概念,第二通孔134的數目可繼續增加,且連接圖案136被配置成在第一通孔132與第二通孔134之間進行連接,以繼續增加金屬密度,從而繼續增強半導體裝置及具有所述半導體裝置的半導體封裝的散熱效率。在圖4所示的俯視圖A到俯視圖H中例示的實施例僅用於說明目的,且本發明實施例並不限制第二通孔134的數目以及保護層120上的導電框架130的佈局。
圖5說明根據本發明一些示例性實施例的不同半導體封裝的熱阻模擬結果。圖5中的表顯示在具有不同金屬密度的不同半導體封裝(例示於圖5所示的俯視圖A到俯視圖D中)中對熱阻的減小的模擬結果。圖5所示的俯視圖A到俯視圖D顯示在不同半導體封裝中位於保護層120(在所述表中指示為層“PM0”)上的導電框架130及第四通孔150的不同佈局。以細線繪示的通孔表示第一通孔132,以粗線繪示的通孔表示第二通孔134,且以虛線繪示的通孔表示第四通孔150。在圖2中所述的相同或類似的元件將使用相同的參考編號,且本文中將不再對相同的元件予以贅述。
因此,在圖5所示的俯視圖B中,第一通孔132環繞保護層120的區域R1,而第二通孔134設置在區域R1內並被第一通孔132環繞。因此,導電框架130包括環繞保護層120的區域R1的第一連接圖案136a以連接第一通孔132,而不包括第二連接圖案136b以連接第二通孔134。透過此種配置,參照圖5所示表的列(2),保護層120(層PM0)上的金屬密度是17.7%,而半導體封裝的熱阻減小0.2%(相比於圖5所示的俯視圖A中的參考半導體封裝的熱阻)。
在圖5所示俯視圖C中所示的一個實施例中,導電框架130僅包括第二連接圖案136b以連接第二通孔134,而不包括環繞保護層120的區域R1以連接第一通孔132的第一連接圖案136a。透過此種配置,參照圖5所示表的列(3),在圖5C中保護層120(層PM0)上的金屬密度是10.3%,此實際上小於圖5B所示的金屬密度。然而,半導體封裝的熱阻顯著地減小3.4%。此外,在圖5所示的俯視圖D中,導電框架130包括第一連接圖案136a及第二連接圖案136b兩者。透過此種配置,參照圖5所示表的列(4),保護層120(層PM0)上的金屬密度是19.5%,而半導體封裝的熱阻減小3.5%(相比於圖5所示的俯視圖A中作為參考指標的半導體封裝的熱阻)。因此,用於在第一通孔132與第二通孔134之間進行連接的第二連接圖案136b在減小熱阻方面發揮重要作用。
圖6說明根據本發明一些示例性實施例的不同半導體封裝的熱阻模擬結果。圖6中的表顯示在重佈線結構400中的重佈線通孔具有不同排列形式的不同半導體封裝(例示於圖6所示的剖視圖A到剖視圖C中)中對熱阻的減小的模擬結果。在圖3中所述的相同或類似的元件將使用相同的參考編號,且本文中將不再對相同的元件予以贅述。
在圖6所示的剖視圖A中示出的實施例中,重佈線結構400包括位於重佈線結構400的第一層上的第二組第一重佈線通孔412b、位於重佈線結構400的第二層上的第二重佈線通孔422b、以及位於重佈線結構400的第三層上的多個第三重佈線通孔432b。連接第二通孔134的第二組第一重佈線通孔412b不與第二重佈線通孔422b及第三重佈線通孔432b對齊,且圖6所示的剖視圖A中的半導體封裝的熱阻被視為參考熱阻。
因此,在圖6所示的剖視圖B中示出的實施例中,第二組第一重佈線通孔412b與至少一組第二重佈線通孔422b對齊,並且還與至少一組第三重佈線通孔432b對齊。透過此種配置,參照圖6所示表的列(2),圖6所示剖視圖B中的半導體封裝的熱阻減小37.3%(相比於圖6所示的俯視圖A中的半導體封裝的參考熱阻)。
在圖6所示的剖視圖C中示出的實施例中,第二組第一重佈線通孔412b與至少一組第二重佈線通孔422b對齊,且不與第三重佈線通孔432b對齊。透過此種配置,參照圖6所示表的列(3),圖6所示剖視圖C中的半導體封裝的熱阻減小22.2%(相比於圖6所示的俯視圖A中的半導體封裝的參考熱阻),此仍有優異的散熱效果。因此,在一些實施例中,第二組第一重佈線通孔412b可至少與一組第二重佈線通孔422b對齊,以進一步增強半導體封裝的散熱效率。
根據一些實施例,一種半導體裝置包括晶粒、保護層、多個第一導電性通孔、多個第二導電性通孔、多個導熱性通孔以及連接圖案。所述晶粒包括多個第一接墊及多個第二接墊。所述保護層設置在所述晶粒上。所述多個第一導電性通孔及所述多個第二導電性通孔延伸穿過所述保護層並分別接觸所述第一接墊及所述第二接墊。所述多個導熱性通孔設置在所述保護層之上,其中所述導熱性通孔中的每一個與所述第一導電性通孔及所述第二導電性通孔間隔開。所述連接圖案設置在所述保護層上且連接所述第一導電性通孔及所述導熱性通孔。所述導熱性通孔透過所述連接圖案及所述第一導電性通孔連接到所述第一接墊。
根據一些實施例,所述第一導電性通孔分別設置在所述第一接墊正上方,且所述第二導電性通孔分別設置在所述第二接墊正上方。
根據一些實施例,所述連接圖案環繞所述保護層的區域以連接所述第一導電性通孔與所述導熱性通孔中的至少一組導熱性通孔。
根據一些實施例,所述連接圖案包括第一連接圖案以及第二連接圖案。所述第一連接圖案環繞所述保護層的區域以連接所述第一導電性通孔。所述第二連接圖案連接所述第一導電性通孔與所述導熱性通孔,其中所述導熱性通孔設置在所述區域內且被所述第一導電性通孔環繞。
根據一些實施例,所述連接圖案包括第一連接圖案以及第二連接圖案。所述第一連接圖案環繞所述保護層的區域以連接所述第一導電性通孔與所述導熱性通孔中的第一組導熱性通孔。所述第二連接圖案連接所述第一導電性通孔與所述導熱性通孔中的第二組導熱性通孔,其中所述導熱性通孔中的所述第二組導熱性通孔設置在所述區域內並被所述第一導電性通孔及所述導熱性通孔中的所述第一組導熱性通孔環繞。
根據一些實施例,所述連接圖案包括第一連接圖案以及第二連接圖案。所述第一連接圖案環繞所述保護層的一區域以連接所述第一導電性通孔與所述導熱性通孔中的第一組導熱性通孔。所述第二連接圖案連接所述第一連接圖案與所述導熱性通孔中的第二組導熱性通孔,其中所述第二組導熱性通孔設置在所述區域內且被所述第一導電性通孔及所述第一組導熱性通孔環繞。
根據一些實施例,所述半導體裝置還包括多個接地通孔,所述接地通孔與所述第一導電性通孔及所述導熱性通孔隔離且接觸所述晶粒的多個接地接墊。所述第一接墊是所述晶粒的多個電源接墊且所述第二接墊是所述晶粒的多個信號接墊。
根據一些實施例,一種半導體裝置包括晶粒、保護層、導電框架以及多個第三通孔。所述晶粒包括多個第一接墊及多個第二接墊。所述保護層設置在所述晶粒上並暴露出所述第一接墊及所述第二接墊。所述導電框架設置在所述保護層上且包括多個第一通孔及多個第二通孔,所述第一通孔貫穿所述保護層以分別接觸所述第一接墊,所述第二通孔完全設置在所述保護層的上方且透過所述導電框架連接到所述第一接墊。所述第三通孔貫穿所述保護層以分別接觸所述第二接墊。
根據一些實施例,所述第一通孔分別設置在所述第一接墊正上方,且所述第三通孔分別設置在所述第二接墊正上方。
根據一些實施例,所述導電框架環繞所述保護層的一區域。
根據一些實施例,所述導電框架環繞所述保護層的一區域以連接所述第一通孔,且所述導電框架朝所述區域的中心延伸以連接所述第二通孔。
根據一些實施例,所述導電框架環繞所述保護層的一區域以連接所述第一通孔與所述第二通孔中的第一組第二通孔,且所述導電框架朝所述區域的中心延伸以連接所述第二通孔中的第二組第二通孔。
根據一些實施例,所述半導體裝置進一步包括多個第四通孔,所述多個第四通孔與所述導電框架隔離且接觸所述晶粒的多個接地接墊,且所述第二接墊是所述晶粒的多個信號接墊。
根據一些實施例,一種半導體封裝包括模封半導體裝置以及重佈線結構。所述模封半導體裝置包括半導體裝置及包封所述半導體裝置的封裝膠體。所述半導體裝置包括晶粒、保護層、導電框架以及多個第三通孔。所述晶粒包括多個第一接墊及多個第二接墊。所述保護層設置在所述晶粒上且暴露出所述第一接墊及所述第二接墊。所述導電框架設置在所述保護層上且包括多個第一通孔及多個第二通孔,所述第一通孔貫穿所述保護層以分別接觸所述第一接墊,所述第二通孔設置在所述保護層的上方且透過所述導電框架連接到所述第一接墊。所述多個第三通孔貫穿所述保護層以接觸所述第二接墊。所述重佈線結構設置在所述模封半導體裝置上且包括多個第一重佈線通孔,其中所述第一重佈線通孔中的第一組第一重佈線通孔連接所述第一通孔且所述第一重佈線通孔中的第二組第一重佈線通孔連接所述第二通孔。
根據一些實施例,所述第一通孔分別設置在所述第一接墊正上方,且所述第二通孔分別設置在所述第二接墊正上方。
根據一些實施例,所述導電框架環繞所述保護層的一區域。
根據一些實施例,所述導電框架環繞所述保護層的一區域以連接所述第一通孔,且所述導電框架朝所述區域的中心延伸以連接所述第二通孔。
根據一些實施例,所述導電框架環繞所述保護層的一區域以連接所述第一通孔與所述第二通孔中的第一組第二通孔,且所述導電框架朝所述區域的中心延伸以連接所述第二通孔中的第二組第二通孔。
根據一些實施例,所述半導體裝置進一步包括多個第四通孔,所述多個第四通孔與所述導電框架隔離且接觸所述晶粒的多個接地接墊,其中所述第一接墊是所述晶粒的多個電源接墊,且所述第二接墊是所述晶粒的多個信號接墊。
根據一些實施例,所述重佈線結構還包括第一介電層、第一重佈線路、第二介電層以及多個第二重佈線通孔。所述第一介電層設置在所述模封半導體裝置上,其中所述第一重佈線通孔貫穿所述第一介電層。所述第一重佈線路設置在所述第一介電層上且連接所述第一重佈線通孔。所述第二介電層設置在所述第一介電層上。所述第二重佈線通孔貫穿所述第二介電層且連接所述第一重佈線路,其中所述第二組第一重佈線通孔與所述第二重佈線通孔中的一組第二重佈線通孔對齊。
雖然本發明已以實施例揭露如上,然其並非用以限定本發明,任何所屬技術領域中具有通常知識者,在不脫離本發明的精神和範圍內,當可作些許的更動與潤飾,故本發明的保護範圍當視後附的申請專利範圍所界定者為準。
10‧‧‧半導體封裝
20‧‧‧載體
100‧‧‧半導體裝置
110‧‧‧晶粒
112‧‧‧第一接墊
113‧‧‧第二接墊
114‧‧‧接地接墊
120‧‧‧保護層
130‧‧‧導電框架
132‧‧‧第一通孔
134‧‧‧第二通孔
136‧‧‧連接圖案
136a‧‧‧第一連接圖案
136b‧‧‧第二連接圖案
140、140a‧‧‧保護層
150‧‧‧第四通孔
160‧‧‧第三通孔
200、200a‧‧‧封裝膠體
300、300a‧‧‧模封半導體裝置
310‧‧‧層間貫孔
400‧‧‧重佈線結構
412a、412b‧‧‧第一重佈線通孔
414‧‧‧第一介電層
416‧‧‧第一重佈線路
418‧‧‧接地重佈線通孔
422a、422b‧‧‧第二重佈線通孔
424‧‧‧第二介電層
432b‧‧‧第三重佈線通孔
500‧‧‧印刷電路板
OP‧‧‧開口
R1‧‧‧區域
S1‧‧‧第一側
S2‧‧‧第二側
圖1是依照本發明的一些示例性實施例的半導體裝置的示意性剖視圖。 圖2A到圖2F是依照本發明的一些示例性實施例的半導體裝置的示意性平面圖。 圖3A到圖3C是依照本發明的一些示例性實施例的半導體封裝的製程的示意性剖視圖。 圖4是依照本發明的一些示例性實施例的不同半導體封裝的熱阻模擬(thermal resistance simulation)結果。 圖5是依照本發明的一些示例性實施例的不同半導體封裝的熱阻模擬結果。 圖6是依照本發明的一些示例性實施例的不同半導體封裝的熱阻模擬結果。
Claims (1)
- 一種半導體裝置,包括: 一晶粒,包括多個第一接墊及多個第二接墊; 一保護層,設置在所述晶粒上; 多個第一導電性通孔及多個第二導電性通孔,延伸穿過所述保護層並分別接觸所述第一接墊及所述第二接墊; 多個導熱性通孔,設置在所述保護層之上,其中各所述導熱性通孔與所述第一導電性通孔及所述第二導電性通孔間隔開;以及 一連接圖案,設置在所述保護層上且連接所述導熱性通孔及所述第一導電性通孔,其中所述導熱性通孔透過所述連接圖案及所述第一導電性通孔連接到所述第一接墊。
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JPS62194652A (ja) * | 1986-02-21 | 1987-08-27 | Hitachi Ltd | 半導体装置 |
US6468894B1 (en) * | 2001-03-21 | 2002-10-22 | Advanced Micro Devices, Inc. | Metal interconnection structure with dummy vias |
US7224069B2 (en) * | 2005-07-25 | 2007-05-29 | Taiwan Semiconductor Manufacturing Company, Ltd. | Dummy structures extending from seal ring into active circuit area of integrated circuit chip |
US7838988B1 (en) * | 2009-05-28 | 2010-11-23 | Texas Instruments Incorporated | Stud bumps as local heat sinks during transient power operations |
US8294261B2 (en) * | 2010-01-29 | 2012-10-23 | Texas Instruments Incorporated | Protruding TSV tips for enhanced heat dissipation for IC devices |
US8174124B2 (en) * | 2010-04-08 | 2012-05-08 | Taiwan Semiconductor Manufacturing Co., Ltd. | Dummy pattern in wafer backside routing |
US8581400B2 (en) * | 2011-10-13 | 2013-11-12 | Taiwan Semiconductor Manufacturing Company, Ltd. | Post-passivation interconnect structure |
US9082761B2 (en) * | 2013-06-01 | 2015-07-14 | Taiwan Semiconductor Manufacturing Company, Ltd. | Polymer layers embedded with metal pads for heat dissipation |
US10431564B2 (en) * | 2014-01-27 | 2019-10-01 | Mediatek Inc. | Structure and formation method of chip package structure |
US9768147B2 (en) * | 2014-02-03 | 2017-09-19 | Micron Technology, Inc. | Thermal pads between stacked semiconductor dies and associated systems and methods |
US9515002B2 (en) * | 2015-02-09 | 2016-12-06 | Micron Technology, Inc. | Bonding pads with thermal pathways |
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