TW201903972A - Vertical memory and manufacturing method thereof - Google Patents
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- H10B43/20—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
- H10B43/23—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
- H10B43/27—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
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Abstract
Description
本發明係關於一種垂直式記憶體及其製作方法，尤指一種具有較佳效能的影像感測器及其製作方法。The invention relates to a vertical memory and a manufacturing method thereof, and more particularly to an image sensor with better performance and a manufacturing method thereof.
對於傳統的平面式記憶體結構而言，記憶單元(cell)中的閘極、源極、以及汲極等部件皆係設置在同一平面上，故有效記憶單元的面積僅能依靠改變曝光機台的曝光線寬(CD)來微縮化(scale down)，其記憶體單位面積下所能製作的記憶單元數目很難有突破性的成長。特別係現今的記憶體製程已進入了線寬40奈米(nm)以下之世代，具備如此線寬能力的曝光機台所費不貲，故製程技術的開發成本十分昂貴。現今業界中有開發出許多製程，得以使用現有的曝光機台製作出尺寸更為微縮的元件或結構，然該些製程大多相當複雜，容易導致產品良率的下降，是為其一大缺點。再者，對於平面式記憶體結構而言，當尺寸微縮到一定程度以下時，相鄰記憶單元之間必定會有嚴重的干擾效應，導致電性的劣化。For the traditional planar memory structure, the gate, source, and drain components in the memory cell are all set on the same plane, so the area of the effective memory unit can only be changed by changing the exposure machine. To scale down the exposure line width (CD), the number of memory cells that can be made per unit area of memory is difficult to grow breakthroughly. In particular, the current memory system has entered the generation with a line width of 40 nanometers (nm) or less. The exposure machine with such a line width capability is expensive, so the development cost of process technology is very expensive. Many processes have been developed in the industry today, which can use the existing exposure equipment to make components or structures with smaller dimensions. However, most of these processes are quite complicated, which can easily lead to the decline of product yield, which is a major disadvantage. Furthermore, for a planar memory structure, when the size is reduced to a certain level or less, there must be a serious interference effect between adjacent memory units, resulting in electrical degradation.
鑑於現今平面式記憶體結構在尺寸微縮方面已到達了瓶頸，業界遂開始研究開發垂直式之記憶體，以大幅地降低有效記憶單元所需之面積，以期記憶體的記憶單元數目能有突破性的成長。然而，如何改良以增進垂直式之記憶體的寫入/抹除效率及電荷保持性仍為所述技術領域的技術人員須努力研究之課題。In view of the fact that today's planar memory structures have reached a bottleneck in terms of size reduction, the industry has begun to research and develop vertical memory to greatly reduce the area required for effective memory cells, in order to achieve a breakthrough in the number of memory cells. Growth. However, how to improve the write / erase efficiency and charge retention of the vertical memory is still a subject for those skilled in the art to study.
本發明提供了一種具有空氣間隙層的垂直式記憶體及其製作方法，以改善垂直式記憶體的效能。The invention provides a vertical memory with an air gap layer and a manufacturing method thereof to improve the performance of the vertical memory.
本發明之實施例提供了一種垂直式記憶體，其包括複數個記憶單元，記憶單元沿垂直於一基底表面的一第一方向依序堆疊，其中各記憶單元包括一通道層、一閘極、一儲存層、一穿隧層、一阻擋層以及一空氣間隙層。通道層沿第一方向延伸，而閘極沿著平行於基底表面的一第二方向設置於通道層之一側。儲存層設置於通道層與閘極之間，並沿第一方向延伸。穿隧層設置於通道層與儲存層之間，並沿第一方向延伸。阻擋層設置於閘極與儲存層之間，其中阻擋層覆蓋閘極之一頂面、一底面及一側面。空氣間隙層沿第一方向延伸，並設置於儲存層與阻擋層之間或設置於儲存層與穿隧層之間。An embodiment of the present invention provides a vertical memory including a plurality of memory cells. The memory cells are sequentially stacked along a first direction perpendicular to a substrate surface. Each memory cell includes a channel layer, a gate, A storage layer, a tunneling layer, a barrier layer, and an air gap layer. The channel layer extends along the first direction, and the gate electrode is disposed on one side of the channel layer along a second direction parallel to the surface of the substrate. The storage layer is disposed between the channel layer and the gate electrode, and extends along the first direction. The tunneling layer is disposed between the channel layer and the storage layer, and extends along the first direction. The barrier layer is disposed between the gate electrode and the storage layer, wherein the barrier layer covers a top surface, a bottom surface, and a side surface of the gate electrode. The air gap layer extends along the first direction and is disposed between the storage layer and the barrier layer or between the storage layer and the tunneling layer.
本發明之實施例另提供了一種垂直式記憶體的製作方法，其包括下列步驟。首先，提供一基底，在基底上形成由多個絕緣層與多個第一犧牲層所交替堆疊的一多層結構。於多層結構中形成一第一通孔，其中第一通孔沿垂直於基底表面的一第一方向延伸。接著，在第一通孔的側壁表面形成沿第一方向延伸之一第二犧牲層、一儲存層、一穿隧層與一通道層，其中穿隧層設置於儲存層與通道層之間。於多層結構中形成一第二通孔，鄰近於第一通孔設置，並由第二通孔移除第一犧牲層，以形成多個凹槽。然後，於凹槽中分別共形地形成一個阻擋層，並於凹槽中分別形成一閘極填滿各凹槽，其中閘極沿著平行於基底表面的一第二方向設置於通道層之一側，阻擋層設置於閘極與儲存層之間，且阻擋層覆蓋閘極之一頂面、一底面及一側面。接著，移除第二犧牲層，以形成沿第一方向延伸之一空氣間隙層。An embodiment of the present invention further provides a method for manufacturing a vertical memory, which includes the following steps. First, a substrate is provided, and a multilayer structure is formed on the substrate by alternately stacking a plurality of insulating layers and a plurality of first sacrificial layers. A first through hole is formed in the multilayer structure, wherein the first through hole extends in a first direction perpendicular to the surface of the substrate. Next, a second sacrificial layer, a storage layer, a tunneling layer, and a channel layer extending along the first direction are formed on the sidewall surface of the first through hole, and the tunneling layer is disposed between the storage layer and the channel layer. A second through hole is formed in the multilayer structure, and is disposed adjacent to the first through hole. The first sacrificial layer is removed from the second through hole to form a plurality of grooves. Then, a barrier layer is formed conformally in the groove, and a gate is formed in the groove to fill each groove, wherein the gate is arranged on the channel layer along a second direction parallel to the surface of the substrate. On one side, the barrier layer is disposed between the gate electrode and the storage layer, and the barrier layer covers one of the top surface, one bottom surface, and one side surface of the gate electrode. Then, the second sacrificial layer is removed to form an air gap layer extending in the first direction.
為使熟習本發明所屬技術領域之一般技藝者能更進一步瞭解本發明，下文特列舉本發明之較佳實施例，並配合所附圖示，詳細說明本發明的垂直式記憶體及其製作方法及所欲達成的功效。In order to make a person skilled in the art who is familiar with the technical field of the present invention further understand the present invention, the preferred embodiments of the present invention are enumerated below, and the accompanying drawings are used to describe the vertical memory of the present invention and its manufacturing method in detail. And the desired effect.
請參考第1圖與第2圖，第1圖為本發明垂直式記憶體之第一實施例的剖面示意圖，而第2圖為沿第1圖中切線A-A’的俯視圖。為了使讀者容易瞭解本發明特徵，剖面示意圖或俯視圖中各膜層或元件的尺寸及比例並不完全依照實際的尺寸及比例繪示，且本發明各膜層或元件的尺寸及比例並不以圖式所示為限。如第1圖與第2圖所示，本實施例的垂直式記憶體1包括一基底100及複數條記憶體串列10，其中記憶體串列10設置於基底100上。為了突顯本發明的特徵，第1圖僅繪示出兩條記憶體串列10作為示意，但本發明並不以此為限。在本實施例中，基底100可包括矽基底、磊晶矽基底、矽鍺基底、碳化矽基底或絕緣層覆矽(silicon-on-insulator，SOI)基底，但並不以此為限。各個記憶體串列10係由複數個記憶單元101沿垂直於基底100表面的一第一方向D1依序堆疊所構成，其中各記憶單元101包括一通道層102、一閘極104、一儲存層106、一穿隧層108、一阻擋層110以及一空氣間隙層112。通道層102沿第一方向D1延伸，其中本實施例的通道層102為多晶矽層，如n型或p型的多晶矽層，但不以此為限。在其他實施例中，通道層102可包括其他適合的半導體材料。閘極104沿著平行於基底100表面的一第二方向D2設置於通道層102之一側，其中本實施例的第一方向D1係垂直於第二方向D2，且第二方向D2平行於基底100的表面。本實施例的閘極104包括金屬材料，但不以此為限。在其他實施例中，閘極104可包括多晶矽或其他適合的導電材料。儲存層106設置於通道層102與閘極104之間，穿隧層108設置於通道層102與儲存層106之間，阻擋層110設置於閘極104與儲存層106之間，其中儲存層106及穿隧層108沿第一方向D1延伸，而阻擋層110覆蓋閘極104之一頂面、一底面及面對儲存層106之一側面。在本實施例中，儲存層106為一氮化矽層，穿隧層108為一氧化矽層，而阻擋層110為一氧化鋁層，但不以此為限。藉此，儲存層106的兩側分別受到穿隧層108與阻擋層110所包覆。在此設置下，兩側的穿隧層108與阻擋層110作為儲存層106與外部結構之間的絕緣層，使電荷得以儲存在儲存層106中，以達到資料儲存之效果。再者，閘極104可為記憶單元101的控制閘(CG)，用以控制儲存層106中所儲存的電荷之釋放與否，以進行資料的儲存及消除。此外，在其他實施例中，阻擋層110亦可包括其他適合的高介電常數材料或絕緣材料，而穿隧層108亦可包括其他適合的絕緣材料。Please refer to FIG. 1 and FIG. 2. FIG. 1 is a schematic cross-sectional view of the first embodiment of the vertical memory of the present invention, and FIG. 2 is a top view taken along a tangent line A-A 'in FIG. In order to make the reader easy to understand the features of the present invention, the dimensions and proportions of the film layers or elements in the schematic cross-section diagram or the top view are not completely drawn according to the actual dimensions and proportions, and the dimensions and proportions of the film layers or elements of the present invention are not The figure shows the limits. As shown in FIG. 1 and FIG. 2, the vertical memory 1 of this embodiment includes a substrate 100 and a plurality of memory strings 10. The memory string 10 is disposed on the substrate 100. In order to highlight the features of the present invention, FIG. 1 only shows two memory strings 10 as an illustration, but the present invention is not limited thereto. In this embodiment, the substrate 100 may include a silicon substrate, an epitaxial silicon substrate, a silicon germanium substrate, a silicon carbide substrate, or a silicon-on-insulator (SOI) substrate, but is not limited thereto. Each memory string 10 is formed by sequentially stacking a plurality of memory cells 101 along a first direction D1 perpendicular to the surface of the substrate 100. Each memory cell 101 includes a channel layer 102, a gate 104, and a storage layer. 106. A tunneling layer 108, a blocking layer 110, and an air gap layer 112. The channel layer 102 extends along the first direction D1. The channel layer 102 in this embodiment is a polycrystalline silicon layer, such as an n-type or p-type polycrystalline silicon layer, but is not limited thereto. In other embodiments, the channel layer 102 may include other suitable semiconductor materials. The gate electrode 104 is disposed on one side of the channel layer 102 along a second direction D2 parallel to the surface of the substrate 100. The first direction D1 in this embodiment is perpendicular to the second direction D2, and the second direction D2 is parallel to the substrate. 100 surface. The gate electrode 104 in this embodiment includes a metal material, but is not limited thereto. In other embodiments, the gate 104 may include polycrystalline silicon or other suitable conductive materials. The storage layer 106 is disposed between the channel layer 102 and the gate 104, the tunneling layer 108 is disposed between the channel layer 102 and the storage layer 106, and the barrier layer 110 is disposed between the gate 104 and the storage layer 106, where the storage layer 106 The tunneling layer 108 extends along the first direction D1, and the barrier layer 110 covers a top surface, a bottom surface of the gate electrode 104, and a side surface facing the storage layer 106. In this embodiment, the storage layer 106 is a silicon nitride layer, the tunneling layer 108 is a silicon oxide layer, and the barrier layer 110 is an aluminum oxide layer, but it is not limited thereto. Accordingly, both sides of the storage layer 106 are covered by the tunneling layer 108 and the barrier layer 110, respectively. Under this setting, the tunneling layer 108 and the barrier layer 110 on both sides serve as an insulating layer between the storage layer 106 and the external structure, so that charges can be stored in the storage layer 106 to achieve the effect of data storage. In addition, the gate 104 may be a control gate (CG) of the memory unit 101, and is used to control the release or non-charge of the electric charge stored in the storage layer 106 for data storage and elimination. In addition, in other embodiments, the barrier layer 110 may also include other suitable high dielectric constant materials or insulating materials, and the tunneling layer 108 may also include other suitable insulating materials.
空氣間隙層112沿第一方向D1延伸，且本實施例的空氣間隙層112設置於儲存層106與阻擋層110之間，但空氣間隙層112設置的位置並不以此為限。舉例而言，以往使用多晶矽作為閘極以及使用氧化矽作為阻擋層的垂直式記憶體，其中電子從閘極回灌至儲存層所需克服的能障為約3.2電子伏特。在本實施例中，閘極104為金屬並在閘極104與儲存層106之間多了一層空氣間隙層112，此時電子從閘極104回灌至儲存層106所需克服的能障為約5.2電子伏特。因此，當本實施例的記憶單元101處於抹除(erase)的階段時，由於空氣間隙層112存在於儲存層106與阻擋層110之間，使得原先欲從閘極104回灌至儲存層106的電子受到空氣間隙層112產生的高能障所阻擋，減少電子從閘極104回灌至儲存層106發生的機率，進而提升記憶單元101與垂直式記憶體1的抹除效率。The air gap layer 112 extends along the first direction D1, and the air gap layer 112 in this embodiment is disposed between the storage layer 106 and the barrier layer 110, but the position where the air gap layer 112 is disposed is not limited thereto. For example, in the past, vertical memory using polycrystalline silicon as a gate and silicon oxide as a blocking layer has an energy barrier of about 3.2 electron volts that must be overcome for recharging electrons from the gate to the storage layer. In this embodiment, the gate 104 is metal and an air gap layer 112 is added between the gate 104 and the storage layer 106. At this time, the energy barrier to be recharged from the gate 104 to the storage layer 106 is: About 5.2 electron volts. Therefore, when the memory unit 101 of this embodiment is in the erasing phase, the air gap layer 112 exists between the storage layer 106 and the barrier layer 110, so that the original intention to recharge from the gate 104 to the storage layer 106 is The electrons are blocked by the high energy barrier generated by the air gap layer 112, which reduces the probability of electrons being recharged from the gate 104 to the storage layer 106, thereby improving the erasing efficiency of the memory unit 101 and the vertical memory 1.
另一方面，本實施例的垂直式記憶體1包括複數個柱狀結構20a，其中柱狀結構20a設置於基底100上，且任一個柱狀結構20a係設置於一條記憶體串列10之中，或是說一個柱狀結構20a被一條記憶體串列10所包圍。為了突顯本發明的特徵，第1圖僅繪示出兩個柱狀結構20a作為示意，但本發明並不以此為限。柱狀結構20a包括一氧化物柱118、通道層102、儲存層106、穿隧層108及空氣間隙層112。氧化物柱118設置於柱狀結構20a的中心，並沿第一方向D1從基底100向上延伸。本實施例氧化物柱118的材料為氧化矽，但不以此為限。在其他實施例中，氧化物柱118的材料亦可包括其他適合的絕緣材料。如第2圖所示，通道層102、穿隧層108、儲存層106及空氣間隙層112係以氧化物柱118為中心，以平行於基底100的表面（或沿第二方向D2）依序地由內往外環狀包圍氧化物柱118，形成同心圓環。此外，柱狀結構20a外的閘極104及阻擋層110亦環狀包圍柱狀結構20a。換言之，對於同一條記憶體串列10中互相堆疊的記憶單元101而言，各記憶單元101中的閘極104分別對應柱狀結構20a中同一通道層102、儲存層106、穿隧層108及空氣間隙層112的一部分，因此同一條記憶體串列10中之各記憶單元101的通道層102、儲存層106、穿隧層108及空氣間隙層112係互相連通。此外，在記憶體串列10中，任兩相鄰之記憶單元101之閘極104係由一絕緣層120隔開，而這些絕緣層120亦環狀包圍柱狀結構20a，並位於上、下相鄰的記憶單元101的阻擋層110之間。本實施例的絕緣層120包括氧化物，例如氧化矽，但不以此為限。On the other hand, the vertical memory 1 of this embodiment includes a plurality of columnar structures 20 a, wherein the columnar structures 20 a are disposed on the substrate 100, and any of the columnar structures 20 a are disposed in a memory string 10. Or, a columnar structure 20 a is surrounded by a memory string 10. In order to highlight the features of the present invention, FIG. 1 only shows two columnar structures 20 a as a schematic diagram, but the present invention is not limited thereto. The pillar structure 20 a includes an oxide pillar 118, a channel layer 102, a storage layer 106, a tunneling layer 108, and an air gap layer 112. The oxide pillar 118 is disposed at the center of the pillar structure 20 a and extends upward from the substrate 100 in the first direction D1. The material of the oxide pillar 118 in this embodiment is silicon oxide, but it is not limited thereto. In other embodiments, the material of the oxide pillar 118 may also include other suitable insulating materials. As shown in FIG. 2, the channel layer 102, the tunneling layer 108, the storage layer 106, and the air gap layer 112 are centered on the oxide pillar 118 and are parallel to the surface of the substrate 100 (or along the second direction D2) in order. The ground surrounds the oxide pillars 118 from the inside to the outside, forming a concentric ring. In addition, the gate 104 and the barrier layer 110 outside the columnar structure 20a also surround the columnar structure 20a in a ring shape. In other words, for the memory cells 101 stacked on each other in the same memory string 10, the gate 104 in each memory cell 101 corresponds to the same channel layer 102, storage layer 106, tunneling layer 108, and A part of the air gap layer 112, therefore, the channel layer 102, the storage layer 106, the tunneling layer 108, and the air gap layer 112 of each memory cell 101 in the same memory series 10 communicate with each other. In addition, in the memory string 10, the gates 104 of any two adjacent memory cells 101 are separated by an insulating layer 120, and these insulating layers 120 also surround the columnar structure 20a in a ring shape and are located above and below. Between the barrier layers 110 of the adjacent memory cells 101. The insulating layer 120 in this embodiment includes an oxide, such as silicon oxide, but is not limited thereto.
如第1圖所示，本實施例的記憶單元101另包括一源極線114與一隔離結構116，兩者皆沿第一方向D1延伸。閘極104設置於通道層102與源極線114之間，且源極線114可與通道層102電性連接(未示於第1圖)。藉此，儲存訊號可經由源極線114傳入通道層102中，而作為控制閘的閘極104可產生電場，使電荷會固限在儲存層106中，達成資料儲存之效果。源極線114可包括導電材料如摻雜多晶矽，或是金屬如鎢、鈦、鈷、鎳或其合金等。隔離結構116設置於閘極104與源極線114之間，可包括絕緣材料，使得閘極104與源極線114電性隔絕。簡而言之，在本實施例中，一條記憶體串列10中的記憶單元101係對應同一條源極線114，且記憶體串列10與其所對應之源極線114之間係以隔離結構116隔開，但不以此為限。As shown in FIG. 1, the memory unit 101 of this embodiment further includes a source line 114 and an isolation structure 116, both of which extend along the first direction D1. The gate electrode 104 is disposed between the channel layer 102 and the source line 114, and the source line 114 can be electrically connected to the channel layer 102 (not shown in FIG. 1). As a result, the storage signal can be transmitted into the channel layer 102 through the source line 114, and the gate 104 as a control gate can generate an electric field, so that the charges are confined in the storage layer 106 to achieve the effect of data storage. The source line 114 may include a conductive material such as doped polycrystalline silicon, or a metal such as tungsten, titanium, cobalt, nickel, or an alloy thereof. The isolation structure 116 is disposed between the gate electrode 104 and the source line 114 and may include an insulating material so that the gate electrode 104 is electrically isolated from the source line 114. In short, in this embodiment, the memory cells 101 in a memory string 10 correspond to the same source line 114, and the memory string 10 and its corresponding source line 114 are isolated. The structures 116 are separated, but not limited thereto.
在本實施例之垂直式記憶體1中，柱狀結構20a另可選擇性地包括一第一多晶矽層122，設置於柱狀結構20a靠近基底100的一端，並位於通道層102底部與基底100之間，或是位於最下層之記憶單元101之通道層102與基底100之間。此外，記憶體串列10於靠近基底100的一端可選擇性地包括一第一選擇閘極126、一絕緣部分128與一介電部分130。第一選擇閘極126對應第一多晶矽層122設置並設置於最下層之記憶單元101之閘極104與基底100之間，且第一選擇閘極126係作為源極端選擇閘極(SGS)。絕緣部分128對應第一選擇閘極126設置於第一多晶矽層122上，並設置於第一多晶矽層122與第一選擇閘極126之間，且介電部分130設置於第一選擇閘極126與絕緣部分128之間。換言之，第一選擇閘極126、絕緣部分128、介電部分130與第一多晶矽層122可視為記憶體串列10中之一個選擇電晶體(select transistor)。本實施例絕緣部分128的材料可包括氧化矽，但不以此為限。第一選擇閘極126的材料可與前文之閘極104相同，而介電部分130的材料可與前文之阻擋層110相同，於此不再贅述。另一方面，記憶體串列10於相反於基底100的另一端（在第1圖中為記憶體串列10的頂端）可選擇性地包括一第二選擇閘極132，其係作為汲極端選擇閘極(SGD)。第二選擇閘極132的設置方式與記憶單元101之閘極104類似，且對應於柱狀結構20a中的通道層102、穿隧層108、儲存層106、空氣間隙層112，並藉由阻擋層110將第二選擇閘極132與柱狀結構20a隔開。第二選擇閘極132與上述的元件可視為記憶體串列10中之另一個選擇電晶體。第二選擇閘極132的材料可與前文之閘極104相同，而上述第二選擇閘極132對應之其餘元件的材料選擇皆已於前文介紹，於此不再贅述。簡而言之，在本實施例之記憶體串列10中，記憶單元101的閘極104皆設置於第一選擇閘極126與第二選擇閘極132之間，而記憶單元101皆設置於兩選擇電晶體之間，但不以此為限。In the vertical memory 1 of this embodiment, the columnar structure 20a may optionally further include a first polycrystalline silicon layer 122 disposed at an end of the columnar structure 20a near the substrate 100 and located at the bottom of the channel layer 102 and Between the substrates 100 or between the channel layer 102 and the substrate 100 of the lowermost memory unit 101. In addition, the memory string 10 may optionally include a first selection gate 126, an insulating portion 128, and a dielectric portion 130 at an end near the substrate 100. The first selection gate 126 is disposed corresponding to the first polycrystalline silicon layer 122 and is disposed between the gate 104 of the lowermost memory cell 101 and the substrate 100, and the first selection gate 126 is used as a source extreme selection gate (SGS). ). The insulating portion 128 is disposed on the first polycrystalline silicon layer 122 corresponding to the first selection gate 126, and is disposed between the first polycrystalline silicon layer 122 and the first selection gate 126, and the dielectric portion 130 is disposed on the first A selection is made between the gate electrode 126 and the insulating portion 128. In other words, the first selection gate 126, the insulating portion 128, the dielectric portion 130, and the first polycrystalline silicon layer 122 can be regarded as one of the select transistors in the memory string 10. The material of the insulating portion 128 in this embodiment may include silicon oxide, but is not limited thereto. The material of the first selection gate electrode 126 may be the same as that of the gate electrode 104 described above, and the material of the dielectric portion 130 may be the same as that of the barrier layer 110 described above, and details are not described herein again. On the other hand, the other side of the memory string 10 opposite to the substrate 100 (the top of the memory string 10 in FIG. 1) may optionally include a second selection gate 132 as a drain terminal. Select the gate (SGD). The arrangement of the second selection gate 132 is similar to that of the gate 104 of the memory cell 101, and corresponds to the channel layer 102, the tunneling layer 108, the storage layer 106, and the air gap layer 112 in the columnar structure 20a, and is blocked by The layer 110 separates the second selection gate 132 from the pillar structure 20 a. The second selection gate 132 and the aforementioned components can be regarded as another selection transistor in the memory string 10. The material of the second selection gate 132 may be the same as that of the gate 104 described above, and the material selection of the remaining components corresponding to the second selection gate 132 described above has been described above, and will not be described again here. In short, in the memory string 10 of this embodiment, the gates 104 of the memory unit 101 are all disposed between the first selection gate 126 and the second selection gate 132, and the memory units 101 are disposed at Between the two selection transistors, but not limited to this.
在本實施例中，柱狀結構20a另可選擇性地包括一第二多晶矽層124，設置於柱狀結構20a相反於基底100的另一端，並位於通道層102上。換言之，第一多晶矽層122與第二多晶矽層124分別設置於柱狀結構20a的兩端，因此記憶單元101(或記憶體串列10)之通道層102係設置於第一多晶矽層122與第二多晶矽層124之間。第二多晶矽層124可用來作為接觸墊，並可跟垂直式記憶體1中之其他訊號線(未示於第1圖中)電性連接。此外，本實施例柱狀結構20a具有第二多晶矽層124的一端係突出於記憶體串列10，其中空氣間隙層112的頂面與記憶體串列10的頂面共平面，且鄰近第二多晶矽層124之部分儲存層106係突出於空氣間隙層112與記憶體串列10，並沒有被空氣間隙層112與記憶體串列10包覆。此外，垂直式記憶體1另包括一覆蓋層134，覆蓋記憶體串列10、柱狀結構20a、源極線114與隔離結構116，換言之，覆蓋層134覆蓋了第二多晶矽層124、空氣間隙層112、儲存層106以及阻檔層110。In this embodiment, the columnar structure 20 a may optionally include a second polycrystalline silicon layer 124 disposed on the other end of the columnar structure 20 a opposite to the substrate 100 and located on the channel layer 102. In other words, the first polycrystalline silicon layer 122 and the second polycrystalline silicon layer 124 are respectively disposed at both ends of the columnar structure 20a. Therefore, the channel layer 102 of the memory unit 101 (or the memory string 10) is disposed at the first polysilicon layer. Between the crystalline silicon layer 122 and the second polycrystalline silicon layer 124. The second polycrystalline silicon layer 124 can be used as a contact pad, and can be electrically connected to other signal lines (not shown in FIG. 1) in the vertical memory 1. In addition, in this embodiment, one end of the columnar structure 20a having the second polycrystalline silicon layer 124 protrudes from the memory array 10, wherein the top surface of the air gap layer 112 and the top surface of the memory array 10 are coplanar and adjacent to each other. Part of the storage layer 106 of the second polycrystalline silicon layer 124 protrudes from the air gap layer 112 and the memory string 10, and is not covered by the air gap layer 112 and the memory string 10. In addition, the vertical memory 1 further includes a cover layer 134 covering the memory string 10, the columnar structure 20a, the source line 114 and the isolation structure 116. In other words, the cover layer 134 covers the second polycrystalline silicon layer 124, The air gap layer 112, the storage layer 106, and the barrier layer 110.
請參考第3圖至第10圖，第3圖至第9圖為本發明垂直式記憶體製作方法之第一實施例的製程示意圖，而第10圖為本發明垂直式記憶體製作方法之第一實施例的步驟流程圖。首先如第3圖所示，提供基底100，在基底100上形成由多個絕緣層120與多個第一犧牲層136所交替堆疊的一多層結構30。舉例而言，多層結構30可藉由沉積製程分別輪流地沉積絕緣層120與第一犧牲層136所形成，其中最下層與最上層的絕緣層120較厚於此兩者之間的絕緣層120。本實施例的第一犧牲層136為氮化矽，但不以此為限。然後，於多層結構30中形成多個第一通孔138(第3圖僅繪示兩個第一通孔138作為示意)，其中第一通孔138沿垂直於基底100表面的第一方向D1延伸。舉例而言，第一通孔138可藉由微影暨蝕刻製程所形成。接著，如第4圖所示，於第一通孔138的底部形成第一多晶矽層122，且第一多晶矽層122填滿第一通孔138的底部。舉例而言，第一多晶矽層122可藉由磊晶方法形成。然後，在第一多晶矽層122上之第一通孔138的側壁表面形成沿第一方向D1延伸之第二犧牲層140、儲存層106、穿隧層108與通道層102。在本實施例中，係以第二犧牲層140、儲存層106、穿隧層108與通道層102之順序依序形成於第一通孔138的側壁表面上，使得儲存層106設置於第一通孔138的側壁表面與通道層102之間，穿隧層108設置於儲存層106與通道層102之間，而第二犧牲層140設置於儲存層106與第一通孔138的側壁表面之間。另外，本實施例的第二犧牲層140的材料包括氧化物例如氧化矽，但不以此為限。在形成完通道層102後，第一通孔138的中心部分未被填滿，而本實施例在形成完通道層102後形成氧化物柱118以填滿第一通孔138。此時，第二犧牲層140、儲存層106、穿隧層108、通道層102與氧化物柱118可構成一柱狀結構20b。第二犧牲層140、儲存層106、穿隧層108、通道層102與氧化物柱118可例如係以沉積製程分別形成，但不以此為限。Please refer to FIG. 3 to FIG. 10. FIGS. 3 to 9 are process schematic diagrams of the first embodiment of the vertical memory fabrication method of the present invention, and FIG. 10 is the first diagram of the vertical memory fabrication method of the present invention. Step flowchart of an embodiment. First, as shown in FIG. 3, a substrate 100 is provided, and a multilayer structure 30 is alternately stacked on the substrate 100 by a plurality of insulating layers 120 and a plurality of first sacrificial layers 136. For example, the multilayer structure 30 may be formed by depositing an insulating layer 120 and a first sacrificial layer 136 in turn by a deposition process, in which the lowermost layer and the uppermost insulating layer 120 are thicker than the insulating layer 120 therebetween. . The first sacrificial layer 136 in this embodiment is silicon nitride, but is not limited thereto. Then, a plurality of first through holes 138 are formed in the multilayer structure 30 (only two first through holes 138 are shown in FIG. 3 as a schematic diagram), where the first through holes 138 are along a first direction D1 perpendicular to the surface of the substrate 100. extend. For example, the first through hole 138 may be formed by a photolithography and etching process. Next, as shown in FIG. 4, a first polycrystalline silicon layer 122 is formed on the bottom of the first through hole 138, and the first polycrystalline silicon layer 122 fills the bottom of the first through hole 138. For example, the first polycrystalline silicon layer 122 may be formed by an epitaxial method. Then, a second sacrificial layer 140, a storage layer 106, a tunneling layer 108, and a channel layer 102 are formed on the sidewall surface of the first through-hole 138 on the first polycrystalline silicon layer 122 and extend along the first direction D1. In this embodiment, the second sacrificial layer 140, the storage layer 106, the tunneling layer 108, and the channel layer 102 are sequentially formed on the sidewall surface of the first through hole 138 in this order, so that the storage layer 106 is disposed on the first Between the sidewall surface of the through hole 138 and the channel layer 102, a tunneling layer 108 is disposed between the storage layer 106 and the channel layer 102, and a second sacrificial layer 140 is provided between the storage layer 106 and the sidewall surface of the first through hole 138 between. In addition, the material of the second sacrificial layer 140 in this embodiment includes an oxide such as silicon oxide, but is not limited thereto. After the channel layer 102 is formed, the center portion of the first through hole 138 is not filled. In this embodiment, after the channel layer 102 is formed, an oxide pillar 118 is formed to fill the first through hole 138. At this time, the second sacrificial layer 140, the storage layer 106, the tunneling layer 108, the channel layer 102, and the oxide pillar 118 may form a pillar structure 20b. The second sacrificial layer 140, the storage layer 106, the tunneling layer 108, the channel layer 102, and the oxide pillar 118 may be separately formed by a deposition process, but not limited thereto.
接著，如第5圖所示，先移除第一通孔138頂端的部分第二犧牲層140、部分儲存層106、部分穿隧層108、部分通道層102與部分氧化物柱118及其鄰近之一部分的絕緣層120以形成一開口，再於開口中形成第二多晶矽層124。舉例而言，開口可藉由微影暨蝕刻製程所形成，而第二多晶矽層124可藉由磊晶方法形成。然後，如第6圖所示，於多層結構30中形成沿著第一方向D1延伸的至少一第二通孔142，鄰近於第一通孔138設置，亦可視為鄰近於柱狀結構20b設置，本實施例的第二通孔142舉例可位於相鄰第一通孔138之間。第二通孔142貫穿多層結構30，以暴露出多層結構30中各絕緣層120及各第一犧牲層136的側面。接著，由第二通孔142移除第一犧牲層136以形成多個凹槽144。舉例而言，可藉由（但不限於）濕蝕刻製程並將蝕刻液通入第二通孔142中，使蝕刻液與被暴露的第一犧牲層136接觸並產生反應。另外，可使用對於絕緣層120及第一犧牲層136具有高選擇蝕刻比的蝕刻液，以於移除第一犧牲層136的同時並保留絕緣層120。需注意的是，移除第一犧牲層136或形成凹槽144的方法不限於濕蝕刻製程，可使用任何適合的其他製程來完成此步驟。然後，透過對應第一多晶矽層122的凹槽144於第一多晶矽層122的表面形成絕緣部分128，其形成方式舉例包括氧化製程，但不以此為限。Next, as shown in FIG. 5, a part of the second sacrificial layer 140, a part of the storage layer 106, a part of the tunneling layer 108, a part of the channel layer 102 and a part of the oxide pillar 118 and the vicinity of the top of the first via 138 are removed first. A portion of the insulating layer 120 forms an opening, and a second polycrystalline silicon layer 124 is formed in the opening. For example, the opening may be formed by a lithography and etching process, and the second polycrystalline silicon layer 124 may be formed by an epitaxial method. Then, as shown in FIG. 6, at least one second through-hole 142 extending along the first direction D1 is formed in the multilayer structure 30, and is disposed adjacent to the first through-hole 138, and can also be regarded as disposed adjacent to the columnar structure 20 b. For example, the second through hole 142 in this embodiment may be located between adjacent first through holes 138. The second through hole 142 penetrates the multilayer structure 30 to expose the sides of the insulating layers 120 and the first sacrificial layers 136 in the multilayer structure 30. Then, the first sacrificial layer 136 is removed from the second through hole 142 to form a plurality of grooves 144. For example, the wet etching process and the etching solution can be passed into the second through hole 142 to make the etching solution contact the exposed first sacrificial layer 136 and generate a reaction. In addition, an etching solution having a high selective etching ratio for the insulating layer 120 and the first sacrificial layer 136 may be used to remove the first sacrificial layer 136 while retaining the insulating layer 120. It should be noted that the method of removing the first sacrificial layer 136 or forming the groove 144 is not limited to the wet etching process, and any suitable other process may be used to complete this step. Then, an insulating portion 128 is formed on the surface of the first polycrystalline silicon layer 122 through the groove 144 corresponding to the first polycrystalline silicon layer 122. Examples of the formation method include an oxidation process, but not limited thereto.
接著，如第7圖所示，於各凹槽144中分別共形地（conformally）形成一阻擋層110，其中阻擋層110並未將凹槽144完全填滿。然後，於尚未填滿的凹槽144內分別形成導電材料並填滿各凹槽114，作為閘極104。此時，閘極104係沿著平行於基底100表面的第二方向D2設置於通道層102之一側，阻擋層110設置於閘極104與儲存層106之間，且阻擋層110覆蓋閘極104之頂面、底面及鄰近通道層102的側面。舉例而言，阻擋層110與閘極104可分別以沉積製程依序形成，但不以此為限。在本實施例中，最靠近基底100的閘極104及阻擋層110係分別作為第一選擇閘極126與介電部分130，而最遠離基底100的閘極104係作為第二選擇閘極132。Next, as shown in FIG. 7, a blocking layer 110 is conformally formed in each of the grooves 144. The blocking layer 110 does not completely fill the grooves 144. Then, conductive materials are formed in the unfilled grooves 144 and the grooves 114 are filled as the gate electrodes 104. At this time, the gate electrode 104 is disposed on one side of the channel layer 102 along the second direction D2 parallel to the surface of the substrate 100, the barrier layer 110 is disposed between the gate electrode 104 and the storage layer 106, and the barrier layer 110 covers the gate electrode The top and bottom surfaces of 104 and the sides adjacent to the channel layer 102. For example, the barrier layer 110 and the gate electrode 104 may be sequentially formed by a deposition process, but not limited thereto. In this embodiment, the gate 104 and the barrier layer 110 closest to the substrate 100 are used as the first selection gate 126 and the dielectric portion 130, and the gate 104 farthest from the substrate 100 is used as the second selection gate 132. .
接著，如第8圖所示，於第二通孔142中形成沿第一方向D1延伸之隔離結構116與源極線114。舉例而言，可先於第二通孔142的側壁表面形成隔離結構116，其中隔離結構116並未將第二通孔142完全填滿。然後，再於第二通孔142中形成源極線114並填滿第二通孔142，使得隔離結構116位於閘極104與源極線114之間。隔離結構116與源極線114可分別藉由沉積製程依序形成，但不以此為限。然後，移除多層結構30中位於最上層的絕緣層120以及隔離結構116與源極線114的頂部，以暴露出一部分的第二犧牲層140及第二多晶矽層124。此步驟可藉由蝕刻製程所進行，但不以此為限。Next, as shown in FIG. 8, an isolation structure 116 and a source line 114 extending in the first direction D1 are formed in the second through hole 142. For example, an isolation structure 116 may be formed before the sidewall surface of the second through hole 142, wherein the isolation structure 116 does not completely fill the second through hole 142. Then, a source line 114 is formed in the second through hole 142 and the second through hole 142 is filled, so that the isolation structure 116 is located between the gate electrode 104 and the source line 114. The isolation structures 116 and the source lines 114 may be sequentially formed by a deposition process, but are not limited thereto. Then, the top layer of the insulating layer 120 and the isolation structure 116 and the source line 114 in the multilayer structure 30 are removed to expose a part of the second sacrificial layer 140 and the second polycrystalline silicon layer 124. This step can be performed by an etching process, but is not limited thereto.
接著，如第9圖所示，移除第二犧牲層140以形成沿第一方向D1延伸之空氣間隙層112。由於一部分位於頂部的第二犧牲層140已被暴露，因此上述移除步驟可包括蝕刻製程，且蝕刻劑能夠與第二犧牲層140接觸產生反應，進而沿著第一方向D1將整個第二犧牲層140移除。此時，空氣間隙層112、儲存層106、穿隧層108、通道層102與氧化物柱118可構成柱狀結構20a。然後，於第一通孔138(亦即第9圖的柱狀結構20a)、多層結構30、隔離結構116與源極線114上全面形成一覆蓋層134，其中覆蓋層134封閉空氣間隙層112，藉此形成如第1圖所示的垂直式記憶體1。Next, as shown in FIG. 9, the second sacrificial layer 140 is removed to form an air gap layer 112 extending in the first direction D1. Since a part of the second sacrificial layer 140 on the top has been exposed, the above removal step may include an etching process, and the etchant can be in contact with the second sacrificial layer 140 to react, and then the entire second sacrificial layer is sacrificed along the first direction D1. The layer 140 is removed. At this time, the air gap layer 112, the storage layer 106, the tunneling layer 108, the channel layer 102, and the oxide pillar 118 may form a columnar structure 20a. Then, a covering layer 134 is formed on the first through hole 138 (that is, the columnar structure 20 a in FIG. 9), the multilayer structure 30, the isolation structure 116, and the source line 114. The covering layer 134 closes the air gap layer 112. Thus, the vertical memory 1 shown in FIG. 1 is formed.
綜上所述，本發明垂直式記憶體1的製作方法主要包括第10圖所示之步驟：In summary, the method for manufacturing the vertical memory 1 of the present invention mainly includes the steps shown in FIG. 10:
步驟S10：提供一基底，在基底上形成由多個絕緣層與多個第一犧牲層所交替堆疊的一多層結構；Step S10: providing a substrate on which a multilayer structure alternately stacked by a plurality of insulating layers and a plurality of first sacrificial layers is formed;
步驟S12：於多層結構中形成一第一通孔，其中第一通孔沿垂直於基底表面的一第一方向延伸；Step S12: forming a first through hole in the multilayer structure, wherein the first through hole extends along a first direction perpendicular to the surface of the substrate;
步驟S14：在第一通孔的側壁表面形成沿第一方向延伸之一第二犧牲層、一儲存層、一穿隧層與一通道層，其中儲存層設置於第一通孔的側壁表面與通道層之間，穿隧層設置於儲存層與通道層之間；Step S14: forming a second sacrificial layer, a storage layer, a tunneling layer, and a channel layer extending along the first direction on the sidewall surface of the first through hole, wherein the storage layer is disposed on the sidewall surface of the first through hole and Between the channel layers, a tunneling layer is provided between the storage layer and the channel layer;
步驟S16：於多層結構中形成一第二通孔，鄰近於第一通孔設置，並由第二通孔移除第一犧牲層，以形成多個凹槽；Step S16: forming a second through hole in the multilayer structure, disposed adjacent to the first through hole, and removing the first sacrificial layer from the second through hole to form a plurality of grooves;
步驟S18：於凹槽中分別共形地形成一個阻擋層，並於凹槽中分別形成一閘極填滿各凹槽，其中閘極沿著平行於基底表面的一第二方向設置於通道層之一側，阻擋層設置於閘極與儲存層之間，且阻擋層覆蓋閘極之一頂面、一底面及一側面；以及Step S18: Conformally forming a barrier layer in the groove, and forming a gate in the groove to fill each groove, wherein the gate is arranged on the channel layer along a second direction parallel to the surface of the substrate. On one side, the barrier layer is disposed between the gate electrode and the storage layer, and the barrier layer covers one of the top surface, one bottom surface, and one side surface of the gate electrode; and
步驟S20：移除第二犧牲層，以形成沿第一方向延伸之一空氣間隙層。Step S20: removing the second sacrificial layer to form an air gap layer extending in the first direction.
本發明之垂直式記憶體及其製作方法並不以上述實施例為限。下文將繼續揭示本發明之其它實施例，然為了簡化說明並突顯各實施例之間的差異，下文中使用相同標號標注相同元件，並不再對重覆部分作贅述。The vertical memory of the present invention and the manufacturing method thereof are not limited to the above embodiments. The following will continue to disclose other embodiments of the present invention, but in order to simplify the description and highlight the differences between the embodiments, the same elements are labeled with the same reference numerals in the following, and repeated details will not be repeated.
請參考第11圖與第12圖，第11圖為本發明垂直式記憶體之第二實施例的剖面示意圖，而第12圖為沿第11圖中切線B-B’的俯視圖。如第11圖所示，本實施例與第一實施例不同的地方在於，垂直式記憶體2之空氣間隙層112係設置於儲存層106與穿隧層108之間。因此，如第12圖所示，本實施例之通道層102、穿隧層108、空氣間隙層112及儲存層106係以氧化物柱118為中心，沿第二方向D2（或平行於基底100表面的方向）依序地由內往外環狀包圍氧化物柱118以構成柱狀結構20c。此外，如第11圖所示，空氣間隙層112及儲存層106的頂面係與記憶體串列10的頂面共平面，且鄰近第二多晶矽層124之穿隧層108的一部分係突出於空氣間隙層112、儲存層106與記憶體串列10，並沒有被空氣間隙層112、儲存層106與記憶體串列10包覆。一般而言，習知的垂直式記憶體於抹除的階段時，會沿通道層至儲存層的方向將電洞注入至儲存層，以提升抹除儲存層中電荷的效率。然而，由於電洞必須穿透穿隧層才能移動至儲存層，因此此舉將破壞穿隧層的結構，進而使得儲存層中的電子從穿隧層漏出的機率增加，反而使得垂直式記憶體之電荷保持性不佳。相對的，由於本實施例的垂直式記憶體2於儲存層106與穿隧層108之間具有空氣間隙層112，使得電子從儲存層106移動至通道層102的過程中受到空氣間隙層112產生的高能障所阻擋，減少電子從儲存層106往通道層102漏出的機率，進而提升記憶單元101與垂直式記憶體2的電荷保持性。Please refer to FIG. 11 and FIG. 12. FIG. 11 is a schematic cross-sectional view of a second embodiment of the vertical memory of the present invention, and FIG. 12 is a top view taken along a tangent line B-B 'in FIG. As shown in FIG. 11, this embodiment is different from the first embodiment in that the air gap layer 112 of the vertical memory 2 is disposed between the storage layer 106 and the tunneling layer 108. Therefore, as shown in FIG. 12, the channel layer 102, the tunneling layer 108, the air gap layer 112, and the storage layer 106 in this embodiment are centered on the oxide pillar 118 along the second direction D2 (or parallel to the substrate 100). The direction of the surface) sequentially surrounds the oxide pillars 118 from the inside to the outside to form a columnar structure 20c. In addition, as shown in FIG. 11, the top surfaces of the air gap layer 112 and the storage layer 106 are coplanar with the top surface of the memory string 10, and a part of the tunneling layer 108 adjacent to the second polycrystalline silicon layer 124 Protruding from the air gap layer 112, the storage layer 106, and the memory series 10 are not covered by the air gap layer 112, the storage layer 106, and the memory series 10. Generally speaking, during the erasing phase of the conventional vertical memory, holes are injected into the storage layer in the direction of the channel layer to the storage layer to improve the efficiency of erasing the charges in the storage layer. However, since the hole must penetrate the tunneling layer to move to the storage layer, this will destroy the structure of the tunneling layer, which will increase the probability of the electrons in the storage layer leaking from the tunneling layer, instead making the vertical memory The charge retention is poor. In contrast, since the vertical memory 2 of this embodiment has an air gap layer 112 between the storage layer 106 and the tunneling layer 108, electrons are generated by the air gap layer 112 during the process of moving electrons from the storage layer 106 to the channel layer 102. The high energy barriers reduce the probability of electrons leaking from the storage layer 106 to the channel layer 102, thereby improving the charge retention of the memory unit 101 and the vertical memory 2.
請參考第13圖與第14圖，其為本發明垂直式記憶體製作方法之第二實施例的製程示意圖。在第二實施例中，第13圖係接續第3圖的製程。如第13圖所示，本實施例與第一實施例不同的地方在於，本實施例係以儲存層106、第二犧牲層140、穿隧層108與通道層102之順序依序形成於第一通孔138的側壁表面上，最後於第一通孔138的中心形成氧化物柱118以填滿第一通孔138，而形成柱狀結構20d。本實施例在形成第13圖所示的結構後，至形成閘極104及阻擋層110之間的步驟皆類似於第一實施例，並可參考第5圖至第7圖，在此不再贅述。此外，本實施例與第一實施例另一不同的地方在於，在移除多層結構30中位於最上層的絕緣層120以及隔離結構116與源極線114的頂部之後，一部分的儲存層106係被暴露的。接著，如第14圖所示，藉由蝕刻製程移除被暴露的部分儲存層106，使得原先被該部分儲存層106包覆的第二犧牲層140於此時暴露出來，此移除過程並不以蝕刻製程為限。在此之後的製程與第一實施例相似，可參考第9圖之相關敘述，其中包括藉由移除第二犧牲層140而於儲存層106與穿遂層108之間形成空氣間隙層112，以得到第11圖所示的垂直記憶體1之結構，不再贅述。Please refer to FIG. 13 and FIG. 14, which are process schematic diagrams of a second embodiment of a method for fabricating a vertical memory according to the present invention. In the second embodiment, FIG. 13 is a process following FIG. 3. As shown in FIG. 13, this embodiment is different from the first embodiment in that this embodiment is sequentially formed in the order of the storage layer 106, the second sacrificial layer 140, the tunneling layer 108, and the channel layer 102. On the sidewall surface of a through-hole 138, an oxide pillar 118 is finally formed at the center of the first through-hole 138 to fill the first through-hole 138 to form a columnar structure 20d. After the structure shown in FIG. 13 is formed in this embodiment, the steps between the formation of the gate electrode 104 and the barrier layer 110 are similar to those of the first embodiment, and reference may be made to FIGS. 5 to 7, which will not be repeated here. To repeat. In addition, this embodiment is different from the first embodiment in that a part of the storage layer 106 is removed after the tops of the insulation layer 120 and the isolation structure 116 and the source line 114 in the multilayer structure 30 are removed. Exposed. Then, as shown in FIG. 14, an exposed part of the storage layer 106 is removed by an etching process, so that the second sacrificial layer 140 originally covered by the part of the storage layer 106 is exposed at this time. Not limited to the etching process. The manufacturing process thereafter is similar to the first embodiment, and reference may be made to the related description in FIG. 9, which includes forming an air gap layer 112 between the storage layer 106 and the tunneling layer 108 by removing the second sacrificial layer 140. The structure of the vertical memory 1 shown in FIG. 11 is obtained, and details are not described again.
綜上所述，本發明垂直式記憶體在儲存層與阻擋層之間或在儲存層與穿隧層之間設置空氣間隙層。在空氣間隙層設置於儲存層與阻擋層之間的結構中，當垂直式記憶體處於抹除階段時，電子會受到空氣間隙層產生的高能障所阻擋，減少電子從閘極回灌至儲存層發生的機率，進而提升垂直式記憶體的抹除效率。在空氣間隙層設置於儲存層與穿隧層之間的結構中，電子從儲存層移動至通道層的過程中會受到空氣間隙層產生的高能障所阻擋，能減少電子從儲存層往通道層漏出的機率，進而提升垂直式記憶體的電荷保持性。 以上所述僅為本發明之較佳實施例，凡依本發明申請專利範圍所做之均等變化與修飾，皆應屬本發明之涵蓋範圍。In summary, the vertical memory of the present invention provides an air gap layer between the storage layer and the barrier layer or between the storage layer and the tunneling layer. In the structure where the air gap layer is disposed between the storage layer and the barrier layer, when the vertical memory is in the erasing stage, electrons will be blocked by the high energy barrier generated by the air gap layer, reducing the backflow of electrons from the gate to the storage Probability of layer occurrence, which in turn improves the erasing efficiency of vertical memory. In the structure in which the air gap layer is disposed between the storage layer and the tunneling layer, the electrons from the storage layer to the channel layer are blocked by the high energy barrier generated by the air gap layer, which can reduce the electrons from the storage layer to the channel layer. Leakage probability, which improves the charge retention of the vertical memory. The above description is only a preferred embodiment of the present invention, and all equivalent changes and modifications made in accordance with the scope of patent application of the present invention shall fall within the scope of the present invention.
1、2‧‧‧垂直式記憶體1, 2‧‧‧ vertical memory
10‧‧‧記憶體串列10‧‧‧Memory Serial
20a、20b、20c、20d‧‧‧柱狀結構20a, 20b, 20c, 20d
30‧‧‧多層結構30‧‧‧multi-layer structure
100‧‧‧基底100‧‧‧ substrate
101‧‧‧記憶單元101‧‧‧memory unit
102‧‧‧通道層102‧‧‧Channel layer
104‧‧‧閘極104‧‧‧Gate
106‧‧‧儲存層106‧‧‧Storage layer
108‧‧‧穿隧層108‧‧‧ tunneling layer
110‧‧‧阻擋層110‧‧‧ barrier
112‧‧‧空氣間隙層112‧‧‧Air gap layer
114‧‧‧源極線114‧‧‧source line
116‧‧‧隔離結構116‧‧‧Isolation structure
118‧‧‧氧化物柱118‧‧‧oxide column
120‧‧‧絕緣層120‧‧‧ Insulation
122‧‧‧第一多晶矽層122‧‧‧The first polycrystalline silicon layer
124‧‧‧第二多晶矽層124‧‧‧Second polycrystalline silicon layer
126‧‧‧第一選擇閘極126‧‧‧First choice gate
128‧‧‧絕緣部分128‧‧‧ Insulation
130‧‧‧介電部分130‧‧‧ Dielectric section
132‧‧‧第二選擇閘極132‧‧‧Second choice gate
134‧‧‧覆蓋層134‧‧‧ Overlay
136‧‧‧第一犧牲層136‧‧‧First sacrificial layer
138‧‧‧第一通孔138‧‧‧first through hole
140‧‧‧第二犧牲層140‧‧‧Second sacrifice layer
142‧‧‧第二通孔142‧‧‧Second through hole
144‧‧‧凹槽144‧‧‧Groove
D1‧‧‧第一方向D1‧‧‧ first direction
D2‧‧‧第二方向D2‧‧‧ Second direction
S10~S20‧‧‧步驟S10 ~ S20‧‧‧‧steps
第1圖為本發明垂直式記憶體之第一實施例的剖面示意圖。 第2圖為沿第1圖中切線A-A’的俯視圖。 第3圖至第9圖為本發明垂直式記憶體製作方法之第一實施例的製程示意圖。 第10圖為本發明垂直式記憶體製作方法之第一實施例的步驟流程圖。 第11圖為本發明垂直式記憶體之第二實施例的剖面示意圖。 第12圖為沿第11圖中切線B-B’的俯視圖。 第13圖至第14圖為本發明垂直式記憶體製作方法之第二實施例的製程示意圖。FIG. 1 is a schematic cross-sectional view of a first embodiment of a vertical memory according to the present invention. Fig. 2 is a plan view taken along a tangent line A-A 'in Fig. 1. FIG. 3 to FIG. 9 are process schematic diagrams of the first embodiment of the method for fabricating a vertical memory according to the present invention. FIG. 10 is a flowchart of steps in a first embodiment of a method for manufacturing a vertical memory according to the present invention. FIG. 11 is a schematic cross-sectional view of a second embodiment of the vertical memory of the present invention. Fig. 12 is a plan view taken along a tangent line B-B 'in Fig. 11. 13 to 14 are schematic diagrams of a manufacturing process of a second embodiment of a method for manufacturing a vertical memory according to the present invention.
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| TWI701811B (en) * | 2019-05-15 | 2020-08-11 | 力晶積成電子製造股份有限公司 | Non-volatile memory structure |
| TWI758031B (en) * | 2020-10-19 | 2022-03-11 | 大陸商長江存儲科技有限責任公司 | Three-dimensional memory devices with channel structures having plum blossom shape |
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| CN110600422B (en) * | 2019-08-28 | 2024-04-05 | 长江存储科技有限责任公司 | 3D NAND flash memory and preparation method thereof |
| CN112885842B (en) * | 2021-03-22 | 2023-04-07 | 长江存储科技有限责任公司 | Three-dimensional memory and preparation method thereof |
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| US8455940B2 (en) * | 2010-05-24 | 2013-06-04 | Samsung Electronics Co., Ltd. | Nonvolatile memory device, method of manufacturing the nonvolatile memory device, and memory module and system including the nonvolatile memory device |
| KR20120007838A (en) * | 2010-07-15 | 2012-01-25 | 삼성전자주식회사 | Vertical non-volatile memory device and methods of fabricating the same |
| DE102012109612A1 (en) * | 2011-10-13 | 2013-04-18 | Samsung Electronics Co., Ltd. | Method for programming non-volatile memory e.g. programmable ROM, involves changing threshold voltage of first memory cell transistor via first peripheral |
| KR20130072911A (en) * | 2011-12-22 | 2013-07-02 | 에스케이하이닉스 주식회사 | Nonvolatile memory device and method for fabricating the same |
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| US9177966B1 (en) * | 2014-07-08 | 2015-11-03 | Sandisk Technologies Inc. | Three dimensional NAND devices with air gap or low-k core |
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| TWI758031B (en) * | 2020-10-19 | 2022-03-11 | 大陸商長江存儲科技有限責任公司 | Three-dimensional memory devices with channel structures having plum blossom shape |
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