TW201900544A - 半導體器件 - Google Patents

半導體器件 Download PDF

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TW201900544A
TW201900544A TW106121847A TW106121847A TW201900544A TW 201900544 A TW201900544 A TW 201900544A TW 106121847 A TW106121847 A TW 106121847A TW 106121847 A TW106121847 A TW 106121847A TW 201900544 A TW201900544 A TW 201900544A
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type semiconductor
semiconductor layer
nano
conductive film
carbon tube
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TWI667191B (zh
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張金
魏洋
姜開利
范守善
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鴻海精密工業股份有限公司
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Abstract

一半導體器件，該半導體器件包括：一柵極及一絕緣層，所述絕緣層設置於柵極的表面；一第一奈米碳管及一第二奈米碳管，所述第一奈米碳管和第二奈米碳管間隔設置於絕緣層的表面；一P型半導體層及一N型半導體層，所述P型半導體層覆蓋第一奈米碳管，並設置於絕緣層的表面，所述N型半導體層覆蓋第二奈米碳管，並設置於絕緣層的表面；一導電膜，所述導電膜設置於P型半導體層和N型半導體層的表面，其中，P型半導體層位於導電膜和第一奈米碳管之間，N型半導體層位於導電膜和第二奈米碳管之間。

Description

半導體器件
本發明涉及一種半導體器件。
近年來，范德華異質結是最近兩年的新興研究領域。范德華異質結通過將具有不同性質（電學以及光學等）的二維材料堆到一起，可以實現對組合而成的“新”材料的性質進行人工調控；由於層間弱的范德華作用力，相鄰的層間不再受晶格必須相匹配的限制；並且，由於沒有成分過渡，所形成的異質結具有原子級陡峭的載流子（勢場）梯度；由於以過渡金屬雙硫族化物為代表的非石墨烯二維層狀材料通常可以形成二類能帶關係，因此以它們為基礎搭建的異質結具有非常強的載流子分離能力；此外，由於超薄的厚度以及特殊的二維結構，使其具有強的柵極回應能力，以及與傳統微電子加工工藝和柔性基底相相容的特性。
本發明提供了新型的含有範德華異質結的半導體器件。
一半導體器件，該半導體器件包括：一柵極，該柵極為一層狀結構；一絕緣層，所述絕緣層設置於柵極的表面；一第一奈米碳管及一第二奈米碳管，所述第一奈米碳管和第二奈米碳管間隔設置於絕緣層的表面；一P型半導體層及一N型半導體層，所述P型半導體層覆蓋第一奈米碳管，並設置於絕緣層的表面，所述N型半導體層覆蓋第二奈米碳管，並設置於絕緣層的表面；一導電膜，所述導電膜設置於P型半導體層和N型半導體層的表面，其中，P型半導體層位於導電膜和第一奈米碳管之間，N型半導體層位於導電膜和第二奈米碳管之間；一第一電極，該第一電極與第一奈米碳管電連接；一第二電極，該第二電極與第二奈米碳管電連接；以及一第三電極，該第三電極與導電膜電連接。
相較於先前技術，本發明提供了一種新型的半導體器件，該半導體器件在未來的奈米電子學和奈米光電子學領域具有巨大的應用潛力。
以下將結合附圖及具體實施例對本發明的半導體器件作進一步的詳細說明。
請參閱圖1及圖2，本發明第一實施例提供一種半導體器件100。該半導體器件100包括：一柵極102、一絕緣層104，一第一奈米碳管106、一第二奈米碳管108、一P型半導體層110、一N型半導體層112、一導電膜114、一第一電極116、一第二電極118及一第三電極120。所述柵極102為一層狀結構。所述絕緣層104設置於柵極102的表面。所述第一奈米碳管106和第二奈米碳管108間隔設置於絕緣層104的表面。所述P型半導體層110覆蓋第一奈米碳管106，並設置於絕緣層104的表面。所述N型半導體層112覆蓋第二奈米碳管108，並設置於絕緣層104的表面。所述導電膜114設置於P型半導體層110和N型半導體層112的表面。所述P型半導體層110位於導電膜114和第一奈米碳管106之間。所述N型半導體層112位於導電膜114和第二奈米碳管108之間。所述第一電極116與第一奈米碳管106電連接。所述第二電極118與第二奈米碳管108電連接。所述第三電極120與導電膜114電連接。
所述柵極102由導電材料組成，該導電材料可選擇為金屬、ITO、ATO、導電銀膠、導電聚合物以及導電奈米碳管等。該金屬材料可以為鋁、銅、鎢、鉬、金、鈦、鈀或任意組合的合金。本實施例中，所述柵極102為一層狀結構，絕緣層104設置於柵極102的表面，所述第一奈米碳管106、第二奈米碳管108、P型半導體層110、N型半導體層112、導電膜114、第一電極116及第二電極118均設置於絕緣層104的表面，並由柵極102和絕緣層104支撐。
所述絕緣層104的材料為絕緣材料，其厚度可以為1奈米～100微米。所述絕緣層104使第一奈米碳管106、第二奈米碳管108、P型半導體層110以及N型半導體層112與所述柵極102間隔絕緣設置。本實施例中，絕緣層104的材料為氧化矽。
所述第一奈米碳管106或第二奈米碳管108為金屬型的奈米碳管。第一奈米碳管106或第二奈米碳管108的直徑不限，可以為0.5奈米~150奈米，在某些實施例中，第一奈米碳管106或第二奈米碳管108的直徑可以為1奈米~10奈米。優選地，第一奈米碳管106和第二奈米碳管108均為單壁奈米碳管，其直徑為1奈米~5奈米。本實施例中，第一奈米碳管106和第二奈米碳管108均為金屬型單壁奈米碳管，其直徑為1奈米。本發明中，所述第一奈米碳管106和第二奈米碳管108直接設置在絕緣層104表面，第一奈米碳管106和第二奈米碳管108靠近柵極102，導電膜114遠離柵極102，導電膜114不會在P型半導體層110和柵極102之間或者N型半導體層112與柵極102之間產生屏蔽效應，影像半導體器件100的實際應用。第一奈米碳管106和第二奈米碳管108並列設置於絕緣層104的表面，其之間的距離不限，可以根據實際應用進行調整。在一些實施例中，第一奈米碳管106和第二奈米碳管108之間的距離可以為1奈米～1釐米。第一奈米碳管106和第二奈米碳管108之間的角度不限，可以相互平行或者成一定角度設置，只需確保第一奈米碳管106和第二奈米碳管108之間互不接觸。
所述P型半導體層110或N型半導體層112為一二維結構的半導體層。所述二維結構即半導體層的厚度較小，半導體層的厚度為1奈米~100奈米，優選地，所述P型半導體層110或N型半導體層112的厚度為1奈米~50奈米。所述P型半導體層110或N型半導體層112可以僅包括一層半導體材料，即所述P型半導體層110或N型半導體層112為一個單層的結構。所述P型半導體層110或N型半導體層112的材料不限，可以為無機化合物半導體、元素半導體或有機半導體材料，如：砷化鎵、碳化矽、多晶矽、單晶矽或萘等。N型半導體層112的材料為N型半導體材料。P型半導體層110的材料為P型半導體材料。本實施例中，N型半導體層112的材料為硫化鉬（MoS2 ），其厚度為37奈米，P型半導體層110的材料為硒化鎢（WSe2 ），其厚度為22奈米。所述P型半導體層110和N型半導體層112間隔設置，互不接觸。所述P型半導體層110覆蓋第一奈米碳管106後直接設置在絕緣層104的表面。所述N型半導體層112覆蓋第二奈米碳管108後直接設置在絕緣層104的表面。
所述導電膜114的材料為導電材料，可以為金屬、導電聚合物或ITO。導電膜114直接沉積在P型半導體層110和N型半導體層112的遠離絕緣層104的表面，導電膜114跨過P型半導體層110和N型半導體層112。由於導電膜114 P半導體層110和N型半導體層112間隔設置，其間隔處的導電膜114可以設置於絕緣層104的表面。即導電膜114可以看成分成三部分，一部分位於P型半導體層110遠離絕緣層104的表面；一部分位於N型半導體層112遠離絕緣層104的表面；另一部分位於P型半導體層110和N型半導體層112之間，設置於絕緣層104的表面。導電膜114沉積的具體方法不限，可以為離子濺射、磁控濺射或其他鍍膜方法。所述導電膜114的厚度不限，可以為5奈米～100微米。在一些實施例中，導電膜114的厚度為5奈米～100奈米；在另一些實施例中，導電膜114的厚度為5奈米～20奈米。所述導電膜114的形狀不限，可以為長條形、線性、方形等形狀。本實施例中，所述導電膜114為長條形。
所述第一奈米碳管106、P型半導體層110和導電膜114相互層疊形成一第一多層立體結構122。由於第一奈米碳管106相對於P型半導體層110和導電膜114的尺寸較小，該第一多層立體結構122的橫截面的面積由第一奈米碳管106的直徑和長度決定。由於第一奈米碳管106為奈米材料，該第一多層立體結構122的橫截面面積也是奈米級。所述第一多層立體結構122定義一橫向截面及一豎向截面，所述橫向截面即平行於P型半導體層110的方向的截面，所述縱向截面即垂直於P型半導體層110的表面的方向的截面。所述橫向截面的面積由第一奈米碳管106的直徑和長度決定。所述縱向截面的面積由第一奈米碳管106的長度和第一多層立體結構122的厚度決定。優選地，該第一多層立體結構122的橫截面的面積為0.25nm2 ~1000nm2 。更優選地，該第一多層立體結構122的橫截面的面積為1nm2 ~100nm2 。
所述第二奈米碳管108、N型半導體層112和導電膜114相互層疊形成一第二多層立體結構124。由於第二奈米碳管108相對於N型半導體層112和導電膜114的尺寸較小，該第二多層立體結構124的橫截面的面積由第二奈米碳管108的直徑和長度決定。由於第二奈米碳管108為奈米材料，該第二多層立體結構124的橫截面面積也是奈米級。所述第二多層立體結構124定義一橫向截面及一豎向截面，所述橫向截面即平行於N型半導體層112的方向的截面，所述縱向截面即垂直於N型半導體層112的表面的方向的截面。所述橫向截面的面積由第二奈米碳管108的直徑和長度決定。所述縱向截面的面積由第二奈米碳管108的長度和第二多層立體結構124的厚度決定。優選地，該第二多層立體結構124的橫截面的面積為0.25nm2 ~1000nm2 。更優選地，該第二多層立體結構124的橫截面的面積為1nm2 ~100nm2 。
第一奈米碳管106和導電膜114與二維的P型半導體層110在第一多層立體結構122處形成范德華異質結構。在應用時，第一奈米碳管106和導電膜114與P型半導體層110之間形成肖特基結，電流可以穿過該第一多層立體結構122。由於第一奈米碳管106為奈米材料，該第一多層立體結構122的橫截面面積也是奈米級，即形成了奈米級的半導體結構。該半導體結構具有較低的能耗、奈米級的尺寸以及更高的集成度。
第二奈米碳管108和導電膜114與二維的N型半導體層112在第二多層立體結構124處形成范德華異質結構。在應用時，第二奈米碳管108和導電膜114與N型半導體層112之間形成肖特基結，電流可以穿過該第二多層立體結構124。由於第二奈米碳管108為奈米材料，該第二多層立體結構124的橫截面面積也是奈米級，即形成了奈米級的半導體結構。該半導體結構具有較低的能耗、奈米級的尺寸以及更高的集成度較高的空間解析度以及更高的完整性。
所述第一電極116、第二電極118及第三電極120均由導電材料組成，該導電材料可選擇為金屬、ITO、ATO、導電銀膠、導電聚合物以及導電奈米碳管等。該金屬材料可以為鋁、銅、鎢、鉬、金、鈦、鈀或任意組合的合金。在一些實施例中，所述第一電極116和第二電極118也可以均為一層導電薄膜，該導電薄膜的厚度為2微米～100微米。本實施例中，所述第一電極116、第二電極118為金屬Au，金屬Au的厚度為50奈米。本實施例中，所述第一電極116設置於第一奈米碳管106的一端並貼合於第一奈米碳管106的表面，即Au層設置於第一奈米碳管106表面；所述第二電極118與設置於第二奈米碳管108的一端並貼合於第二奈米碳管108的表面，即Au層設置於Ti層表面。所述第三電極120為一長條狀導電層，其設置於導電膜114的一端，沿導電膜114的一個邊設置於導電膜114的表面。所述第三電極120的材料可以與第一電極116或第二電極118相同。
本發明所提供的半導體器件100包括兩個基於奈米碳管不對稱范德華異質結構。當半導體器件100在應用時，范德華異質結構在相對的源極-漏極偏置處顯示出不對稱的輸出特性。運輸特性的多樣性主要歸因於奈米碳管費米能級易被調製和器件的不對稱接觸，同時奈米碳管電極適用於電子型或者空穴型導電。可調節器件功能以及側向器件尺寸的限制使得這種包括奈米碳管的不對稱范德華異質結構的半導體結構具有獨特性，在未來的奈米電子學和奈米光電子學領域具有巨大的潛力。請參見圖3，所述半導體器件100在用作CMOS器件時，柵極102為輸出端，第三電極120為輸出端，第一電極116和第二電極118接入電源，三條曲線分別對應第一電極116和第二電極118之間的電勢差為0.1伏、0.2伏和0.4伏時，對應的輸出曲線。從圖3可以看出，所述CMOS器件具有良好的工作性能。
所述半導體器件100在應用時，第一奈米碳管106和導電膜114可以看作設置在P型半導體層110的兩個相對表面上的電極，第二奈米碳管108和導電膜114看作N型半導體層112的兩個相對表面上的電極。當在第一奈米碳管106、第二奈米碳管114和導電膜106上施加電壓實現導通時，電流的流動路徑為從第一多層立體結構122的橫截面至第二多層立體結構124的橫截面，所述半導體器件100的有效部分為第一多層立體結構122及第二多層立體結構124。因此，所述半導體器件100的體積只需要確保包括第一多層立體結構122和第二多層立體結構124即可，因此，半導體器件100可以具有較小的尺寸，所述半導體元件100可以為一奈米級的半導體元件。
另外，本領域技術人員還可以在本發明精神內做其他變化，這些依據本發明精神所做的變化，都應包含在本發明所要求保護的範圍內。綜上所述，本發明確已符合發明專利之要件，遂依法提出專利申請。惟，以上所述者僅為本發明之較佳實施例，自不能以此限制本案之申請專利範圍。舉凡習知本案技藝之人士援依本發明之精神所作之等效修飾或變化，皆應涵蓋於以下申請專利範圍內。
100‧‧‧半導體器件
102‧‧‧柵極
104‧‧‧絕緣層
106‧‧‧第一奈米碳管
108‧‧‧第二奈米碳管
110‧‧‧P型半導體層
112‧‧‧N型半導體層
114‧‧‧導電膜
116‧‧‧第一電極
118‧‧‧第二電極
120‧‧‧第三電極
122‧‧‧第一多層立體結構
124‧‧‧第二多層立體結構
圖1為本發明實施例提供的半導體器件的立體結構示意圖。
圖2為本發明實施例提供的半導體器件的側視示意圖。
圖3為本發明實施例提供的半導體器件在用CMOS工作時的特徵曲線圖。
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Claims (10)

  1. 一種半導體器件，其包括: 一柵極，該柵極為一層狀結構； 一絕緣層，所述絕緣層設置於柵極的表面； 一第一奈米碳管及一第二奈米碳管，所述第一奈米碳管和第二奈米碳管間隔設置於絕緣層的表面； 一P型半導體層及一N型半導體層，所述P型半導體層覆蓋第一奈米碳管，並設置於絕緣層的表面，所述N型半導體層覆蓋第二奈米碳管，並設置於絕緣層的表面； 一導電膜，所述導電膜設置於P型半導體層和N型半導體層的表面，其中，P型半導體層位於導電膜和第一奈米碳管之間，N型半導體層位於導電膜和第二奈米碳管之間； 一第一電極，該第一電極與第一奈米碳管電連接； 一第二電極，該第二電極與第二奈米碳管電連接；以及 一第三電極，該第三電極與導電膜電連接。
  2. 如權利要求1所述之半導體器件，其中，所述第一奈米碳管和第二奈米碳管為金屬型奈米碳管。
  3. 如權利要求2所述之半導體器件，其中，所述第一奈米碳管和第二奈米碳管為單壁奈米碳管。
  4. 如權利要求1所述之半導體器件，其中，所述第一奈米碳管、P型半導體層及導電膜相互疊加形成一第一多層立體結構，該第一多層立體結構的橫截面的面積為0.25nm2 ~1000nm2 。
  5. 如權利要求4所述之半導體器件，其中，所述第一多層立體結構的橫截面的面積為1nm2 ~100nm2 。
  6. 如權利要求1所述之半導體器件，其中，所述第二奈米碳管、N型半導體層及導電膜相互疊加形成一第二多層立體結構，該第二多層立體結構122的橫截面的面積為0.25nm2 ~1000nm2 。
  7. 如權利要求1所述之半導體器件，其中，所述P型半導體層或N型半導體層的厚度為1奈米~100奈米。
  8. 如權利要求1所述之半導體器件，其中，所述導電膜的沉積方法包括離子濺射、磁控濺射或其它鍍膜方法。
  9. 如權利要求8所述之半導體器件，其中，所述導電膜的厚度為5奈米～100奈米。
  10. 如權利要求1所述之半導體器件，其中，所述導電膜跨過P型半導體層和N型半導體層，所述導電膜一部分位於P型半導體層遠離絕緣層的表面；一部分位於N型半導體層遠離絕緣層的表面；一部分位於P型半導體層和N型半導體層之間，設置於絕緣層的表面。
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