TW201837972A - 用以提供低介電常數間隔件之方法 - Google Patents

用以提供低介電常數間隔件之方法 Download PDF

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TW201837972A
TW201837972A TW106143448A TW106143448A TW201837972A TW 201837972 A TW201837972 A TW 201837972A TW 106143448 A TW106143448 A TW 106143448A TW 106143448 A TW106143448 A TW 106143448A TW 201837972 A TW201837972 A TW 201837972A
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斯特拉特福 Ａ 王爾德
布萊恩 特西爾
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美商蘭姆研究公司
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Abstract

提供一種形成具有間隔件之半導體元件的方法。SiCO間隔件係形成在特徵部的側面上。形成保護性覆蓋物，該保護性覆蓋物覆蓋SiCO間隔件的第一部分，其中SiCO間隔件的側壁的第二部分不受到保護性覆蓋物的覆蓋。對未由保護性覆蓋物所覆蓋之SiCO間隔件的第二部分提供一轉換製程，該轉換製程改變未由保護性覆蓋物所覆蓋之SiCO間隔件的第二部分的物理特性，其中保護性覆蓋物保護SiCO間隔件的第一部分免於轉換製程。

Description

用以提供低介電常數間隔件之方法
本揭露內容關於在半導體晶圓上形成半導體元件的方法。更具體而言，本揭露內容關於提供間隔件低介電常數。
在形成半導體元件中，側壁間隔件係在特徵部的側面上形成。該側壁間隔件可能造成寄生電容。
為實現上述內容且根據本揭露內容之目的，提供一種形成具有間隔件之半導體元件的方法。SiCO間隔件係形成在特徵部的側面上。在SiCO間隔件的第一部分之上形成保護性覆蓋物，其中SiCO間隔件的側壁的第二部分不受到保護性覆蓋物的覆蓋。對未由保護性覆蓋物所覆蓋之SiCO間隔件的第二部分提供一轉換製程，該轉換製程改變未由保護性覆蓋物所覆蓋之SiCO間隔件的第二部分的物理特性，其中保護性覆蓋物保護SiCO間隔件的第一部分免於轉換製程。
在另一實施例中，提供一種形成具有間隔件之半導體元件的方法。SiCO間隔件係形成在特徵部的側面上。在SiCO間隔件側壁的一部分及頂部之上形成保護性蓋層，其中SiCO間隔件的側壁的底部部分不受到保護性蓋層的覆蓋。對未由保護性蓋層所覆蓋之SiCO間隔件的側壁的部分提供一轉換製程，該轉換製程降低未由保護性蓋層所覆蓋之SiCO間隔件的側壁的部分的k值，其中保護性蓋層保護SiCO間隔件的側壁的受覆蓋部分免於轉換製程。
本發明的這些及其他特徵將以下列本發明的詳細敘述結合下列圖示更詳細地加以描述。
本發明現將參照如隨附圖式中所說明的幾個較佳實施例詳細描述。在以下說明中，為了提供本發明的透徹理解，說明許多具體細節。然而，顯然地，對於熟習本項技術之人士而言，本發明可不具有某些或全部這些具體細節而實施。另一方面，為了不要不必要地模糊本發明，未詳細說明眾所周知的製程步驟及/或結構。
圖1為實施例的高階流程圖。在此實施例中，矽碳氧化物(SiCO)間隔件係在特徵部的側面上形成(步驟104)。在SiCO間隔件側壁的部分及頂部之上形成保護性蓋層，其中SiCO間隔件的側壁的底部部分不受到保護性蓋層覆蓋(步驟108)。對不受到保護性蓋層覆蓋之SiCO間隔件的側壁的暴露部分提供轉換製程，該製程降低SiCO間隔件的側壁的暴露部分的k值，其中該保護性蓋層保護SiCO間隔件的側壁的受覆蓋部分免於該轉換製程(步驟112)。移除保護性蓋層(步驟116)。未由保護性蓋層覆蓋之SiCO間隔件的側壁的暴露的底部部分受到覆蓋(步驟120)。SiCO間隔件的頂部係暴露至蝕刻製程或CMP製程(步驟124)。範例
在此範例中，SiCO間隔件係在特徵部的側面上形成(步驟104)。圖2A為堆疊200示意的橫剖面圖，該堆疊200具有基板204及特徵部208。在此範例中，該特徵部具有多晶矽閘極的底部部分212與閘極蓋層的頂部部分216。SiCO間隔件220係在特徵部208的側面上形成。不同方法可用以在特徵部208的側面上形成SiCO間隔件220。在一範例中，可在特徵部208與基板之上形成保形的SiCO層。可蝕刻去除保形的SiCO層的水平表面，留下SiCO間隔件220。旋塗硬遮罩(SOH)係沉積在特徵部208與間隔件220之上。部分地蝕刻SOH 224以暴露特徵部208與間隔件220的頂部。圖2B為已經部分地蝕刻SOH 224以暴露特徵部208與間隔件220的頂部之後，堆疊的示意的橫剖面圖。
在SiCO間隔件220側壁的部分及頂部之上以及在特徵部208的頂部上形成保護性蓋層，其中SiCO間隔件的側壁的底部部分不受到保護性蓋層覆蓋(步驟108)。在此範例中，該蓋層藉由沉積保形的保護性層而形成。在範例中，藉由使5-30 sccm的CH4 或CH3 F以及100-200 sccm Ar流通處理腔室來提供蓋層形成氣體，同時將腔室壓力維持在3至5毫托之間。藉由提供100至600瓦特的RF功率至腔室來使蓋層形成氣體轉變成為電漿。提供該製程10至30秒，其造成保形的保護性層的形成。圖2C為已經形成在SiCO間隔件220的頂部及側壁的部分之上以及在特徵部208的頂部之上的保形保護性層228之後，堆疊200的示意的橫剖面圖。保形的保護性層228在SOH層224的頂部上形成。移除SOH層224以及在SOH層224的頂部上之保形的保護性層228的部分。用於移除SOH 224以及在SOH 224的頂部上之保形的保護性層228的部分之配方使50至200 sccm的N2 及H2 或者H2 及CO2 或者N2 及O2 之移除氣體流動，同時維持20至60毫托的壓力。藉由提供300至1000瓦特的RF功率至腔室來使移除氣體形成為電漿。提供該製程30至120秒，直到SOH 224及保形的保護性層228的特定部分受到移除。圖2D為在SOH層與保護性層的部分受到移除之後，堆疊200的示意的橫剖面圖。保護性層的餘留部分形成在SiCO間隔件220的頂部及側壁的部分之上以及在特徵部208的頂部之上的保護性蓋層232。SiCO間隔件220的側壁的底部部分不受到保護性蓋層232覆蓋。
對不受到保護性蓋層覆蓋之SiCO間隔件的側壁的暴露部分提供轉換製程，該製程降低SiCO間隔件的側壁的暴露部分的k值，其中該保護性蓋層保護SiCO間隔件的側壁的受覆蓋部分免於轉換製程(步驟112)。用於提供轉換製程之配方的範例使2000至4000 sccm O2 與500 sccm N2 的轉換氣體流入製程腔室內，同時維持1至2托的壓力與200℃至300℃的溫度。藉由提供3000至4000瓦特的RF功率至腔室來使轉換氣體形成為電漿。提供該製程30至60秒，直到SiCO間隔件的暴露部分藉由降低該暴露部分的k值而受到轉換。圖2E為已經提供轉換製程之後，堆疊200的示意的橫剖面圖。SiCO間隔件220的側壁的底部部分236已經受到處理以降低SiCO間隔件的介電k值。在此範例中，該k值係從4.9降低至4.4。
移除保護性蓋層(步驟116)。用於移除保護性蓋層之配方的範例使5至20 sccm CF4 或SF6 以及150 sccm He之蓋層移除氣體流動，同時維持5至30毫托的壓力。藉由提供300至1000瓦特的RF功率至腔室來使蓋層移除氣體形成為電漿。該製程時間係基於保護性蓋層的厚度。圖2F為已經移除保護性蓋層之後，堆疊200的示意的橫剖面圖。
額外步驟可在該等步驟的之前或之後或之間提供以進一步處理堆疊。例如，在SiCO間隔件形成之後且保護性蓋層形成之前，源極與汲極區域可在特徵部之間形成。在保護性蓋層受到移除之後的一製程的範例中，可沉積介電層以填充間隔件之間的空間。所沉積的介電層造成未由保護性蓋層覆蓋之SiCO間隔件的側壁的暴露的底部部分受到覆蓋(步驟120)。在一範例中，所沉積的介電層可使用可流動的次大氣壓力化學氣相沉積或原子層沉積的氧化物來沉積。圖2G為在沉積介電層240以填充側壁間隔件之間的空間之後，堆疊200的示意的橫剖面圖。SiCO間隔件的頂部係暴露至蝕刻製程或化學機械拋光(CMP)製程(步驟124)。圖2H為在SiCO間隔件的頂部經受CMP製程之後，堆疊200的示意的橫剖面圖。自對準接點可電性地連接至特徵部的頂部。
此範例利用使單一前驅物活化的自由基化學物(SPARC)膜藉由暴露至各種基於電漿的化學物來修改如此之膜的特性之能力（例如使此模對於蝕刻交互反應及稀釋的氫氟酸(dHF)濕式清潔較不耐受），同時降低介電k值。
在此範例中，保護性蓋層保護側壁間隔件的頂部部分免於轉換製程，該轉換製程降低側壁間隔件的未保護的較低部分的k值。結果是，側壁間隔件的頂部部分維持其較高的碳含量及蝕刻抗性。在此範例中，側壁的底部部分可暴露至降低k值及使側壁的底部部分較不具蝕刻抗性之轉換製程，使得側壁的底部部分比側壁的受保護部分更容易受到濕式HF或電漿蝕刻的影響。因為側壁的底部部分較不具有蝕刻抗性，所以沉積介電層以保護側壁的底部部分並以進一步形成元件。
可使用由Fremont, CA之Lam Research Corp. 所製造的Striker腔室來沉積SiCO側壁。
較佳的是，SiCO側壁間隔件初始地具有在4.7及4.9之間(含4.7及4.9)的介電常數k。轉換製程降低至少0.4的介電常數k。結果是，經轉換的SiCO側壁具有低於4.5的介電常數。結果是，介電常數降低約8%至10%。因而，寄生電容降低約8%至10%。
在其他實施例中，側壁間隔件非頂部的其他部分可受到保護以免於轉換製程，而側壁間隔件非底部的其他部分可暴露至轉換製程。如此實施例可用於處理多重積體化設計。其他實施例可使用其他轉換製程步驟以降低側壁間隔件的k值。例如，使用基於一形成氣體的灰化可代替使用基於O2 的灰化。形成氣體為具有氫及氮的氣體。如此一氣體可由N2 與H2 或NH3 或NH4 OH或如此氣體的組合形成。在其他實施例中，其他轉換製程可用以改變側壁間隔件的其他物理特性而非降低k值。
在先進鰭式場效電晶體元件中，的寄生電容是關鍵的效能瓶頸。閘極到觸點的電容是在7奈米及更小節點之總等效電容的主要支配因子。在7奈米節點上，寄生電容造成約40%的等效電容。因而，寄生電容的顯著減少將造成等效電容的顯著減少。
雖然本發明已由幾個較佳的實施例加以描述，但仍存在變更、變化、置換、及各種替代等同物，其皆落入本發明的範疇之內。亦應注意有許多替代的方式實施本發明的方法及設備。因此，下列隨附申請專利範圍意欲被解釋為包含落入本發明的真實精神及範圍內的所有這些變更、變化、置換、及各種替代等同物。
104‧‧‧方塊
108‧‧‧方塊
112‧‧‧方塊
116‧‧‧方塊
120‧‧‧方塊
124‧‧‧方塊
200‧‧‧堆疊
204‧‧‧基板
208‧‧‧特徵部
212‧‧‧底部部分
216‧‧‧頂部部分
220‧‧‧間隔件
224‧‧‧旋塗硬遮罩
228‧‧‧保護性層
232‧‧‧保護性蓋層
236‧‧‧底部部分
240‧‧‧介電層
在隨附圖式的圖中，本揭露內容係以示例為目的而不是以限制為目的加以說明，且其中類似的參考數字係關於相似的元件，且其中：
圖1為實施例的高階流程圖。
圖2A-H為根據實施例處理之堆疊的示意的橫剖面圖。

Claims (20)

  1. 一種形成具有間隔件之半導體元件的方法，該方法包含： 在特徵部的側面上形成SiCO間隔件； 形成保護性覆蓋物於該SiCO間隔件的第一部分之上，其中該SiCO間隔件的第二部分不受到該保護性覆蓋物的覆蓋；及 對不受到該保護性覆蓋物所覆蓋之該SiCO間隔件的該第二部分提供一轉換製程，該轉換製程改變不受到該保護性覆蓋物所覆蓋之該SiCO間隔件的該第二部分的物理特性，其中該保護性覆蓋物保護該SiCO間隔件的該第一部分免於該轉換製程。
  2. 如申請專利範圍第1項之形成具有間隔件之半導體元件的方法，其中該SiCO間隔件的該第一部分為該SiCO間隔件的頂部以及該SiCO間隔件的該側壁的頂部部分，且其中該SiCO間隔件的該第二部分為該SiCO間隔件的該側壁的底部部分，且其中該保護性覆蓋物形成保護性蓋層。
  3. 如申請專利範圍第2項之形成具有間隔件之半導體元件的方法，其中該轉換製程將該SiCO間隔件的該第二部分的介電常數值降低至少0.4。
  4. 如申請專利範圍第3項之形成具有間隔件之半導體元件的方法，更包含在提供該轉換製程之後移除該保護性蓋層。
  5. 如申請專利範圍第4項之形成具有間隔件之半導體元件的方法，更包含覆蓋經受該轉換製程之該SiCO間隔件的該第二部分。
  6. 如申請專利範圍第5項之形成具有間隔件之半導體元件的方法，其中覆蓋經受該轉換製程之該SiCO間隔件的該第二部分的該步驟包含使用一介電層填充該SiCO間隔件之間的空間。
  7. 如申請專利範圍第6項之形成具有間隔件之半導體元件的方法，更包含將該SiCO間隔件的該頂部暴露至蝕刻製程或化學機械拋光(CMP)製程。
  8. 如申請專利範圍第7項之形成具有間隔件之半導體元件的方法，其中該轉換製程包含將不受到該保護性蓋層所覆蓋之該SiCO間隔件的該第二部分暴露至一電漿，該電漿係由包含氧或一形成氣體之一氣體所形成。
  9. 如申請專利範圍第8項之形成具有間隔件之半導體元件的方法，其中該保護性蓋層的該形成步驟包含： 在該SiCO間隔件的該頂部暴露的情況下，在該SiCO間隔件之間提供一犧牲層； 沉積一保護性層於該SiCO間隔件的該頂部上以及於該犧牲層的頂部上；及 移除該犧牲層及移除於該犧牲層的該頂部上之該保護性層的部分。
  10. 如申請專利範圍第2項之形成具有間隔件之半導體元件的方法，其中該保護性蓋層的該形成步驟包含： 在該SiCO間隔件的該頂部暴露的情況下，在該SiCO間隔件之間提供一犧牲層； 沉積一保護性層於該SiCO間隔件的該頂部上以及於該犧牲層的頂部上；及 移除該犧牲層及移除於該犧牲層的該頂部之該保護性層的部分。
  11. 如申請專利範圍第1項之形成具有間隔件之半導體元件的方法，其中該轉換製程將該SiCO間隔件的該第二部分的介電常數值降低至少0.4。
  12. 如申請專利範圍第1項之形成具有間隔件之半導體元件的方法，更包含在提供該轉換製程之後移除該保護性覆蓋物。
  13. 如申請專利範圍第1項之形成具有間隔件之半導體元件的方法，更包含覆蓋經受該轉換製程之該SiCO間隔件的該第二部分。
  14. 如申請專利範圍第1項之形成具有間隔件之半導體元件的方法，更包含將該SiCO間隔件的該第一部分暴露至蝕刻製程或化學機械拋光(CMP)製程。
  15. 如申請專利範圍第1項之形成具有間隔件之半導體元件的方法，其中該轉換製程包含將不受到該保護性覆蓋物所覆蓋之該SiCO間隔件的該第二部分暴露至一電漿，該電漿係由包含氧或一形成氣體之一氣體所形成。
  16. 一種形成具有間隔件之半導體元件的方法，該方法包含： 在特徵部的側面上形成SiCO間隔件； 形成保護性蓋層於該SiCO間隔件的頂部及側壁的部分之上，其中該SiCO間隔件的該側壁的底部部分不受到該保護性蓋層的覆蓋；及 對不受到該保護性蓋層所覆蓋之該SiCO間隔件的該側壁的部分提供一轉換製程，該轉換製程降低不受到該保護性蓋層所覆蓋之該SiCO間隔件的該側壁的該部分的介電常數值，其中該保護性蓋層保護該SiCO間隔件的該側壁的受覆蓋部分免於該轉換製程。
  17. 如申請專利範圍第16項之形成具有間隔件之半導體元件的方法，其中該轉換製程將不受到該保護性蓋層所覆蓋之該SiCO間隔件的該側壁的該部分的介電常數值降低至少0.4。
  18. 如申請專利範圍第17項之形成具有間隔件之半導體元件的方法，更包含在提供該轉換製程之後移除該保護性蓋層。
  19. 如申請專利範圍第18項之形成具有間隔件之半導體元件的方法，更包含藉由使用一介電層填充該SiCO間隔件之間的空間來覆蓋經受該轉換製程之該SiCO間隔件的該側壁的該部分。
  20. 如申請專利範圍第19項之形成具有間隔件之半導體元件的方法，其中該轉換製程包含將不受到該保護性蓋層所覆蓋之該SiCO間隔件的該第二部分暴露至一電漿，該電漿係由包含氧或一形成氣體之一氣體所形成。
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US7115974B2 (en) * 2004-04-27 2006-10-03 Taiwan Semiconductor Manfacturing Company, Ltd. Silicon oxycarbide and silicon carbonitride based materials for MOS devices
JP2007096002A (ja) 2005-09-29 2007-04-12 Matsushita Electric Ind Co Ltd 半導体装置の製造方法および半導体装置
US7393746B2 (en) * 2006-10-12 2008-07-01 International Business Machines Corporation Post-silicide spacer removal
US7667263B2 (en) * 2007-02-07 2010-02-23 International Business Machines Corporation Semiconductor structure including doped silicon carbon liner layer and method for fabrication thereof
US8268727B2 (en) * 2009-04-20 2012-09-18 GlobalFoundries, Inc. Methods for fabricating FinFET semiconductor devices using planarized spacers
KR20100127668A (ko) * 2009-05-26 2010-12-06 주식회사 하이닉스반도체 수직형 트랜지스터의 매몰 비트 라인 형성 방법
CN102110651B (zh) 2009-12-29 2014-01-29 中国科学院微电子研究所 一种半导体器件及其制造方法
US8039386B1 (en) * 2010-03-26 2011-10-18 Freescale Semiconductor, Inc. Method for forming a through silicon via (TSV)
DE102010028462B4 (de) 2010-04-30 2015-06-11 Globalfoundries Dresden Module One Limited Liability Company & Co. Kg Verspannungsgedächtnistechnik mit geringerer Randzonenkapazität auf der Grundlage von Siliziumnitrid in MOS-Halbleiterbauelementen
US8247278B2 (en) * 2010-12-31 2012-08-21 Institute of Microelectronics, Chinese Academy of Sciences Method for manufacturing semiconductor device
US9287385B2 (en) 2011-09-01 2016-03-15 Taiwan Semiconductor Manufacturing Company, Ltd. Multi-fin device and method of making same
US9111746B2 (en) * 2012-03-22 2015-08-18 Tokyo Electron Limited Method for reducing damage to low-k gate spacer during etching
US8574978B1 (en) * 2012-04-11 2013-11-05 United Microelectronics Corp. Method for forming semiconductor device
US10832904B2 (en) * 2012-06-12 2020-11-10 Lam Research Corporation Remote plasma based deposition of oxygen doped silicon carbide films
US10297442B2 (en) * 2013-05-31 2019-05-21 Lam Research Corporation Remote plasma based deposition of graded or multi-layered silicon carbide film
KR102050779B1 (ko) * 2013-06-13 2019-12-02 삼성전자 주식회사 반도체 소자 및 이의 제조 방법
JP6218459B2 (ja) * 2013-07-02 2017-10-25 キヤノン株式会社 除振装置、除振方法、リソグラフィ装置及びデバイスの製造方法
US10158000B2 (en) * 2013-11-26 2018-12-18 Taiwan Semiconductor Manufacturing Company Limited Low-K dielectric sidewall spacer treatment
US9378975B2 (en) 2014-02-10 2016-06-28 Tokyo Electron Limited Etching method to form spacers having multiple film layers
US9171736B2 (en) 2014-03-03 2015-10-27 Tokyo Electron Limited Spacer material modification to improve K-value and etch properties
US9202751B2 (en) * 2014-04-07 2015-12-01 Globalfoundries Inc. Transistor contacts self-aligned in two dimensions
US9269792B2 (en) * 2014-06-09 2016-02-23 International Business Machines Corporation Method and structure for robust finFET replacement metal gate integration
US9478660B2 (en) * 2015-01-12 2016-10-25 Taiwan Semiconductor Manufacturing Co., Ltd. Protection layer on fin of fin field effect transistor (FinFET) device structure
US10090360B2 (en) * 2015-02-13 2018-10-02 Taiwan Semiconductor Manufacturing Co., Ltd. Method of manufacturing a semiconductor structure including a plurality of trenches
US9437694B1 (en) 2015-04-01 2016-09-06 Stmicroelectronics (Crolles 2) Sas Transistor with a low-k sidewall spacer and method of making same
KR102251061B1 (ko) * 2015-05-04 2021-05-14 삼성전자주식회사 변형된 채널층을 갖는 반도체 소자 및 그 제조 방법
US9385318B1 (en) * 2015-07-28 2016-07-05 Lam Research Corporation Method to integrate a halide-containing ALD film on sensitive materials
US9711533B2 (en) * 2015-10-16 2017-07-18 Taiwan Semiconductor Manufacturing Company, Ltd. FinFET devices having different source/drain proximities for input/output devices and non-input/output devices and the method of fabrication thereof
US9786765B2 (en) * 2016-02-16 2017-10-10 Globalfoundries Inc. FINFET having notched fins and method of forming same

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US10224414B2 (en) 2019-03-05
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KR102450406B9 (ko) 2023-12-15
KR20190088065A (ko) 2019-07-25
WO2018111627A1 (en) 2018-06-21
KR102450406B1 (ko) 2022-09-30
TWI745505B (zh) 2021-11-11
CN110073467A (zh) 2019-07-30
US20180175161A1 (en) 2018-06-21
KR20220137174A (ko) 2022-10-11

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