TW201804575A - 整合扇出型封裝 - Google Patents

整合扇出型封裝 Download PDF

Info

Publication number
TW201804575A
TW201804575A TW105132986A TW105132986A TW201804575A TW 201804575 A TW201804575 A TW 201804575A TW 105132986 A TW105132986 A TW 105132986A TW 105132986 A TW105132986 A TW 105132986A TW 201804575 A TW201804575 A TW 201804575A
Authority
TW
Taiwan
Prior art keywords
conductive
reconfiguration
layer
die
circuit structure
Prior art date
Application number
TW105132986A
Other languages
English (en)
Inventor
黃見翎
謝靜華
廖信宏
黃英叡
Original Assignee
台灣積體電路製造股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 台灣積體電路製造股份有限公司 filed Critical 台灣積體電路製造股份有限公司
Publication of TW201804575A publication Critical patent/TW201804575A/zh

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49805—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers the leads being also applied on the sidewalls or the bottom of the substrate, e.g. leadless packages for surface mounting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/486—Via connections through the substrate with or without pins
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5389—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates the chips being integrally enclosed by the interconnect and support structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/19—Manufacturing methods of high density interconnect preforms
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/20—Structure, shape, material or disposition of high density interconnect preforms
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/60—Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation
    • H01L2021/60007—Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation involving a soldering or an alloying process
    • H01L2021/60022—Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation involving a soldering or an alloying process using bump connectors, e.g. for flip chip mounting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68359—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used as a support during manufacture of interconnect decals or build up layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0237—Disposition of the redistribution layers
    • H01L2224/02379—Fan-out arrangement
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/024—Material of the insulating layers therebetween
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/1301—Shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13147—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16235—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a via metallisation of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16237—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bonding area disposed in a recess of the surface of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73253—Bump and layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1532—Connection portion the connection portion being formed on the die mounting surface of the substrate
    • H01L2924/1533—Connection portion the connection portion being formed on the die mounting surface of the substrate the connection portion being formed both on the die mounting surface of the substrate and outside the die mounting surface of the substrate
    • H01L2924/15331—Connection portion the connection portion being formed on the die mounting surface of the substrate the connection portion being formed both on the die mounting surface of the substrate and outside the die mounting surface of the substrate being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1532—Connection portion the connection portion being formed on the die mounting surface of the substrate
    • H01L2924/1533—Connection portion the connection portion being formed on the die mounting surface of the substrate the connection portion being formed both on the die mounting surface of the substrate and outside the die mounting surface of the substrate
    • H01L2924/15332—Connection portion the connection portion being formed on the die mounting surface of the substrate the connection portion being formed both on the die mounting surface of the substrate and outside the die mounting surface of the substrate being a pin array, e.g. PGA

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Electric Connection Of Electric Components To Printed Circuits (AREA)
  • Structures For Mounting Electric Components On Printed Circuit Boards (AREA)

Abstract

一種整合扇出型封裝包括晶粒、第一重配置線路結構、第二重配置線路結構、多個焊點、多個導電柱以及絕緣包封體。第一重配置線路結構與第二重配置線路結構分別形成在所述晶粒的背面與主動表面上，以將所述晶粒夾在其中。焊點形成在所述晶粒旁且與所述第一重配置線路結構連接。導電柱分別形成在所述焊點上且與所述第二重配置線路結構連接，並藉由所述焊點與所述第一重配置線路結構連接。絕緣包封體包封所述晶粒的多個側壁、所述導電柱的多個側壁以及所述焊點的多個側壁。本發明實施例亦提供一種整合扇出型封裝的製造。

Description

整合扇出型封裝
本發明實施例是有關於一種封裝，且特別是有關於一種整合扇出型封裝。
由於各種電子元件（例如電晶體、二極體、電阻器、電容器等）的積集密度不斷提升，因此，半導體工業快速成長。近年來，這種積集密度的提升，大多因為最小特徵尺寸的持續縮小，因此可以將更多的元件整合在一定的區域中。相較於以前的封裝體，這些較小的電子元件也僅需要使用較小面積的較小封裝體。半導體元件中的一些較小型式的封裝包括有四面扁平封裝（quad flat packages，QFPs）、針格陣列（pin grid array，PGA）封裝、球格陣列（ball grid array，BGA）封裝等。
目前，整合扇出型封裝由於其密度而趨於熱門。如何減少整合扇出型封裝的製造成本將成為重要的議題。
本發明實施例提供一種整合扇出型封裝包括晶粒、第一重配置線路結構、第二重配置線路結構、多個焊點、多個導電柱以及絕緣包封體。第一重配置線路結構與第二重配置線路結構分別形成在所述晶粒的背面與主動表面上，以夾住所述晶粒。焊點形成在所述晶粒旁且與所述第一重配置線路結構連接。導電柱分別形成在所述焊點上且與所述第二重配置線路結構連接，並藉由所述焊點與所述第一重配置線路結構連接。絕緣包封體包封所述晶粒的多個側壁、所述導電柱的多個側壁以及所述焊點的多個側壁。
以下揭露內容提供用於實施所提供的標的之不同特徵的許多不同實施例或實例。以下所描述的構件及位的具體實例是為了以簡化的方式傳達本揭露為目的。當然，這些僅僅為實例而非用以限制。舉例來說，於以下描述中，在第二特徵上方或在第二特徵上形成第一特徵可包括第一特徵與第二特徵形成為直接接觸的實施例，且亦可包括第一特徵與第二特徵之間可形成額外特徵使得第一特徵與第二特徵可不直接接觸的實施例。此外，本揭露在各種實例中可使用相同的元件符號及/或字母來指代相同或類似的部件。元件符號的重複使用是為了簡單及清楚起見，且並不表示所欲討論的各個實施例及/或位本身之間的關係。
另外，為了易於描述附圖中所繪示的一個構件或特徵與另一組件或特徵的關係，本文中可使用例如「在...下」、「在...下方」、「下部」、「在…上」、「在…上方」、「上部」及類似術語的空間相對術語。除了附圖中所繪示的定向之外，所述空間相對術語意欲涵蓋元件在使用或操作時的不同定向。設備可被另外定向（旋轉90度或在其他定向），而本文所用的空間相對術語相應地作出解釋。
圖1至圖15為依照本揭露一些實施例的一種整合扇出型封裝的製造過程的各種階段的剖面示意圖。
請參照圖1，提供載體C，載體C具有形成在其上的剝離層（de-bonding layer）DB與第一介電層102a，其中剝離層DB形成在載體C與第一介電層102a之間。在一些實施例中，載體C為玻璃基板，剝離層DB為形成在玻璃基板上的光熱轉換（light-to-heat conversion，LTHC）離形層，而第一介電層102a為形成在剝離層DB上的光敏聚苯噁唑（photosensitive polybenzoxazole，PBO）層。在替代實施例中，剝離層DB也可以是在光固化過程中會降低其黏性的光固化離形膜（photo-curable release film），或者是在熱固化過程中會降低其黏性的熱固化離形膜（thermal curable release film）。而第一介電層102a也可以由其他的光敏或非光敏介電材料所製成。在一些實施例中，第一介電層102a可以是聚苯噁唑（PBO）層、聚醯亞胺（PI）層或其他合適的介電層。
請參照圖2，藉由例如物理氣相沈積法在第一介電層102a上形成晶種層104。在一些實施例中，物理氣相沈積法包括濺鍍法、蒸鍍法或任何其他合適方法。晶種層104可以是包括銅、鋁、鈦、其合金或其多層的金屬晶種層。在一些實施例中，晶種層104包括第一金屬層（例如鈦層（未繪示））以及位在第一金屬層上的第二金屬層（例如銅層（未繪示））。
請參照圖3，在形成晶種層104之後，在晶種層104上形成圖案化光阻層106。圖案化光阻層106具有多個開口，使得部分晶種層104外露於圖案化光阻層106的開口。
請參照圖4，進行例如電鍍製程以於部分晶種層104上形成第一重配置導電層102b、102c。具體來說，第一重配置導電層102b位在第一重配置導電層102c的兩旁。第一重配置導電層102b、102c被電鍍在外露於圖案化光阻層106的開口的部分晶種層104上。在一些實施例中，第一重配置導電層102b、102c可以是金屬層，其包括銅、鋁、鈦或其合金。
請參照圖4與圖5，在形成第一重配置導電層102b、102c之後，剝離圖案化光阻層106，使得未被第一重配置導電層102b、102c所覆蓋的部分晶種層104外露。
如圖6所示，藉由使用第一重配置導電層102b、102c當作罩幕，移除未被第一重配置導電層102b、102c所覆蓋的部分晶種層104，以形成晶種層104a並暴露第一介電層102a的表面。也就是說，被第一重配置導電層102b、102c所覆蓋的部分晶種層104未被蝕刻並且被留下以形成晶種層104a。第一重配置線路結構102包括第一介電層102a與其上的第一重配置導電層102b、102c。在全文中，晶種層的剩餘部分104a可視為第一重配置導電層102b、102c的底部。在後續圖式中，晶種層的剩餘部分104a被視為第一重配置導電層102b、102c的一部分且不個別繪示。
另一方面，如圖6所示，雖然圖6中僅繪示一層第一介電層102a、一層第一重配置導電層102b以及一層第一重配置導電層102c，但本揭露不以此為限。在替代實施例中，第一介電層102a與第一重配置導電層102b、102c的數量與配置可依產品的設計與需求來進行調整。在形成第一重配置線路結構102之後，另一個介電層可直接形成在第一重配置線路結構102上，然而，另一個介電層的圖案化製程可被省略。
請參照圖7與圖8，在第一重配置導電層102b上形成多個焊膏107。於焊膏107上分別安置多個導電柱110。接著，進行迴焊製程，焊膏107可經迴焊以形成焊點108，且導電柱110可藉由焊點108與第一重配置導電層102b接合。參照圖7與圖8，焊膏107的材料與導電柱110的材料不同。在一些實施例中，焊膏107的熔點小於導電柱110的熔點。在一些實施例中，焊膏107的材料可包括金屬材料，其包括錫、銀、銅或其合金。焊膏107的形成方法可例如是印刷法、噴塗法或其他合適的方法。導電柱110的材料包括金屬，其包括銅或其他合適金屬。在一些實施例中，導電柱110為預先製作的（pre-fabricated）且可由材料供應商所提供。
請參照圖8，導電結構130包括第一部分與第二部分。第一部分可例如是焊點108，而第二部分可例如是導電柱110。焊點108的側壁與導電柱110的側壁具有不同輪廓。在一些實施例中，導電柱110具有直線型（straight）的側壁，而焊點108具有錐形（tapered）的側壁（如圖8所示），或者是導電柱110c具有階梯型（stepped）的側壁，而焊點108具有弧形的側壁（arc-sidewalls）（如圖19所示）。
圖16A至圖16C為圖8之整合扇出型封裝的製造過程的各種階段的立體示意圖。詳細地說，如圖16A與圖16B所示，在模板10上提供多個預製的導電柱110a，並將導電柱110a放置在模板10的多個孔洞12a中。在一些實施例中，預製的導電柱110a包括銅柱或其他合適的金屬柱。舉例來說，藉由振動機器（vibration machine）振動模板10，使得預製的導電柱110a可部分***模板10的孔洞12a中。由於導電柱110a是預先製作的，因此，容易製造出具有預定高寬比的導電柱110a。此外，由於導電柱110a不需要藉由濺鍍製程、微影製程、電鍍製程以及光阻剝除製程來製造，因此，可減少導電柱110a的製造成本與製造週期（fabrication cycle time）。
在一些實施例中，導電柱110a可被預先製作。預製的導電柱110a的特性（例如寬度、高度、形狀、導電性等）可事先檢查。因此，導電柱110a的生產良率可被提升。
請參照圖16B與圖16C，將載體C倒置在模板10上（亦即將載體C上下翻轉）。後續步驟請參照圖17A至圖17C。
圖17A至圖17C為圖16C之A-A’切線的整合扇出型封裝的製造過程的各種階段的剖面示意圖。圖18為依照本揭露之替代實施例的一種模板的剖面示意圖。如圖17A與圖17B所示，倒置的載體C上的焊膏107面向模板10之孔洞12a中的導電柱110a，使得焊膏107對準模板10之孔洞12a中的導電柱110a。在一些實施例中，導電柱110a可以是I型導電柱且配置在圖17A之由盲孔所形成的孔洞12a中。在替代實施例中，如圖18所示，導電柱110b亦可以是T型導電柱（如圖19所示）或其他合適形狀且容易製造的導電柱，其配置在由貫孔所形成的孔洞12b中。
接著，如圖17B與圖17C所示，將倒置的載體C上的焊膏107與導電柱110a的表面111a接觸。之後，進行迴焊製程，使得焊膏107經迴焊以形成焊點108，且導電柱110a藉由焊點108固定在第一重配置導電層102b上（如圖17C所示）。由於焊膏107的熔點小於導電柱110a的熔點，因此，當迴焊溫度達到焊膏107的熔點時，焊膏107會先熔融，以達到接合功效。此時，導電柱110a仍維持其形狀而不熔融。
在替代實施例中，當載體C倒置並接合在模板10上時，第一重配置導電層102c並未與模板10的上表面接觸。在第一重配置導電層102b與導電柱110a的表面111a接合後，驅動載體C向上移動並從模板10的孔洞12a中拉出導電柱110a。焊點108提供足夠的附著力以從模板10的孔洞12a中拉出導電柱110a，使得導電柱110a轉移接合（transfer-bonded）至第一重配置導電層102b。然後，再次將載體C上下翻轉，如圖17C所示，使得固定在第一重配置導電層102b上的導電柱110a的表面111a面向下（亦即朝向載體C），而導電柱110a的表面111b面向上變成上表面111b。
如圖17B與圖17C所示，由於模板10的孔洞12a具有平坦的下表面且預製的導電柱110a具有相似或相同的高度，因此，圖17C的導電柱110a的上表面111b的共面性比習知電鍍後的導電柱好。在安置導電柱110a之後，多個導電柱110a的上表面111b實質上共平面，而不需要進行後續導電柱110a的研磨製程。如此一來，可進一步地減少本揭露實施例之整合扇出型封裝的製造成本與製造週期。
圖19為圖8之導電柱的放大部分剖面示意圖。請參照圖19，將導電柱110c從模板10轉移接合至第一重配置導電層102b之後，導電柱110c的底部可位在焊點108a上或內埋於焊點108b中。導電柱110c下方的焊點108b的厚度t2可小於導電柱110c的高度t3。導電柱110c的高度t3可例如是100微米（μm）至500微米，而導電柱110c下方的焊點108b的厚度t2可例如是2微米至10微米。在一些實施例中，t2/t3的比值為0.004至0.1。在一些實施例中，導電柱110c的底部的內埋深度t1可小於導電柱110c的高度t3的三分之一。也就是說，t1/t3的比值小於三分之一。在一些實施例中，導電柱110c的底部的內埋深度t1可小於30微米。在替代實施例中，導電柱110c的底部的內埋深度t1可小於10微米。多個導電柱110c之間的上表面111b的水平高度差（level height different）ΔH可小於10微米。此水平高度差ΔH可視為共平面，而不影響後續製程，因此，導電柱110c的研磨製程可被省略。
詳細地說，如圖19所示，焊點108a、108b中之至少一者具有弧形側壁S108，其朝著相對應的焊點108a、108b的中心凹陷。以焊點108a為例，焊點108a具有錐形（tapered）側壁S108。焊點108a的水平截面積自第一重配置導電層102b往對應的導電柱110c的方向漸縮。在一些實施例中，焊點108a的上部寬度W2等於位在焊點108a上的導電柱110c的下部寬度W1，而焊點108a的下部寬度W3大於位在焊點108a上的導電柱110c的下部寬度W1。在替代實施例中，由於焊點108b覆蓋對應的導電柱110c的側壁S110的一部分，因此，焊點108b的上部寬度W4大於位在焊點108b上的導電柱110c的下部寬度W1，其中上部寬度W4位在焊點108b與導電柱110c之間的界面處。換言之，在迴焊製程之後，焊點108b的頂面具有凹陷R。凹陷R的深度t1可例如小於10微米。導電柱110c的底部可部分***所述凹陷R中。
請回頭參照圖8與圖9，藉由黏膠（adhesive）AD將晶粒112安置在第一重配置導電層102c上。在一些實施例中，晶粒112可藉由黏膠AD直接接合至第一重配置導電層102c上。黏膠AD填入第一重配置導電層102c中的開口並覆蓋第一重配置導電層102c的上表面。因此，晶粒112藉由黏膠AD與第一重配置導電層102c電性絕緣。在一些實施例中，黏膠AD可以是晶片貼覆膜（die attach film，DAF）或線路上覆膜（film over wire，FoW）。晶粒112具有主動表面112a以及相對於主動表面112a的背面112f。在一些實施例中，晶粒112包括多個接墊112b、鈍化層112c以及多個導電柱112d。鈍化層112c覆蓋主動表面112a以及部分接墊112b。接墊112b部分外露於鈍化層112c。導電柱112d形成在接墊112b上，並與接墊112b電性連接。晶粒112的背面112f與黏膠AD接觸。導電柱112d可例如是銅柱或其他合適的金屬柱。
在圖9中，雖然只有一個晶粒112安置在第一重配置導電層102c上。然而，晶粒112的數量僅是用以說明，本揭露不限於此。在替代實施例中，可將多個晶粒112安置在第一重配置導電層102c上，且安置在第一重配置導電層102c上的晶粒112可排列成陣列。當多個晶粒112安置在第一重配置導電層102c上，多個導電柱110的群組可被安置在第一重配置導電層102b上，且導電柱110的群組中之一環繞各晶粒112。
參照圖10，在載體C上形成絕緣材料（未繪示）以覆蓋焊點108、導電柱110以及晶粒112的表面。在一些實施例中，絕緣材料可以是藉由模製製程（molding process）所形成的模製化合物（molding compound）。在一些實施例中，絕緣材料可包括環氧化合物或其他適合的材料。接著，研磨絕緣材料以及部分晶粒112以暴露出導電柱112d的上表面113d。研磨絕緣材料之後，絕緣包封體114形成在第一重配置線路結構102上，以包封晶粒112的側壁、導電柱110的側壁以及焊點108的側壁。在一些實施例中，在上述研磨製程期間，部分絕緣材料、部分導電柱112d以及部分導電柱110被移除，以暴露導電柱112d的上表面113d與導電柱110的上表面111b。在一些實施例中，絕緣包封體114可藉由機械研磨法以及/或化學機械研磨法（CMP）形成。
絕緣包封體114包封晶粒112的側壁以及導電結構130的側壁。換言之，導電結構130與晶粒112內埋在絕緣包封體114中。也就是說，導電結構130（其包括焊點108與導電柱110）貫穿絕緣包封體114，且暴露出導電柱110的上表面111b。需注意的是，在經過研磨製程後，導電柱110的上表面111b、導電柱112d的上表面113d以及絕緣包封體114的上表面114a實質上共平面。
在替代實施例中，由於導電柱110的上表面111b之間的共面性夠好，因此，研磨製程可被省略。詳細地說，當晶粒112安置在第一重配置導電層102c上之後，導電柱110的上表面111b以及導電柱112d的上表面113d實質上共平面。可將離形膜（未繪示）附著在導電柱110的上表面111b以及導電柱112d的上表面113d上。接著，利用模具固定具有離形膜、晶粒112以及導電柱110的載體C。之後，將絕緣材料填入離形膜、晶粒112以及導電柱110之間的空隙，並接著固化，以形成絕緣包封體114。換言之，離形膜可避免絕緣包封體114附著在導電柱110的上表面111b以及導電柱112d的上表面113d上。因此，本揭露實施例可省略研磨製程，以減少製造成本與製造週期。
請參照圖11，在形成絕緣包封體114之後，在導電柱110的上表面111b上、絕緣包封體114的上表面114a上以及導電柱112d的上表面113d上形成第二重配置線路結構116。如圖11所示，第二重配置線路結構116包括交替堆疊的多個第二介電層116a以及多個第二重配置導電層116b。第二重配置導電層116b與晶粒112的導電柱112d以及導電柱110電性連接。也就是說，導電結構130（其包括焊點108與導電柱110）電性連接第一重配置線路結構102與第二重配置線路結構116。在一些實施例中，導電柱112d的上表面113d以及導電柱110的上表面111b接觸第二重配置線路結構116的最底的第二重配置導電層116b。最底部的第二介電層116a部分覆蓋導電柱112d的上表面113d以及導電柱110的上表面111b。此外，最頂的第二重配置導電層116b具有多個接墊。在一些實施例中，上述接墊包括多個球底金屬（under-ball metallurgy，UBM）圖案116b1以及/或至少一個連接接墊116b2。UBM圖案116b1可用以安置焊球，而連接接墊116b2可用以安置被動元件。UBM圖案116b1以及連接接墊116b2的數量不限於本揭露。
請參照圖12，在形成第二重配置線路結構116之後，在UBM圖案116b1上安置多個導電端子（conductive terminals）118，並在連接接墊116b2上安置多個被動元件120。在一些實施例中，可藉由植球製程將導電端子118安置在UBM圖案116b1上，並可藉由焊接製程或迴焊製程將被動元件120安置在連接接墊116b2上。
請參照圖12與圖13，在第二重配置線路結構116上安置導電端子118與被動元件120之後，將第一介電層102a與剝離層DB剝離，使得第一介電層102a與剝離層DB以及載體C分離或分層。在一些實施例中，剝離層DB（例如是光熱轉換釋放層）可藉由照射紫外光雷射，以使第一介電層102a與載體C剝離。
如圖13所示，接著，圖案化第一介電層102a，以形成多個接觸開口122並暴露出第一重配置導電層102b的下表面。在一些實施例中，第一介電層102a中的接觸開口122的數量對應於第一重配置導電層102b的數量。
請參照圖14，在第一介電層102a中形成接觸開口122之後，多個導電端子124（例如是導電球）被放置在外露於接觸開口122的第一重配置導電層102b的下表面上。在一些實施例中，導電端子124（例如是導電球）可被迴焊以固定在第一重配置導電層102b的被暴露的表面上。換句話說，導電端子124與第一重配置導電層102b電性連接。如圖14所示，在形成導電端子118、124之後，可完成具有雙側端子（dual-side terminals）的整合扇出型封裝100。
請參照圖15，接著提供另一種封裝200。在一些實施例中，封裝200可以是記憶元件。封裝200藉由導電端子124堆疊並電性連接至圖14的整合扇出型封裝100，以製造出堆疊式封裝（package-on-package，POP）結構。
根據一些實施例，晶粒可藉由黏膠直接安置在第一重配置線路結構上。另外，晶粒的背面上的第一重配置線路結構以及晶粒的主動面上的第二重配置線路結構可藉由多個焊點與多個導電柱相互連接。導電柱可藉由焊點安置在第一重配置線路結構上。焊點形成在第一重配置線路結構與導電柱之間，以提升導電柱的上表面之間的共面性。
根據一些實施例，一種整合扇出型封裝包括晶粒、第一重配置線路結構、第二重配置線路結構、多個焊點、多個導電柱以及絕緣包封體。第一重配置線路結構與第二重配置線路結構分別形成在所述晶粒的背面與主動表面上，以將所述晶粒配置在上述兩者之間。焊點形成在所述晶粒旁且與所述第一重配置線路結構連接。導電柱分別形成在所述焊點上且與所述第二重配置線路結構連接，並藉由所述焊點與所述第一重配置線路結構連接。絕緣包封體包封所述晶粒的多個側壁、所述導電柱的多個側壁以及所述焊點的多個側壁。
根據一些實施例，所述晶粒藉由黏膠與所述第一重配置線路結構接合。所述焊點的材料與所述導電柱的材料不同。所述導電柱下方的所述焊點的厚度小於所述導電柱的高度。所述焊點的至少一者具有多個弧形側壁或多個錐形側壁。各所述焊點的上部寬度大於或等於各所述導電柱的下部寬度，而各所述焊點的下部寬度大於各所述導電柱的下部寬度。所述焊點的至少一者的水平截面積往相對應的導電柱漸縮。所述導電柱包括I型導電柱、T型導電柱或其組合。所述焊點的至少一者覆蓋相對應的導電柱的多個側壁的一部分。
根據一些實施例，一種整合扇出型封裝包括晶粒、第一重配置線路結構、第二重配置線路結構、絕緣包封體、多個導電結構、多個第一導電端子以及多個第二導電端子。第一重配置線路結構形成在晶粒的背面上。第二重配置線路結構形成在晶粒的主動表面上。絕緣包封體形成在晶粒旁，以包封晶粒。導電結構貫穿絕緣包封體。所述導電結構之至少一者包括第一部分與位在第一部分上的第二部分。第一部分與第一重配置線路結構電性連接。第二部分與第二重配置線路結構電性連接，並藉由第一部分與第一重配置線路結構電性連接。第一部分的材料與第二部分的材料不同。第一導電端子與第二重配置線路結構電性連接。第二導電端子與第一重配置線路結構電性連接。
根據一些實施例，所述第一部分的熔點低於所述第二部分的熔點。所述第一部分具有多個弧形側壁或多個錐形側壁。所述晶粒藉由黏膠與所述第一重配置線路結構接合。所述第一部分還覆蓋所述第二部分的多個側壁的一部分。
根據一些實施例，一種整合扇出型封裝的製造方法，其步驟如下。在載體上形成第一重配置線路結構。第一重配置線路結構包括第一介電層以及位在第一介電層上的多個第一重配置導電層。在第一重配置導電層的一部分上形成多個焊點。藉由多個焊點將多個導電柱分別安置在所述第一重配置導電層上。藉由黏膠將晶粒安置在第一重配置導電層的另一部分上。形成絕緣包封體，以包封晶粒的多個側壁、導電柱的多個側壁以及焊點的多個側壁。在絕緣包封體、晶粒以及導電柱上形成第二重配置線路結構。將第二重配置線路結構電性連接至晶粒以及導電柱。移除載體。
根據一些實施例，在所述焊點上安置所述導電柱的方法包括將所述導電柱分別放置在模板的多個孔洞中；在所述載體的所述第一重配置導電層的一部分上形成多個焊膏；將具有所述焊膏的所述載體倒置在所述模板上，以將所述載體的所述焊膏對齊所述模板的所述孔洞中的所述導電柱；以及對所述焊膏進行迴焊製程，以形成所述焊點並將所述導電柱固定在所述焊點上。所述模板的所述孔洞包括多個盲孔或多個貫孔。進行所述迴焊製程之後，所述導電柱的多個上表面實質上共平面。進行所述迴焊製程之後，所述導電柱之間的上表面的水平高度差小於10微米。所述整合扇出型封裝的製造方法，更包括在移除所述載體之前，在所述第二重配置線路結構上分別形成多個第一導電端子；以及在移除所述載體之後，圖案化所述第一介電層，以暴露所述第一重配置導電層的多個表面，且在所述第一重配置導電層的被暴露的表面上形成多個第二導電端子。
以上概述了數個實施例的特徵，使本領域具有通常知識者可更佳了解本揭露的態樣。本領域具有通常知識者應理解，其可輕易地使用本揭露作為設計或修改其他製程與結構的依據，以實行本文所介紹的實施例的相同目的及/或達到相同優點。本領域具有通常知識者還應理解，這種等效的位並不悖離本揭露的精神與範疇，且本領域具有通常知識者在不悖離本揭露的精神與範疇的情況下可對本文做出各種改變、置換以及變更。
雖然本發明已以實施例揭露如上，然其並非用以限定本發明，任何所屬技術領域中具有通常知識者，在不脫離本發明的精神和範圍內，當可作些許的更動與潤飾，故本發明的保護範圍當視後附的申請專利範圍所界定者為準。
10‧‧‧模板
12a、12b‧‧‧孔洞
100‧‧‧整合扇出型封裝
102‧‧‧第一重配置線路結構
102a‧‧‧第一介電層
102b、102c‧‧‧第一重配置導電層
104、104a‧‧‧晶種層
106‧‧‧圖案化光阻層
107‧‧‧焊膏
108、108a、108b‧‧‧焊點
110、110a、110b、110c‧‧‧導電柱
111a‧‧‧表面
111b、113d、114a‧‧‧上表面
112‧‧‧晶粒
112a‧‧‧主動表面
112b‧‧‧接墊
112c‧‧‧鈍化層
112d‧‧‧導電柱
112f‧‧‧背面
114‧‧‧絕緣包封體
116‧‧‧第二重配置線路結構
116a‧‧‧第二介電層
116b‧‧‧第二重配置導電層
116b1‧‧‧球底金屬圖案
116b2‧‧‧連接接墊
118‧‧‧導電端子
120‧‧‧被動元件
122‧‧‧接觸開口
124‧‧‧導電端子
130‧‧‧導電結構
200‧‧‧封裝
AD‧‧‧黏膠
C‧‧‧載體
DB‧‧‧剝離層
R‧‧‧凹陷
S108‧‧‧弧形側壁
S110‧‧‧側壁
W1、W3‧‧‧下部寬度
W2、W4‧‧‧上部寬度
ΔH‧‧‧水平高度差
t1‧‧‧深度
t2‧‧‧厚度
t3‧‧‧高度
圖1至圖15為依照本揭露一些實施例的一種整合扇出型封裝的製造過程的各種階段的剖面示意圖。 圖16A至圖16C為圖8之整合扇出型封裝的製造過程的各種階段的立體示意圖。 圖17A至圖17C為圖16C之A-A’切線的整合扇出型封裝的製造過程的各種階段的剖面示意圖。 圖18為依照本揭露之替代實施例的一種模板的剖面示意圖。 圖19為圖8之導電柱的放大部分剖面示意圖。
100‧‧‧整合扇出型封裝
102‧‧‧第一重配置線路結構
102a‧‧‧第一介電層
102b、102c‧‧‧第一重配置導電層
108‧‧‧焊點
110‧‧‧導電柱
112‧‧‧晶粒
112d‧‧‧導電柱
114‧‧‧絕緣包封體
116‧‧‧第二重配置線路結構
116a‧‧‧第二介電層
116b‧‧‧第二重配置導電層
116b1‧‧‧球底金屬圖案
116b2‧‧‧連接接墊
118‧‧‧導電端子
120‧‧‧被動元件
124‧‧‧導電端子
130‧‧‧導電結構
200‧‧‧封裝
AD‧‧‧黏膠

Claims (1)

  1. 一種整合扇出型封裝，包括： 晶粒； 第一重配置線路結構與第二重配置線路結構，分別位在所述晶粒的背面與主動表面上，以將所述晶粒夾在其中； 多個焊點，位在所述晶粒旁且與所述第一重配置線路結構連接； 多個導電柱，分別位在所述焊點上且與所述第二重配置線路結構連接，並藉由所述焊點與所述第一重配置線路結構連接；以及 絕緣包封體，包封所述晶粒的多個側壁、所述導電柱的多個側壁以及所述焊點的多個側壁。
TW105132986A 2016-07-21 2016-10-13 整合扇出型封裝 TW201804575A (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US15/215,598 2016-07-21
US15/215,598 US9984960B2 (en) 2016-07-21 2016-07-21 Integrated fan-out package and method of fabricating the same

Publications (1)

Publication Number Publication Date
TW201804575A true TW201804575A (zh) 2018-02-01

Family

ID=60990103

Family Applications (1)

Application Number Title Priority Date Filing Date
TW105132986A TW201804575A (zh) 2016-07-21 2016-10-13 整合扇出型封裝

Country Status (3)

Country Link
US (1) US9984960B2 (zh)
CN (1) CN107644860A (zh)
TW (1) TW201804575A (zh)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10573573B2 (en) 2018-03-20 2020-02-25 Taiwan Semiconductor Manufacturing Co., Ltd. Package and package-on-package structure having elliptical conductive columns

Families Citing this family (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10636757B2 (en) * 2017-08-29 2020-04-28 Taiwan Semiconductor Manufacturing Co., Ltd. Integrated circuit component package and method of fabricating the same
US10347574B2 (en) * 2017-09-28 2019-07-09 Taiwan Semiconductor Manufacturing Co., Ltd. Integrated fan-out packages
US10304697B2 (en) * 2017-10-05 2019-05-28 Amkor Technology, Inc. Electronic device with top side pin array and manufacturing method thereof
US10886231B2 (en) 2018-06-29 2021-01-05 Taiwan Semiconductor Manufacturing Company, Ltd. Method of forming RDLS and structure formed thereof
US10825773B2 (en) * 2018-09-27 2020-11-03 Taiwan Semiconductor Manufacturing Co., Ltd. Package structure with reinforcement structures in a redistribution circuit structure and method of manufacturing the same
TWI736859B (zh) * 2019-03-18 2021-08-21 矽品精密工業股份有限公司 電子封裝件及其製法
US11600590B2 (en) * 2019-03-22 2023-03-07 Advanced Semiconductor Engineering, Inc. Semiconductor device and semiconductor package
CN110034061B (zh) * 2019-04-24 2021-05-14 京东方科技集团股份有限公司 芯片转移方法、芯片及目标基板
US11862587B2 (en) * 2019-07-25 2024-01-02 Advanced Semiconductor Engineering, Inc. Semiconductor package structure and method of manufacturing the same
US11410902B2 (en) * 2019-09-16 2022-08-09 Advanced Semiconductor Engineering, Inc. Semiconductor device package and method of manufacturing the same
US20220328394A1 (en) * 2021-04-07 2022-10-13 Mediatek Inc. Three-dimensional pad structure and interconnection structure for electronic devices

Family Cites Families (33)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4418857A (en) * 1980-12-31 1983-12-06 International Business Machines Corp. High melting point process for Au:Sn:80:20 brazing alloy for chip carriers
US4672739A (en) * 1985-04-11 1987-06-16 International Business Machines Corporation Method for use in brazing an interconnect pin to a metallization pattern situated on a brittle dielectric substrate
JP2716336B2 (ja) * 1993-03-10 1998-02-18 日本電気株式会社 集積回路装置
US6555757B2 (en) * 2000-04-10 2003-04-29 Ngk Spark Plug Co., Ltd. Pin solder jointed to a resin substrate, made having a predetermined hardness and dimensions
US8193034B2 (en) * 2006-11-10 2012-06-05 Stats Chippac, Ltd. Semiconductor device and method of forming vertical interconnect structure using stud bumps
US8759964B2 (en) 2007-07-17 2014-06-24 Taiwan Semiconductor Manufacturing Company, Ltd. Wafer level package structure and fabrication methods
US9048233B2 (en) 2010-05-26 2015-06-02 Taiwan Semiconductor Manufacturing Company, Ltd. Package systems having interposers
US8669651B2 (en) * 2010-07-26 2014-03-11 Taiwan Semiconductor Manufacturing Company, Ltd. Package-on-package structures with reduced bump bridging
US8361842B2 (en) 2010-07-30 2013-01-29 Taiwan Semiconductor Manufacturing Company, Ltd. Embedded wafer-level bonding approaches
US8884431B2 (en) 2011-09-09 2014-11-11 Taiwan Semiconductor Manufacturing Company, Ltd. Packaging methods and structures for semiconductor devices
US9064879B2 (en) 2010-10-14 2015-06-23 Taiwan Semiconductor Manufacturing Company, Ltd. Packaging methods and structures using a die attach film
US8829676B2 (en) 2011-06-28 2014-09-09 Taiwan Semiconductor Manufacturing Company, Ltd. Interconnect structure for wafer level package
US8975741B2 (en) * 2011-10-17 2015-03-10 Taiwan Semiconductor Manufacturing Company, Ltd. Process for forming package-on-package structures
US9000584B2 (en) 2011-12-28 2015-04-07 Taiwan Semiconductor Manufacturing Company, Ltd. Packaged semiconductor device with a molding compound and a method of forming the same
US8680647B2 (en) 2011-12-29 2014-03-25 Taiwan Semiconductor Manufacturing Company, Ltd. Packages with passive devices and methods of forming the same
US9111949B2 (en) 2012-04-09 2015-08-18 Taiwan Semiconductor Manufacturing Company, Ltd. Methods and apparatus of wafer level package for heterogeneous integration technology
US9991190B2 (en) 2012-05-18 2018-06-05 Taiwan Semiconductor Manufacturing Company, Ltd. Packaging with interposer frame
US8703542B2 (en) 2012-05-18 2014-04-22 Taiwan Semiconductor Manufacturing Company, Ltd. Wafer-level packaging mechanisms
US8809996B2 (en) 2012-06-29 2014-08-19 Taiwan Semiconductor Manufacturing Company, Ltd. Package with passive devices and method of forming the same
US9443797B2 (en) * 2012-09-14 2016-09-13 STATS ChipPAC Pte. Ltd. Semiconductor device having wire studs as vertical interconnect in FO-WLP
US8785299B2 (en) 2012-11-30 2014-07-22 Taiwan Semiconductor Manufacturing Company, Ltd. Package with a fan-out structure and method of forming the same
US8803306B1 (en) 2013-01-18 2014-08-12 Taiwan Semiconductor Manufacturing Company, Ltd. Fan-out package structure and methods for forming the same
US8778738B1 (en) 2013-02-19 2014-07-15 Taiwan Semiconductor Manufacturing Company, Ltd. Packaged semiconductor devices and packaging devices and methods
US9263511B2 (en) 2013-02-11 2016-02-16 Taiwan Semiconductor Manufacturing Co., Ltd. Package with metal-insulator-metal capacitor and method of manufacturing the same
US9048222B2 (en) 2013-03-06 2015-06-02 Taiwan Semiconductor Manufacturing Company, Ltd. Method of fabricating interconnect structure for package-on-package devices
US9368460B2 (en) 2013-03-15 2016-06-14 Taiwan Semiconductor Manufacturing Company, Ltd. Fan-out interconnect structure and method for forming same
US8877554B2 (en) 2013-03-15 2014-11-04 Taiwan Semiconductor Manufacturing Company, Ltd. Packaged semiconductor devices, methods of packaging semiconductor devices, and PoP devices
US9252065B2 (en) * 2013-11-22 2016-02-02 Taiwan Semiconductor Manufacturing Co., Ltd. Mechanisms for forming package structure
KR101538573B1 (ko) * 2014-02-05 2015-07-21 앰코 테크놀로지 코리아 주식회사 반도체 디바이스의 제조 방법 및 이에 따른 반도체 디바이스
US10177115B2 (en) * 2014-09-05 2019-01-08 Taiwan Semiconductor Manufacturing Company, Ltd. Package structures and methods of forming
KR101634067B1 (ko) * 2014-10-01 2016-06-30 주식회사 네패스 반도체 패키지 및 그 제조방법
US9461018B1 (en) * 2015-04-17 2016-10-04 Taiwan Semiconductor Manufacturing Company, Ltd. Fan-out PoP structure with inconsecutive polymer layer
US9520385B1 (en) * 2015-06-29 2016-12-13 Taiwan Semiconductor Manufacturing Company, Ltd. Package structure and method for forming same

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10573573B2 (en) 2018-03-20 2020-02-25 Taiwan Semiconductor Manufacturing Co., Ltd. Package and package-on-package structure having elliptical conductive columns
TWI769359B (zh) * 2018-03-20 2022-07-01 台灣積體電路製造股份有限公司 封裝、疊層封裝結構及製造疊層封裝結構的方法
US11404341B2 (en) 2018-03-20 2022-08-02 Taiwan Semiconductor Manufacturing Company, Ltd. Package and package-on-package structure having elliptical columns and ellipsoid joint terminals

Also Published As

Publication number Publication date
CN107644860A (zh) 2018-01-30
US9984960B2 (en) 2018-05-29
US20180025966A1 (en) 2018-01-25

Similar Documents

Publication Publication Date Title
TW201804575A (zh) 整合扇出型封裝
TWI576927B (zh) 半導體裝置及其製造方法
US9870997B2 (en) Integrated fan-out package and method of fabricating the same
US10446411B2 (en) Semiconductor device package with a conductive post
TWI649845B (zh) 半導體封裝結構及其製造方法
TWI644403B (zh) 封裝結構及其製造方法
TWI460845B (zh) 具有區域陣列單元連接器之可堆疊模製微電子封裝
US10734328B2 (en) Semiconductor package and manufacturing method thereof
TWI761342B (zh) 半導體封裝及其製造方法
US8569885B2 (en) Stacked semiconductor packages and related methods
TWI731888B (zh) 堆疊式半導體元件的製造方法
TW201742081A (zh) 導電圖案
US9978716B2 (en) Package structure and method for manufacturing the same
US11276660B2 (en) Semiconductor device package having a core substrate and an embedded component in the core substrate
US20200381395A1 (en) Semiconductor devices and related methods
US10192802B2 (en) Thin film based fan out and multi die package platform
US10062626B2 (en) Semiconductor device and manufacturing method thereof
US20190259731A1 (en) Substrate based fan-out wafer level packaging
TW201637147A (zh) 使用在電鍍的側壁之囊封劑開口中之接點的半導體封裝
TWI612627B (zh) 電子封裝件及其製法
US11594479B2 (en) Semiconductor structure and manufacturing method thereof
TWI820992B (zh) 毫米波天線模組封裝結構及其製造方法
US11764179B2 (en) Semiconductor device package
JP2016032088A (ja) 半導体装置及び半導体装置の製造方法